1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * MediaTek 8365 ALSA SoC AFE platform driver
4 *
5 * Copyright (c) 2024 MediaTek Inc.
6 * Authors: Jia Zeng <jia.zeng@mediatek.com>
7 * Alexandre Mergnat <amergnat@baylibre.com>
8 */
9
10 #include <linux/delay.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_address.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/pm_runtime.h>
16 #include <sound/soc.h>
17 #include <sound/pcm_params.h>
18 #include "mt8365-afe-common.h"
19 #include "mt8365-afe-clk.h"
20 #include "mt8365-reg.h"
21 #include "../common/mtk-base-afe.h"
22 #include "../common/mtk-afe-platform-driver.h"
23 #include "../common/mtk-afe-fe-dai.h"
24
25 #define AFE_BASE_END_OFFSET 8
26
27 static unsigned int mCM2Input;
28
29 static const unsigned int mt8365_afe_backup_list[] = {
30 AUDIO_TOP_CON0,
31 AFE_CONN0,
32 AFE_CONN1,
33 AFE_CONN3,
34 AFE_CONN4,
35 AFE_CONN5,
36 AFE_CONN6,
37 AFE_CONN7,
38 AFE_CONN8,
39 AFE_CONN9,
40 AFE_CONN10,
41 AFE_CONN11,
42 AFE_CONN12,
43 AFE_CONN13,
44 AFE_CONN14,
45 AFE_CONN15,
46 AFE_CONN16,
47 AFE_CONN17,
48 AFE_CONN18,
49 AFE_CONN19,
50 AFE_CONN20,
51 AFE_CONN21,
52 AFE_CONN26,
53 AFE_CONN27,
54 AFE_CONN28,
55 AFE_CONN29,
56 AFE_CONN30,
57 AFE_CONN31,
58 AFE_CONN32,
59 AFE_CONN33,
60 AFE_CONN34,
61 AFE_CONN35,
62 AFE_CONN36,
63 AFE_CONN_24BIT,
64 AFE_CONN_24BIT_1,
65 AFE_DAC_CON0,
66 AFE_DAC_CON1,
67 AFE_DL1_BASE,
68 AFE_DL1_END,
69 AFE_DL2_BASE,
70 AFE_DL2_END,
71 AFE_VUL_BASE,
72 AFE_VUL_END,
73 AFE_AWB_BASE,
74 AFE_AWB_END,
75 AFE_VUL3_BASE,
76 AFE_VUL3_END,
77 AFE_HDMI_OUT_BASE,
78 AFE_HDMI_OUT_END,
79 AFE_HDMI_IN_2CH_BASE,
80 AFE_HDMI_IN_2CH_END,
81 AFE_ADDA_UL_DL_CON0,
82 AFE_ADDA_DL_SRC2_CON0,
83 AFE_ADDA_DL_SRC2_CON1,
84 AFE_I2S_CON,
85 AFE_I2S_CON1,
86 AFE_I2S_CON2,
87 AFE_I2S_CON3,
88 AFE_ADDA_UL_SRC_CON0,
89 AFE_AUD_PAD_TOP,
90 AFE_HD_ENGEN_ENABLE,
91 };
92
93 static const struct snd_pcm_hardware mt8365_afe_hardware = {
94 .info = (SNDRV_PCM_INFO_MMAP |
95 SNDRV_PCM_INFO_INTERLEAVED |
96 SNDRV_PCM_INFO_MMAP_VALID),
97 .buffer_bytes_max = 256 * 1024,
98 .period_bytes_min = 512,
99 .period_bytes_max = 128 * 1024,
100 .periods_min = 2,
101 .periods_max = 256,
102 .fifo_size = 0,
103 };
104
105 struct mt8365_afe_rate {
106 unsigned int rate;
107 unsigned int reg_val;
108 };
109
110 static const struct mt8365_afe_rate mt8365_afe_fs_rates[] = {
111 { .rate = 8000, .reg_val = MT8365_FS_8K },
112 { .rate = 11025, .reg_val = MT8365_FS_11D025K },
113 { .rate = 12000, .reg_val = MT8365_FS_12K },
114 { .rate = 16000, .reg_val = MT8365_FS_16K },
115 { .rate = 22050, .reg_val = MT8365_FS_22D05K },
116 { .rate = 24000, .reg_val = MT8365_FS_24K },
117 { .rate = 32000, .reg_val = MT8365_FS_32K },
118 { .rate = 44100, .reg_val = MT8365_FS_44D1K },
119 { .rate = 48000, .reg_val = MT8365_FS_48K },
120 { .rate = 88200, .reg_val = MT8365_FS_88D2K },
121 { .rate = 96000, .reg_val = MT8365_FS_96K },
122 { .rate = 176400, .reg_val = MT8365_FS_176D4K },
123 { .rate = 192000, .reg_val = MT8365_FS_192K },
124 };
125
mt8365_afe_fs_timing(unsigned int rate)126 int mt8365_afe_fs_timing(unsigned int rate)
127 {
128 int i;
129
130 for (i = 0; i < ARRAY_SIZE(mt8365_afe_fs_rates); i++)
131 if (mt8365_afe_fs_rates[i].rate == rate)
132 return mt8365_afe_fs_rates[i].reg_val;
133
134 return -EINVAL;
135 }
136
mt8365_afe_rate_supported(unsigned int rate,unsigned int id)137 bool mt8365_afe_rate_supported(unsigned int rate, unsigned int id)
138 {
139 switch (id) {
140 case MT8365_AFE_IO_TDM_IN:
141 if (rate >= 8000 && rate <= 192000)
142 return true;
143 break;
144 case MT8365_AFE_IO_DMIC:
145 if (rate >= 8000 && rate <= 48000)
146 return true;
147 break;
148 default:
149 break;
150 }
151
152 return false;
153 }
154
mt8365_afe_channel_supported(unsigned int channel,unsigned int id)155 bool mt8365_afe_channel_supported(unsigned int channel, unsigned int id)
156 {
157 switch (id) {
158 case MT8365_AFE_IO_TDM_IN:
159 if (channel >= 1 && channel <= 8)
160 return true;
161 break;
162 case MT8365_AFE_IO_DMIC:
163 if (channel >= 1 && channel <= 8)
164 return true;
165 break;
166 default:
167 break;
168 }
169
170 return false;
171 }
172
mt8365_afe_clk_group_44k(int sample_rate)173 static bool mt8365_afe_clk_group_44k(int sample_rate)
174 {
175 if (sample_rate == 11025 ||
176 sample_rate == 22050 ||
177 sample_rate == 44100 ||
178 sample_rate == 88200 ||
179 sample_rate == 176400)
180 return true;
181 else
182 return false;
183 }
184
mt8365_afe_clk_group_48k(int sample_rate)185 static bool mt8365_afe_clk_group_48k(int sample_rate)
186 {
187 return (!mt8365_afe_clk_group_44k(sample_rate));
188 }
189
mt8365_dai_set_priv(struct mtk_base_afe * afe,int id,int priv_size,const void * priv_data)190 int mt8365_dai_set_priv(struct mtk_base_afe *afe, int id,
191 int priv_size, const void *priv_data)
192 {
193 struct mt8365_afe_private *afe_priv = afe->platform_priv;
194 void *temp_data;
195
196 temp_data = devm_kzalloc(afe->dev, priv_size, GFP_KERNEL);
197 if (!temp_data)
198 return -ENOMEM;
199
200 if (priv_data)
201 memcpy(temp_data, priv_data, priv_size);
202
203 afe_priv->dai_priv[id] = temp_data;
204
205 return 0;
206 }
207
mt8365_afe_irq_direction_enable(struct mtk_base_afe * afe,int irq_id,int direction)208 static int mt8365_afe_irq_direction_enable(struct mtk_base_afe *afe,
209 int irq_id, int direction)
210 {
211 struct mtk_base_afe_irq *irq;
212
213 if (irq_id >= MT8365_AFE_IRQ_NUM)
214 return -1;
215
216 irq = &afe->irqs[irq_id];
217
218 if (direction == MT8365_AFE_IRQ_DIR_MCU) {
219 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_DSP_EN,
220 (1 << irq->irq_data->irq_clr_shift),
221 0);
222 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_EN,
223 (1 << irq->irq_data->irq_clr_shift),
224 (1 << irq->irq_data->irq_clr_shift));
225 } else if (direction == MT8365_AFE_IRQ_DIR_DSP) {
226 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_DSP_EN,
227 (1 << irq->irq_data->irq_clr_shift),
228 (1 << irq->irq_data->irq_clr_shift));
229 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_EN,
230 (1 << irq->irq_data->irq_clr_shift),
231 0);
232 } else {
233 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_DSP_EN,
234 (1 << irq->irq_data->irq_clr_shift),
235 (1 << irq->irq_data->irq_clr_shift));
236 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_EN,
237 (1 << irq->irq_data->irq_clr_shift),
238 (1 << irq->irq_data->irq_clr_shift));
239 }
240 return 0;
241 }
242
mt8365_memif_fs(struct snd_pcm_substream * substream,unsigned int rate)243 static int mt8365_memif_fs(struct snd_pcm_substream *substream,
244 unsigned int rate)
245 {
246 return mt8365_afe_fs_timing(rate);
247 }
248
mt8365_irq_fs(struct snd_pcm_substream * substream,unsigned int rate)249 static int mt8365_irq_fs(struct snd_pcm_substream *substream,
250 unsigned int rate)
251 {
252 return mt8365_memif_fs(substream, rate);
253 }
254
255 static const struct mt8365_cm_ctrl_reg cm_ctrl_reg[MT8365_CM_NUM] = {
256 [MT8365_CM1] = {
257 .con0 = AFE_CM1_CON0,
258 .con1 = AFE_CM1_CON1,
259 .con2 = AFE_CM1_CON2,
260 .con3 = AFE_CM1_CON3,
261 .con4 = AFE_CM1_CON4,
262 },
263 [MT8365_CM2] = {
264 .con0 = AFE_CM2_CON0,
265 .con1 = AFE_CM2_CON1,
266 .con2 = AFE_CM2_CON2,
267 .con3 = AFE_CM2_CON3,
268 .con4 = AFE_CM2_CON4,
269 }
270 };
271
mt8365_afe_cm2_mux_conn(struct mtk_base_afe * afe)272 static int mt8365_afe_cm2_mux_conn(struct mtk_base_afe *afe)
273 {
274 struct mt8365_afe_private *afe_priv = afe->platform_priv;
275 unsigned int input = afe_priv->cm2_mux_input;
276
277 /* TDM_IN interconnect to CM2 */
278 regmap_update_bits(afe->regmap, AFE_CM2_CONN0,
279 CM2_AFE_CM2_CONN_CFG1_MASK,
280 CM2_AFE_CM2_CONN_CFG1(TDM_IN_CH0));
281 regmap_update_bits(afe->regmap, AFE_CM2_CONN0,
282 CM2_AFE_CM2_CONN_CFG2_MASK,
283 CM2_AFE_CM2_CONN_CFG2(TDM_IN_CH1));
284 regmap_update_bits(afe->regmap, AFE_CM2_CONN0,
285 CM2_AFE_CM2_CONN_CFG3_MASK,
286 CM2_AFE_CM2_CONN_CFG3(TDM_IN_CH2));
287 regmap_update_bits(afe->regmap, AFE_CM2_CONN0,
288 CM2_AFE_CM2_CONN_CFG4_MASK,
289 CM2_AFE_CM2_CONN_CFG4(TDM_IN_CH3));
290 regmap_update_bits(afe->regmap, AFE_CM2_CONN0,
291 CM2_AFE_CM2_CONN_CFG5_MASK,
292 CM2_AFE_CM2_CONN_CFG5(TDM_IN_CH4));
293 regmap_update_bits(afe->regmap, AFE_CM2_CONN0,
294 CM2_AFE_CM2_CONN_CFG6_MASK,
295 CM2_AFE_CM2_CONN_CFG6(TDM_IN_CH5));
296 regmap_update_bits(afe->regmap, AFE_CM2_CONN1,
297 CM2_AFE_CM2_CONN_CFG7_MASK,
298 CM2_AFE_CM2_CONN_CFG7(TDM_IN_CH6));
299 regmap_update_bits(afe->regmap, AFE_CM2_CONN1,
300 CM2_AFE_CM2_CONN_CFG8_MASK,
301 CM2_AFE_CM2_CONN_CFG8(TDM_IN_CH7));
302
303 /* ref data interconnect to CM2 */
304 if (input == MT8365_FROM_GASRC1) {
305 regmap_update_bits(afe->regmap, AFE_CM2_CONN1,
306 CM2_AFE_CM2_CONN_CFG9_MASK,
307 CM2_AFE_CM2_CONN_CFG9(GENERAL1_ASRC_OUT_LCH));
308 regmap_update_bits(afe->regmap, AFE_CM2_CONN1,
309 CM2_AFE_CM2_CONN_CFG10_MASK,
310 CM2_AFE_CM2_CONN_CFG10(GENERAL1_ASRC_OUT_RCH));
311 } else if (input == MT8365_FROM_GASRC2) {
312 regmap_update_bits(afe->regmap, AFE_CM2_CONN1,
313 CM2_AFE_CM2_CONN_CFG9_MASK,
314 CM2_AFE_CM2_CONN_CFG9(GENERAL2_ASRC_OUT_LCH));
315 regmap_update_bits(afe->regmap, AFE_CM2_CONN1,
316 CM2_AFE_CM2_CONN_CFG10_MASK,
317 CM2_AFE_CM2_CONN_CFG10(GENERAL2_ASRC_OUT_RCH));
318 } else if (input == MT8365_FROM_TDM_ASRC) {
319 regmap_update_bits(afe->regmap, AFE_CM2_CONN1,
320 CM2_AFE_CM2_CONN_CFG9_MASK,
321 CM2_AFE_CM2_CONN_CFG9(TDM_OUT_ASRC_CH0));
322 regmap_update_bits(afe->regmap, AFE_CM2_CONN1,
323 CM2_AFE_CM2_CONN_CFG10_MASK,
324 CM2_AFE_CM2_CONN_CFG10(TDM_OUT_ASRC_CH1));
325 regmap_update_bits(afe->regmap, AFE_CM2_CONN1,
326 CM2_AFE_CM2_CONN_CFG11_MASK,
327 CM2_AFE_CM2_CONN_CFG11(TDM_OUT_ASRC_CH2));
328 regmap_update_bits(afe->regmap, AFE_CM2_CONN1,
329 CM2_AFE_CM2_CONN_CFG12_MASK,
330 CM2_AFE_CM2_CONN_CFG12(TDM_OUT_ASRC_CH3));
331 regmap_update_bits(afe->regmap, AFE_CM2_CONN2,
332 CM2_AFE_CM2_CONN_CFG13_MASK,
333 CM2_AFE_CM2_CONN_CFG13(TDM_OUT_ASRC_CH4));
334 regmap_update_bits(afe->regmap, AFE_CM2_CONN2,
335 CM2_AFE_CM2_CONN_CFG14_MASK,
336 CM2_AFE_CM2_CONN_CFG14(TDM_OUT_ASRC_CH5));
337 regmap_update_bits(afe->regmap, AFE_CM2_CONN2,
338 CM2_AFE_CM2_CONN_CFG15_MASK,
339 CM2_AFE_CM2_CONN_CFG15(TDM_OUT_ASRC_CH6));
340 regmap_update_bits(afe->regmap, AFE_CM2_CONN2,
341 CM2_AFE_CM2_CONN_CFG16_MASK,
342 CM2_AFE_CM2_CONN_CFG16(TDM_OUT_ASRC_CH7));
343 } else {
344 dev_err(afe->dev, "%s wrong CM2 input %d\n", __func__, input);
345 return -1;
346 }
347
348 return 0;
349 }
350
mt8365_afe_get_cm_update_cnt(struct mtk_base_afe * afe,enum mt8365_cm_num cmNum,unsigned int rate,unsigned int channel)351 static int mt8365_afe_get_cm_update_cnt(struct mtk_base_afe *afe,
352 enum mt8365_cm_num cmNum,
353 unsigned int rate, unsigned int channel)
354 {
355 unsigned int total_cnt, div_cnt, ch_pair, best_cnt;
356 unsigned int ch_update_cnt[MT8365_CM_UPDATA_CNT_SET];
357 int i;
358
359 /* calculate cm update cnt
360 * total_cnt = clk / fs, clk is 26m or 24m or 22m
361 * div_cnt = total_cnt / ch_pair, max ch 16ch ,2ch is a set
362 * best_cnt < div_cnt ,we set best_cnt = div_cnt -10
363 * ch01 = best_cnt, ch23 = 2* ch01_up_cnt
364 * ch45 = 3* ch01_up_cnt ...ch1415 = 8* ch01_up_cnt
365 */
366
367 if (cmNum == MT8365_CM1) {
368 total_cnt = MT8365_CLK_26M / rate;
369 } else if (cmNum == MT8365_CM2) {
370 if (mt8365_afe_clk_group_48k(rate))
371 total_cnt = MT8365_CLK_24M / rate;
372 else
373 total_cnt = MT8365_CLK_22M / rate;
374 } else {
375 return -1;
376 }
377
378 if (channel % 2)
379 ch_pair = (channel / 2) + 1;
380 else
381 ch_pair = channel / 2;
382
383 div_cnt = total_cnt / ch_pair;
384 best_cnt = div_cnt - 10;
385
386 if (best_cnt <= 0)
387 return -1;
388
389 for (i = 0; i < ch_pair; i++)
390 ch_update_cnt[i] = (i + 1) * best_cnt;
391
392 switch (channel) {
393 case 16:
394 fallthrough;
395 case 15:
396 regmap_update_bits(afe->regmap, cm_ctrl_reg[cmNum].con4,
397 CM_AFE_CM_UPDATE_CNT2_MASK,
398 CM_AFE_CM_UPDATE_CNT2(ch_update_cnt[7]));
399 fallthrough;
400 case 14:
401 fallthrough;
402 case 13:
403 regmap_update_bits(afe->regmap, cm_ctrl_reg[cmNum].con4,
404 CM_AFE_CM_UPDATE_CNT1_MASK,
405 CM_AFE_CM_UPDATE_CNT1(ch_update_cnt[6]));
406 fallthrough;
407 case 12:
408 fallthrough;
409 case 11:
410 regmap_update_bits(afe->regmap, cm_ctrl_reg[cmNum].con3,
411 CM_AFE_CM_UPDATE_CNT2_MASK,
412 CM_AFE_CM_UPDATE_CNT2(ch_update_cnt[5]));
413 fallthrough;
414 case 10:
415 fallthrough;
416 case 9:
417 regmap_update_bits(afe->regmap, cm_ctrl_reg[cmNum].con3,
418 CM_AFE_CM_UPDATE_CNT1_MASK,
419 CM_AFE_CM_UPDATE_CNT1(ch_update_cnt[4]));
420 fallthrough;
421 case 8:
422 fallthrough;
423 case 7:
424 regmap_update_bits(afe->regmap, cm_ctrl_reg[cmNum].con2,
425 CM_AFE_CM_UPDATE_CNT2_MASK,
426 CM_AFE_CM_UPDATE_CNT2(ch_update_cnt[3]));
427 fallthrough;
428 case 6:
429 fallthrough;
430 case 5:
431 regmap_update_bits(afe->regmap, cm_ctrl_reg[cmNum].con2,
432 CM_AFE_CM_UPDATE_CNT1_MASK,
433 CM_AFE_CM_UPDATE_CNT1(ch_update_cnt[2]));
434 fallthrough;
435 case 4:
436 fallthrough;
437 case 3:
438 regmap_update_bits(afe->regmap, cm_ctrl_reg[cmNum].con1,
439 CM_AFE_CM_UPDATE_CNT2_MASK,
440 CM_AFE_CM_UPDATE_CNT2(ch_update_cnt[1]));
441 fallthrough;
442 case 2:
443 fallthrough;
444 case 1:
445 regmap_update_bits(afe->regmap, cm_ctrl_reg[cmNum].con1,
446 CM_AFE_CM_UPDATE_CNT1_MASK,
447 CM_AFE_CM_UPDATE_CNT1(ch_update_cnt[0]));
448 break;
449 default:
450 return -1;
451 }
452
453 return 0;
454 }
455
mt8365_afe_configure_cm(struct mtk_base_afe * afe,enum mt8365_cm_num cmNum,unsigned int channels,unsigned int rate)456 static int mt8365_afe_configure_cm(struct mtk_base_afe *afe,
457 enum mt8365_cm_num cmNum,
458 unsigned int channels,
459 unsigned int rate)
460 {
461 unsigned int val, mask;
462 unsigned int fs = mt8365_afe_fs_timing(rate);
463
464 val = FIELD_PREP(CM_AFE_CM_CH_NUM_MASK, (channels - 1)) |
465 FIELD_PREP(CM_AFE_CM_START_DATA_MASK, 0);
466
467 mask = CM_AFE_CM_CH_NUM_MASK |
468 CM_AFE_CM_START_DATA_MASK;
469
470 if (cmNum == MT8365_CM1) {
471 val |= FIELD_PREP(CM_AFE_CM1_IN_MODE_MASK, fs);
472
473 mask |= CM_AFE_CM1_VUL_SEL |
474 CM_AFE_CM1_IN_MODE_MASK;
475 } else if (cmNum == MT8365_CM2) {
476 if (mt8365_afe_clk_group_48k(rate))
477 val |= FIELD_PREP(CM_AFE_CM2_CLK_SEL, 0);
478 else
479 val |= FIELD_PREP(CM_AFE_CM2_CLK_SEL, 1);
480
481 val |= FIELD_PREP(CM_AFE_CM2_TDM_SEL, 1);
482
483 mask |= CM_AFE_CM2_TDM_SEL |
484 CM_AFE_CM1_IN_MODE_MASK |
485 CM_AFE_CM2_CLK_SEL;
486
487 mt8365_afe_cm2_mux_conn(afe);
488 } else {
489 return -1;
490 }
491
492 regmap_update_bits(afe->regmap, cm_ctrl_reg[cmNum].con0, mask, val);
493
494 mt8365_afe_get_cm_update_cnt(afe, cmNum, rate, channels);
495
496 return 0;
497 }
498
mt8365_afe_fe_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)499 static int mt8365_afe_fe_startup(struct snd_pcm_substream *substream,
500 struct snd_soc_dai *dai)
501 {
502 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
503 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
504 struct snd_pcm_runtime *runtime = substream->runtime;
505 int memif_num = snd_soc_rtd_to_cpu(rtd, 0)->id;
506 struct mtk_base_afe_memif *memif = &afe->memif[memif_num];
507 int ret;
508
509 memif->substream = substream;
510
511 snd_pcm_hw_constraint_step(substream->runtime, 0,
512 SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 16);
513
514 snd_soc_set_runtime_hwparams(substream, afe->mtk_afe_hardware);
515
516 ret = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
517 if (ret < 0)
518 dev_err(afe->dev, "snd_pcm_hw_constraint_integer failed\n");
519
520 mt8365_afe_enable_main_clk(afe);
521 return ret;
522 }
523
mt8365_afe_fe_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)524 static void mt8365_afe_fe_shutdown(struct snd_pcm_substream *substream,
525 struct snd_soc_dai *dai)
526 {
527 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
528 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
529 int memif_num = snd_soc_rtd_to_cpu(rtd, 0)->id;
530 struct mtk_base_afe_memif *memif = &afe->memif[memif_num];
531
532 memif->substream = NULL;
533
534 mt8365_afe_disable_main_clk(afe);
535 }
536
mt8365_afe_fe_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)537 static int mt8365_afe_fe_hw_params(struct snd_pcm_substream *substream,
538 struct snd_pcm_hw_params *params,
539 struct snd_soc_dai *dai)
540 {
541 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
542 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
543 struct mt8365_afe_private *afe_priv = afe->platform_priv;
544 struct mt8365_control_data *ctrl_data = &afe_priv->ctrl_data;
545 int dai_id = snd_soc_rtd_to_cpu(rtd, 0)->id;
546 struct mtk_base_afe_memif *memif = &afe->memif[dai_id];
547 struct mt8365_fe_dai_data *fe_data = &afe_priv->fe_data[dai_id];
548 size_t request_size = params_buffer_bytes(params);
549 unsigned int channels = params_channels(params);
550 unsigned int rate = params_rate(params);
551 unsigned int base_end_offset = 8;
552 int ret, fs;
553
554 dev_info(afe->dev, "%s %s period = %d rate = %d channels = %d\n",
555 __func__, memif->data->name, params_period_size(params),
556 rate, channels);
557
558 if (dai_id == MT8365_AFE_MEMIF_VUL2) {
559 if (!ctrl_data->bypass_cm1)
560 /* configure cm1 */
561 mt8365_afe_configure_cm(afe, MT8365_CM1,
562 channels, rate);
563 else
564 regmap_update_bits(afe->regmap, AFE_CM1_CON0,
565 CM_AFE_CM1_VUL_SEL,
566 CM_AFE_CM1_VUL_SEL);
567 } else if (dai_id == MT8365_AFE_MEMIF_TDM_IN) {
568 if (!ctrl_data->bypass_cm2)
569 /* configure cm2 */
570 mt8365_afe_configure_cm(afe, MT8365_CM2,
571 channels, rate);
572 else
573 regmap_update_bits(afe->regmap, AFE_CM2_CON0,
574 CM_AFE_CM2_TDM_SEL,
575 ~CM_AFE_CM2_TDM_SEL);
576
577 base_end_offset = 4;
578 }
579
580 if (request_size > fe_data->sram_size) {
581 ret = snd_pcm_lib_malloc_pages(substream, request_size);
582 if (ret < 0) {
583 dev_err(afe->dev,
584 "%s %s malloc pages %zu bytes failed %d\n",
585 __func__, memif->data->name, request_size, ret);
586 return ret;
587 }
588
589 fe_data->use_sram = false;
590
591 mt8365_afe_emi_clk_on(afe);
592 } else {
593 struct snd_dma_buffer *dma_buf = &substream->dma_buffer;
594
595 dma_buf->dev.type = SNDRV_DMA_TYPE_DEV;
596 dma_buf->dev.dev = substream->pcm->card->dev;
597 dma_buf->area = (unsigned char *)fe_data->sram_vir_addr;
598 dma_buf->addr = fe_data->sram_phy_addr;
599 dma_buf->bytes = request_size;
600 snd_pcm_set_runtime_buffer(substream, dma_buf);
601
602 fe_data->use_sram = true;
603 }
604
605 memif->phys_buf_addr = lower_32_bits(substream->runtime->dma_addr);
606 memif->buffer_size = substream->runtime->dma_bytes;
607
608 /* start */
609 regmap_write(afe->regmap, memif->data->reg_ofs_base,
610 memif->phys_buf_addr);
611 /* end */
612 regmap_write(afe->regmap,
613 memif->data->reg_ofs_base + base_end_offset,
614 memif->phys_buf_addr + memif->buffer_size - 1);
615
616 /* set channel */
617 if (memif->data->mono_shift >= 0) {
618 unsigned int mono = (params_channels(params) == 1) ? 1 : 0;
619
620 if (memif->data->mono_reg < 0)
621 dev_info(afe->dev, "%s mono_reg is NULL\n", __func__);
622 else
623 regmap_update_bits(afe->regmap, memif->data->mono_reg,
624 1 << memif->data->mono_shift,
625 mono << memif->data->mono_shift);
626 }
627
628 /* set rate */
629 if (memif->data->fs_shift < 0)
630 return 0;
631
632 fs = afe->memif_fs(substream, params_rate(params));
633
634 if (fs < 0)
635 return -EINVAL;
636
637 if (memif->data->fs_reg < 0)
638 dev_info(afe->dev, "%s fs_reg is NULL\n", __func__);
639 else
640 regmap_update_bits(afe->regmap, memif->data->fs_reg,
641 memif->data->fs_maskbit << memif->data->fs_shift,
642 fs << memif->data->fs_shift);
643
644 return 0;
645 }
646
mt8365_afe_fe_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)647 static int mt8365_afe_fe_hw_free(struct snd_pcm_substream *substream,
648 struct snd_soc_dai *dai)
649 {
650 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
651 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
652 struct mt8365_afe_private *afe_priv = afe->platform_priv;
653 int dai_id = snd_soc_rtd_to_cpu(rtd, 0)->id;
654 struct mt8365_fe_dai_data *fe_data = &afe_priv->fe_data[dai_id];
655 int ret = 0;
656
657 if (fe_data->use_sram) {
658 snd_pcm_set_runtime_buffer(substream, NULL);
659 } else {
660 ret = snd_pcm_lib_free_pages(substream);
661
662 mt8365_afe_emi_clk_off(afe);
663 }
664
665 return ret;
666 }
667
mt8365_afe_fe_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)668 static int mt8365_afe_fe_prepare(struct snd_pcm_substream *substream,
669 struct snd_soc_dai *dai)
670 {
671 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
672 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
673 int dai_id = snd_soc_rtd_to_cpu(rtd, 0)->id;
674 struct mtk_base_afe_memif *memif = &afe->memif[dai_id];
675
676 /* set format */
677 if (memif->data->hd_reg >= 0) {
678 switch (substream->runtime->format) {
679 case SNDRV_PCM_FORMAT_S16_LE:
680 regmap_update_bits(afe->regmap, memif->data->hd_reg,
681 3 << memif->data->hd_shift,
682 0 << memif->data->hd_shift);
683 break;
684 case SNDRV_PCM_FORMAT_S32_LE:
685 regmap_update_bits(afe->regmap, memif->data->hd_reg,
686 3 << memif->data->hd_shift,
687 3 << memif->data->hd_shift);
688
689 if (dai_id == MT8365_AFE_MEMIF_TDM_IN) {
690 regmap_update_bits(afe->regmap,
691 memif->data->hd_reg,
692 3 << memif->data->hd_shift,
693 1 << memif->data->hd_shift);
694 regmap_update_bits(afe->regmap,
695 memif->data->hd_reg,
696 1 << memif->data->hd_align_mshift,
697 1 << memif->data->hd_align_mshift);
698 }
699 break;
700 case SNDRV_PCM_FORMAT_S24_LE:
701 regmap_update_bits(afe->regmap, memif->data->hd_reg,
702 3 << memif->data->hd_shift,
703 1 << memif->data->hd_shift);
704 break;
705 default:
706 return -EINVAL;
707 }
708 }
709
710 mt8365_afe_irq_direction_enable(afe, memif->irq_usage,
711 MT8365_AFE_IRQ_DIR_MCU);
712
713 return 0;
714 }
715
mt8365_afe_fe_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)716 static int mt8365_afe_fe_trigger(struct snd_pcm_substream *substream, int cmd,
717 struct snd_soc_dai *dai)
718 {
719 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
720 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
721 struct mt8365_afe_private *afe_priv = afe->platform_priv;
722 int dai_id = snd_soc_rtd_to_cpu(rtd, 0)->id;
723 struct mt8365_control_data *ctrl_data = &afe_priv->ctrl_data;
724
725 switch (cmd) {
726 case SNDRV_PCM_TRIGGER_START:
727 case SNDRV_PCM_TRIGGER_RESUME:
728 /* enable channel merge */
729 if (dai_id == MT8365_AFE_MEMIF_VUL2 &&
730 !ctrl_data->bypass_cm1) {
731 regmap_update_bits(afe->regmap, AFE_CM1_CON0,
732 CM_AFE_CM_ON, CM_AFE_CM_ON);
733 } else if (dai_id == MT8365_AFE_MEMIF_TDM_IN &&
734 !ctrl_data->bypass_cm2) {
735 regmap_update_bits(afe->regmap, AFE_CM2_CON0,
736 CM_AFE_CM_ON, CM_AFE_CM_ON);
737 }
738 break;
739 case SNDRV_PCM_TRIGGER_STOP:
740 case SNDRV_PCM_TRIGGER_SUSPEND:
741 /* disable channel merge */
742 if (dai_id == MT8365_AFE_MEMIF_VUL2 &&
743 !ctrl_data->bypass_cm1) {
744 regmap_update_bits(afe->regmap, AFE_CM1_CON0,
745 CM_AFE_CM_ON, ~CM_AFE_CM_ON);
746 } else if (dai_id == MT8365_AFE_MEMIF_TDM_IN &&
747 !ctrl_data->bypass_cm2) {
748 regmap_update_bits(afe->regmap, AFE_CM2_CON0,
749 CM_AFE_CM_ON, ~CM_AFE_CM_ON);
750 }
751 break;
752 default:
753 break;
754 }
755
756 return mtk_afe_fe_trigger(substream, cmd, dai);
757 }
758
mt8365_afe_hw_gain1_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)759 static int mt8365_afe_hw_gain1_startup(struct snd_pcm_substream *substream,
760 struct snd_soc_dai *dai)
761 {
762 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
763
764 mt8365_afe_enable_main_clk(afe);
765 return 0;
766 }
767
mt8365_afe_hw_gain1_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)768 static void mt8365_afe_hw_gain1_shutdown(struct snd_pcm_substream *substream,
769 struct snd_soc_dai *dai)
770 {
771 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
772 struct mt8365_afe_private *afe_priv = afe->platform_priv;
773 struct mt8365_be_dai_data *be =
774 &afe_priv->be_data[dai->id - MT8365_AFE_BACKEND_BASE];
775
776 if (be->prepared[substream->stream]) {
777 regmap_update_bits(afe->regmap, AFE_GAIN1_CON0,
778 AFE_GAIN1_CON0_EN_MASK, 0);
779 be->prepared[substream->stream] = false;
780 }
781 mt8365_afe_disable_main_clk(afe);
782 }
783
mt8365_afe_hw_gain1_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)784 static int mt8365_afe_hw_gain1_prepare(struct snd_pcm_substream *substream,
785 struct snd_soc_dai *dai)
786 {
787 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
788 struct mt8365_afe_private *afe_priv = afe->platform_priv;
789 struct mt8365_be_dai_data *be =
790 &afe_priv->be_data[dai->id - MT8365_AFE_BACKEND_BASE];
791
792 int fs;
793 unsigned int val1 = 0, val2 = 0;
794
795 if (be->prepared[substream->stream]) {
796 dev_info(afe->dev, "%s prepared already\n", __func__);
797 return 0;
798 }
799
800 fs = mt8365_afe_fs_timing(substream->runtime->rate);
801 regmap_update_bits(afe->regmap, AFE_GAIN1_CON0,
802 AFE_GAIN1_CON0_MODE_MASK, (unsigned int)fs << 4);
803
804 regmap_read(afe->regmap, AFE_GAIN1_CON1, &val1);
805 regmap_read(afe->regmap, AFE_GAIN1_CUR, &val2);
806 if ((val1 & AFE_GAIN1_CON1_MASK) != (val2 & AFE_GAIN1_CUR_MASK))
807 regmap_update_bits(afe->regmap, AFE_GAIN1_CUR,
808 AFE_GAIN1_CUR_MASK, val1);
809
810 regmap_update_bits(afe->regmap, AFE_GAIN1_CON0,
811 AFE_GAIN1_CON0_EN_MASK, 1);
812 be->prepared[substream->stream] = true;
813
814 return 0;
815 }
816
817 static const struct snd_pcm_hardware mt8365_hostless_hardware = {
818 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
819 SNDRV_PCM_INFO_MMAP_VALID),
820 .period_bytes_min = 256,
821 .period_bytes_max = 4 * 48 * 1024,
822 .periods_min = 2,
823 .periods_max = 256,
824 .buffer_bytes_max = 8 * 48 * 1024,
825 .fifo_size = 0,
826 };
827
828 /* dai ops */
mtk_dai_hostless_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)829 static int mtk_dai_hostless_startup(struct snd_pcm_substream *substream,
830 struct snd_soc_dai *dai)
831 {
832 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
833 struct snd_pcm_runtime *runtime = substream->runtime;
834 int ret;
835
836 snd_soc_set_runtime_hwparams(substream, &mt8365_hostless_hardware);
837
838 ret = snd_pcm_hw_constraint_integer(runtime,
839 SNDRV_PCM_HW_PARAM_PERIODS);
840 if (ret < 0)
841 dev_err(afe->dev, "snd_pcm_hw_constraint_integer failed\n");
842 return ret;
843 }
844
845 /* FE DAIs */
846 static const struct snd_soc_dai_ops mt8365_afe_fe_dai_ops = {
847 .startup = mt8365_afe_fe_startup,
848 .shutdown = mt8365_afe_fe_shutdown,
849 .hw_params = mt8365_afe_fe_hw_params,
850 .hw_free = mt8365_afe_fe_hw_free,
851 .prepare = mt8365_afe_fe_prepare,
852 .trigger = mt8365_afe_fe_trigger,
853 };
854
855 static const struct snd_soc_dai_ops mt8365_dai_hostless_ops = {
856 .startup = mtk_dai_hostless_startup,
857 };
858
859 static const struct snd_soc_dai_ops mt8365_afe_hw_gain1_ops = {
860 .startup = mt8365_afe_hw_gain1_startup,
861 .shutdown = mt8365_afe_hw_gain1_shutdown,
862 .prepare = mt8365_afe_hw_gain1_prepare,
863 };
864
865 static struct snd_soc_dai_driver mt8365_memif_dai_driver[] = {
866 /* FE DAIs: memory intefaces to CPU */
867 {
868 .name = "DL1",
869 .id = MT8365_AFE_MEMIF_DL1,
870 .playback = {
871 .stream_name = "DL1",
872 .channels_min = 1,
873 .channels_max = 2,
874 .rates = SNDRV_PCM_RATE_8000_192000,
875 .formats = SNDRV_PCM_FMTBIT_S16_LE |
876 SNDRV_PCM_FMTBIT_S32_LE,
877 },
878 .ops = &mt8365_afe_fe_dai_ops,
879 }, {
880 .name = "DL2",
881 .id = MT8365_AFE_MEMIF_DL2,
882 .playback = {
883 .stream_name = "DL2",
884 .channels_min = 1,
885 .channels_max = 2,
886 .rates = SNDRV_PCM_RATE_8000_192000,
887 .formats = SNDRV_PCM_FMTBIT_S16_LE |
888 SNDRV_PCM_FMTBIT_S32_LE,
889 },
890 .ops = &mt8365_afe_fe_dai_ops,
891 }, {
892 .name = "TDM_OUT",
893 .id = MT8365_AFE_MEMIF_TDM_OUT,
894 .playback = {
895 .stream_name = "TDM_OUT",
896 .channels_min = 1,
897 .channels_max = 8,
898 .rates = SNDRV_PCM_RATE_8000_192000,
899 .formats = SNDRV_PCM_FMTBIT_S16_LE |
900 SNDRV_PCM_FMTBIT_S32_LE,
901 },
902 .ops = &mt8365_afe_fe_dai_ops,
903 }, {
904 .name = "AWB",
905 .id = MT8365_AFE_MEMIF_AWB,
906 .capture = {
907 .stream_name = "AWB",
908 .channels_min = 1,
909 .channels_max = 2,
910 .rates = SNDRV_PCM_RATE_8000_192000,
911 .formats = SNDRV_PCM_FMTBIT_S16_LE |
912 SNDRV_PCM_FMTBIT_S32_LE,
913 },
914 .ops = &mt8365_afe_fe_dai_ops,
915 }, {
916 .name = "VUL",
917 .id = MT8365_AFE_MEMIF_VUL,
918 .capture = {
919 .stream_name = "VUL",
920 .channels_min = 1,
921 .channels_max = 2,
922 .rates = SNDRV_PCM_RATE_8000_192000,
923 .formats = SNDRV_PCM_FMTBIT_S16_LE |
924 SNDRV_PCM_FMTBIT_S32_LE,
925 },
926 .ops = &mt8365_afe_fe_dai_ops,
927 }, {
928 .name = "VUL2",
929 .id = MT8365_AFE_MEMIF_VUL2,
930 .capture = {
931 .stream_name = "VUL2",
932 .channels_min = 1,
933 .channels_max = 16,
934 .rates = SNDRV_PCM_RATE_8000_192000,
935 .formats = SNDRV_PCM_FMTBIT_S16_LE |
936 SNDRV_PCM_FMTBIT_S32_LE,
937 },
938 .ops = &mt8365_afe_fe_dai_ops,
939 }, {
940 .name = "VUL3",
941 .id = MT8365_AFE_MEMIF_VUL3,
942 .capture = {
943 .stream_name = "VUL3",
944 .channels_min = 1,
945 .channels_max = 2,
946 .rates = SNDRV_PCM_RATE_8000_192000,
947 .formats = SNDRV_PCM_FMTBIT_S16_LE |
948 SNDRV_PCM_FMTBIT_S32_LE,
949 },
950 .ops = &mt8365_afe_fe_dai_ops,
951 }, {
952 .name = "TDM_IN",
953 .id = MT8365_AFE_MEMIF_TDM_IN,
954 .capture = {
955 .stream_name = "TDM_IN",
956 .channels_min = 1,
957 .channels_max = 16,
958 .rates = SNDRV_PCM_RATE_8000_192000,
959 .formats = SNDRV_PCM_FMTBIT_S16_LE |
960 SNDRV_PCM_FMTBIT_S32_LE,
961 },
962 .ops = &mt8365_afe_fe_dai_ops,
963 }, {
964 .name = "Hostless FM DAI",
965 .id = MT8365_AFE_IO_VIRTUAL_FM,
966 .playback = {
967 .stream_name = "Hostless FM DL",
968 .channels_min = 1,
969 .channels_max = 2,
970 .rates = SNDRV_PCM_RATE_8000_192000,
971 .formats = SNDRV_PCM_FMTBIT_S16_LE |
972 SNDRV_PCM_FMTBIT_S24_LE |
973 SNDRV_PCM_FMTBIT_S32_LE,
974 },
975 .capture = {
976 .stream_name = "Hostless FM UL",
977 .channels_min = 1,
978 .channels_max = 2,
979 .rates = SNDRV_PCM_RATE_8000_192000,
980 .formats = SNDRV_PCM_FMTBIT_S16_LE |
981 SNDRV_PCM_FMTBIT_S24_LE |
982 SNDRV_PCM_FMTBIT_S32_LE,
983 },
984 .ops = &mt8365_dai_hostless_ops,
985 }, {
986 .name = "HW_GAIN1",
987 .id = MT8365_AFE_IO_HW_GAIN1,
988 .playback = {
989 .stream_name = "HW Gain 1 In",
990 .channels_min = 1,
991 .channels_max = 2,
992 .rates = SNDRV_PCM_RATE_8000_192000,
993 .formats = SNDRV_PCM_FMTBIT_S16_LE |
994 SNDRV_PCM_FMTBIT_S24_LE |
995 SNDRV_PCM_FMTBIT_S32_LE,
996 },
997 .capture = {
998 .stream_name = "HW Gain 1 Out",
999 .channels_min = 1,
1000 .channels_max = 2,
1001 .rates = SNDRV_PCM_RATE_8000_192000,
1002 .formats = SNDRV_PCM_FMTBIT_S16_LE |
1003 SNDRV_PCM_FMTBIT_S24_LE |
1004 SNDRV_PCM_FMTBIT_S32_LE,
1005 },
1006 .ops = &mt8365_afe_hw_gain1_ops,
1007 .symmetric_rate = 1,
1008 .symmetric_channels = 1,
1009 .symmetric_sample_bits = 1,
1010 },
1011 };
1012
1013 static const struct snd_kcontrol_new mt8365_afe_o00_mix[] = {
1014 SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN0, 5, 1, 0),
1015 SOC_DAPM_SINGLE_AUTODISABLE("I07 Switch", AFE_CONN0, 7, 1, 0),
1016 };
1017
1018 static const struct snd_kcontrol_new mt8365_afe_o01_mix[] = {
1019 SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN1, 6, 1, 0),
1020 SOC_DAPM_SINGLE_AUTODISABLE("I08 Switch", AFE_CONN1, 8, 1, 0),
1021 };
1022
1023 static const struct snd_kcontrol_new mt8365_afe_o03_mix[] = {
1024 SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN3, 5, 1, 0),
1025 SOC_DAPM_SINGLE_AUTODISABLE("I07 Switch", AFE_CONN3, 7, 1, 0),
1026 SOC_DAPM_SINGLE_AUTODISABLE("I00 Switch", AFE_CONN3, 0, 1, 0),
1027 SOC_DAPM_SINGLE_AUTODISABLE("I10 Switch", AFE_CONN3, 10, 1, 0),
1028 };
1029
1030 static const struct snd_kcontrol_new mt8365_afe_o04_mix[] = {
1031 SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN4, 6, 1, 0),
1032 SOC_DAPM_SINGLE_AUTODISABLE("I08 Switch", AFE_CONN4, 8, 1, 0),
1033 SOC_DAPM_SINGLE_AUTODISABLE("I01 Switch", AFE_CONN4, 1, 1, 0),
1034 SOC_DAPM_SINGLE_AUTODISABLE("I11 Switch", AFE_CONN4, 11, 1, 0),
1035 };
1036
1037 static const struct snd_kcontrol_new mt8365_afe_o05_mix[] = {
1038 SOC_DAPM_SINGLE_AUTODISABLE("I00 Switch", AFE_CONN5, 0, 1, 0),
1039 SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN5, 3, 1, 0),
1040 SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN5, 5, 1, 0),
1041 SOC_DAPM_SINGLE_AUTODISABLE("I07 Switch", AFE_CONN5, 7, 1, 0),
1042 SOC_DAPM_SINGLE_AUTODISABLE("I09 Switch", AFE_CONN5, 9, 1, 0),
1043 SOC_DAPM_SINGLE_AUTODISABLE("I14 Switch", AFE_CONN5, 14, 1, 0),
1044 SOC_DAPM_SINGLE_AUTODISABLE("I16 Switch", AFE_CONN5, 16, 1, 0),
1045 SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN5, 18, 1, 0),
1046 SOC_DAPM_SINGLE_AUTODISABLE("I20 Switch", AFE_CONN5, 20, 1, 0),
1047 SOC_DAPM_SINGLE_AUTODISABLE("I23 Switch", AFE_CONN5, 23, 1, 0),
1048 SOC_DAPM_SINGLE_AUTODISABLE("I10L Switch", AFE_CONN5, 10, 1, 0),
1049 };
1050
1051 static const struct snd_kcontrol_new mt8365_afe_o06_mix[] = {
1052 SOC_DAPM_SINGLE_AUTODISABLE("I01 Switch", AFE_CONN6, 1, 1, 0),
1053 SOC_DAPM_SINGLE_AUTODISABLE("I04 Switch", AFE_CONN6, 4, 1, 0),
1054 SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN6, 6, 1, 0),
1055 SOC_DAPM_SINGLE_AUTODISABLE("I08 Switch", AFE_CONN6, 8, 1, 0),
1056 SOC_DAPM_SINGLE_AUTODISABLE("I22 Switch", AFE_CONN6, 22, 1, 0),
1057 SOC_DAPM_SINGLE_AUTODISABLE("I15 Switch", AFE_CONN6, 15, 1, 0),
1058 SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN6, 17, 1, 0),
1059 SOC_DAPM_SINGLE_AUTODISABLE("I19 Switch", AFE_CONN6, 19, 1, 0),
1060 SOC_DAPM_SINGLE_AUTODISABLE("I21 Switch", AFE_CONN6, 21, 1, 0),
1061 SOC_DAPM_SINGLE_AUTODISABLE("I24 Switch", AFE_CONN6, 24, 1, 0),
1062 SOC_DAPM_SINGLE_AUTODISABLE("I11L Switch", AFE_CONN6, 11, 1, 0),
1063 };
1064
1065 static const struct snd_kcontrol_new mt8365_afe_o07_mix[] = {
1066 SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN7, 5, 1, 0),
1067 SOC_DAPM_SINGLE_AUTODISABLE("I07 Switch", AFE_CONN7, 7, 1, 0),
1068 };
1069
1070 static const struct snd_kcontrol_new mt8365_afe_o08_mix[] = {
1071 SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN8, 6, 1, 0),
1072 SOC_DAPM_SINGLE_AUTODISABLE("I08 Switch", AFE_CONN8, 8, 1, 0),
1073 };
1074
1075 static const struct snd_kcontrol_new mt8365_afe_o09_mix[] = {
1076 SOC_DAPM_SINGLE_AUTODISABLE("I00 Switch", AFE_CONN9, 0, 1, 0),
1077 SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN9, 3, 1, 0),
1078 SOC_DAPM_SINGLE_AUTODISABLE("I09 Switch", AFE_CONN9, 9, 1, 0),
1079 SOC_DAPM_SINGLE_AUTODISABLE("I14 Switch", AFE_CONN9, 14, 1, 0),
1080 SOC_DAPM_SINGLE_AUTODISABLE("I16 Switch", AFE_CONN9, 16, 1, 0),
1081 SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN9, 18, 1, 0),
1082 SOC_DAPM_SINGLE_AUTODISABLE("I20 Switch", AFE_CONN9, 20, 1, 0),
1083 };
1084
1085 static const struct snd_kcontrol_new mt8365_afe_o10_mix[] = {
1086 SOC_DAPM_SINGLE_AUTODISABLE("I01 Switch", AFE_CONN10, 1, 1, 0),
1087 SOC_DAPM_SINGLE_AUTODISABLE("I04 Switch", AFE_CONN10, 4, 1, 0),
1088 SOC_DAPM_SINGLE_AUTODISABLE("I22 Switch", AFE_CONN10, 22, 1, 0),
1089 SOC_DAPM_SINGLE_AUTODISABLE("I15 Switch", AFE_CONN10, 15, 1, 0),
1090 SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN10, 17, 1, 0),
1091 SOC_DAPM_SINGLE_AUTODISABLE("I19 Switch", AFE_CONN10, 19, 1, 0),
1092 SOC_DAPM_SINGLE_AUTODISABLE("I21 Switch", AFE_CONN10, 21, 1, 0),
1093 };
1094
1095 static const struct snd_kcontrol_new mt8365_afe_o11_mix[] = {
1096 SOC_DAPM_SINGLE_AUTODISABLE("I00 Switch", AFE_CONN11, 0, 1, 0),
1097 SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN11, 3, 1, 0),
1098 SOC_DAPM_SINGLE_AUTODISABLE("I09 Switch", AFE_CONN11, 9, 1, 0),
1099 SOC_DAPM_SINGLE_AUTODISABLE("I14 Switch", AFE_CONN11, 14, 1, 0),
1100 SOC_DAPM_SINGLE_AUTODISABLE("I16 Switch", AFE_CONN11, 16, 1, 0),
1101 SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN11, 18, 1, 0),
1102 SOC_DAPM_SINGLE_AUTODISABLE("I20 Switch", AFE_CONN11, 20, 1, 0),
1103 };
1104
1105 static const struct snd_kcontrol_new mt8365_afe_o12_mix[] = {
1106 SOC_DAPM_SINGLE_AUTODISABLE("I01 Switch", AFE_CONN12, 1, 1, 0),
1107 SOC_DAPM_SINGLE_AUTODISABLE("I04 Switch", AFE_CONN12, 4, 1, 0),
1108 SOC_DAPM_SINGLE_AUTODISABLE("I22 Switch", AFE_CONN12, 22, 1, 0),
1109 SOC_DAPM_SINGLE_AUTODISABLE("I15 Switch", AFE_CONN12, 15, 1, 0),
1110 SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN12, 17, 1, 0),
1111 SOC_DAPM_SINGLE_AUTODISABLE("I19 Switch", AFE_CONN12, 19, 1, 0),
1112 SOC_DAPM_SINGLE_AUTODISABLE("I21 Switch", AFE_CONN12, 21, 1, 0),
1113 };
1114
1115 static const struct snd_kcontrol_new mt8365_afe_o13_mix[] = {
1116 SOC_DAPM_SINGLE_AUTODISABLE("I00 Switch", AFE_CONN13, 0, 1, 0),
1117 };
1118
1119 static const struct snd_kcontrol_new mt8365_afe_o14_mix[] = {
1120 SOC_DAPM_SINGLE_AUTODISABLE("I01 Switch", AFE_CONN14, 1, 1, 0),
1121 };
1122
1123 static const struct snd_kcontrol_new mt8365_afe_o15_mix[] = {
1124 };
1125
1126 static const struct snd_kcontrol_new mt8365_afe_o16_mix[] = {
1127 };
1128
1129 static const struct snd_kcontrol_new mt8365_afe_o17_mix[] = {
1130 SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN17, 3, 1, 0),
1131 SOC_DAPM_SINGLE_AUTODISABLE("I14 Switch", AFE_CONN17, 14, 1, 0),
1132 };
1133
1134 static const struct snd_kcontrol_new mt8365_afe_o18_mix[] = {
1135 SOC_DAPM_SINGLE_AUTODISABLE("I04 Switch", AFE_CONN18, 4, 1, 0),
1136 SOC_DAPM_SINGLE_AUTODISABLE("I15 Switch", AFE_CONN18, 15, 1, 0),
1137 SOC_DAPM_SINGLE_AUTODISABLE("I23 Switch", AFE_CONN18, 23, 1, 0),
1138 SOC_DAPM_SINGLE_AUTODISABLE("I25 Switch", AFE_CONN18, 25, 1, 0),
1139 };
1140
1141 static const struct snd_kcontrol_new mt8365_afe_o19_mix[] = {
1142 SOC_DAPM_SINGLE_AUTODISABLE("I04 Switch", AFE_CONN19, 4, 1, 0),
1143 SOC_DAPM_SINGLE_AUTODISABLE("I16 Switch", AFE_CONN19, 16, 1, 0),
1144 SOC_DAPM_SINGLE_AUTODISABLE("I23 Switch", AFE_CONN19, 23, 1, 0),
1145 SOC_DAPM_SINGLE_AUTODISABLE("I24 Switch", AFE_CONN19, 24, 1, 0),
1146 SOC_DAPM_SINGLE_AUTODISABLE("I25 Switch", AFE_CONN19, 25, 1, 0),
1147 SOC_DAPM_SINGLE_AUTODISABLE("I26 Switch", AFE_CONN19, 26, 1, 0),
1148 };
1149
1150 static const struct snd_kcontrol_new mt8365_afe_o20_mix[] = {
1151 SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN20, 17, 1, 0),
1152 SOC_DAPM_SINGLE_AUTODISABLE("I24 Switch", AFE_CONN20, 24, 1, 0),
1153 SOC_DAPM_SINGLE_AUTODISABLE("I26 Switch", AFE_CONN20, 26, 1, 0),
1154 };
1155
1156 static const struct snd_kcontrol_new mt8365_afe_o21_mix[] = {
1157 SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN21, 18, 1, 0),
1158 SOC_DAPM_SINGLE_AUTODISABLE("I23 Switch", AFE_CONN21, 23, 1, 0),
1159 SOC_DAPM_SINGLE_AUTODISABLE("I25 Switch", AFE_CONN21, 25, 1, 0),
1160 };
1161
1162 static const struct snd_kcontrol_new mt8365_afe_o22_mix[] = {
1163 SOC_DAPM_SINGLE_AUTODISABLE("I19 Switch", AFE_CONN22, 19, 1, 0),
1164 SOC_DAPM_SINGLE_AUTODISABLE("I24 Switch", AFE_CONN22, 24, 1, 0),
1165 SOC_DAPM_SINGLE_AUTODISABLE("I26 Switch", AFE_CONN22, 26, 1, 0),
1166 };
1167
1168 static const struct snd_kcontrol_new mt8365_afe_o23_mix[] = {
1169 SOC_DAPM_SINGLE_AUTODISABLE("I20 Switch", AFE_CONN23, 20, 1, 0),
1170 SOC_DAPM_SINGLE_AUTODISABLE("I23 Switch", AFE_CONN23, 23, 1, 0),
1171 SOC_DAPM_SINGLE_AUTODISABLE("I25 Switch", AFE_CONN23, 25, 1, 0),
1172 };
1173
1174 static const struct snd_kcontrol_new mt8365_afe_o24_mix[] = {
1175 SOC_DAPM_SINGLE_AUTODISABLE("I21 Switch", AFE_CONN24, 21, 1, 0),
1176 SOC_DAPM_SINGLE_AUTODISABLE("I24 Switch", AFE_CONN24, 24, 1, 0),
1177 SOC_DAPM_SINGLE_AUTODISABLE("I26 Switch", AFE_CONN24, 26, 1, 0),
1178 SOC_DAPM_SINGLE_AUTODISABLE("I23 Switch", AFE_CONN24, 23, 1, 0),
1179 SOC_DAPM_SINGLE_AUTODISABLE("I25 Switch", AFE_CONN24, 25, 1, 0),
1180 };
1181
1182 static const struct snd_kcontrol_new mt8365_afe_o25_mix[] = {
1183 SOC_DAPM_SINGLE_AUTODISABLE("I27 Switch", AFE_CONN25, 27, 1, 0),
1184 SOC_DAPM_SINGLE_AUTODISABLE("I23 Switch", AFE_CONN25, 23, 1, 0),
1185 SOC_DAPM_SINGLE_AUTODISABLE("I25 Switch", AFE_CONN25, 25, 1, 0),
1186 };
1187
1188 static const struct snd_kcontrol_new mt8365_afe_o26_mix[] = {
1189 SOC_DAPM_SINGLE_AUTODISABLE("I28 Switch", AFE_CONN26, 28, 1, 0),
1190 SOC_DAPM_SINGLE_AUTODISABLE("I24 Switch", AFE_CONN26, 24, 1, 0),
1191 SOC_DAPM_SINGLE_AUTODISABLE("I26 Switch", AFE_CONN26, 26, 1, 0),
1192 };
1193
1194 static const struct snd_kcontrol_new mt8365_afe_o27_mix[] = {
1195 SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN27, 5, 1, 0),
1196 SOC_DAPM_SINGLE_AUTODISABLE("I07 Switch", AFE_CONN27, 7, 1, 0),
1197 };
1198
1199 static const struct snd_kcontrol_new mt8365_afe_o28_mix[] = {
1200 SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN28, 6, 1, 0),
1201 SOC_DAPM_SINGLE_AUTODISABLE("I08 Switch", AFE_CONN28, 8, 1, 0),
1202 };
1203
1204 static const struct snd_kcontrol_new mt8365_afe_o29_mix[] = {
1205 SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN29, 5, 1, 0),
1206 SOC_DAPM_SINGLE_AUTODISABLE("I07 Switch", AFE_CONN29, 7, 1, 0),
1207 };
1208
1209 static const struct snd_kcontrol_new mt8365_afe_o30_mix[] = {
1210 SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN30, 6, 1, 0),
1211 SOC_DAPM_SINGLE_AUTODISABLE("I08 Switch", AFE_CONN30, 8, 1, 0),
1212 };
1213
1214 static const struct snd_kcontrol_new mt8365_afe_o31_mix[] = {
1215 SOC_DAPM_SINGLE_AUTODISABLE("I29 Switch", AFE_CONN31, 29, 1, 0),
1216 };
1217
1218 static const struct snd_kcontrol_new mt8365_afe_o32_mix[] = {
1219 SOC_DAPM_SINGLE_AUTODISABLE("I30 Switch", AFE_CONN32, 30, 1, 0),
1220 };
1221
1222 static const struct snd_kcontrol_new mt8365_afe_o33_mix[] = {
1223 SOC_DAPM_SINGLE_AUTODISABLE("I31 Switch", AFE_CONN33, 31, 1, 0),
1224 };
1225
1226 static const struct snd_kcontrol_new mt8365_afe_o34_mix[] = {
1227 SOC_DAPM_SINGLE_AUTODISABLE("I32 Switch", AFE_CONN34_1, 0, 1, 0),
1228 };
1229
1230 static const struct snd_kcontrol_new mt8365_afe_o35_mix[] = {
1231 SOC_DAPM_SINGLE_AUTODISABLE("I33 Switch", AFE_CONN35_1, 1, 1, 0),
1232 };
1233
1234 static const struct snd_kcontrol_new mt8365_afe_o36_mix[] = {
1235 SOC_DAPM_SINGLE_AUTODISABLE("I34 Switch", AFE_CONN36_1, 2, 1, 0),
1236 };
1237
1238 static const struct snd_kcontrol_new mtk_hw_gain1_in_ch1_mix[] = {
1239 SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH1 Switch", AFE_CONN13,
1240 0, 1, 0),
1241 };
1242
1243 static const struct snd_kcontrol_new mtk_hw_gain1_in_ch2_mix[] = {
1244 SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH2 Switch", AFE_CONN14,
1245 1, 1, 0),
1246 };
1247
mt8365_afe_cm2_io_input_mux_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1248 static int mt8365_afe_cm2_io_input_mux_get(struct snd_kcontrol *kcontrol,
1249 struct snd_ctl_elem_value *ucontrol)
1250 {
1251 ucontrol->value.integer.value[0] = mCM2Input;
1252
1253 return 0;
1254 }
1255
mt8365_afe_cm2_io_input_mux_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1256 static int mt8365_afe_cm2_io_input_mux_put(struct snd_kcontrol *kcontrol,
1257 struct snd_ctl_elem_value *ucontrol)
1258 {
1259 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kcontrol);
1260 struct snd_soc_component *comp = snd_soc_dapm_to_component(dapm);
1261 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(comp);
1262 struct mt8365_afe_private *afe_priv = afe->platform_priv;
1263 int ret;
1264
1265 mCM2Input = ucontrol->value.enumerated.item[0];
1266
1267 afe_priv->cm2_mux_input = mCM2Input;
1268 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1269
1270 return ret;
1271 }
1272
1273 static const char * const fmhwgain_text[] = {
1274 "OPEN", "FM_HW_GAIN_IO"
1275 };
1276
1277 static const char * const ain_text[] = {
1278 "INT ADC", "EXT ADC",
1279 };
1280
1281 static const char * const vul2_in_input_text[] = {
1282 "VUL2_IN_FROM_O17O18", "VUL2_IN_FROM_CM1",
1283 };
1284
1285 static const char * const mt8365_afe_cm2_mux_text[] = {
1286 "OPEN", "FROM_GASRC1_OUT", "FROM_GASRC2_OUT", "FROM_TDM_ASRC_OUT",
1287 };
1288
1289 static SOC_ENUM_SINGLE_VIRT_DECL(fmhwgain_enum, fmhwgain_text);
1290 static SOC_ENUM_SINGLE_DECL(ain_enum, AFE_ADDA_TOP_CON0, 0, ain_text);
1291 static SOC_ENUM_SINGLE_VIRT_DECL(vul2_in_input_enum, vul2_in_input_text);
1292 static SOC_ENUM_SINGLE_VIRT_DECL(mt8365_afe_cm2_mux_input_enum,
1293 mt8365_afe_cm2_mux_text);
1294
1295 static const struct snd_kcontrol_new fmhwgain_mux =
1296 SOC_DAPM_ENUM("FM HW Gain Source", fmhwgain_enum);
1297
1298 static const struct snd_kcontrol_new ain_mux =
1299 SOC_DAPM_ENUM("AIN Source", ain_enum);
1300
1301 static const struct snd_kcontrol_new vul2_in_input_mux =
1302 SOC_DAPM_ENUM("VUL2 Input", vul2_in_input_enum);
1303
1304 static const struct snd_kcontrol_new mt8365_afe_cm2_mux_input_mux =
1305 SOC_DAPM_ENUM_EXT("CM2_MUX Source", mt8365_afe_cm2_mux_input_enum,
1306 mt8365_afe_cm2_io_input_mux_get,
1307 mt8365_afe_cm2_io_input_mux_put);
1308
1309 static const struct snd_soc_dapm_widget mt8365_memif_widgets[] = {
1310 /* inter-connections */
1311 SND_SOC_DAPM_MIXER("I00", SND_SOC_NOPM, 0, 0, NULL, 0),
1312 SND_SOC_DAPM_MIXER("I01", SND_SOC_NOPM, 0, 0, NULL, 0),
1313 SND_SOC_DAPM_MIXER("I03", SND_SOC_NOPM, 0, 0, NULL, 0),
1314 SND_SOC_DAPM_MIXER("I04", SND_SOC_NOPM, 0, 0, NULL, 0),
1315 SND_SOC_DAPM_MIXER("I05", SND_SOC_NOPM, 0, 0, NULL, 0),
1316 SND_SOC_DAPM_MIXER("I06", SND_SOC_NOPM, 0, 0, NULL, 0),
1317 SND_SOC_DAPM_MIXER("I07", SND_SOC_NOPM, 0, 0, NULL, 0),
1318 SND_SOC_DAPM_MIXER("I08", SND_SOC_NOPM, 0, 0, NULL, 0),
1319 SND_SOC_DAPM_MIXER("I05L", SND_SOC_NOPM, 0, 0, NULL, 0),
1320 SND_SOC_DAPM_MIXER("I06L", SND_SOC_NOPM, 0, 0, NULL, 0),
1321 SND_SOC_DAPM_MIXER("I07L", SND_SOC_NOPM, 0, 0, NULL, 0),
1322 SND_SOC_DAPM_MIXER("I08L", SND_SOC_NOPM, 0, 0, NULL, 0),
1323 SND_SOC_DAPM_MIXER("I09", SND_SOC_NOPM, 0, 0, NULL, 0),
1324 SND_SOC_DAPM_MIXER("I10", SND_SOC_NOPM, 0, 0, NULL, 0),
1325 SND_SOC_DAPM_MIXER("I11", SND_SOC_NOPM, 0, 0, NULL, 0),
1326 SND_SOC_DAPM_MIXER("I10L", SND_SOC_NOPM, 0, 0, NULL, 0),
1327 SND_SOC_DAPM_MIXER("I11L", SND_SOC_NOPM, 0, 0, NULL, 0),
1328 SND_SOC_DAPM_MIXER("I12", SND_SOC_NOPM, 0, 0, NULL, 0),
1329 SND_SOC_DAPM_MIXER("I13", SND_SOC_NOPM, 0, 0, NULL, 0),
1330 SND_SOC_DAPM_MIXER("I14", SND_SOC_NOPM, 0, 0, NULL, 0),
1331 SND_SOC_DAPM_MIXER("I15", SND_SOC_NOPM, 0, 0, NULL, 0),
1332 SND_SOC_DAPM_MIXER("I16", SND_SOC_NOPM, 0, 0, NULL, 0),
1333 SND_SOC_DAPM_MIXER("I17", SND_SOC_NOPM, 0, 0, NULL, 0),
1334 SND_SOC_DAPM_MIXER("I18", SND_SOC_NOPM, 0, 0, NULL, 0),
1335 SND_SOC_DAPM_MIXER("I19", SND_SOC_NOPM, 0, 0, NULL, 0),
1336 SND_SOC_DAPM_MIXER("I20", SND_SOC_NOPM, 0, 0, NULL, 0),
1337 SND_SOC_DAPM_MIXER("I21", SND_SOC_NOPM, 0, 0, NULL, 0),
1338 SND_SOC_DAPM_MIXER("I22", SND_SOC_NOPM, 0, 0, NULL, 0),
1339 SND_SOC_DAPM_MIXER("I23", SND_SOC_NOPM, 0, 0, NULL, 0),
1340 SND_SOC_DAPM_MIXER("I24", SND_SOC_NOPM, 0, 0, NULL, 0),
1341 SND_SOC_DAPM_MIXER("I25", SND_SOC_NOPM, 0, 0, NULL, 0),
1342 SND_SOC_DAPM_MIXER("I26", SND_SOC_NOPM, 0, 0, NULL, 0),
1343 SND_SOC_DAPM_MIXER("I27", SND_SOC_NOPM, 0, 0, NULL, 0),
1344 SND_SOC_DAPM_MIXER("I28", SND_SOC_NOPM, 0, 0, NULL, 0),
1345 SND_SOC_DAPM_MIXER("I29", SND_SOC_NOPM, 0, 0, NULL, 0),
1346 SND_SOC_DAPM_MIXER("I30", SND_SOC_NOPM, 0, 0, NULL, 0),
1347 SND_SOC_DAPM_MIXER("I31", SND_SOC_NOPM, 0, 0, NULL, 0),
1348 SND_SOC_DAPM_MIXER("I32", SND_SOC_NOPM, 0, 0, NULL, 0),
1349 SND_SOC_DAPM_MIXER("I33", SND_SOC_NOPM, 0, 0, NULL, 0),
1350 SND_SOC_DAPM_MIXER("I34", SND_SOC_NOPM, 0, 0, NULL, 0),
1351 SND_SOC_DAPM_MIXER("O00", SND_SOC_NOPM, 0, 0,
1352 mt8365_afe_o00_mix, ARRAY_SIZE(mt8365_afe_o00_mix)),
1353 SND_SOC_DAPM_MIXER("O01", SND_SOC_NOPM, 0, 0,
1354 mt8365_afe_o01_mix, ARRAY_SIZE(mt8365_afe_o01_mix)),
1355 SND_SOC_DAPM_MIXER("O03", SND_SOC_NOPM, 0, 0,
1356 mt8365_afe_o03_mix, ARRAY_SIZE(mt8365_afe_o03_mix)),
1357 SND_SOC_DAPM_MIXER("O04", SND_SOC_NOPM, 0, 0,
1358 mt8365_afe_o04_mix, ARRAY_SIZE(mt8365_afe_o04_mix)),
1359 SND_SOC_DAPM_MIXER("O05", SND_SOC_NOPM, 0, 0,
1360 mt8365_afe_o05_mix, ARRAY_SIZE(mt8365_afe_o05_mix)),
1361 SND_SOC_DAPM_MIXER("O06", SND_SOC_NOPM, 0, 0,
1362 mt8365_afe_o06_mix, ARRAY_SIZE(mt8365_afe_o06_mix)),
1363 SND_SOC_DAPM_MIXER("O07", SND_SOC_NOPM, 0, 0,
1364 mt8365_afe_o07_mix, ARRAY_SIZE(mt8365_afe_o07_mix)),
1365 SND_SOC_DAPM_MIXER("O08", SND_SOC_NOPM, 0, 0,
1366 mt8365_afe_o08_mix, ARRAY_SIZE(mt8365_afe_o08_mix)),
1367 SND_SOC_DAPM_MIXER("O09", SND_SOC_NOPM, 0, 0,
1368 mt8365_afe_o09_mix, ARRAY_SIZE(mt8365_afe_o09_mix)),
1369 SND_SOC_DAPM_MIXER("O10", SND_SOC_NOPM, 0, 0,
1370 mt8365_afe_o10_mix, ARRAY_SIZE(mt8365_afe_o10_mix)),
1371 SND_SOC_DAPM_MIXER("O11", SND_SOC_NOPM, 0, 0,
1372 mt8365_afe_o11_mix, ARRAY_SIZE(mt8365_afe_o11_mix)),
1373 SND_SOC_DAPM_MIXER("O12", SND_SOC_NOPM, 0, 0,
1374 mt8365_afe_o12_mix, ARRAY_SIZE(mt8365_afe_o12_mix)),
1375 SND_SOC_DAPM_MIXER("O13", SND_SOC_NOPM, 0, 0,
1376 mt8365_afe_o13_mix, ARRAY_SIZE(mt8365_afe_o13_mix)),
1377 SND_SOC_DAPM_MIXER("O14", SND_SOC_NOPM, 0, 0,
1378 mt8365_afe_o14_mix, ARRAY_SIZE(mt8365_afe_o14_mix)),
1379 SND_SOC_DAPM_MIXER("O15", SND_SOC_NOPM, 0, 0,
1380 mt8365_afe_o15_mix, ARRAY_SIZE(mt8365_afe_o15_mix)),
1381 SND_SOC_DAPM_MIXER("O16", SND_SOC_NOPM, 0, 0,
1382 mt8365_afe_o16_mix, ARRAY_SIZE(mt8365_afe_o16_mix)),
1383 SND_SOC_DAPM_MIXER("O17", SND_SOC_NOPM, 0, 0,
1384 mt8365_afe_o17_mix, ARRAY_SIZE(mt8365_afe_o17_mix)),
1385 SND_SOC_DAPM_MIXER("O18", SND_SOC_NOPM, 0, 0,
1386 mt8365_afe_o18_mix, ARRAY_SIZE(mt8365_afe_o18_mix)),
1387 SND_SOC_DAPM_MIXER("O19", SND_SOC_NOPM, 0, 0,
1388 mt8365_afe_o19_mix, ARRAY_SIZE(mt8365_afe_o19_mix)),
1389 SND_SOC_DAPM_MIXER("O20", SND_SOC_NOPM, 0, 0,
1390 mt8365_afe_o20_mix, ARRAY_SIZE(mt8365_afe_o20_mix)),
1391 SND_SOC_DAPM_MIXER("O21", SND_SOC_NOPM, 0, 0,
1392 mt8365_afe_o21_mix, ARRAY_SIZE(mt8365_afe_o21_mix)),
1393 SND_SOC_DAPM_MIXER("O22", SND_SOC_NOPM, 0, 0,
1394 mt8365_afe_o22_mix, ARRAY_SIZE(mt8365_afe_o22_mix)),
1395 SND_SOC_DAPM_MIXER("O23", SND_SOC_NOPM, 0, 0,
1396 mt8365_afe_o23_mix, ARRAY_SIZE(mt8365_afe_o23_mix)),
1397 SND_SOC_DAPM_MIXER("O24", SND_SOC_NOPM, 0, 0,
1398 mt8365_afe_o24_mix, ARRAY_SIZE(mt8365_afe_o24_mix)),
1399 SND_SOC_DAPM_MIXER("O25", SND_SOC_NOPM, 0, 0,
1400 mt8365_afe_o25_mix, ARRAY_SIZE(mt8365_afe_o25_mix)),
1401 SND_SOC_DAPM_MIXER("O26", SND_SOC_NOPM, 0, 0,
1402 mt8365_afe_o26_mix, ARRAY_SIZE(mt8365_afe_o26_mix)),
1403 SND_SOC_DAPM_MIXER("O27", SND_SOC_NOPM, 0, 0,
1404 mt8365_afe_o27_mix, ARRAY_SIZE(mt8365_afe_o27_mix)),
1405 SND_SOC_DAPM_MIXER("O28", SND_SOC_NOPM, 0, 0,
1406 mt8365_afe_o28_mix, ARRAY_SIZE(mt8365_afe_o28_mix)),
1407 SND_SOC_DAPM_MIXER("O29", SND_SOC_NOPM, 0, 0,
1408 mt8365_afe_o29_mix, ARRAY_SIZE(mt8365_afe_o29_mix)),
1409 SND_SOC_DAPM_MIXER("O30", SND_SOC_NOPM, 0, 0,
1410 mt8365_afe_o30_mix, ARRAY_SIZE(mt8365_afe_o30_mix)),
1411 SND_SOC_DAPM_MIXER("O31", SND_SOC_NOPM, 0, 0,
1412 mt8365_afe_o31_mix, ARRAY_SIZE(mt8365_afe_o31_mix)),
1413 SND_SOC_DAPM_MIXER("O32", SND_SOC_NOPM, 0, 0,
1414 mt8365_afe_o32_mix, ARRAY_SIZE(mt8365_afe_o32_mix)),
1415 SND_SOC_DAPM_MIXER("O33", SND_SOC_NOPM, 0, 0,
1416 mt8365_afe_o33_mix, ARRAY_SIZE(mt8365_afe_o33_mix)),
1417 SND_SOC_DAPM_MIXER("O34", SND_SOC_NOPM, 0, 0,
1418 mt8365_afe_o34_mix, ARRAY_SIZE(mt8365_afe_o34_mix)),
1419 SND_SOC_DAPM_MIXER("O35", SND_SOC_NOPM, 0, 0,
1420 mt8365_afe_o35_mix, ARRAY_SIZE(mt8365_afe_o35_mix)),
1421 SND_SOC_DAPM_MIXER("O36", SND_SOC_NOPM, 0, 0,
1422 mt8365_afe_o36_mix, ARRAY_SIZE(mt8365_afe_o36_mix)),
1423 SND_SOC_DAPM_MIXER("CM2_Mux IO", SND_SOC_NOPM, 0, 0, NULL, 0),
1424 SND_SOC_DAPM_MIXER("CM1_IO", SND_SOC_NOPM, 0, 0, NULL, 0),
1425 SND_SOC_DAPM_MIXER("O17O18", SND_SOC_NOPM, 0, 0, NULL, 0),
1426 /* inter-connections */
1427 SND_SOC_DAPM_MIXER("HW_GAIN1_IN_CH1", SND_SOC_NOPM, 0, 0,
1428 mtk_hw_gain1_in_ch1_mix,
1429 ARRAY_SIZE(mtk_hw_gain1_in_ch1_mix)),
1430 SND_SOC_DAPM_MIXER("HW_GAIN1_IN_CH2", SND_SOC_NOPM, 0, 0,
1431 mtk_hw_gain1_in_ch2_mix,
1432 ARRAY_SIZE(mtk_hw_gain1_in_ch2_mix)),
1433
1434 SND_SOC_DAPM_INPUT("DL Source"),
1435
1436 SND_SOC_DAPM_MUX("CM2_Mux_IO Input Mux", SND_SOC_NOPM, 0, 0,
1437 &mt8365_afe_cm2_mux_input_mux),
1438
1439 SND_SOC_DAPM_MUX("AIN Mux", SND_SOC_NOPM, 0, 0, &ain_mux),
1440 SND_SOC_DAPM_MUX("VUL2 Input Mux", SND_SOC_NOPM, 0, 0,
1441 &vul2_in_input_mux),
1442
1443 SND_SOC_DAPM_MUX("FM HW Gain Mux", SND_SOC_NOPM, 0, 0, &fmhwgain_mux),
1444
1445 SND_SOC_DAPM_INPUT("HW Gain 1 Out Endpoint"),
1446 SND_SOC_DAPM_OUTPUT("HW Gain 1 In Endpoint"),
1447 };
1448
1449 static const struct snd_soc_dapm_route mt8365_memif_routes[] = {
1450 /* downlink */
1451 {"I00", NULL, "2ND I2S Capture"},
1452 {"I01", NULL, "2ND I2S Capture"},
1453 {"I05", NULL, "DL1"},
1454 {"I06", NULL, "DL1"},
1455 {"I07", NULL, "DL2"},
1456 {"I08", NULL, "DL2"},
1457
1458 {"O03", "I05 Switch", "I05"},
1459 {"O04", "I06 Switch", "I06"},
1460 {"O00", "I05 Switch", "I05"},
1461 {"O01", "I06 Switch", "I06"},
1462 {"O07", "I05 Switch", "I05"},
1463 {"O08", "I06 Switch", "I06"},
1464 {"O27", "I05 Switch", "I05"},
1465 {"O28", "I06 Switch", "I06"},
1466 {"O29", "I05 Switch", "I05"},
1467 {"O30", "I06 Switch", "I06"},
1468
1469 {"O03", "I07 Switch", "I07"},
1470 {"O04", "I08 Switch", "I08"},
1471 {"O00", "I07 Switch", "I07"},
1472 {"O01", "I08 Switch", "I08"},
1473 {"O07", "I07 Switch", "I07"},
1474 {"O08", "I08 Switch", "I08"},
1475
1476 /* uplink */
1477 {"AWB", NULL, "O05"},
1478 {"AWB", NULL, "O06"},
1479 {"VUL", NULL, "O09"},
1480 {"VUL", NULL, "O10"},
1481 {"VUL3", NULL, "O11"},
1482 {"VUL3", NULL, "O12"},
1483
1484 {"AIN Mux", "EXT ADC", "I2S Capture"},
1485 {"I03", NULL, "AIN Mux"},
1486 {"I04", NULL, "AIN Mux"},
1487
1488 {"HW_GAIN1_IN_CH1", "CONNSYS_I2S_CH1", "Hostless FM DL"},
1489 {"HW_GAIN1_IN_CH2", "CONNSYS_I2S_CH2", "Hostless FM DL"},
1490
1491 {"HW Gain 1 In Endpoint", NULL, "HW Gain 1 In"},
1492 {"HW Gain 1 Out", NULL, "HW Gain 1 Out Endpoint"},
1493 {"HW Gain 1 In", NULL, "HW_GAIN1_IN_CH1"},
1494 {"HW Gain 1 In", NULL, "HW_GAIN1_IN_CH2"},
1495
1496 {"FM HW Gain Mux", "FM_HW_GAIN_IO", "HW Gain 1 Out"},
1497 {"Hostless FM UL", NULL, "FM HW Gain Mux"},
1498 {"Hostless FM UL", NULL, "FM 2ND I2S Mux"},
1499
1500 {"O05", "I05 Switch", "I05L"},
1501 {"O06", "I06 Switch", "I06L"},
1502 {"O05", "I07 Switch", "I07L"},
1503 {"O06", "I08 Switch", "I08L"},
1504
1505 {"O05", "I03 Switch", "I03"},
1506 {"O06", "I04 Switch", "I04"},
1507 {"O05", "I00 Switch", "I00"},
1508 {"O06", "I01 Switch", "I01"},
1509 {"O05", "I09 Switch", "I09"},
1510 {"O06", "I22 Switch", "I22"},
1511 {"O05", "I14 Switch", "I14"},
1512 {"O06", "I15 Switch", "I15"},
1513 {"O05", "I16 Switch", "I16"},
1514 {"O06", "I17 Switch", "I17"},
1515 {"O05", "I18 Switch", "I18"},
1516 {"O06", "I19 Switch", "I19"},
1517 {"O05", "I20 Switch", "I20"},
1518 {"O06", "I21 Switch", "I21"},
1519 {"O05", "I23 Switch", "I23"},
1520 {"O06", "I24 Switch", "I24"},
1521
1522 {"O09", "I03 Switch", "I03"},
1523 {"O10", "I04 Switch", "I04"},
1524 {"O09", "I00 Switch", "I00"},
1525 {"O10", "I01 Switch", "I01"},
1526 {"O09", "I09 Switch", "I09"},
1527 {"O10", "I22 Switch", "I22"},
1528 {"O09", "I14 Switch", "I14"},
1529 {"O10", "I15 Switch", "I15"},
1530 {"O09", "I16 Switch", "I16"},
1531 {"O10", "I17 Switch", "I17"},
1532 {"O09", "I18 Switch", "I18"},
1533 {"O10", "I19 Switch", "I19"},
1534 {"O09", "I20 Switch", "I20"},
1535 {"O10", "I21 Switch", "I21"},
1536
1537 {"O11", "I03 Switch", "I03"},
1538 {"O12", "I04 Switch", "I04"},
1539 {"O11", "I00 Switch", "I00"},
1540 {"O12", "I01 Switch", "I01"},
1541 {"O11", "I09 Switch", "I09"},
1542 {"O12", "I22 Switch", "I22"},
1543 {"O11", "I14 Switch", "I14"},
1544 {"O12", "I15 Switch", "I15"},
1545 {"O11", "I16 Switch", "I16"},
1546 {"O12", "I17 Switch", "I17"},
1547 {"O11", "I18 Switch", "I18"},
1548 {"O12", "I19 Switch", "I19"},
1549 {"O11", "I20 Switch", "I20"},
1550 {"O12", "I21 Switch", "I21"},
1551
1552 /* CM2_Mux*/
1553 {"CM2_Mux IO", NULL, "CM2_Mux_IO Input Mux"},
1554
1555 /* VUL2 */
1556 {"VUL2", NULL, "VUL2 Input Mux"},
1557 {"VUL2 Input Mux", "VUL2_IN_FROM_O17O18", "O17O18"},
1558 {"VUL2 Input Mux", "VUL2_IN_FROM_CM1", "CM1_IO"},
1559
1560 {"O17O18", NULL, "O17"},
1561 {"O17O18", NULL, "O18"},
1562 {"CM1_IO", NULL, "O17"},
1563 {"CM1_IO", NULL, "O18"},
1564 {"CM1_IO", NULL, "O19"},
1565 {"CM1_IO", NULL, "O20"},
1566 {"CM1_IO", NULL, "O21"},
1567 {"CM1_IO", NULL, "O22"},
1568 {"CM1_IO", NULL, "O23"},
1569 {"CM1_IO", NULL, "O24"},
1570 {"CM1_IO", NULL, "O25"},
1571 {"CM1_IO", NULL, "O26"},
1572 {"CM1_IO", NULL, "O31"},
1573 {"CM1_IO", NULL, "O32"},
1574 {"CM1_IO", NULL, "O33"},
1575 {"CM1_IO", NULL, "O34"},
1576 {"CM1_IO", NULL, "O35"},
1577 {"CM1_IO", NULL, "O36"},
1578
1579 {"O17", "I14 Switch", "I14"},
1580 {"O18", "I15 Switch", "I15"},
1581 {"O19", "I16 Switch", "I16"},
1582 {"O20", "I17 Switch", "I17"},
1583 {"O21", "I18 Switch", "I18"},
1584 {"O22", "I19 Switch", "I19"},
1585 {"O23", "I20 Switch", "I20"},
1586 {"O24", "I21 Switch", "I21"},
1587 {"O25", "I23 Switch", "I23"},
1588 {"O26", "I24 Switch", "I24"},
1589 {"O25", "I25 Switch", "I25"},
1590 {"O26", "I26 Switch", "I26"},
1591
1592 {"O17", "I03 Switch", "I03"},
1593 {"O18", "I04 Switch", "I04"},
1594 {"O18", "I23 Switch", "I23"},
1595 {"O18", "I25 Switch", "I25"},
1596 {"O19", "I04 Switch", "I04"},
1597 {"O19", "I23 Switch", "I23"},
1598 {"O19", "I24 Switch", "I24"},
1599 {"O19", "I25 Switch", "I25"},
1600 {"O19", "I26 Switch", "I26"},
1601 {"O20", "I24 Switch", "I24"},
1602 {"O20", "I26 Switch", "I26"},
1603 {"O21", "I23 Switch", "I23"},
1604 {"O21", "I25 Switch", "I25"},
1605 {"O22", "I24 Switch", "I24"},
1606 {"O22", "I26 Switch", "I26"},
1607
1608 {"O23", "I23 Switch", "I23"},
1609 {"O23", "I25 Switch", "I25"},
1610 {"O24", "I24 Switch", "I24"},
1611 {"O24", "I26 Switch", "I26"},
1612 {"O24", "I23 Switch", "I23"},
1613 {"O24", "I25 Switch", "I25"},
1614 {"O13", "I00 Switch", "I00"},
1615 {"O14", "I01 Switch", "I01"},
1616 {"O03", "I10 Switch", "I10"},
1617 {"O04", "I11 Switch", "I11"},
1618 };
1619
1620 static const struct mtk_base_memif_data memif_data[MT8365_AFE_MEMIF_NUM] = {
1621 {
1622 .name = "DL1",
1623 .id = MT8365_AFE_MEMIF_DL1,
1624 .reg_ofs_base = AFE_DL1_BASE,
1625 .reg_ofs_cur = AFE_DL1_CUR,
1626 .fs_reg = AFE_DAC_CON1,
1627 .fs_shift = 0,
1628 .fs_maskbit = 0xf,
1629 .mono_reg = AFE_DAC_CON1,
1630 .mono_shift = 21,
1631 .hd_reg = AFE_MEMIF_PBUF_SIZE,
1632 .hd_shift = 16,
1633 .enable_reg = AFE_DAC_CON0,
1634 .enable_shift = 1,
1635 .msb_reg = -1,
1636 .msb_shift = -1,
1637 .agent_disable_reg = -1,
1638 .agent_disable_shift = -1,
1639 }, {
1640 .name = "DL2",
1641 .id = MT8365_AFE_MEMIF_DL2,
1642 .reg_ofs_base = AFE_DL2_BASE,
1643 .reg_ofs_cur = AFE_DL2_CUR,
1644 .fs_reg = AFE_DAC_CON1,
1645 .fs_shift = 4,
1646 .fs_maskbit = 0xf,
1647 .mono_reg = AFE_DAC_CON1,
1648 .mono_shift = 22,
1649 .hd_reg = AFE_MEMIF_PBUF_SIZE,
1650 .hd_shift = 18,
1651 .enable_reg = AFE_DAC_CON0,
1652 .enable_shift = 2,
1653 .msb_reg = -1,
1654 .msb_shift = -1,
1655 .agent_disable_reg = -1,
1656 .agent_disable_shift = -1,
1657 }, {
1658 .name = "TDM OUT",
1659 .id = MT8365_AFE_MEMIF_TDM_OUT,
1660 .reg_ofs_base = AFE_HDMI_OUT_BASE,
1661 .reg_ofs_cur = AFE_HDMI_OUT_CUR,
1662 .fs_reg = -1,
1663 .fs_shift = -1,
1664 .fs_maskbit = -1,
1665 .mono_reg = -1,
1666 .mono_shift = -1,
1667 .hd_reg = AFE_MEMIF_PBUF_SIZE,
1668 .hd_shift = 28,
1669 .enable_reg = AFE_HDMI_OUT_CON0,
1670 .enable_shift = 0,
1671 .msb_reg = -1,
1672 .msb_shift = -1,
1673 .agent_disable_reg = -1,
1674 .agent_disable_shift = -1,
1675 }, {
1676 .name = "AWB",
1677 .id = MT8365_AFE_MEMIF_AWB,
1678 .reg_ofs_base = AFE_AWB_BASE,
1679 .reg_ofs_cur = AFE_AWB_CUR,
1680 .fs_reg = AFE_DAC_CON1,
1681 .fs_shift = 12,
1682 .fs_maskbit = 0xf,
1683 .mono_reg = AFE_DAC_CON1,
1684 .mono_shift = 24,
1685 .hd_reg = AFE_MEMIF_PBUF_SIZE,
1686 .hd_shift = 20,
1687 .enable_reg = AFE_DAC_CON0,
1688 .enable_shift = 6,
1689 .msb_reg = AFE_MEMIF_MSB,
1690 .msb_shift = 17,
1691 .agent_disable_reg = -1,
1692 .agent_disable_shift = -1,
1693 }, {
1694 .name = "VUL",
1695 .id = MT8365_AFE_MEMIF_VUL,
1696 .reg_ofs_base = AFE_VUL_BASE,
1697 .reg_ofs_cur = AFE_VUL_CUR,
1698 .fs_reg = AFE_DAC_CON1,
1699 .fs_shift = 16,
1700 .fs_maskbit = 0xf,
1701 .mono_reg = AFE_DAC_CON1,
1702 .mono_shift = 27,
1703 .hd_reg = AFE_MEMIF_PBUF_SIZE,
1704 .hd_shift = 22,
1705 .enable_reg = AFE_DAC_CON0,
1706 .enable_shift = 3,
1707 .msb_reg = AFE_MEMIF_MSB,
1708 .msb_shift = 20,
1709 .agent_disable_reg = -1,
1710 .agent_disable_shift = -1,
1711 }, {
1712 .name = "VUL2",
1713 .id = MT8365_AFE_MEMIF_VUL2,
1714 .reg_ofs_base = AFE_VUL_D2_BASE,
1715 .reg_ofs_cur = AFE_VUL_D2_CUR,
1716 .fs_reg = AFE_DAC_CON0,
1717 .fs_shift = 20,
1718 .fs_maskbit = 0xf,
1719 .mono_reg = -1,
1720 .mono_shift = -1,
1721 .hd_reg = AFE_MEMIF_PBUF_SIZE,
1722 .hd_shift = 14,
1723 .enable_reg = AFE_DAC_CON0,
1724 .enable_shift = 9,
1725 .msb_reg = AFE_MEMIF_MSB,
1726 .msb_shift = 21,
1727 .agent_disable_reg = -1,
1728 .agent_disable_shift = -1,
1729 }, {
1730 .name = "VUL3",
1731 .id = MT8365_AFE_MEMIF_VUL3,
1732 .reg_ofs_base = AFE_VUL3_BASE,
1733 .reg_ofs_cur = AFE_VUL3_CUR,
1734 .fs_reg = AFE_DAC_CON1,
1735 .fs_shift = 8,
1736 .fs_maskbit = 0xf,
1737 .mono_reg = AFE_DAC_CON0,
1738 .mono_shift = 13,
1739 .hd_reg = AFE_MEMIF_PBUF2_SIZE,
1740 .hd_shift = 10,
1741 .enable_reg = AFE_DAC_CON0,
1742 .enable_shift = 12,
1743 .msb_reg = AFE_MEMIF_MSB,
1744 .msb_shift = 27,
1745 .agent_disable_reg = -1,
1746 .agent_disable_shift = -1,
1747 }, {
1748 .name = "TDM IN",
1749 .id = MT8365_AFE_MEMIF_TDM_IN,
1750 .reg_ofs_base = AFE_HDMI_IN_2CH_BASE,
1751 .reg_ofs_cur = AFE_HDMI_IN_2CH_CUR,
1752 .fs_reg = -1,
1753 .fs_shift = -1,
1754 .fs_maskbit = -1,
1755 .mono_reg = AFE_HDMI_IN_2CH_CON0,
1756 .mono_shift = 1,
1757 .hd_reg = AFE_MEMIF_PBUF2_SIZE,
1758 .hd_shift = 8,
1759 .hd_align_mshift = 5,
1760 .enable_reg = AFE_HDMI_IN_2CH_CON0,
1761 .enable_shift = 0,
1762 .msb_reg = AFE_MEMIF_MSB,
1763 .msb_shift = 28,
1764 .agent_disable_reg = -1,
1765 .agent_disable_shift = -1,
1766 },
1767 };
1768
1769 static const struct mtk_base_irq_data irq_data[MT8365_AFE_IRQ_NUM] = {
1770 {
1771 .id = MT8365_AFE_IRQ1,
1772 .irq_cnt_reg = AFE_IRQ_MCU_CNT1,
1773 .irq_cnt_shift = 0,
1774 .irq_cnt_maskbit = 0x3ffff,
1775 .irq_en_reg = AFE_IRQ_MCU_CON,
1776 .irq_en_shift = 0,
1777 .irq_fs_reg = AFE_IRQ_MCU_CON,
1778 .irq_fs_shift = 4,
1779 .irq_fs_maskbit = 0xf,
1780 .irq_clr_reg = AFE_IRQ_MCU_CLR,
1781 .irq_clr_shift = 0,
1782 }, {
1783 .id = MT8365_AFE_IRQ2,
1784 .irq_cnt_reg = AFE_IRQ_MCU_CNT2,
1785 .irq_cnt_shift = 0,
1786 .irq_cnt_maskbit = 0x3ffff,
1787 .irq_en_reg = AFE_IRQ_MCU_CON,
1788 .irq_en_shift = 1,
1789 .irq_fs_reg = AFE_IRQ_MCU_CON,
1790 .irq_fs_shift = 8,
1791 .irq_fs_maskbit = 0xf,
1792 .irq_clr_reg = AFE_IRQ_MCU_CLR,
1793 .irq_clr_shift = 1,
1794 }, {
1795 .id = MT8365_AFE_IRQ3,
1796 .irq_cnt_reg = AFE_IRQ_MCU_CNT3,
1797 .irq_cnt_shift = 0,
1798 .irq_cnt_maskbit = 0x3ffff,
1799 .irq_en_reg = AFE_IRQ_MCU_CON,
1800 .irq_en_shift = 2,
1801 .irq_fs_reg = AFE_IRQ_MCU_CON,
1802 .irq_fs_shift = 16,
1803 .irq_fs_maskbit = 0xf,
1804 .irq_clr_reg = AFE_IRQ_MCU_CLR,
1805 .irq_clr_shift = 2,
1806 }, {
1807 .id = MT8365_AFE_IRQ4,
1808 .irq_cnt_reg = AFE_IRQ_MCU_CNT4,
1809 .irq_cnt_shift = 0,
1810 .irq_cnt_maskbit = 0x3ffff,
1811 .irq_en_reg = AFE_IRQ_MCU_CON,
1812 .irq_en_shift = 3,
1813 .irq_fs_reg = AFE_IRQ_MCU_CON,
1814 .irq_fs_shift = 20,
1815 .irq_fs_maskbit = 0xf,
1816 .irq_clr_reg = AFE_IRQ_MCU_CLR,
1817 .irq_clr_shift = 3,
1818 }, {
1819 .id = MT8365_AFE_IRQ5,
1820 .irq_cnt_reg = AFE_IRQ_MCU_CNT5,
1821 .irq_cnt_shift = 0,
1822 .irq_cnt_maskbit = 0x3ffff,
1823 .irq_en_reg = AFE_IRQ_MCU_CON2,
1824 .irq_en_shift = 3,
1825 .irq_fs_reg = -1,
1826 .irq_fs_shift = 0,
1827 .irq_fs_maskbit = 0x0,
1828 .irq_clr_reg = AFE_IRQ_MCU_CLR,
1829 .irq_clr_shift = 4,
1830 }, {
1831 .id = MT8365_AFE_IRQ6,
1832 .irq_cnt_reg = -1,
1833 .irq_cnt_shift = 0,
1834 .irq_cnt_maskbit = 0x0,
1835 .irq_en_reg = AFE_IRQ_MCU_CON,
1836 .irq_en_shift = 13,
1837 .irq_fs_reg = -1,
1838 .irq_fs_shift = 0,
1839 .irq_fs_maskbit = 0x0,
1840 .irq_clr_reg = AFE_IRQ_MCU_CLR,
1841 .irq_clr_shift = 5,
1842 }, {
1843 .id = MT8365_AFE_IRQ7,
1844 .irq_cnt_reg = AFE_IRQ_MCU_CNT7,
1845 .irq_cnt_shift = 0,
1846 .irq_cnt_maskbit = 0x3ffff,
1847 .irq_en_reg = AFE_IRQ_MCU_CON,
1848 .irq_en_shift = 14,
1849 .irq_fs_reg = AFE_IRQ_MCU_CON,
1850 .irq_fs_shift = 24,
1851 .irq_fs_maskbit = 0xf,
1852 .irq_clr_reg = AFE_IRQ_MCU_CLR,
1853 .irq_clr_shift = 6,
1854 }, {
1855 .id = MT8365_AFE_IRQ8,
1856 .irq_cnt_reg = AFE_IRQ_MCU_CNT8,
1857 .irq_cnt_shift = 0,
1858 .irq_cnt_maskbit = 0x3ffff,
1859 .irq_en_reg = AFE_IRQ_MCU_CON,
1860 .irq_en_shift = 15,
1861 .irq_fs_reg = AFE_IRQ_MCU_CON,
1862 .irq_fs_shift = 28,
1863 .irq_fs_maskbit = 0xf,
1864 .irq_clr_reg = AFE_IRQ_MCU_CLR,
1865 .irq_clr_shift = 7,
1866 }, {
1867 .id = MT8365_AFE_IRQ9,
1868 .irq_cnt_reg = -1,
1869 .irq_cnt_shift = 0,
1870 .irq_cnt_maskbit = 0x0,
1871 .irq_en_reg = AFE_IRQ_MCU_CON2,
1872 .irq_en_shift = 2,
1873 .irq_fs_reg = -1,
1874 .irq_fs_shift = 0,
1875 .irq_fs_maskbit = 0x0,
1876 .irq_clr_reg = AFE_IRQ_MCU_CLR,
1877 .irq_clr_shift = 8,
1878 }, {
1879 .id = MT8365_AFE_IRQ10,
1880 .irq_cnt_reg = AFE_IRQ_MCU_CNT10,
1881 .irq_cnt_shift = 0,
1882 .irq_cnt_maskbit = 0x3ffff,
1883 .irq_en_reg = AFE_IRQ_MCU_CON2,
1884 .irq_en_shift = 4,
1885 .irq_fs_reg = -1,
1886 .irq_fs_shift = 0,
1887 .irq_fs_maskbit = 0x0,
1888 .irq_clr_reg = AFE_IRQ_MCU_CLR,
1889 .irq_clr_shift = 9,
1890 },
1891 };
1892
1893 static int memif_specified_irqs[MT8365_AFE_MEMIF_NUM] = {
1894 [MT8365_AFE_MEMIF_DL1] = MT8365_AFE_IRQ1,
1895 [MT8365_AFE_MEMIF_DL2] = MT8365_AFE_IRQ2,
1896 [MT8365_AFE_MEMIF_TDM_OUT] = MT8365_AFE_IRQ5,
1897 [MT8365_AFE_MEMIF_AWB] = MT8365_AFE_IRQ3,
1898 [MT8365_AFE_MEMIF_VUL] = MT8365_AFE_IRQ4,
1899 [MT8365_AFE_MEMIF_VUL2] = MT8365_AFE_IRQ7,
1900 [MT8365_AFE_MEMIF_VUL3] = MT8365_AFE_IRQ8,
1901 [MT8365_AFE_MEMIF_TDM_IN] = MT8365_AFE_IRQ10,
1902 };
1903
1904 static const struct regmap_config mt8365_afe_regmap_config = {
1905 .reg_bits = 32,
1906 .reg_stride = 4,
1907 .val_bits = 32,
1908 .max_register = MAX_REGISTER,
1909 .cache_type = REGCACHE_NONE,
1910 };
1911
mt8365_afe_irq_handler(int irq,void * dev_id)1912 static irqreturn_t mt8365_afe_irq_handler(int irq, void *dev_id)
1913 {
1914 struct mtk_base_afe *afe = dev_id;
1915 unsigned int reg_value;
1916 unsigned int mcu_irq_mask;
1917 int i, ret;
1918
1919 ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, ®_value);
1920 if (ret) {
1921 dev_err_ratelimited(afe->dev, "%s irq status err\n", __func__);
1922 reg_value = AFE_IRQ_STATUS_BITS;
1923 goto err_irq;
1924 }
1925
1926 ret = regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_irq_mask);
1927 if (ret) {
1928 dev_err_ratelimited(afe->dev, "%s irq mcu_en err\n", __func__);
1929 reg_value = AFE_IRQ_STATUS_BITS;
1930 goto err_irq;
1931 }
1932
1933 /* only clr cpu irq */
1934 reg_value &= mcu_irq_mask;
1935
1936 for (i = 0; i < MT8365_AFE_MEMIF_NUM; i++) {
1937 struct mtk_base_afe_memif *memif = &afe->memif[i];
1938 struct mtk_base_afe_irq *mcu_irq;
1939
1940 if (memif->irq_usage < 0)
1941 continue;
1942
1943 mcu_irq = &afe->irqs[memif->irq_usage];
1944
1945 if (!(reg_value & (1 << mcu_irq->irq_data->irq_clr_shift)))
1946 continue;
1947
1948 snd_pcm_period_elapsed(memif->substream);
1949 }
1950
1951 err_irq:
1952 /* clear irq */
1953 regmap_write(afe->regmap, AFE_IRQ_MCU_CLR,
1954 reg_value & AFE_IRQ_STATUS_BITS);
1955
1956 return IRQ_HANDLED;
1957 }
1958
mt8365_afe_runtime_suspend(struct device * dev)1959 static int mt8365_afe_runtime_suspend(struct device *dev)
1960 {
1961 return 0;
1962 }
1963
mt8365_afe_runtime_resume(struct device * dev)1964 static int mt8365_afe_runtime_resume(struct device *dev)
1965 {
1966 return 0;
1967 }
1968
mt8365_afe_suspend(struct device * dev)1969 static int mt8365_afe_suspend(struct device *dev)
1970 {
1971 struct mtk_base_afe *afe = dev_get_drvdata(dev);
1972 struct regmap *regmap = afe->regmap;
1973 int i;
1974
1975 mt8365_afe_enable_main_clk(afe);
1976
1977 if (!afe->reg_back_up)
1978 afe->reg_back_up =
1979 devm_kcalloc(dev, afe->reg_back_up_list_num,
1980 sizeof(unsigned int), GFP_KERNEL);
1981
1982 for (i = 0; i < afe->reg_back_up_list_num; i++)
1983 regmap_read(regmap, afe->reg_back_up_list[i],
1984 &afe->reg_back_up[i]);
1985
1986 mt8365_afe_disable_main_clk(afe);
1987
1988 return 0;
1989 }
1990
mt8365_afe_resume(struct device * dev)1991 static int mt8365_afe_resume(struct device *dev)
1992 {
1993 struct mtk_base_afe *afe = dev_get_drvdata(dev);
1994 struct regmap *regmap = afe->regmap;
1995 int i = 0;
1996
1997 if (!afe->reg_back_up)
1998 return 0;
1999
2000 mt8365_afe_enable_main_clk(afe);
2001
2002 for (i = 0; i < afe->reg_back_up_list_num; i++)
2003 regmap_write(regmap, afe->reg_back_up_list[i],
2004 afe->reg_back_up[i]);
2005
2006 mt8365_afe_disable_main_clk(afe);
2007
2008 return 0;
2009 }
2010
mt8365_afe_dev_runtime_suspend(struct device * dev)2011 static int mt8365_afe_dev_runtime_suspend(struct device *dev)
2012 {
2013 struct mtk_base_afe *afe = dev_get_drvdata(dev);
2014
2015 if (pm_runtime_status_suspended(dev) || afe->suspended)
2016 return 0;
2017
2018 mt8365_afe_suspend(dev);
2019 afe->suspended = true;
2020 return 0;
2021 }
2022
mt8365_afe_dev_runtime_resume(struct device * dev)2023 static int mt8365_afe_dev_runtime_resume(struct device *dev)
2024 {
2025 struct mtk_base_afe *afe = dev_get_drvdata(dev);
2026
2027 if (pm_runtime_status_suspended(dev) || !afe->suspended)
2028 return 0;
2029
2030 mt8365_afe_resume(dev);
2031 afe->suspended = false;
2032 return 0;
2033 }
2034
mt8365_afe_init_registers(struct mtk_base_afe * afe)2035 static int mt8365_afe_init_registers(struct mtk_base_afe *afe)
2036 {
2037 size_t i;
2038
2039 static struct {
2040 unsigned int reg;
2041 unsigned int mask;
2042 unsigned int val;
2043 } init_regs[] = {
2044 { AFE_CONN_24BIT, GENMASK(31, 0), GENMASK(31, 0) },
2045 { AFE_CONN_24BIT_1, GENMASK(21, 0), GENMASK(21, 0) },
2046 };
2047
2048 mt8365_afe_enable_main_clk(afe);
2049
2050 for (i = 0; i < ARRAY_SIZE(init_regs); i++)
2051 regmap_update_bits(afe->regmap, init_regs[i].reg,
2052 init_regs[i].mask, init_regs[i].val);
2053
2054 mt8365_afe_disable_main_clk(afe);
2055
2056 return 0;
2057 }
2058
mt8365_dai_memif_register(struct mtk_base_afe * afe)2059 static int mt8365_dai_memif_register(struct mtk_base_afe *afe)
2060 {
2061 struct mtk_base_afe_dai *dai;
2062
2063 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
2064 if (!dai)
2065 return -ENOMEM;
2066
2067 list_add(&dai->list, &afe->sub_dais);
2068
2069 dai->dai_drivers = mt8365_memif_dai_driver;
2070 dai->num_dai_drivers = ARRAY_SIZE(mt8365_memif_dai_driver);
2071
2072 dai->dapm_widgets = mt8365_memif_widgets;
2073 dai->num_dapm_widgets = ARRAY_SIZE(mt8365_memif_widgets);
2074 dai->dapm_routes = mt8365_memif_routes;
2075 dai->num_dapm_routes = ARRAY_SIZE(mt8365_memif_routes);
2076 return 0;
2077 }
2078
2079 typedef int (*dai_register_cb)(struct mtk_base_afe *);
2080 static const dai_register_cb dai_register_cbs[] = {
2081 mt8365_dai_pcm_register,
2082 mt8365_dai_i2s_register,
2083 mt8365_dai_adda_register,
2084 mt8365_dai_dmic_register,
2085 mt8365_dai_memif_register,
2086 };
2087
mt8365_afe_pcm_dev_probe(struct platform_device * pdev)2088 static int mt8365_afe_pcm_dev_probe(struct platform_device *pdev)
2089 {
2090 struct mtk_base_afe *afe;
2091 struct mt8365_afe_private *afe_priv;
2092 struct device *dev;
2093 int ret, i, sel_irq;
2094 unsigned int irq_id;
2095 struct resource *res;
2096
2097 afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
2098 if (!afe)
2099 return -ENOMEM;
2100 platform_set_drvdata(pdev, afe);
2101
2102 afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
2103 GFP_KERNEL);
2104 if (!afe->platform_priv)
2105 return -ENOMEM;
2106
2107 afe_priv = afe->platform_priv;
2108 afe->dev = &pdev->dev;
2109 dev = afe->dev;
2110
2111 spin_lock_init(&afe_priv->afe_ctrl_lock);
2112 mutex_init(&afe_priv->afe_clk_mutex);
2113
2114 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2115 afe->base_addr = devm_ioremap_resource(&pdev->dev, res);
2116 if (IS_ERR(afe->base_addr))
2117 return PTR_ERR(afe->base_addr);
2118
2119 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2120 if (res) {
2121 afe_priv->afe_sram_vir_addr =
2122 devm_ioremap_resource(&pdev->dev, res);
2123 if (!IS_ERR(afe_priv->afe_sram_vir_addr)) {
2124 afe_priv->afe_sram_phy_addr = res->start;
2125 afe_priv->afe_sram_size = resource_size(res);
2126 }
2127 }
2128
2129 /* initial audio related clock */
2130 ret = mt8365_afe_init_audio_clk(afe);
2131 if (ret)
2132 return dev_err_probe(afe->dev, ret, "mt8365_afe_init_audio_clk fail\n");
2133
2134 afe->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "top_audio_sel",
2135 afe->base_addr,
2136 &mt8365_afe_regmap_config);
2137 if (IS_ERR(afe->regmap))
2138 return PTR_ERR(afe->regmap);
2139
2140 /* memif % irq initialize*/
2141 afe->memif_size = MT8365_AFE_MEMIF_NUM;
2142 afe->memif = devm_kcalloc(afe->dev, afe->memif_size,
2143 sizeof(*afe->memif), GFP_KERNEL);
2144 if (!afe->memif)
2145 return -ENOMEM;
2146
2147 afe->irqs_size = MT8365_AFE_IRQ_NUM;
2148 afe->irqs = devm_kcalloc(afe->dev, afe->irqs_size,
2149 sizeof(*afe->irqs), GFP_KERNEL);
2150 if (!afe->irqs)
2151 return -ENOMEM;
2152
2153 for (i = 0; i < afe->irqs_size; i++)
2154 afe->irqs[i].irq_data = &irq_data[i];
2155
2156 ret = platform_get_irq(pdev, 0);
2157 if (ret < 0)
2158 return ret;
2159
2160 irq_id = ret;
2161 ret = devm_request_irq(afe->dev, irq_id, mt8365_afe_irq_handler,
2162 0, "Afe_ISR_Handle", (void *)afe);
2163 if (ret)
2164 return dev_err_probe(afe->dev, ret, "could not request_irq\n");
2165
2166 /* init sub_dais */
2167 INIT_LIST_HEAD(&afe->sub_dais);
2168
2169 for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
2170 ret = dai_register_cbs[i](afe);
2171 if (ret) {
2172 dev_warn(afe->dev, "dai register i %d fail, ret %d\n",
2173 i, ret);
2174 return ret;
2175 }
2176 }
2177
2178 /* init dai_driver and component_driver */
2179 ret = mtk_afe_combine_sub_dai(afe);
2180 if (ret) {
2181 dev_warn(afe->dev, "mtk_afe_combine_sub_dai fail, ret %d\n",
2182 ret);
2183 return ret;
2184 }
2185
2186 for (i = 0; i < afe->memif_size; i++) {
2187 afe->memif[i].data = &memif_data[i];
2188 sel_irq = memif_specified_irqs[i];
2189 if (sel_irq >= 0) {
2190 afe->memif[i].irq_usage = sel_irq;
2191 afe->memif[i].const_irq = 1;
2192 afe->irqs[sel_irq].irq_occupyed = true;
2193 } else {
2194 afe->memif[i].irq_usage = -1;
2195 }
2196 }
2197
2198 afe->mtk_afe_hardware = &mt8365_afe_hardware;
2199 afe->memif_fs = mt8365_memif_fs;
2200 afe->irq_fs = mt8365_irq_fs;
2201
2202 ret = devm_pm_runtime_enable(&pdev->dev);
2203 if (ret)
2204 return ret;
2205
2206 pm_runtime_get_sync(&pdev->dev);
2207 afe->reg_back_up_list = mt8365_afe_backup_list;
2208 afe->reg_back_up_list_num = ARRAY_SIZE(mt8365_afe_backup_list);
2209 afe->runtime_resume = mt8365_afe_runtime_resume;
2210 afe->runtime_suspend = mt8365_afe_runtime_suspend;
2211
2212 /* open afe pdn for dapm read/write audio register */
2213 mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_AFE);
2214
2215 /* Set 26m parent clk */
2216 mt8365_afe_set_clk_parent(afe,
2217 afe_priv->clocks[MT8365_CLK_TOP_AUD_SEL],
2218 afe_priv->clocks[MT8365_CLK_CLK26M]);
2219
2220 ret = devm_snd_soc_register_component(&pdev->dev,
2221 &mtk_afe_pcm_platform,
2222 afe->dai_drivers,
2223 afe->num_dai_drivers);
2224 if (ret) {
2225 dev_warn(dev, "err_platform\n");
2226 return ret;
2227 }
2228
2229 mt8365_afe_init_registers(afe);
2230
2231 return 0;
2232 }
2233
mt8365_afe_pcm_dev_remove(struct platform_device * pdev)2234 static void mt8365_afe_pcm_dev_remove(struct platform_device *pdev)
2235 {
2236 struct mtk_base_afe *afe = platform_get_drvdata(pdev);
2237
2238 mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_AFE);
2239
2240 if (!pm_runtime_status_suspended(&pdev->dev))
2241 mt8365_afe_runtime_suspend(&pdev->dev);
2242 }
2243
2244 static const struct of_device_id mt8365_afe_pcm_dt_match[] = {
2245 { .compatible = "mediatek,mt8365-afe-pcm", },
2246 { }
2247 };
2248 MODULE_DEVICE_TABLE(of, mt8365_afe_pcm_dt_match);
2249
2250 static const struct dev_pm_ops mt8365_afe_pm_ops = {
2251 RUNTIME_PM_OPS(mt8365_afe_dev_runtime_suspend,
2252 mt8365_afe_dev_runtime_resume, NULL)
2253 SYSTEM_SLEEP_PM_OPS(mt8365_afe_suspend, mt8365_afe_resume)
2254 };
2255
2256 static struct platform_driver mt8365_afe_pcm_driver = {
2257 .driver = {
2258 .name = "mt8365-afe-pcm",
2259 .of_match_table = mt8365_afe_pcm_dt_match,
2260 .pm = pm_ptr(&mt8365_afe_pm_ops),
2261 },
2262 .probe = mt8365_afe_pcm_dev_probe,
2263 .remove = mt8365_afe_pcm_dev_remove,
2264 };
2265
2266 module_platform_driver(mt8365_afe_pcm_driver);
2267
2268 MODULE_DESCRIPTION("MediaTek ALSA SoC AFE platform driver");
2269 MODULE_AUTHOR("Jia Zeng <jia.zeng@mediatek.com>");
2270 MODULE_AUTHOR("Alexandre Mergnat <amergnat@baylibre.com>");
2271 MODULE_LICENSE("GPL");
2272