1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // Copyright(c) 2022 Mediatek Inc. All rights reserved.
4 //
5 // Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
6 // Tinghan Shen <tinghan.shen@mediatek.com>
7
8 /*
9 * Hardware interface for audio DSP on mt8186
10 */
11
12 #include <linux/delay.h>
13 #include <linux/firmware.h>
14 #include <linux/io.h>
15 #include <linux/of_irq.h>
16 #include <linux/of_platform.h>
17 #include <linux/of_reserved_mem.h>
18 #include <linux/module.h>
19
20 #include <sound/sof.h>
21 #include <sound/sof/xtensa.h>
22 #include "../../ops.h"
23 #include "../../sof-of-dev.h"
24 #include "../adsp_helper.h"
25 #include "../mtk-adsp-common.h"
26 #include "mt8186.h"
27 #include "mt8186-clk.h"
28
mt8186_get_mailbox_offset(struct snd_sof_dev * sdev)29 static int mt8186_get_mailbox_offset(struct snd_sof_dev *sdev)
30 {
31 return MBOX_OFFSET;
32 }
33
mt8186_get_window_offset(struct snd_sof_dev * sdev,u32 id)34 static int mt8186_get_window_offset(struct snd_sof_dev *sdev, u32 id)
35 {
36 return MBOX_OFFSET;
37 }
38
39 static const struct mtk_adsp_ipc_ops dsp_ops = {
40 .handle_reply = mtk_adsp_handle_reply,
41 .handle_request = mtk_adsp_handle_request,
42 };
43
platform_parse_resource(struct platform_device * pdev,void * data)44 static int platform_parse_resource(struct platform_device *pdev, void *data)
45 {
46 struct resource *mmio;
47 struct resource res;
48 struct device *dev = &pdev->dev;
49 struct mtk_adsp_chip_info *adsp = data;
50 int ret;
51
52 ret = of_reserved_mem_device_init(dev);
53 if (ret) {
54 dev_err(dev, "of_reserved_mem_device_init failed\n");
55 return ret;
56 }
57
58 ret = of_reserved_mem_region_to_resource(dev->of_node, 1, &res);
59 if (ret) {
60 dev_err(dev, "of_address_to_resource sysmem failed\n");
61 return ret;
62 }
63
64 adsp->pa_dram = (phys_addr_t)res.start;
65 if (adsp->pa_dram & DRAM_REMAP_MASK) {
66 dev_err(dev, "adsp memory(%#x) is not 4K-aligned\n",
67 (u32)adsp->pa_dram);
68 return -EINVAL;
69 }
70
71 adsp->dramsize = resource_size(&res);
72 if (adsp->dramsize < TOTAL_SIZE_SHARED_DRAM_FROM_TAIL) {
73 dev_err(dev, "adsp memory(%#x) is not enough for share\n",
74 adsp->dramsize);
75 return -EINVAL;
76 }
77
78 dev_dbg(dev, "dram pbase=%pa size=%#x\n", &adsp->pa_dram, adsp->dramsize);
79
80 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
81 if (!mmio) {
82 dev_err(dev, "no ADSP-CFG register resource\n");
83 return -ENXIO;
84 }
85
86 adsp->va_cfgreg = devm_ioremap_resource(dev, mmio);
87 if (IS_ERR(adsp->va_cfgreg))
88 return PTR_ERR(adsp->va_cfgreg);
89
90 adsp->pa_cfgreg = (phys_addr_t)mmio->start;
91 adsp->cfgregsize = resource_size(mmio);
92
93 dev_dbg(dev, "cfgreg pbase=%pa size=%#x\n", &adsp->pa_cfgreg, adsp->cfgregsize);
94
95 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
96 if (!mmio) {
97 dev_err(dev, "no SRAM resource\n");
98 return -ENXIO;
99 }
100
101 adsp->pa_sram = (phys_addr_t)mmio->start;
102 adsp->sramsize = resource_size(mmio);
103
104 dev_dbg(dev, "sram pbase=%pa size=%#x\n", &adsp->pa_sram, adsp->sramsize);
105
106 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sec");
107 if (!mmio) {
108 dev_err(dev, "no SEC register resource\n");
109 return -ENXIO;
110 }
111
112 adsp->va_secreg = devm_ioremap_resource(dev, mmio);
113 if (IS_ERR(adsp->va_secreg))
114 return PTR_ERR(adsp->va_secreg);
115
116 adsp->pa_secreg = (phys_addr_t)mmio->start;
117 adsp->secregsize = resource_size(mmio);
118
119 dev_dbg(dev, "secreg pbase=%pa size=%#x\n", &adsp->pa_secreg, adsp->secregsize);
120
121 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bus");
122 if (!mmio) {
123 dev_err(dev, "no BUS register resource\n");
124 return -ENXIO;
125 }
126
127 adsp->va_busreg = devm_ioremap_resource(dev, mmio);
128 if (IS_ERR(adsp->va_busreg))
129 return PTR_ERR(adsp->va_busreg);
130
131 adsp->pa_busreg = (phys_addr_t)mmio->start;
132 adsp->busregsize = resource_size(mmio);
133
134 dev_dbg(dev, "busreg pbase=%pa size=%#x\n", &adsp->pa_busreg, adsp->busregsize);
135
136 return 0;
137 }
138
adsp_sram_power_on(struct snd_sof_dev * sdev)139 static void adsp_sram_power_on(struct snd_sof_dev *sdev)
140 {
141 snd_sof_dsp_update_bits(sdev, DSP_BUSREG_BAR, ADSP_SRAM_POOL_CON,
142 DSP_SRAM_POOL_PD_MASK, 0);
143 }
144
adsp_sram_power_off(struct snd_sof_dev * sdev)145 static void adsp_sram_power_off(struct snd_sof_dev *sdev)
146 {
147 snd_sof_dsp_update_bits(sdev, DSP_BUSREG_BAR, ADSP_SRAM_POOL_CON,
148 DSP_SRAM_POOL_PD_MASK, DSP_SRAM_POOL_PD_MASK);
149 }
150
151 /* Init the basic DSP DRAM address */
adsp_memory_remap_init(struct snd_sof_dev * sdev,struct mtk_adsp_chip_info * adsp)152 static int adsp_memory_remap_init(struct snd_sof_dev *sdev, struct mtk_adsp_chip_info *adsp)
153 {
154 u32 offset;
155
156 offset = adsp->pa_dram - DRAM_PHYS_BASE_FROM_DSP_VIEW;
157 adsp->dram_offset = offset;
158 offset >>= DRAM_REMAP_SHIFT;
159
160 dev_dbg(sdev->dev, "adsp->pa_dram %pa, offset %#x\n", &adsp->pa_dram, offset);
161
162 snd_sof_dsp_write(sdev, DSP_BUSREG_BAR, DSP_C0_EMI_MAP_ADDR, offset);
163 snd_sof_dsp_write(sdev, DSP_BUSREG_BAR, DSP_C0_DMAEMI_MAP_ADDR, offset);
164
165 if (offset != snd_sof_dsp_read(sdev, DSP_BUSREG_BAR, DSP_C0_EMI_MAP_ADDR) ||
166 offset != snd_sof_dsp_read(sdev, DSP_BUSREG_BAR, DSP_C0_DMAEMI_MAP_ADDR)) {
167 dev_err(sdev->dev, "emi remap fail\n");
168 return -EIO;
169 }
170
171 return 0;
172 }
173
mt8186_run(struct snd_sof_dev * sdev)174 static int mt8186_run(struct snd_sof_dev *sdev)
175 {
176 u32 adsp_bootup_addr;
177
178 adsp_bootup_addr = SRAM_PHYS_BASE_FROM_DSP_VIEW;
179 dev_dbg(sdev->dev, "HIFIxDSP boot from base : 0x%08X\n", adsp_bootup_addr);
180 mt8186_sof_hifixdsp_boot_sequence(sdev, adsp_bootup_addr);
181
182 return 0;
183 }
184
mt8186_dsp_probe(struct snd_sof_dev * sdev)185 static int mt8186_dsp_probe(struct snd_sof_dev *sdev)
186 {
187 struct platform_device *pdev = to_platform_device(sdev->dev);
188 struct adsp_priv *priv;
189 int ret;
190
191 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
192 if (!priv)
193 return -ENOMEM;
194
195 sdev->pdata->hw_pdata = priv;
196 priv->dev = sdev->dev;
197 priv->sdev = sdev;
198
199 priv->adsp = devm_kzalloc(&pdev->dev, sizeof(struct mtk_adsp_chip_info), GFP_KERNEL);
200 if (!priv->adsp)
201 return -ENOMEM;
202
203 ret = platform_parse_resource(pdev, priv->adsp);
204 if (ret)
205 return ret;
206
207 sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev,
208 priv->adsp->pa_sram,
209 priv->adsp->sramsize);
210 if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) {
211 dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n",
212 &priv->adsp->pa_sram, priv->adsp->sramsize);
213 return -ENOMEM;
214 }
215
216 priv->adsp->va_sram = sdev->bar[SOF_FW_BLK_TYPE_IRAM];
217
218 sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap(sdev->dev,
219 priv->adsp->pa_dram,
220 priv->adsp->dramsize);
221
222 if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) {
223 dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n",
224 &priv->adsp->pa_dram, priv->adsp->dramsize);
225 return -ENOMEM;
226 }
227
228 priv->adsp->va_dram = sdev->bar[SOF_FW_BLK_TYPE_SRAM];
229
230 sdev->bar[DSP_REG_BAR] = priv->adsp->va_cfgreg;
231 sdev->bar[DSP_SECREG_BAR] = priv->adsp->va_secreg;
232 sdev->bar[DSP_BUSREG_BAR] = priv->adsp->va_busreg;
233
234 sdev->mmio_bar = SOF_FW_BLK_TYPE_SRAM;
235 sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM;
236
237 /* set default mailbox offset for FW ready message */
238 sdev->dsp_box.offset = mt8186_get_mailbox_offset(sdev);
239
240 ret = adsp_memory_remap_init(sdev, priv->adsp);
241 if (ret) {
242 dev_err(sdev->dev, "adsp_memory_remap_init fail!\n");
243 return ret;
244 }
245
246 /* enable adsp clock before touching registers */
247 ret = mt8186_adsp_init_clock(sdev);
248 if (ret) {
249 dev_err(sdev->dev, "mt8186_adsp_init_clock failed\n");
250 return ret;
251 }
252
253 ret = mt8186_adsp_clock_on(sdev);
254 if (ret) {
255 dev_err(sdev->dev, "mt8186_adsp_clock_on fail!\n");
256 return ret;
257 }
258
259 adsp_sram_power_on(sdev);
260
261 priv->ipc_dev = platform_device_register_data(&pdev->dev, "mtk-adsp-ipc",
262 PLATFORM_DEVID_NONE,
263 pdev, sizeof(*pdev));
264 if (IS_ERR(priv->ipc_dev)) {
265 ret = PTR_ERR(priv->ipc_dev);
266 dev_err(sdev->dev, "failed to create mtk-adsp-ipc device\n");
267 goto err_adsp_off;
268 }
269
270 priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev);
271 if (!priv->dsp_ipc) {
272 ret = -EPROBE_DEFER;
273 dev_err(sdev->dev, "failed to get drvdata\n");
274 goto exit_pdev_unregister;
275 }
276
277 mtk_adsp_ipc_set_data(priv->dsp_ipc, priv);
278 priv->dsp_ipc->ops = &dsp_ops;
279
280 return 0;
281
282 exit_pdev_unregister:
283 platform_device_unregister(priv->ipc_dev);
284 err_adsp_off:
285 adsp_sram_power_off(sdev);
286 mt8186_adsp_clock_off(sdev);
287
288 return ret;
289 }
290
mt8186_dsp_remove(struct snd_sof_dev * sdev)291 static void mt8186_dsp_remove(struct snd_sof_dev *sdev)
292 {
293 struct adsp_priv *priv = sdev->pdata->hw_pdata;
294
295 platform_device_unregister(priv->ipc_dev);
296 mt8186_sof_hifixdsp_shutdown(sdev);
297 adsp_sram_power_off(sdev);
298 mt8186_adsp_clock_off(sdev);
299 }
300
mt8186_dsp_shutdown(struct snd_sof_dev * sdev)301 static int mt8186_dsp_shutdown(struct snd_sof_dev *sdev)
302 {
303 return snd_sof_suspend(sdev->dev);
304 }
305
mt8186_dsp_suspend(struct snd_sof_dev * sdev,u32 target_state)306 static int mt8186_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)
307 {
308 mt8186_sof_hifixdsp_shutdown(sdev);
309 adsp_sram_power_off(sdev);
310 mt8186_adsp_clock_off(sdev);
311
312 return 0;
313 }
314
mt8186_dsp_resume(struct snd_sof_dev * sdev)315 static int mt8186_dsp_resume(struct snd_sof_dev *sdev)
316 {
317 int ret;
318
319 ret = mt8186_adsp_clock_on(sdev);
320 if (ret) {
321 dev_err(sdev->dev, "mt8186_adsp_clock_on fail!\n");
322 return ret;
323 }
324
325 adsp_sram_power_on(sdev);
326
327 return ret;
328 }
329
mt8186_adsp_dump(struct snd_sof_dev * sdev,u32 flags)330 static void mt8186_adsp_dump(struct snd_sof_dev *sdev, u32 flags)
331 {
332 u32 dbg_pc, dbg_data, dbg_inst, dbg_ls0stat, dbg_status, faultinfo;
333
334 /* dump debug registers */
335 dbg_pc = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGPC);
336 dbg_data = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGDATA);
337 dbg_inst = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGINST);
338 dbg_ls0stat = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGLS0STAT);
339 dbg_status = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGSTATUS);
340 faultinfo = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PFAULTINFO);
341
342 dev_info(sdev->dev, "adsp dump : pc %#x, data %#x, dbg_inst %#x,",
343 dbg_pc, dbg_data, dbg_inst);
344 dev_info(sdev->dev, "ls0stat %#x, status %#x, faultinfo %#x",
345 dbg_ls0stat, dbg_status, faultinfo);
346
347 mtk_adsp_dump(sdev, flags);
348 }
349
350 static struct snd_soc_dai_driver mt8186_dai[] = {
351 {
352 .name = "SOF_DL1",
353 .playback = {
354 .channels_min = 1,
355 .channels_max = 2,
356 },
357 },
358 {
359 .name = "SOF_DL2",
360 .playback = {
361 .channels_min = 1,
362 .channels_max = 2,
363 },
364 },
365 {
366 .name = "SOF_UL1",
367 .capture = {
368 .channels_min = 1,
369 .channels_max = 2,
370 },
371 },
372 {
373 .name = "SOF_UL2",
374 .capture = {
375 .channels_min = 1,
376 .channels_max = 2,
377 },
378 },
379 };
380
381 /* mt8186 ops */
382 static const struct snd_sof_dsp_ops sof_mt8186_ops = {
383 /* probe and remove */
384 .probe = mt8186_dsp_probe,
385 .remove = mt8186_dsp_remove,
386 .shutdown = mt8186_dsp_shutdown,
387
388 /* DSP core boot */
389 .run = mt8186_run,
390
391 /* Block IO */
392 .block_read = sof_block_read,
393 .block_write = sof_block_write,
394
395 /* Mailbox IO */
396 .mailbox_read = sof_mailbox_read,
397 .mailbox_write = sof_mailbox_write,
398
399 /* Register IO */
400 .write = sof_io_write,
401 .read = sof_io_read,
402 .write64 = sof_io_write64,
403 .read64 = sof_io_read64,
404
405 /* ipc */
406 .send_msg = mtk_adsp_send_msg,
407 .get_mailbox_offset = mt8186_get_mailbox_offset,
408 .get_window_offset = mt8186_get_window_offset,
409 .ipc_msg_data = sof_ipc_msg_data,
410 .set_stream_data_offset = sof_set_stream_data_offset,
411
412 /* misc */
413 .get_bar_index = mtk_adsp_get_bar_index,
414
415 /* stream callbacks */
416 .pcm_open = sof_stream_pcm_open,
417 .pcm_hw_params = mtk_adsp_stream_pcm_hw_params,
418 .pcm_pointer = mtk_adsp_stream_pcm_pointer,
419 .pcm_close = sof_stream_pcm_close,
420
421 /* firmware loading */
422 .load_firmware = snd_sof_load_firmware_memcpy,
423
424 /* Firmware ops */
425 .dsp_arch_ops = &sof_xtensa_arch_ops,
426
427 /* DAI drivers */
428 .drv = mt8186_dai,
429 .num_drv = ARRAY_SIZE(mt8186_dai),
430
431 /* Debug information */
432 .dbg_dump = mt8186_adsp_dump,
433 .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
434
435 /* PM */
436 .suspend = mt8186_dsp_suspend,
437 .resume = mt8186_dsp_resume,
438
439 /* ALSA HW info flags */
440 .hw_info = SNDRV_PCM_INFO_MMAP |
441 SNDRV_PCM_INFO_MMAP_VALID |
442 SNDRV_PCM_INFO_INTERLEAVED |
443 SNDRV_PCM_INFO_PAUSE |
444 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
445 };
446
447 static struct snd_sof_of_mach sof_mt8186_machs[] = {
448 {
449 .compatible = "mediatek,mt8186",
450 .sof_tplg_filename = "sof-mt8186.tplg",
451 },
452 {}
453 };
454
455 static const struct sof_dev_desc sof_of_mt8186_desc = {
456 .of_machines = sof_mt8186_machs,
457 .ipc_supported_mask = BIT(SOF_IPC_TYPE_3),
458 .ipc_default = SOF_IPC_TYPE_3,
459 .default_fw_path = {
460 [SOF_IPC_TYPE_3] = "mediatek/sof",
461 },
462 .default_tplg_path = {
463 [SOF_IPC_TYPE_3] = "mediatek/sof-tplg",
464 },
465 .default_fw_filename = {
466 [SOF_IPC_TYPE_3] = "sof-mt8186.ri",
467 },
468 .nocodec_tplg_filename = "sof-mt8186-nocodec.tplg",
469 .ops = &sof_mt8186_ops,
470 };
471
472 /*
473 * DL2, DL3, UL4, UL5 are registered as SOF FE, so creating the corresponding
474 * SOF BE to complete the pipeline.
475 */
476 static struct snd_soc_dai_driver mt8188_dai[] = {
477 {
478 .name = "SOF_DL2",
479 .playback = {
480 .channels_min = 1,
481 .channels_max = 2,
482 },
483 },
484 {
485 .name = "SOF_DL3",
486 .playback = {
487 .channels_min = 1,
488 .channels_max = 2,
489 },
490 },
491 {
492 .name = "SOF_UL4",
493 .capture = {
494 .channels_min = 1,
495 .channels_max = 2,
496 },
497 },
498 {
499 .name = "SOF_UL5",
500 .capture = {
501 .channels_min = 1,
502 .channels_max = 2,
503 },
504 },
505 };
506
507 /* mt8188 ops */
508 static struct snd_sof_dsp_ops sof_mt8188_ops;
509
sof_mt8188_ops_init(struct snd_sof_dev * sdev)510 static int sof_mt8188_ops_init(struct snd_sof_dev *sdev)
511 {
512 /* common defaults */
513 memcpy(&sof_mt8188_ops, &sof_mt8186_ops, sizeof(sof_mt8188_ops));
514
515 sof_mt8188_ops.drv = mt8188_dai;
516 sof_mt8188_ops.num_drv = ARRAY_SIZE(mt8188_dai);
517
518 return 0;
519 }
520
521 static struct snd_sof_of_mach sof_mt8188_machs[] = {
522 {
523 .compatible = "mediatek,mt8188",
524 .sof_tplg_filename = "sof-mt8188.tplg",
525 },
526 {}
527 };
528
529 static const struct sof_dev_desc sof_of_mt8188_desc = {
530 .of_machines = sof_mt8188_machs,
531 .ipc_supported_mask = BIT(SOF_IPC_TYPE_3),
532 .ipc_default = SOF_IPC_TYPE_3,
533 .default_fw_path = {
534 [SOF_IPC_TYPE_3] = "mediatek/sof",
535 },
536 .default_tplg_path = {
537 [SOF_IPC_TYPE_3] = "mediatek/sof-tplg",
538 },
539 .default_fw_filename = {
540 [SOF_IPC_TYPE_3] = "sof-mt8188.ri",
541 },
542 .nocodec_tplg_filename = "sof-mt8188-nocodec.tplg",
543 .ops = &sof_mt8188_ops,
544 .ops_init = sof_mt8188_ops_init,
545 };
546
547 static const struct of_device_id sof_of_mt8186_ids[] = {
548 { .compatible = "mediatek,mt8186-dsp", .data = &sof_of_mt8186_desc},
549 { .compatible = "mediatek,mt8188-dsp", .data = &sof_of_mt8188_desc},
550 { }
551 };
552 MODULE_DEVICE_TABLE(of, sof_of_mt8186_ids);
553
554 /* DT driver definition */
555 static struct platform_driver snd_sof_of_mt8186_driver = {
556 .probe = sof_of_probe,
557 .remove = sof_of_remove,
558 .shutdown = sof_of_shutdown,
559 .driver = {
560 .name = "sof-audio-of-mt8186",
561 .pm = pm_ptr(&sof_of_pm),
562 .of_match_table = sof_of_mt8186_ids,
563 },
564 };
565 module_platform_driver(snd_sof_of_mt8186_driver);
566
567 MODULE_LICENSE("Dual BSD/GPL");
568 MODULE_DESCRIPTION("SOF support for MT8186/MT8188 platforms");
569 MODULE_IMPORT_NS("SND_SOC_SOF_XTENSA");
570 MODULE_IMPORT_NS("SND_SOC_SOF_MTK_COMMON");
571