1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Mediatek ALSA SoC AFE platform driver for 8183
4 //
5 // Copyright (c) 2018 MediaTek Inc.
6 // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
7
8 #include <linux/delay.h>
9 #include <linux/module.h>
10 #include <linux/mfd/syscon.h>
11 #include <linux/of.h>
12 #include <linux/of_address.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/reset.h>
15
16 #include "mt8183-afe-common.h"
17 #include "mt8183-afe-clk.h"
18 #include "mt8183-interconnection.h"
19 #include "mt8183-reg.h"
20 #include "../common/mtk-afe-platform-driver.h"
21 #include "../common/mtk-afe-fe-dai.h"
22
23 enum {
24 MTK_AFE_RATE_8K = 0,
25 MTK_AFE_RATE_11K = 1,
26 MTK_AFE_RATE_12K = 2,
27 MTK_AFE_RATE_384K = 3,
28 MTK_AFE_RATE_16K = 4,
29 MTK_AFE_RATE_22K = 5,
30 MTK_AFE_RATE_24K = 6,
31 MTK_AFE_RATE_130K = 7,
32 MTK_AFE_RATE_32K = 8,
33 MTK_AFE_RATE_44K = 9,
34 MTK_AFE_RATE_48K = 10,
35 MTK_AFE_RATE_88K = 11,
36 MTK_AFE_RATE_96K = 12,
37 MTK_AFE_RATE_176K = 13,
38 MTK_AFE_RATE_192K = 14,
39 MTK_AFE_RATE_260K = 15,
40 };
41
42 enum {
43 MTK_AFE_DAI_MEMIF_RATE_8K = 0,
44 MTK_AFE_DAI_MEMIF_RATE_16K = 1,
45 MTK_AFE_DAI_MEMIF_RATE_32K = 2,
46 MTK_AFE_DAI_MEMIF_RATE_48K = 3,
47 };
48
49 enum {
50 MTK_AFE_PCM_RATE_8K = 0,
51 MTK_AFE_PCM_RATE_16K = 1,
52 MTK_AFE_PCM_RATE_32K = 2,
53 MTK_AFE_PCM_RATE_48K = 3,
54 };
55
mt8183_general_rate_transform(struct device * dev,unsigned int rate)56 unsigned int mt8183_general_rate_transform(struct device *dev,
57 unsigned int rate)
58 {
59 switch (rate) {
60 case 8000:
61 return MTK_AFE_RATE_8K;
62 case 11025:
63 return MTK_AFE_RATE_11K;
64 case 12000:
65 return MTK_AFE_RATE_12K;
66 case 16000:
67 return MTK_AFE_RATE_16K;
68 case 22050:
69 return MTK_AFE_RATE_22K;
70 case 24000:
71 return MTK_AFE_RATE_24K;
72 case 32000:
73 return MTK_AFE_RATE_32K;
74 case 44100:
75 return MTK_AFE_RATE_44K;
76 case 48000:
77 return MTK_AFE_RATE_48K;
78 case 88200:
79 return MTK_AFE_RATE_88K;
80 case 96000:
81 return MTK_AFE_RATE_96K;
82 case 130000:
83 return MTK_AFE_RATE_130K;
84 case 176400:
85 return MTK_AFE_RATE_176K;
86 case 192000:
87 return MTK_AFE_RATE_192K;
88 case 260000:
89 return MTK_AFE_RATE_260K;
90 default:
91 dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n",
92 __func__, rate, MTK_AFE_RATE_48K);
93 return MTK_AFE_RATE_48K;
94 }
95 }
96
dai_memif_rate_transform(struct device * dev,unsigned int rate)97 static unsigned int dai_memif_rate_transform(struct device *dev,
98 unsigned int rate)
99 {
100 switch (rate) {
101 case 8000:
102 return MTK_AFE_DAI_MEMIF_RATE_8K;
103 case 16000:
104 return MTK_AFE_DAI_MEMIF_RATE_16K;
105 case 32000:
106 return MTK_AFE_DAI_MEMIF_RATE_32K;
107 case 48000:
108 return MTK_AFE_DAI_MEMIF_RATE_48K;
109 default:
110 dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n",
111 __func__, rate, MTK_AFE_DAI_MEMIF_RATE_16K);
112 return MTK_AFE_DAI_MEMIF_RATE_16K;
113 }
114 }
115
mt8183_rate_transform(struct device * dev,unsigned int rate,int aud_blk)116 unsigned int mt8183_rate_transform(struct device *dev,
117 unsigned int rate, int aud_blk)
118 {
119 switch (aud_blk) {
120 case MT8183_MEMIF_MOD_DAI:
121 return dai_memif_rate_transform(dev, rate);
122 default:
123 return mt8183_general_rate_transform(dev, rate);
124 }
125 }
126
127 static const struct snd_pcm_hardware mt8183_afe_hardware = {
128 .info = SNDRV_PCM_INFO_MMAP |
129 SNDRV_PCM_INFO_INTERLEAVED |
130 SNDRV_PCM_INFO_MMAP_VALID,
131 .formats = SNDRV_PCM_FMTBIT_S16_LE |
132 SNDRV_PCM_FMTBIT_S24_LE |
133 SNDRV_PCM_FMTBIT_S32_LE,
134 .period_bytes_min = 256,
135 .period_bytes_max = 4 * 48 * 1024,
136 .periods_min = 2,
137 .periods_max = 256,
138 .buffer_bytes_max = 8 * 48 * 1024,
139 .fifo_size = 0,
140 };
141
mt8183_memif_fs(struct snd_pcm_substream * substream,unsigned int rate)142 static int mt8183_memif_fs(struct snd_pcm_substream *substream,
143 unsigned int rate)
144 {
145 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
146 struct snd_soc_component *component =
147 snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
148 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
149 int id = snd_soc_rtd_to_cpu(rtd, 0)->id;
150
151 return mt8183_rate_transform(afe->dev, rate, id);
152 }
153
mt8183_irq_fs(struct snd_pcm_substream * substream,unsigned int rate)154 static int mt8183_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
155 {
156 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
157 struct snd_soc_component *component =
158 snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
159 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
160
161 return mt8183_general_rate_transform(afe->dev, rate);
162 }
163
164 #define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\
165 SNDRV_PCM_RATE_88200 |\
166 SNDRV_PCM_RATE_96000 |\
167 SNDRV_PCM_RATE_176400 |\
168 SNDRV_PCM_RATE_192000)
169
170 #define MTK_PCM_DAI_RATES (SNDRV_PCM_RATE_8000 |\
171 SNDRV_PCM_RATE_16000 |\
172 SNDRV_PCM_RATE_32000 |\
173 SNDRV_PCM_RATE_48000)
174
175 #define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
176 SNDRV_PCM_FMTBIT_S24_LE |\
177 SNDRV_PCM_FMTBIT_S32_LE)
178
179 static struct snd_soc_dai_driver mt8183_memif_dai_driver[] = {
180 /* FE DAIs: memory intefaces to CPU */
181 {
182 .name = "DL1",
183 .id = MT8183_MEMIF_DL1,
184 .playback = {
185 .stream_name = "DL1",
186 .channels_min = 1,
187 .channels_max = 2,
188 .rates = MTK_PCM_RATES,
189 .formats = MTK_PCM_FORMATS,
190 },
191 .ops = &mtk_afe_fe_ops,
192 },
193 {
194 .name = "DL2",
195 .id = MT8183_MEMIF_DL2,
196 .playback = {
197 .stream_name = "DL2",
198 .channels_min = 1,
199 .channels_max = 2,
200 .rates = MTK_PCM_RATES,
201 .formats = MTK_PCM_FORMATS,
202 },
203 .ops = &mtk_afe_fe_ops,
204 },
205 {
206 .name = "DL3",
207 .id = MT8183_MEMIF_DL3,
208 .playback = {
209 .stream_name = "DL3",
210 .channels_min = 1,
211 .channels_max = 2,
212 .rates = MTK_PCM_RATES,
213 .formats = MTK_PCM_FORMATS,
214 },
215 .ops = &mtk_afe_fe_ops,
216 },
217 {
218 .name = "UL1",
219 .id = MT8183_MEMIF_VUL12,
220 .capture = {
221 .stream_name = "UL1",
222 .channels_min = 1,
223 .channels_max = 2,
224 .rates = MTK_PCM_RATES,
225 .formats = MTK_PCM_FORMATS,
226 },
227 .ops = &mtk_afe_fe_ops,
228 },
229 {
230 .name = "UL2",
231 .id = MT8183_MEMIF_AWB,
232 .capture = {
233 .stream_name = "UL2",
234 .channels_min = 1,
235 .channels_max = 2,
236 .rates = MTK_PCM_RATES,
237 .formats = MTK_PCM_FORMATS,
238 },
239 .ops = &mtk_afe_fe_ops,
240 },
241 {
242 .name = "UL3",
243 .id = MT8183_MEMIF_VUL2,
244 .capture = {
245 .stream_name = "UL3",
246 .channels_min = 1,
247 .channels_max = 2,
248 .rates = MTK_PCM_RATES,
249 .formats = MTK_PCM_FORMATS,
250 },
251 .ops = &mtk_afe_fe_ops,
252 },
253 {
254 .name = "UL4",
255 .id = MT8183_MEMIF_AWB2,
256 .capture = {
257 .stream_name = "UL4",
258 .channels_min = 1,
259 .channels_max = 2,
260 .rates = MTK_PCM_RATES,
261 .formats = MTK_PCM_FORMATS,
262 },
263 .ops = &mtk_afe_fe_ops,
264 },
265 {
266 .name = "UL_MONO_1",
267 .id = MT8183_MEMIF_MOD_DAI,
268 .capture = {
269 .stream_name = "UL_MONO_1",
270 .channels_min = 1,
271 .channels_max = 1,
272 .rates = MTK_PCM_DAI_RATES,
273 .formats = MTK_PCM_FORMATS,
274 },
275 .ops = &mtk_afe_fe_ops,
276 },
277 {
278 .name = "HDMI",
279 .id = MT8183_MEMIF_HDMI,
280 .playback = {
281 .stream_name = "HDMI",
282 .channels_min = 2,
283 .channels_max = 8,
284 .rates = MTK_PCM_RATES,
285 .formats = MTK_PCM_FORMATS,
286 },
287 .ops = &mtk_afe_fe_ops,
288 },
289 };
290
291 /* dma widget & routes*/
292 static const struct snd_kcontrol_new memif_ul1_ch1_mix[] = {
293 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN21,
294 I_ADDA_UL_CH1, 1, 0),
295 SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1", AFE_CONN21,
296 I_I2S0_CH1, 1, 0),
297 };
298
299 static const struct snd_kcontrol_new memif_ul1_ch2_mix[] = {
300 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN22,
301 I_ADDA_UL_CH2, 1, 0),
302 SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2", AFE_CONN21,
303 I_I2S0_CH2, 1, 0),
304 };
305
306 static const struct snd_kcontrol_new memif_ul2_ch1_mix[] = {
307 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN5,
308 I_ADDA_UL_CH1, 1, 0),
309 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN5,
310 I_DL1_CH1, 1, 0),
311 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN5,
312 I_DL2_CH1, 1, 0),
313 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN5,
314 I_DL3_CH1, 1, 0),
315 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1", AFE_CONN5,
316 I_I2S2_CH1, 1, 0),
317 };
318
319 static const struct snd_kcontrol_new memif_ul2_ch2_mix[] = {
320 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN6,
321 I_ADDA_UL_CH2, 1, 0),
322 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN6,
323 I_DL1_CH2, 1, 0),
324 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN6,
325 I_DL2_CH2, 1, 0),
326 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN6,
327 I_DL3_CH2, 1, 0),
328 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2", AFE_CONN6,
329 I_I2S2_CH2, 1, 0),
330 };
331
332 static const struct snd_kcontrol_new memif_ul3_ch1_mix[] = {
333 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN32,
334 I_ADDA_UL_CH1, 1, 0),
335 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1", AFE_CONN32,
336 I_I2S2_CH1, 1, 0),
337 };
338
339 static const struct snd_kcontrol_new memif_ul3_ch2_mix[] = {
340 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN33,
341 I_ADDA_UL_CH2, 1, 0),
342 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2", AFE_CONN33,
343 I_I2S2_CH2, 1, 0),
344 };
345
346 static const struct snd_kcontrol_new memif_ul4_ch1_mix[] = {
347 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN38,
348 I_ADDA_UL_CH1, 1, 0),
349 };
350
351 static const struct snd_kcontrol_new memif_ul4_ch2_mix[] = {
352 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN39,
353 I_ADDA_UL_CH2, 1, 0),
354 };
355
356 static const struct snd_kcontrol_new memif_ul_mono_1_mix[] = {
357 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN12,
358 I_ADDA_UL_CH1, 1, 0),
359 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN12,
360 I_ADDA_UL_CH2, 1, 0),
361 };
362
363 static const struct snd_soc_dapm_widget mt8183_memif_widgets[] = {
364 /* memif */
365 SND_SOC_DAPM_MIXER("UL1_CH1", SND_SOC_NOPM, 0, 0,
366 memif_ul1_ch1_mix, ARRAY_SIZE(memif_ul1_ch1_mix)),
367 SND_SOC_DAPM_MIXER("UL1_CH2", SND_SOC_NOPM, 0, 0,
368 memif_ul1_ch2_mix, ARRAY_SIZE(memif_ul1_ch2_mix)),
369
370 SND_SOC_DAPM_MIXER("UL2_CH1", SND_SOC_NOPM, 0, 0,
371 memif_ul2_ch1_mix, ARRAY_SIZE(memif_ul2_ch1_mix)),
372 SND_SOC_DAPM_MIXER("UL2_CH2", SND_SOC_NOPM, 0, 0,
373 memif_ul2_ch2_mix, ARRAY_SIZE(memif_ul2_ch2_mix)),
374
375 SND_SOC_DAPM_MIXER("UL3_CH1", SND_SOC_NOPM, 0, 0,
376 memif_ul3_ch1_mix, ARRAY_SIZE(memif_ul3_ch1_mix)),
377 SND_SOC_DAPM_MIXER("UL3_CH2", SND_SOC_NOPM, 0, 0,
378 memif_ul3_ch2_mix, ARRAY_SIZE(memif_ul3_ch2_mix)),
379
380 SND_SOC_DAPM_MIXER("UL4_CH1", SND_SOC_NOPM, 0, 0,
381 memif_ul4_ch1_mix, ARRAY_SIZE(memif_ul4_ch1_mix)),
382 SND_SOC_DAPM_MIXER("UL4_CH2", SND_SOC_NOPM, 0, 0,
383 memif_ul4_ch2_mix, ARRAY_SIZE(memif_ul4_ch2_mix)),
384
385 SND_SOC_DAPM_MIXER("UL_MONO_1_CH1", SND_SOC_NOPM, 0, 0,
386 memif_ul_mono_1_mix,
387 ARRAY_SIZE(memif_ul_mono_1_mix)),
388 };
389
390 static const struct snd_soc_dapm_route mt8183_memif_routes[] = {
391 /* capture */
392 {"UL1", NULL, "UL1_CH1"},
393 {"UL1", NULL, "UL1_CH2"},
394 {"UL1_CH1", "ADDA_UL_CH1", "ADDA Capture"},
395 {"UL1_CH2", "ADDA_UL_CH2", "ADDA Capture"},
396 {"UL1_CH1", "I2S0_CH1", "I2S0"},
397 {"UL1_CH2", "I2S0_CH2", "I2S0"},
398
399 {"UL2", NULL, "UL2_CH1"},
400 {"UL2", NULL, "UL2_CH2"},
401 {"UL2_CH1", "ADDA_UL_CH1", "ADDA Capture"},
402 {"UL2_CH2", "ADDA_UL_CH2", "ADDA Capture"},
403 {"UL2_CH1", "I2S2_CH1", "I2S2"},
404 {"UL2_CH2", "I2S2_CH2", "I2S2"},
405
406 {"UL3", NULL, "UL3_CH1"},
407 {"UL3", NULL, "UL3_CH2"},
408 {"UL3_CH1", "ADDA_UL_CH1", "ADDA Capture"},
409 {"UL3_CH2", "ADDA_UL_CH2", "ADDA Capture"},
410 {"UL3_CH1", "I2S2_CH1", "I2S2"},
411 {"UL3_CH2", "I2S2_CH2", "I2S2"},
412
413 {"UL4", NULL, "UL4_CH1"},
414 {"UL4", NULL, "UL4_CH2"},
415 {"UL4_CH1", "ADDA_UL_CH1", "ADDA Capture"},
416 {"UL4_CH2", "ADDA_UL_CH2", "ADDA Capture"},
417
418 {"UL_MONO_1", NULL, "UL_MONO_1_CH1"},
419 {"UL_MONO_1_CH1", "ADDA_UL_CH1", "ADDA Capture"},
420 {"UL_MONO_1_CH1", "ADDA_UL_CH2", "ADDA Capture"},
421 };
422
423 static const struct snd_soc_component_driver mt8183_afe_pcm_dai_component = {
424 .name = "mt8183-afe-pcm-dai",
425 };
426
427 #define MT8183_MEMIF_BASE(_id, _en_reg, _fs_reg, _mono_reg) \
428 [MT8183_MEMIF_##_id] = { \
429 .name = #_id, \
430 .id = MT8183_MEMIF_##_id, \
431 .reg_ofs_base = AFE_##_id##_BASE, \
432 .reg_ofs_cur = AFE_##_id##_CUR, \
433 .reg_ofs_end = AFE_##_id##_END, \
434 .fs_reg = (_fs_reg), \
435 .fs_shift = _id##_MODE_SFT, \
436 .fs_maskbit = _id##_MODE_MASK, \
437 .mono_reg = (_mono_reg), \
438 .mono_shift = _id##_DATA_SFT, \
439 .enable_reg = (_en_reg), \
440 .enable_shift = _id##_ON_SFT, \
441 .hd_reg = AFE_MEMIF_HD_MODE, \
442 .hd_align_reg = AFE_MEMIF_HDALIGN, \
443 .hd_shift = _id##_HD_SFT, \
444 .hd_align_mshift = _id##_HD_ALIGN_SFT, \
445 .agent_disable_reg = -1, \
446 .agent_disable_shift = -1, \
447 .msb_reg = -1, \
448 .msb_shift = -1, \
449 }
450
451 #define MT8183_MEMIF(_id, _fs_reg, _mono_reg) \
452 MT8183_MEMIF_BASE(_id, AFE_DAC_CON0, _fs_reg, _mono_reg)
453
454 /* For convenience with macros: missing register fields */
455 #define MOD_DAI_DATA_SFT -1
456 #define HDMI_MODE_SFT -1
457 #define HDMI_MODE_MASK -1
458 #define HDMI_DATA_SFT -1
459 #define HDMI_ON_SFT -1
460
461 /* For convenience with macros: register name differences */
462 #define AFE_VUL12_BASE AFE_VUL_D2_BASE
463 #define AFE_VUL12_CUR AFE_VUL_D2_CUR
464 #define AFE_VUL12_END AFE_VUL_D2_END
465 #define AWB2_HD_ALIGN_SFT AWB2_ALIGN_SFT
466 #define VUL12_DATA_SFT VUL12_MONO_SFT
467 #define AFE_HDMI_BASE AFE_HDMI_OUT_BASE
468 #define AFE_HDMI_CUR AFE_HDMI_OUT_CUR
469 #define AFE_HDMI_END AFE_HDMI_OUT_END
470
471 static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = {
472 MT8183_MEMIF(DL1, AFE_DAC_CON1, AFE_DAC_CON1),
473 MT8183_MEMIF(DL2, AFE_DAC_CON1, AFE_DAC_CON1),
474 MT8183_MEMIF(DL3, AFE_DAC_CON2, AFE_DAC_CON1),
475 MT8183_MEMIF(VUL2, AFE_DAC_CON2, AFE_DAC_CON2),
476 MT8183_MEMIF(AWB, AFE_DAC_CON1, AFE_DAC_CON1),
477 MT8183_MEMIF(AWB2, AFE_DAC_CON2, AFE_DAC_CON2),
478 MT8183_MEMIF(VUL12, AFE_DAC_CON0, AFE_DAC_CON0),
479 MT8183_MEMIF(MOD_DAI, AFE_DAC_CON1, -1),
480 /* enable control in tdm for sync start */
481 MT8183_MEMIF_BASE(HDMI, -1, -1, -1),
482 };
483
484 #define MT8183_AFE_IRQ_BASE(_id, _fs_reg, _fs_shift, _fs_maskbit) \
485 [MT8183_IRQ_##_id] = { \
486 .id = MT8183_IRQ_##_id, \
487 .irq_cnt_reg = AFE_IRQ_MCU_CNT##_id, \
488 .irq_cnt_shift = 0, \
489 .irq_cnt_maskbit = 0x3ffff, \
490 .irq_fs_reg = _fs_reg, \
491 .irq_fs_shift = _fs_shift, \
492 .irq_fs_maskbit = _fs_maskbit, \
493 .irq_en_reg = AFE_IRQ_MCU_CON0, \
494 .irq_en_shift = IRQ##_id##_MCU_ON_SFT, \
495 .irq_clr_reg = AFE_IRQ_MCU_CLR, \
496 .irq_clr_shift = IRQ##_id##_MCU_CLR_SFT, \
497 }
498
499 #define MT8183_AFE_IRQ(_id) \
500 MT8183_AFE_IRQ_BASE(_id, AFE_IRQ_MCU_CON1 + _id / 8 * 4, \
501 IRQ##_id##_MCU_MODE_SFT, \
502 IRQ##_id##_MCU_MODE_MASK)
503
504 #define MT8183_AFE_IRQ_NOFS(_id) MT8183_AFE_IRQ_BASE(_id, -1, -1, -1)
505
506 static const struct mtk_base_irq_data irq_data[MT8183_IRQ_NUM] = {
507 MT8183_AFE_IRQ(0),
508 MT8183_AFE_IRQ(1),
509 MT8183_AFE_IRQ(2),
510 MT8183_AFE_IRQ(3),
511 MT8183_AFE_IRQ(4),
512 MT8183_AFE_IRQ(5),
513 MT8183_AFE_IRQ(6),
514 MT8183_AFE_IRQ(7),
515 MT8183_AFE_IRQ_NOFS(8),
516 MT8183_AFE_IRQ(11),
517 MT8183_AFE_IRQ(12),
518 };
519
mt8183_is_volatile_reg(struct device * dev,unsigned int reg)520 static bool mt8183_is_volatile_reg(struct device *dev, unsigned int reg)
521 {
522 /* these auto-gen reg has read-only bit, so put it as volatile */
523 /* volatile reg cannot be cached, so cannot be set when power off */
524 switch (reg) {
525 case AUDIO_TOP_CON0 ... AUDIO_TOP_CON1: /* reg bit controlled by CCF */
526 case AUDIO_TOP_CON3:
527 case AFE_DL1_CUR ... AFE_DL1_END:
528 case AFE_DL2_CUR ... AFE_DL2_END:
529 case AFE_AWB_END ... AFE_AWB_CUR:
530 case AFE_VUL_END ... AFE_VUL_CUR:
531 case AFE_MEMIF_MON0 ... AFE_MEMIF_MON9:
532 case AFE_ADDA_SRC_DEBUG_MON0 ... AFE_ADDA_SRC_DEBUG_MON1:
533 case AFE_ADDA_UL_SRC_MON0 ... AFE_ADDA_UL_SRC_MON1:
534 case AFE_SIDETONE_MON:
535 case AFE_SIDETONE_CON0 ... AFE_SIDETONE_COEFF:
536 case AFE_BUS_MON0:
537 case AFE_MRGIF_MON0 ... AFE_I2S_MON:
538 case AFE_DAC_MON:
539 case AFE_VUL2_END ... AFE_VUL2_CUR:
540 case AFE_IRQ0_MCU_CNT_MON ... AFE_IRQ6_MCU_CNT_MON:
541 case AFE_MOD_DAI_END ... AFE_MOD_DAI_CUR:
542 case AFE_VUL_D2_END ... AFE_VUL_D2_CUR:
543 case AFE_DL3_CUR ... AFE_DL3_END:
544 case AFE_HDMI_OUT_CON0:
545 case AFE_HDMI_OUT_CUR ... AFE_HDMI_OUT_END:
546 case AFE_IRQ3_MCU_CNT_MON... AFE_IRQ4_MCU_CNT_MON:
547 case AFE_IRQ_MCU_STATUS ... AFE_IRQ_MCU_CLR:
548 case AFE_IRQ_MCU_MON2:
549 case AFE_IRQ1_MCU_CNT_MON ... AFE_IRQ5_MCU_CNT_MON:
550 case AFE_IRQ7_MCU_CNT_MON:
551 case AFE_GAIN1_CUR:
552 case AFE_GAIN2_CUR:
553 case AFE_SRAM_DELSEL_CON0:
554 case AFE_SRAM_DELSEL_CON2 ... AFE_SRAM_DELSEL_CON3:
555 case AFE_ASRC_2CH_CON12 ... AFE_ASRC_2CH_CON13:
556 case PCM_INTF_CON2:
557 case FPGA_CFG0 ... FPGA_CFG1:
558 case FPGA_CFG2 ... FPGA_CFG3:
559 case AUDIO_TOP_DBG_MON0 ... AUDIO_TOP_DBG_MON1:
560 case AFE_IRQ8_MCU_CNT_MON ... AFE_IRQ12_MCU_CNT_MON:
561 case AFE_CBIP_MON0:
562 case AFE_CBIP_SLV_MUX_MON0 ... AFE_CBIP_SLV_DECODER_MON0:
563 case AFE_ADDA6_SRC_DEBUG_MON0:
564 case AFE_ADD6A_UL_SRC_MON0... AFE_ADDA6_UL_SRC_MON1:
565 case AFE_DL1_CUR_MSB:
566 case AFE_DL2_CUR_MSB:
567 case AFE_AWB_CUR_MSB:
568 case AFE_VUL_CUR_MSB:
569 case AFE_VUL2_CUR_MSB:
570 case AFE_MOD_DAI_CUR_MSB:
571 case AFE_VUL_D2_CUR_MSB:
572 case AFE_DL3_CUR_MSB:
573 case AFE_HDMI_OUT_CUR_MSB:
574 case AFE_AWB2_END ... AFE_AWB2_CUR:
575 case AFE_AWB2_CUR_MSB:
576 case AFE_ADDA_DL_SDM_FIFO_MON ... AFE_ADDA_DL_SDM_OUT_MON:
577 case AFE_CONNSYS_I2S_MON ... AFE_ASRC_2CH_CON0:
578 case AFE_ASRC_2CH_CON2 ... AFE_ASRC_2CH_CON5:
579 case AFE_ASRC_2CH_CON7 ... AFE_ASRC_2CH_CON8:
580 case AFE_MEMIF_MON12 ... AFE_MEMIF_MON24:
581 case AFE_ADDA_MTKAIF_MON0 ... AFE_ADDA_MTKAIF_MON1:
582 case AFE_AUD_PAD_TOP:
583 case AFE_GENERAL1_ASRC_2CH_CON0:
584 case AFE_GENERAL1_ASRC_2CH_CON2 ... AFE_GENERAL1_ASRC_2CH_CON5:
585 case AFE_GENERAL1_ASRC_2CH_CON7 ... AFE_GENERAL1_ASRC_2CH_CON8:
586 case AFE_GENERAL1_ASRC_2CH_CON12 ... AFE_GENERAL1_ASRC_2CH_CON13:
587 case AFE_GENERAL2_ASRC_2CH_CON0:
588 case AFE_GENERAL2_ASRC_2CH_CON2 ... AFE_GENERAL2_ASRC_2CH_CON5:
589 case AFE_GENERAL2_ASRC_2CH_CON7 ... AFE_GENERAL2_ASRC_2CH_CON8:
590 case AFE_GENERAL2_ASRC_2CH_CON12 ... AFE_GENERAL2_ASRC_2CH_CON13:
591 return true;
592 default:
593 return false;
594 };
595 }
596
597 static const struct regmap_config mt8183_afe_regmap_config = {
598 .reg_bits = 32,
599 .reg_stride = 4,
600 .val_bits = 32,
601
602 .volatile_reg = mt8183_is_volatile_reg,
603
604 .max_register = AFE_MAX_REGISTER,
605 .num_reg_defaults_raw = AFE_MAX_REGISTER,
606
607 .cache_type = REGCACHE_FLAT,
608 };
609
mt8183_afe_irq_handler(int irq_id,void * dev)610 static irqreturn_t mt8183_afe_irq_handler(int irq_id, void *dev)
611 {
612 struct mtk_base_afe *afe = dev;
613 struct mtk_base_afe_irq *irq;
614 unsigned int status;
615 unsigned int status_mcu;
616 unsigned int mcu_en;
617 int ret;
618 int i;
619 irqreturn_t irq_ret = IRQ_HANDLED;
620
621 /* get irq that is sent to MCU */
622 regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en);
623
624 ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status);
625 /* only care IRQ which is sent to MCU */
626 status_mcu = status & mcu_en & AFE_IRQ_STATUS_BITS;
627
628 if (ret || status_mcu == 0) {
629 dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n",
630 __func__, ret, status, mcu_en);
631
632 irq_ret = IRQ_NONE;
633 goto err_irq;
634 }
635
636 for (i = 0; i < MT8183_MEMIF_NUM; i++) {
637 struct mtk_base_afe_memif *memif = &afe->memif[i];
638
639 if (!memif->substream)
640 continue;
641
642 if (memif->irq_usage < 0)
643 continue;
644
645 irq = &afe->irqs[memif->irq_usage];
646
647 if (status_mcu & (1 << irq->irq_data->irq_en_shift))
648 snd_pcm_period_elapsed(memif->substream);
649 }
650
651 err_irq:
652 /* clear irq */
653 regmap_write(afe->regmap,
654 AFE_IRQ_MCU_CLR,
655 status_mcu);
656
657 return irq_ret;
658 }
659
mt8183_afe_runtime_suspend(struct device * dev)660 static int mt8183_afe_runtime_suspend(struct device *dev)
661 {
662 struct mtk_base_afe *afe = dev_get_drvdata(dev);
663 struct mt8183_afe_private *afe_priv = afe->platform_priv;
664 unsigned int value;
665 int ret;
666
667 if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
668 goto skip_regmap;
669
670 /* disable AFE */
671 regmap_update_bits(afe->regmap, AFE_DAC_CON0, AFE_ON_MASK_SFT, 0x0);
672
673 ret = regmap_read_poll_timeout(afe->regmap,
674 AFE_DAC_MON,
675 value,
676 (value & AFE_ON_RETM_MASK_SFT) == 0,
677 20,
678 1 * 1000 * 1000);
679 if (ret)
680 dev_warn(afe->dev, "%s(), ret %d\n", __func__, ret);
681
682 /* make sure all irq status are cleared, twice intended */
683 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff);
684 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff);
685
686 /* cache only */
687 regcache_cache_only(afe->regmap, true);
688 regcache_mark_dirty(afe->regmap);
689
690 skip_regmap:
691 return mt8183_afe_disable_clock(afe);
692 }
693
mt8183_afe_runtime_resume(struct device * dev)694 static int mt8183_afe_runtime_resume(struct device *dev)
695 {
696 struct mtk_base_afe *afe = dev_get_drvdata(dev);
697 struct mt8183_afe_private *afe_priv = afe->platform_priv;
698 int ret;
699
700 ret = mt8183_afe_enable_clock(afe);
701 if (ret)
702 return ret;
703
704 if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
705 goto skip_regmap;
706
707 regcache_cache_only(afe->regmap, false);
708 regcache_sync(afe->regmap);
709
710 /* enable audio sys DCM for power saving */
711 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 0x1 << 29, 0x1 << 29);
712
713 /* force cpu use 8_24 format when writing 32bit data */
714 regmap_update_bits(afe->regmap, AFE_MEMIF_MSB,
715 CPU_HD_ALIGN_MASK_SFT, 0 << CPU_HD_ALIGN_SFT);
716
717 /* set all output port to 24bit */
718 regmap_write(afe->regmap, AFE_CONN_24BIT, 0xffffffff);
719 regmap_write(afe->regmap, AFE_CONN_24BIT_1, 0xffffffff);
720
721 /* enable AFE */
722 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
723
724 skip_regmap:
725 return 0;
726 }
727
mt8183_dai_memif_register(struct mtk_base_afe * afe)728 static int mt8183_dai_memif_register(struct mtk_base_afe *afe)
729 {
730 struct mtk_base_afe_dai *dai;
731
732 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
733 if (!dai)
734 return -ENOMEM;
735
736 list_add(&dai->list, &afe->sub_dais);
737
738 dai->dai_drivers = mt8183_memif_dai_driver;
739 dai->num_dai_drivers = ARRAY_SIZE(mt8183_memif_dai_driver);
740
741 dai->dapm_widgets = mt8183_memif_widgets;
742 dai->num_dapm_widgets = ARRAY_SIZE(mt8183_memif_widgets);
743 dai->dapm_routes = mt8183_memif_routes;
744 dai->num_dapm_routes = ARRAY_SIZE(mt8183_memif_routes);
745 return 0;
746 }
747
748 typedef int (*dai_register_cb)(struct mtk_base_afe *);
749 static const dai_register_cb dai_register_cbs[] = {
750 mt8183_dai_adda_register,
751 mt8183_dai_i2s_register,
752 mt8183_dai_pcm_register,
753 mt8183_dai_tdm_register,
754 mt8183_dai_hostless_register,
755 mt8183_dai_memif_register,
756 };
757
mt8183_afe_pcm_dev_probe(struct platform_device * pdev)758 static int mt8183_afe_pcm_dev_probe(struct platform_device *pdev)
759 {
760 struct mtk_base_afe *afe;
761 struct mt8183_afe_private *afe_priv;
762 struct device *dev;
763 struct reset_control *rstc;
764 int i, irq_id, ret;
765
766 afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
767 if (!afe)
768 return -ENOMEM;
769 platform_set_drvdata(pdev, afe);
770
771 afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
772 GFP_KERNEL);
773 if (!afe->platform_priv)
774 return -ENOMEM;
775
776 afe_priv = afe->platform_priv;
777 afe->dev = &pdev->dev;
778 dev = afe->dev;
779
780 /* initial audio related clock */
781 ret = mt8183_init_clock(afe);
782 if (ret) {
783 dev_err(dev, "init clock error\n");
784 return ret;
785 }
786
787 pm_runtime_enable(dev);
788
789 /* regmap init */
790 afe->regmap = syscon_node_to_regmap(dev->parent->of_node);
791 if (IS_ERR(afe->regmap)) {
792 dev_err(dev, "could not get regmap from parent\n");
793 ret = PTR_ERR(afe->regmap);
794 goto err_pm_disable;
795 }
796 ret = regmap_attach_dev(dev, afe->regmap, &mt8183_afe_regmap_config);
797 if (ret) {
798 dev_warn(dev, "regmap_attach_dev fail, ret %d\n", ret);
799 goto err_pm_disable;
800 }
801
802 rstc = devm_reset_control_get(dev, "audiosys");
803 if (IS_ERR(rstc)) {
804 ret = PTR_ERR(rstc);
805 dev_err(dev, "could not get audiosys reset:%d\n", ret);
806 goto err_pm_disable;
807 }
808
809 ret = reset_control_reset(rstc);
810 if (ret) {
811 dev_err(dev, "failed to trigger audio reset:%d\n", ret);
812 goto err_pm_disable;
813 }
814
815 /* enable clock for regcache get default value from hw */
816 afe_priv->pm_runtime_bypass_reg_ctl = true;
817 pm_runtime_get_sync(&pdev->dev);
818
819 ret = regmap_reinit_cache(afe->regmap, &mt8183_afe_regmap_config);
820 if (ret) {
821 dev_err(dev, "regmap_reinit_cache fail, ret %d\n", ret);
822 goto err_pm_disable;
823 }
824
825 pm_runtime_put_sync(&pdev->dev);
826 afe_priv->pm_runtime_bypass_reg_ctl = false;
827
828 regcache_cache_only(afe->regmap, true);
829 regcache_mark_dirty(afe->regmap);
830
831 /* init memif */
832 afe->memif_size = MT8183_MEMIF_NUM;
833 afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
834 GFP_KERNEL);
835 if (!afe->memif) {
836 ret = -ENOMEM;
837 goto err_pm_disable;
838 }
839
840 for (i = 0; i < afe->memif_size; i++) {
841 afe->memif[i].data = &memif_data[i];
842 afe->memif[i].irq_usage = -1;
843 }
844
845 afe->memif[MT8183_MEMIF_HDMI].irq_usage = MT8183_IRQ_8;
846 afe->memif[MT8183_MEMIF_HDMI].const_irq = 1;
847
848 mutex_init(&afe->irq_alloc_lock);
849
850 /* init memif */
851 /* irq initialize */
852 afe->irqs_size = MT8183_IRQ_NUM;
853 afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
854 GFP_KERNEL);
855 if (!afe->irqs) {
856 ret = -ENOMEM;
857 goto err_pm_disable;
858 }
859
860 for (i = 0; i < afe->irqs_size; i++)
861 afe->irqs[i].irq_data = &irq_data[i];
862
863 /* request irq */
864 irq_id = platform_get_irq(pdev, 0);
865 if (irq_id < 0) {
866 ret = irq_id;
867 goto err_pm_disable;
868 }
869
870 ret = devm_request_irq(dev, irq_id, mt8183_afe_irq_handler,
871 IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
872 if (ret) {
873 dev_err(dev, "could not request_irq for asys-isr\n");
874 goto err_pm_disable;
875 }
876
877 /* init sub_dais */
878 INIT_LIST_HEAD(&afe->sub_dais);
879
880 for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
881 ret = dai_register_cbs[i](afe);
882 if (ret) {
883 dev_warn(afe->dev, "dai register i %d fail, ret %d\n",
884 i, ret);
885 goto err_pm_disable;
886 }
887 }
888
889 /* init dai_driver and component_driver */
890 ret = mtk_afe_combine_sub_dai(afe);
891 if (ret) {
892 dev_warn(afe->dev, "mtk_afe_combine_sub_dai fail, ret %d\n",
893 ret);
894 goto err_pm_disable;
895 }
896
897 afe->mtk_afe_hardware = &mt8183_afe_hardware;
898 afe->memif_fs = mt8183_memif_fs;
899 afe->irq_fs = mt8183_irq_fs;
900
901 afe->runtime_resume = mt8183_afe_runtime_resume;
902 afe->runtime_suspend = mt8183_afe_runtime_suspend;
903
904 /* register component */
905 ret = devm_snd_soc_register_component(&pdev->dev,
906 &mtk_afe_pcm_platform,
907 NULL, 0);
908 if (ret) {
909 dev_warn(dev, "err_platform\n");
910 goto err_pm_disable;
911 }
912
913 ret = devm_snd_soc_register_component(afe->dev,
914 &mt8183_afe_pcm_dai_component,
915 afe->dai_drivers,
916 afe->num_dai_drivers);
917 if (ret) {
918 dev_warn(dev, "err_dai_component\n");
919 goto err_pm_disable;
920 }
921
922 return ret;
923
924 err_pm_disable:
925 pm_runtime_disable(&pdev->dev);
926 return ret;
927 }
928
mt8183_afe_pcm_dev_remove(struct platform_device * pdev)929 static void mt8183_afe_pcm_dev_remove(struct platform_device *pdev)
930 {
931 pm_runtime_disable(&pdev->dev);
932 if (!pm_runtime_status_suspended(&pdev->dev))
933 mt8183_afe_runtime_suspend(&pdev->dev);
934 }
935
936 static const struct of_device_id mt8183_afe_pcm_dt_match[] = {
937 { .compatible = "mediatek,mt8183-audio", },
938 {},
939 };
940 MODULE_DEVICE_TABLE(of, mt8183_afe_pcm_dt_match);
941
942 static const struct dev_pm_ops mt8183_afe_pm_ops = {
943 RUNTIME_PM_OPS(mt8183_afe_runtime_suspend,
944 mt8183_afe_runtime_resume, NULL)
945 };
946
947 static struct platform_driver mt8183_afe_pcm_driver = {
948 .driver = {
949 .name = "mt8183-audio",
950 .of_match_table = mt8183_afe_pcm_dt_match,
951 .pm = pm_ptr(&mt8183_afe_pm_ops),
952 },
953 .probe = mt8183_afe_pcm_dev_probe,
954 .remove = mt8183_afe_pcm_dev_remove,
955 };
956
957 module_platform_driver(mt8183_afe_pcm_driver);
958
959 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 8183");
960 MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>");
961 MODULE_LICENSE("GPL v2");
962