1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Mediatek ALSA SoC AFE platform driver for 8183
4 //
5 // Copyright (c) 2018 MediaTek Inc.
6 // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
7
8 #include <linux/delay.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/module.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/of.h>
13 #include <linux/of_address.h>
14 #include <linux/of_reserved_mem.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/reset.h>
17
18 #include "mt8183-afe-common.h"
19 #include "mt8183-afe-clk.h"
20 #include "mt8183-interconnection.h"
21 #include "mt8183-reg.h"
22 #include "../common/mtk-afe-platform-driver.h"
23 #include "../common/mtk-afe-fe-dai.h"
24
25 enum {
26 MTK_AFE_RATE_8K = 0,
27 MTK_AFE_RATE_11K = 1,
28 MTK_AFE_RATE_12K = 2,
29 MTK_AFE_RATE_384K = 3,
30 MTK_AFE_RATE_16K = 4,
31 MTK_AFE_RATE_22K = 5,
32 MTK_AFE_RATE_24K = 6,
33 MTK_AFE_RATE_130K = 7,
34 MTK_AFE_RATE_32K = 8,
35 MTK_AFE_RATE_44K = 9,
36 MTK_AFE_RATE_48K = 10,
37 MTK_AFE_RATE_88K = 11,
38 MTK_AFE_RATE_96K = 12,
39 MTK_AFE_RATE_176K = 13,
40 MTK_AFE_RATE_192K = 14,
41 MTK_AFE_RATE_260K = 15,
42 };
43
44 enum {
45 MTK_AFE_DAI_MEMIF_RATE_8K = 0,
46 MTK_AFE_DAI_MEMIF_RATE_16K = 1,
47 MTK_AFE_DAI_MEMIF_RATE_32K = 2,
48 MTK_AFE_DAI_MEMIF_RATE_48K = 3,
49 };
50
51 enum {
52 MTK_AFE_PCM_RATE_8K = 0,
53 MTK_AFE_PCM_RATE_16K = 1,
54 MTK_AFE_PCM_RATE_32K = 2,
55 MTK_AFE_PCM_RATE_48K = 3,
56 };
57
mt8183_general_rate_transform(struct device * dev,unsigned int rate)58 unsigned int mt8183_general_rate_transform(struct device *dev,
59 unsigned int rate)
60 {
61 switch (rate) {
62 case 8000:
63 return MTK_AFE_RATE_8K;
64 case 11025:
65 return MTK_AFE_RATE_11K;
66 case 12000:
67 return MTK_AFE_RATE_12K;
68 case 16000:
69 return MTK_AFE_RATE_16K;
70 case 22050:
71 return MTK_AFE_RATE_22K;
72 case 24000:
73 return MTK_AFE_RATE_24K;
74 case 32000:
75 return MTK_AFE_RATE_32K;
76 case 44100:
77 return MTK_AFE_RATE_44K;
78 case 48000:
79 return MTK_AFE_RATE_48K;
80 case 88200:
81 return MTK_AFE_RATE_88K;
82 case 96000:
83 return MTK_AFE_RATE_96K;
84 case 130000:
85 return MTK_AFE_RATE_130K;
86 case 176400:
87 return MTK_AFE_RATE_176K;
88 case 192000:
89 return MTK_AFE_RATE_192K;
90 case 260000:
91 return MTK_AFE_RATE_260K;
92 default:
93 dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n",
94 __func__, rate, MTK_AFE_RATE_48K);
95 return MTK_AFE_RATE_48K;
96 }
97 }
98
dai_memif_rate_transform(struct device * dev,unsigned int rate)99 static unsigned int dai_memif_rate_transform(struct device *dev,
100 unsigned int rate)
101 {
102 switch (rate) {
103 case 8000:
104 return MTK_AFE_DAI_MEMIF_RATE_8K;
105 case 16000:
106 return MTK_AFE_DAI_MEMIF_RATE_16K;
107 case 32000:
108 return MTK_AFE_DAI_MEMIF_RATE_32K;
109 case 48000:
110 return MTK_AFE_DAI_MEMIF_RATE_48K;
111 default:
112 dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n",
113 __func__, rate, MTK_AFE_DAI_MEMIF_RATE_16K);
114 return MTK_AFE_DAI_MEMIF_RATE_16K;
115 }
116 }
117
mt8183_rate_transform(struct device * dev,unsigned int rate,int aud_blk)118 unsigned int mt8183_rate_transform(struct device *dev,
119 unsigned int rate, int aud_blk)
120 {
121 switch (aud_blk) {
122 case MT8183_MEMIF_MOD_DAI:
123 return dai_memif_rate_transform(dev, rate);
124 default:
125 return mt8183_general_rate_transform(dev, rate);
126 }
127 }
128
129 static const struct snd_pcm_hardware mt8183_afe_hardware = {
130 .info = SNDRV_PCM_INFO_MMAP |
131 SNDRV_PCM_INFO_INTERLEAVED |
132 SNDRV_PCM_INFO_MMAP_VALID,
133 .formats = SNDRV_PCM_FMTBIT_S16_LE |
134 SNDRV_PCM_FMTBIT_S24_LE |
135 SNDRV_PCM_FMTBIT_S32_LE,
136 .period_bytes_min = 256,
137 .period_bytes_max = 4 * 48 * 1024,
138 .periods_min = 2,
139 .periods_max = 256,
140 .buffer_bytes_max = 8 * 48 * 1024,
141 .fifo_size = 0,
142 };
143
mt8183_memif_fs(struct snd_pcm_substream * substream,unsigned int rate)144 static int mt8183_memif_fs(struct snd_pcm_substream *substream,
145 unsigned int rate)
146 {
147 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
148 struct snd_soc_component *component =
149 snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
150 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
151 int id = snd_soc_rtd_to_cpu(rtd, 0)->id;
152
153 return mt8183_rate_transform(afe->dev, rate, id);
154 }
155
mt8183_irq_fs(struct snd_pcm_substream * substream,unsigned int rate)156 static int mt8183_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
157 {
158 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
159 struct snd_soc_component *component =
160 snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
161 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
162
163 return mt8183_general_rate_transform(afe->dev, rate);
164 }
165
166 #define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\
167 SNDRV_PCM_RATE_88200 |\
168 SNDRV_PCM_RATE_96000 |\
169 SNDRV_PCM_RATE_176400 |\
170 SNDRV_PCM_RATE_192000)
171
172 #define MTK_PCM_DAI_RATES (SNDRV_PCM_RATE_8000 |\
173 SNDRV_PCM_RATE_16000 |\
174 SNDRV_PCM_RATE_32000 |\
175 SNDRV_PCM_RATE_48000)
176
177 #define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
178 SNDRV_PCM_FMTBIT_S24_LE |\
179 SNDRV_PCM_FMTBIT_S32_LE)
180
181 static struct snd_soc_dai_driver mt8183_memif_dai_driver[] = {
182 /* FE DAIs: memory intefaces to CPU */
183 {
184 .name = "DL1",
185 .id = MT8183_MEMIF_DL1,
186 .playback = {
187 .stream_name = "DL1",
188 .channels_min = 1,
189 .channels_max = 2,
190 .rates = MTK_PCM_RATES,
191 .formats = MTK_PCM_FORMATS,
192 },
193 .ops = &mtk_afe_fe_ops,
194 },
195 {
196 .name = "DL2",
197 .id = MT8183_MEMIF_DL2,
198 .playback = {
199 .stream_name = "DL2",
200 .channels_min = 1,
201 .channels_max = 2,
202 .rates = MTK_PCM_RATES,
203 .formats = MTK_PCM_FORMATS,
204 },
205 .ops = &mtk_afe_fe_ops,
206 },
207 {
208 .name = "DL3",
209 .id = MT8183_MEMIF_DL3,
210 .playback = {
211 .stream_name = "DL3",
212 .channels_min = 1,
213 .channels_max = 2,
214 .rates = MTK_PCM_RATES,
215 .formats = MTK_PCM_FORMATS,
216 },
217 .ops = &mtk_afe_fe_ops,
218 },
219 {
220 .name = "UL1",
221 .id = MT8183_MEMIF_VUL12,
222 .capture = {
223 .stream_name = "UL1",
224 .channels_min = 1,
225 .channels_max = 2,
226 .rates = MTK_PCM_RATES,
227 .formats = MTK_PCM_FORMATS,
228 },
229 .ops = &mtk_afe_fe_ops,
230 },
231 {
232 .name = "UL2",
233 .id = MT8183_MEMIF_AWB,
234 .capture = {
235 .stream_name = "UL2",
236 .channels_min = 1,
237 .channels_max = 2,
238 .rates = MTK_PCM_RATES,
239 .formats = MTK_PCM_FORMATS,
240 },
241 .ops = &mtk_afe_fe_ops,
242 },
243 {
244 .name = "UL3",
245 .id = MT8183_MEMIF_VUL2,
246 .capture = {
247 .stream_name = "UL3",
248 .channels_min = 1,
249 .channels_max = 2,
250 .rates = MTK_PCM_RATES,
251 .formats = MTK_PCM_FORMATS,
252 },
253 .ops = &mtk_afe_fe_ops,
254 },
255 {
256 .name = "UL4",
257 .id = MT8183_MEMIF_AWB2,
258 .capture = {
259 .stream_name = "UL4",
260 .channels_min = 1,
261 .channels_max = 2,
262 .rates = MTK_PCM_RATES,
263 .formats = MTK_PCM_FORMATS,
264 },
265 .ops = &mtk_afe_fe_ops,
266 },
267 {
268 .name = "UL_MONO_1",
269 .id = MT8183_MEMIF_MOD_DAI,
270 .capture = {
271 .stream_name = "UL_MONO_1",
272 .channels_min = 1,
273 .channels_max = 1,
274 .rates = MTK_PCM_DAI_RATES,
275 .formats = MTK_PCM_FORMATS,
276 },
277 .ops = &mtk_afe_fe_ops,
278 },
279 {
280 .name = "HDMI",
281 .id = MT8183_MEMIF_HDMI,
282 .playback = {
283 .stream_name = "HDMI",
284 .channels_min = 2,
285 .channels_max = 8,
286 .rates = MTK_PCM_RATES,
287 .formats = MTK_PCM_FORMATS,
288 },
289 .ops = &mtk_afe_fe_ops,
290 },
291 };
292
293 /* dma widget & routes*/
294 static const struct snd_kcontrol_new memif_ul1_ch1_mix[] = {
295 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN21,
296 I_ADDA_UL_CH1, 1, 0),
297 SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1", AFE_CONN21,
298 I_I2S0_CH1, 1, 0),
299 };
300
301 static const struct snd_kcontrol_new memif_ul1_ch2_mix[] = {
302 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN22,
303 I_ADDA_UL_CH2, 1, 0),
304 SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2", AFE_CONN21,
305 I_I2S0_CH2, 1, 0),
306 };
307
308 static const struct snd_kcontrol_new memif_ul2_ch1_mix[] = {
309 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN5,
310 I_ADDA_UL_CH1, 1, 0),
311 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN5,
312 I_DL1_CH1, 1, 0),
313 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN5,
314 I_DL2_CH1, 1, 0),
315 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN5,
316 I_DL3_CH1, 1, 0),
317 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1", AFE_CONN5,
318 I_I2S2_CH1, 1, 0),
319 };
320
321 static const struct snd_kcontrol_new memif_ul2_ch2_mix[] = {
322 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN6,
323 I_ADDA_UL_CH2, 1, 0),
324 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN6,
325 I_DL1_CH2, 1, 0),
326 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN6,
327 I_DL2_CH2, 1, 0),
328 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN6,
329 I_DL3_CH2, 1, 0),
330 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2", AFE_CONN6,
331 I_I2S2_CH2, 1, 0),
332 };
333
334 static const struct snd_kcontrol_new memif_ul3_ch1_mix[] = {
335 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN32,
336 I_ADDA_UL_CH1, 1, 0),
337 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1", AFE_CONN32,
338 I_I2S2_CH1, 1, 0),
339 };
340
341 static const struct snd_kcontrol_new memif_ul3_ch2_mix[] = {
342 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN33,
343 I_ADDA_UL_CH2, 1, 0),
344 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2", AFE_CONN33,
345 I_I2S2_CH2, 1, 0),
346 };
347
348 static const struct snd_kcontrol_new memif_ul4_ch1_mix[] = {
349 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN38,
350 I_ADDA_UL_CH1, 1, 0),
351 };
352
353 static const struct snd_kcontrol_new memif_ul4_ch2_mix[] = {
354 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN39,
355 I_ADDA_UL_CH2, 1, 0),
356 };
357
358 static const struct snd_kcontrol_new memif_ul_mono_1_mix[] = {
359 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN12,
360 I_ADDA_UL_CH1, 1, 0),
361 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN12,
362 I_ADDA_UL_CH2, 1, 0),
363 };
364
365 static const struct snd_soc_dapm_widget mt8183_memif_widgets[] = {
366 /* memif */
367 SND_SOC_DAPM_MIXER("UL1_CH1", SND_SOC_NOPM, 0, 0,
368 memif_ul1_ch1_mix, ARRAY_SIZE(memif_ul1_ch1_mix)),
369 SND_SOC_DAPM_MIXER("UL1_CH2", SND_SOC_NOPM, 0, 0,
370 memif_ul1_ch2_mix, ARRAY_SIZE(memif_ul1_ch2_mix)),
371
372 SND_SOC_DAPM_MIXER("UL2_CH1", SND_SOC_NOPM, 0, 0,
373 memif_ul2_ch1_mix, ARRAY_SIZE(memif_ul2_ch1_mix)),
374 SND_SOC_DAPM_MIXER("UL2_CH2", SND_SOC_NOPM, 0, 0,
375 memif_ul2_ch2_mix, ARRAY_SIZE(memif_ul2_ch2_mix)),
376
377 SND_SOC_DAPM_MIXER("UL3_CH1", SND_SOC_NOPM, 0, 0,
378 memif_ul3_ch1_mix, ARRAY_SIZE(memif_ul3_ch1_mix)),
379 SND_SOC_DAPM_MIXER("UL3_CH2", SND_SOC_NOPM, 0, 0,
380 memif_ul3_ch2_mix, ARRAY_SIZE(memif_ul3_ch2_mix)),
381
382 SND_SOC_DAPM_MIXER("UL4_CH1", SND_SOC_NOPM, 0, 0,
383 memif_ul4_ch1_mix, ARRAY_SIZE(memif_ul4_ch1_mix)),
384 SND_SOC_DAPM_MIXER("UL4_CH2", SND_SOC_NOPM, 0, 0,
385 memif_ul4_ch2_mix, ARRAY_SIZE(memif_ul4_ch2_mix)),
386
387 SND_SOC_DAPM_MIXER("UL_MONO_1_CH1", SND_SOC_NOPM, 0, 0,
388 memif_ul_mono_1_mix,
389 ARRAY_SIZE(memif_ul_mono_1_mix)),
390 };
391
392 static const struct snd_soc_dapm_route mt8183_memif_routes[] = {
393 /* capture */
394 {"UL1", NULL, "UL1_CH1"},
395 {"UL1", NULL, "UL1_CH2"},
396 {"UL1_CH1", "ADDA_UL_CH1", "ADDA Capture"},
397 {"UL1_CH2", "ADDA_UL_CH2", "ADDA Capture"},
398 {"UL1_CH1", "I2S0_CH1", "I2S0"},
399 {"UL1_CH2", "I2S0_CH2", "I2S0"},
400
401 {"UL2", NULL, "UL2_CH1"},
402 {"UL2", NULL, "UL2_CH2"},
403 {"UL2_CH1", "ADDA_UL_CH1", "ADDA Capture"},
404 {"UL2_CH2", "ADDA_UL_CH2", "ADDA Capture"},
405 {"UL2_CH1", "I2S2_CH1", "I2S2"},
406 {"UL2_CH2", "I2S2_CH2", "I2S2"},
407
408 {"UL3", NULL, "UL3_CH1"},
409 {"UL3", NULL, "UL3_CH2"},
410 {"UL3_CH1", "ADDA_UL_CH1", "ADDA Capture"},
411 {"UL3_CH2", "ADDA_UL_CH2", "ADDA Capture"},
412 {"UL3_CH1", "I2S2_CH1", "I2S2"},
413 {"UL3_CH2", "I2S2_CH2", "I2S2"},
414
415 {"UL4", NULL, "UL4_CH1"},
416 {"UL4", NULL, "UL4_CH2"},
417 {"UL4_CH1", "ADDA_UL_CH1", "ADDA Capture"},
418 {"UL4_CH2", "ADDA_UL_CH2", "ADDA Capture"},
419
420 {"UL_MONO_1", NULL, "UL_MONO_1_CH1"},
421 {"UL_MONO_1_CH1", "ADDA_UL_CH1", "ADDA Capture"},
422 {"UL_MONO_1_CH1", "ADDA_UL_CH2", "ADDA Capture"},
423 };
424
425 static const struct snd_soc_component_driver mt8183_afe_pcm_dai_component = {
426 .name = "mt8183-afe-pcm-dai",
427 };
428
429 #define MT8183_MEMIF_BASE(_id, _en_reg, _fs_reg, _mono_reg) \
430 [MT8183_MEMIF_##_id] = { \
431 .name = #_id, \
432 .id = MT8183_MEMIF_##_id, \
433 .reg_ofs_base = AFE_##_id##_BASE, \
434 .reg_ofs_cur = AFE_##_id##_CUR, \
435 .reg_ofs_end = AFE_##_id##_END, \
436 .reg_ofs_base_msb = AFE_##_id##_BASE_MSB, \
437 .reg_ofs_cur_msb = AFE_##_id##_CUR_MSB, \
438 .reg_ofs_end_msb = AFE_##_id##_END_MSB, \
439 .fs_reg = (_fs_reg), \
440 .fs_shift = _id##_MODE_SFT, \
441 .fs_maskbit = _id##_MODE_MASK, \
442 .mono_reg = (_mono_reg), \
443 .mono_shift = _id##_DATA_SFT, \
444 .enable_reg = (_en_reg), \
445 .enable_shift = _id##_ON_SFT, \
446 .hd_reg = AFE_MEMIF_HD_MODE, \
447 .hd_align_reg = AFE_MEMIF_HDALIGN, \
448 .hd_shift = _id##_HD_SFT, \
449 .hd_align_mshift = _id##_HD_ALIGN_SFT, \
450 .agent_disable_reg = -1, \
451 .agent_disable_shift = -1, \
452 .msb_reg = -1, \
453 .msb_shift = -1, \
454 }
455
456 #define MT8183_MEMIF(_id, _fs_reg, _mono_reg) \
457 MT8183_MEMIF_BASE(_id, AFE_DAC_CON0, _fs_reg, _mono_reg)
458
459 /* For convenience with macros: missing register fields */
460 #define MOD_DAI_DATA_SFT -1
461 #define HDMI_MODE_SFT -1
462 #define HDMI_MODE_MASK -1
463 #define HDMI_DATA_SFT -1
464 #define HDMI_ON_SFT -1
465
466 /* For convenience with macros: register name differences */
467 #define AFE_VUL12_BASE AFE_VUL_D2_BASE
468 #define AFE_VUL12_CUR AFE_VUL_D2_CUR
469 #define AFE_VUL12_END AFE_VUL_D2_END
470 #define AFE_VUL12_BASE_MSB AFE_VUL_D2_BASE_MSB
471 #define AFE_VUL12_CUR_MSB AFE_VUL_D2_CUR_MSB
472 #define AFE_VUL12_END_MSB AFE_VUL_D2_END_MSB
473 #define AWB2_HD_ALIGN_SFT AWB2_ALIGN_SFT
474 #define VUL12_DATA_SFT VUL12_MONO_SFT
475 #define AFE_HDMI_BASE AFE_HDMI_OUT_BASE
476 #define AFE_HDMI_CUR AFE_HDMI_OUT_CUR
477 #define AFE_HDMI_END AFE_HDMI_OUT_END
478 #define AFE_HDMI_BASE_MSB AFE_HDMI_OUT_BASE_MSB
479 #define AFE_HDMI_CUR_MSB AFE_HDMI_OUT_CUR_MSB
480 #define AFE_HDMI_END_MSB AFE_HDMI_OUT_END_MSB
481
482 static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = {
483 MT8183_MEMIF(DL1, AFE_DAC_CON1, AFE_DAC_CON1),
484 MT8183_MEMIF(DL2, AFE_DAC_CON1, AFE_DAC_CON1),
485 MT8183_MEMIF(DL3, AFE_DAC_CON2, AFE_DAC_CON1),
486 MT8183_MEMIF(VUL2, AFE_DAC_CON2, AFE_DAC_CON2),
487 MT8183_MEMIF(AWB, AFE_DAC_CON1, AFE_DAC_CON1),
488 MT8183_MEMIF(AWB2, AFE_DAC_CON2, AFE_DAC_CON2),
489 MT8183_MEMIF(VUL12, AFE_DAC_CON0, AFE_DAC_CON0),
490 MT8183_MEMIF(MOD_DAI, AFE_DAC_CON1, -1),
491 /* enable control in tdm for sync start */
492 MT8183_MEMIF_BASE(HDMI, -1, -1, -1),
493 };
494
495 #define MT8183_AFE_IRQ_BASE(_id, _fs_reg, _fs_shift, _fs_maskbit) \
496 [MT8183_IRQ_##_id] = { \
497 .id = MT8183_IRQ_##_id, \
498 .irq_cnt_reg = AFE_IRQ_MCU_CNT##_id, \
499 .irq_cnt_shift = 0, \
500 .irq_cnt_maskbit = 0x3ffff, \
501 .irq_fs_reg = _fs_reg, \
502 .irq_fs_shift = _fs_shift, \
503 .irq_fs_maskbit = _fs_maskbit, \
504 .irq_en_reg = AFE_IRQ_MCU_CON0, \
505 .irq_en_shift = IRQ##_id##_MCU_ON_SFT, \
506 .irq_clr_reg = AFE_IRQ_MCU_CLR, \
507 .irq_clr_shift = IRQ##_id##_MCU_CLR_SFT, \
508 }
509
510 #define MT8183_AFE_IRQ(_id) \
511 MT8183_AFE_IRQ_BASE(_id, AFE_IRQ_MCU_CON1 + _id / 8 * 4, \
512 IRQ##_id##_MCU_MODE_SFT, \
513 IRQ##_id##_MCU_MODE_MASK)
514
515 #define MT8183_AFE_IRQ_NOFS(_id) MT8183_AFE_IRQ_BASE(_id, -1, -1, -1)
516
517 static const struct mtk_base_irq_data irq_data[MT8183_IRQ_NUM] = {
518 MT8183_AFE_IRQ(0),
519 MT8183_AFE_IRQ(1),
520 MT8183_AFE_IRQ(2),
521 MT8183_AFE_IRQ(3),
522 MT8183_AFE_IRQ(4),
523 MT8183_AFE_IRQ(5),
524 MT8183_AFE_IRQ(6),
525 MT8183_AFE_IRQ(7),
526 MT8183_AFE_IRQ_NOFS(8),
527 MT8183_AFE_IRQ(11),
528 MT8183_AFE_IRQ(12),
529 };
530
mt8183_is_volatile_reg(struct device * dev,unsigned int reg)531 static bool mt8183_is_volatile_reg(struct device *dev, unsigned int reg)
532 {
533 /* these auto-gen reg has read-only bit, so put it as volatile */
534 /* volatile reg cannot be cached, so cannot be set when power off */
535 switch (reg) {
536 case AUDIO_TOP_CON0 ... AUDIO_TOP_CON1: /* reg bit controlled by CCF */
537 case AUDIO_TOP_CON3:
538 case AFE_DL1_CUR ... AFE_DL1_END:
539 case AFE_DL2_CUR ... AFE_DL2_END:
540 case AFE_AWB_END ... AFE_AWB_CUR:
541 case AFE_VUL_END ... AFE_VUL_CUR:
542 case AFE_MEMIF_MON0 ... AFE_MEMIF_MON9:
543 case AFE_ADDA_SRC_DEBUG_MON0 ... AFE_ADDA_SRC_DEBUG_MON1:
544 case AFE_ADDA_UL_SRC_MON0 ... AFE_ADDA_UL_SRC_MON1:
545 case AFE_SIDETONE_MON:
546 case AFE_SIDETONE_CON0 ... AFE_SIDETONE_COEFF:
547 case AFE_BUS_MON0:
548 case AFE_MRGIF_MON0 ... AFE_I2S_MON:
549 case AFE_DAC_MON:
550 case AFE_VUL2_END ... AFE_VUL2_CUR:
551 case AFE_IRQ0_MCU_CNT_MON ... AFE_IRQ6_MCU_CNT_MON:
552 case AFE_MOD_DAI_END ... AFE_MOD_DAI_CUR:
553 case AFE_VUL_D2_END ... AFE_VUL_D2_CUR:
554 case AFE_DL3_CUR ... AFE_DL3_END:
555 case AFE_HDMI_OUT_CON0:
556 case AFE_HDMI_OUT_CUR ... AFE_HDMI_OUT_END:
557 case AFE_IRQ3_MCU_CNT_MON... AFE_IRQ4_MCU_CNT_MON:
558 case AFE_IRQ_MCU_STATUS ... AFE_IRQ_MCU_CLR:
559 case AFE_IRQ_MCU_MON2:
560 case AFE_IRQ1_MCU_CNT_MON ... AFE_IRQ5_MCU_CNT_MON:
561 case AFE_IRQ7_MCU_CNT_MON:
562 case AFE_GAIN1_CUR:
563 case AFE_GAIN2_CUR:
564 case AFE_SRAM_DELSEL_CON0:
565 case AFE_SRAM_DELSEL_CON2 ... AFE_SRAM_DELSEL_CON3:
566 case AFE_ASRC_2CH_CON12 ... AFE_ASRC_2CH_CON13:
567 case PCM_INTF_CON2:
568 case FPGA_CFG0 ... FPGA_CFG1:
569 case FPGA_CFG2 ... FPGA_CFG3:
570 case AUDIO_TOP_DBG_MON0 ... AUDIO_TOP_DBG_MON1:
571 case AFE_IRQ8_MCU_CNT_MON ... AFE_IRQ12_MCU_CNT_MON:
572 case AFE_CBIP_MON0:
573 case AFE_CBIP_SLV_MUX_MON0 ... AFE_CBIP_SLV_DECODER_MON0:
574 case AFE_ADDA6_SRC_DEBUG_MON0:
575 case AFE_ADD6A_UL_SRC_MON0... AFE_ADDA6_UL_SRC_MON1:
576 case AFE_DL1_CUR_MSB:
577 case AFE_DL2_CUR_MSB:
578 case AFE_AWB_CUR_MSB:
579 case AFE_VUL_CUR_MSB:
580 case AFE_VUL2_CUR_MSB:
581 case AFE_MOD_DAI_CUR_MSB:
582 case AFE_VUL_D2_CUR_MSB:
583 case AFE_DL3_CUR_MSB:
584 case AFE_HDMI_OUT_CUR_MSB:
585 case AFE_AWB2_END ... AFE_AWB2_CUR:
586 case AFE_AWB2_CUR_MSB:
587 case AFE_ADDA_DL_SDM_FIFO_MON ... AFE_ADDA_DL_SDM_OUT_MON:
588 case AFE_CONNSYS_I2S_MON ... AFE_ASRC_2CH_CON0:
589 case AFE_ASRC_2CH_CON2 ... AFE_ASRC_2CH_CON5:
590 case AFE_ASRC_2CH_CON7 ... AFE_ASRC_2CH_CON8:
591 case AFE_MEMIF_MON12 ... AFE_MEMIF_MON24:
592 case AFE_ADDA_MTKAIF_MON0 ... AFE_ADDA_MTKAIF_MON1:
593 case AFE_AUD_PAD_TOP:
594 case AFE_GENERAL1_ASRC_2CH_CON0:
595 case AFE_GENERAL1_ASRC_2CH_CON2 ... AFE_GENERAL1_ASRC_2CH_CON5:
596 case AFE_GENERAL1_ASRC_2CH_CON7 ... AFE_GENERAL1_ASRC_2CH_CON8:
597 case AFE_GENERAL1_ASRC_2CH_CON12 ... AFE_GENERAL1_ASRC_2CH_CON13:
598 case AFE_GENERAL2_ASRC_2CH_CON0:
599 case AFE_GENERAL2_ASRC_2CH_CON2 ... AFE_GENERAL2_ASRC_2CH_CON5:
600 case AFE_GENERAL2_ASRC_2CH_CON7 ... AFE_GENERAL2_ASRC_2CH_CON8:
601 case AFE_GENERAL2_ASRC_2CH_CON12 ... AFE_GENERAL2_ASRC_2CH_CON13:
602 return true;
603 default:
604 return false;
605 };
606 }
607
608 static const struct regmap_config mt8183_afe_regmap_config = {
609 .reg_bits = 32,
610 .reg_stride = 4,
611 .val_bits = 32,
612
613 .volatile_reg = mt8183_is_volatile_reg,
614
615 .max_register = AFE_MAX_REGISTER,
616 .num_reg_defaults_raw = AFE_MAX_REGISTER,
617
618 .cache_type = REGCACHE_FLAT,
619 };
620
mt8183_afe_irq_handler(int irq_id,void * dev)621 static irqreturn_t mt8183_afe_irq_handler(int irq_id, void *dev)
622 {
623 struct mtk_base_afe *afe = dev;
624 struct mtk_base_afe_irq *irq;
625 unsigned int status;
626 unsigned int status_mcu;
627 unsigned int mcu_en;
628 int ret;
629 int i;
630 irqreturn_t irq_ret = IRQ_HANDLED;
631
632 /* get irq that is sent to MCU */
633 regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en);
634
635 ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status);
636 /* only care IRQ which is sent to MCU */
637 status_mcu = status & mcu_en & AFE_IRQ_STATUS_BITS;
638
639 if (ret || status_mcu == 0) {
640 dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n",
641 __func__, ret, status, mcu_en);
642
643 irq_ret = IRQ_NONE;
644 goto err_irq;
645 }
646
647 for (i = 0; i < MT8183_MEMIF_NUM; i++) {
648 struct mtk_base_afe_memif *memif = &afe->memif[i];
649
650 if (!memif->substream)
651 continue;
652
653 if (memif->irq_usage < 0)
654 continue;
655
656 irq = &afe->irqs[memif->irq_usage];
657
658 if (status_mcu & (1 << irq->irq_data->irq_en_shift))
659 snd_pcm_period_elapsed(memif->substream);
660 }
661
662 err_irq:
663 /* clear irq */
664 regmap_write(afe->regmap,
665 AFE_IRQ_MCU_CLR,
666 status_mcu);
667
668 return irq_ret;
669 }
670
mt8183_afe_runtime_suspend(struct device * dev)671 static int mt8183_afe_runtime_suspend(struct device *dev)
672 {
673 struct mtk_base_afe *afe = dev_get_drvdata(dev);
674 struct mt8183_afe_private *afe_priv = afe->platform_priv;
675 unsigned int value;
676 int ret;
677
678 if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
679 goto skip_regmap;
680
681 /* disable AFE */
682 regmap_update_bits(afe->regmap, AFE_DAC_CON0, AFE_ON_MASK_SFT, 0x0);
683
684 ret = regmap_read_poll_timeout(afe->regmap,
685 AFE_DAC_MON,
686 value,
687 (value & AFE_ON_RETM_MASK_SFT) == 0,
688 20,
689 1 * 1000 * 1000);
690 if (ret)
691 dev_warn(afe->dev, "%s(), ret %d\n", __func__, ret);
692
693 /* make sure all irq status are cleared, twice intended */
694 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff);
695 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff);
696
697 /* cache only */
698 regcache_cache_only(afe->regmap, true);
699 regcache_mark_dirty(afe->regmap);
700
701 skip_regmap:
702 return mt8183_afe_disable_clock(afe);
703 }
704
mt8183_afe_runtime_resume(struct device * dev)705 static int mt8183_afe_runtime_resume(struct device *dev)
706 {
707 struct mtk_base_afe *afe = dev_get_drvdata(dev);
708 struct mt8183_afe_private *afe_priv = afe->platform_priv;
709 int ret;
710
711 ret = mt8183_afe_enable_clock(afe);
712 if (ret)
713 return ret;
714
715 if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
716 goto skip_regmap;
717
718 regcache_cache_only(afe->regmap, false);
719 regcache_sync(afe->regmap);
720
721 /* enable audio sys DCM for power saving */
722 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 0x1 << 29, 0x1 << 29);
723
724 /* force cpu use 8_24 format when writing 32bit data */
725 regmap_update_bits(afe->regmap, AFE_MEMIF_MSB,
726 CPU_HD_ALIGN_MASK_SFT, 0 << CPU_HD_ALIGN_SFT);
727
728 /* set all output port to 24bit */
729 regmap_write(afe->regmap, AFE_CONN_24BIT, 0xffffffff);
730 regmap_write(afe->regmap, AFE_CONN_24BIT_1, 0xffffffff);
731
732 /* enable AFE */
733 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
734
735 skip_regmap:
736 return 0;
737 }
738
mt8183_dai_memif_register(struct mtk_base_afe * afe)739 static int mt8183_dai_memif_register(struct mtk_base_afe *afe)
740 {
741 struct mtk_base_afe_dai *dai;
742
743 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
744 if (!dai)
745 return -ENOMEM;
746
747 list_add(&dai->list, &afe->sub_dais);
748
749 dai->dai_drivers = mt8183_memif_dai_driver;
750 dai->num_dai_drivers = ARRAY_SIZE(mt8183_memif_dai_driver);
751
752 dai->dapm_widgets = mt8183_memif_widgets;
753 dai->num_dapm_widgets = ARRAY_SIZE(mt8183_memif_widgets);
754 dai->dapm_routes = mt8183_memif_routes;
755 dai->num_dapm_routes = ARRAY_SIZE(mt8183_memif_routes);
756 return 0;
757 }
758
759 typedef int (*dai_register_cb)(struct mtk_base_afe *);
760 static const dai_register_cb dai_register_cbs[] = {
761 mt8183_dai_adda_register,
762 mt8183_dai_i2s_register,
763 mt8183_dai_pcm_register,
764 mt8183_dai_tdm_register,
765 mt8183_dai_hostless_register,
766 mt8183_dai_memif_register,
767 };
768
mt8183_afe_pcm_dev_probe(struct platform_device * pdev)769 static int mt8183_afe_pcm_dev_probe(struct platform_device *pdev)
770 {
771 struct mtk_base_afe *afe;
772 struct mt8183_afe_private *afe_priv;
773 struct device *dev = &pdev->dev;
774 struct reset_control *rstc;
775 int i, irq_id, ret;
776
777 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(34));
778 if (ret)
779 return ret;
780
781 afe = devm_kzalloc(dev, sizeof(*afe), GFP_KERNEL);
782 if (!afe)
783 return -ENOMEM;
784 platform_set_drvdata(pdev, afe);
785
786 afe->platform_priv = devm_kzalloc(dev, sizeof(*afe_priv), GFP_KERNEL);
787 if (!afe->platform_priv)
788 return -ENOMEM;
789
790 afe_priv = afe->platform_priv;
791 afe->dev = dev;
792
793 ret = of_reserved_mem_device_init(dev);
794 if (ret) {
795 dev_info(dev, "no reserved memory found, pre-allocating buffers instead\n");
796 afe->preallocate_buffers = true;
797 }
798
799 /* initial audio related clock */
800 ret = mt8183_init_clock(afe);
801 if (ret) {
802 dev_err(dev, "init clock error\n");
803 return ret;
804 }
805
806 pm_runtime_enable(dev);
807
808 /* regmap init */
809 afe->regmap = syscon_node_to_regmap(dev->parent->of_node);
810 if (IS_ERR(afe->regmap)) {
811 dev_err(dev, "could not get regmap from parent\n");
812 ret = PTR_ERR(afe->regmap);
813 goto err_pm_disable;
814 }
815 ret = regmap_attach_dev(dev, afe->regmap, &mt8183_afe_regmap_config);
816 if (ret) {
817 dev_warn(dev, "regmap_attach_dev fail, ret %d\n", ret);
818 goto err_pm_disable;
819 }
820
821 rstc = devm_reset_control_get(dev, "audiosys");
822 if (IS_ERR(rstc)) {
823 ret = PTR_ERR(rstc);
824 dev_err(dev, "could not get audiosys reset:%d\n", ret);
825 goto err_pm_disable;
826 }
827
828 ret = reset_control_reset(rstc);
829 if (ret) {
830 dev_err(dev, "failed to trigger audio reset:%d\n", ret);
831 goto err_pm_disable;
832 }
833
834 /* enable clock for regcache get default value from hw */
835 afe_priv->pm_runtime_bypass_reg_ctl = true;
836 pm_runtime_get_sync(dev);
837
838 ret = regmap_reinit_cache(afe->regmap, &mt8183_afe_regmap_config);
839 if (ret) {
840 dev_err(dev, "regmap_reinit_cache fail, ret %d\n", ret);
841 goto err_pm_disable;
842 }
843
844 pm_runtime_put_sync(dev);
845 afe_priv->pm_runtime_bypass_reg_ctl = false;
846
847 regcache_cache_only(afe->regmap, true);
848 regcache_mark_dirty(afe->regmap);
849
850 /* init memif */
851 afe->memif_size = MT8183_MEMIF_NUM;
852 afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
853 GFP_KERNEL);
854 if (!afe->memif) {
855 ret = -ENOMEM;
856 goto err_pm_disable;
857 }
858
859 for (i = 0; i < afe->memif_size; i++) {
860 afe->memif[i].data = &memif_data[i];
861 afe->memif[i].irq_usage = -1;
862 }
863
864 afe->memif[MT8183_MEMIF_HDMI].irq_usage = MT8183_IRQ_8;
865 afe->memif[MT8183_MEMIF_HDMI].const_irq = 1;
866
867 mutex_init(&afe->irq_alloc_lock);
868
869 /* init memif */
870 /* irq initialize */
871 afe->irqs_size = MT8183_IRQ_NUM;
872 afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
873 GFP_KERNEL);
874 if (!afe->irqs) {
875 ret = -ENOMEM;
876 goto err_pm_disable;
877 }
878
879 for (i = 0; i < afe->irqs_size; i++)
880 afe->irqs[i].irq_data = &irq_data[i];
881
882 /* request irq */
883 irq_id = platform_get_irq(pdev, 0);
884 if (irq_id < 0) {
885 ret = irq_id;
886 goto err_pm_disable;
887 }
888
889 ret = devm_request_irq(dev, irq_id, mt8183_afe_irq_handler,
890 IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
891 if (ret) {
892 dev_err(dev, "could not request_irq for asys-isr\n");
893 goto err_pm_disable;
894 }
895
896 /* init sub_dais */
897 INIT_LIST_HEAD(&afe->sub_dais);
898
899 for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
900 ret = dai_register_cbs[i](afe);
901 if (ret) {
902 dev_warn(dev, "dai register i %d fail, ret %d\n",
903 i, ret);
904 goto err_pm_disable;
905 }
906 }
907
908 /* init dai_driver and component_driver */
909 ret = mtk_afe_combine_sub_dai(afe);
910 if (ret) {
911 dev_warn(dev, "mtk_afe_combine_sub_dai fail, ret %d\n", ret);
912 goto err_pm_disable;
913 }
914
915 afe->mtk_afe_hardware = &mt8183_afe_hardware;
916 afe->memif_fs = mt8183_memif_fs;
917 afe->irq_fs = mt8183_irq_fs;
918
919 afe->runtime_resume = mt8183_afe_runtime_resume;
920 afe->runtime_suspend = mt8183_afe_runtime_suspend;
921
922 /* register component */
923 ret = devm_snd_soc_register_component(dev, &mtk_afe_pcm_platform,
924 NULL, 0);
925 if (ret) {
926 dev_warn(dev, "err_platform\n");
927 goto err_pm_disable;
928 }
929
930 ret = devm_snd_soc_register_component(dev, &mt8183_afe_pcm_dai_component,
931 afe->dai_drivers,
932 afe->num_dai_drivers);
933 if (ret) {
934 dev_warn(dev, "err_dai_component\n");
935 goto err_pm_disable;
936 }
937
938 return ret;
939
940 err_pm_disable:
941 pm_runtime_disable(dev);
942 return ret;
943 }
944
mt8183_afe_pcm_dev_remove(struct platform_device * pdev)945 static void mt8183_afe_pcm_dev_remove(struct platform_device *pdev)
946 {
947 struct device *dev = &pdev->dev;
948
949 pm_runtime_disable(dev);
950 if (!pm_runtime_status_suspended(dev))
951 mt8183_afe_runtime_suspend(dev);
952 }
953
954 static const struct of_device_id mt8183_afe_pcm_dt_match[] = {
955 { .compatible = "mediatek,mt8183-audio", },
956 {},
957 };
958 MODULE_DEVICE_TABLE(of, mt8183_afe_pcm_dt_match);
959
960 static const struct dev_pm_ops mt8183_afe_pm_ops = {
961 RUNTIME_PM_OPS(mt8183_afe_runtime_suspend,
962 mt8183_afe_runtime_resume, NULL)
963 };
964
965 static struct platform_driver mt8183_afe_pcm_driver = {
966 .driver = {
967 .name = "mt8183-audio",
968 .of_match_table = mt8183_afe_pcm_dt_match,
969 .pm = pm_ptr(&mt8183_afe_pm_ops),
970 },
971 .probe = mt8183_afe_pcm_dev_probe,
972 .remove = mt8183_afe_pcm_dev_remove,
973 };
974
975 module_platform_driver(mt8183_afe_pcm_driver);
976
977 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 8183");
978 MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>");
979 MODULE_LICENSE("GPL v2");
980