1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #include <linux/etherdevice.h> 7 #include <linux/of.h> 8 #include <linux/hwmon.h> 9 #include <linux/hwmon-sysfs.h> 10 #include <linux/thermal.h> 11 #include "mt7996.h" 12 #include "mac.h" 13 #include "mcu.h" 14 #include "coredump.h" 15 #include "eeprom.h" 16 17 static const struct ieee80211_iface_limit if_limits_global = { 18 .max = MT7996_MAX_INTERFACES * MT7996_MAX_RADIOS, 19 .types = BIT(NL80211_IFTYPE_STATION) 20 | BIT(NL80211_IFTYPE_ADHOC) 21 | BIT(NL80211_IFTYPE_AP) 22 #ifdef CONFIG_MAC80211_MESH 23 | BIT(NL80211_IFTYPE_MESH_POINT) 24 #endif 25 }; 26 27 static const struct ieee80211_iface_combination if_comb_global = { 28 .limits = &if_limits_global, 29 .n_limits = 1, 30 .max_interfaces = MT7996_MAX_INTERFACES * MT7996_MAX_RADIOS, 31 .num_different_channels = MT7996_MAX_RADIOS, 32 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 33 BIT(NL80211_CHAN_WIDTH_20) | 34 BIT(NL80211_CHAN_WIDTH_40) | 35 BIT(NL80211_CHAN_WIDTH_80) | 36 BIT(NL80211_CHAN_WIDTH_160), 37 }; 38 39 static const struct ieee80211_iface_combination if_comb_global_7992 = { 40 .limits = &if_limits_global, 41 .n_limits = 1, 42 .max_interfaces = 32, 43 .num_different_channels = MT7996_MAX_RADIOS - 1, 44 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 45 BIT(NL80211_CHAN_WIDTH_20) | 46 BIT(NL80211_CHAN_WIDTH_40) | 47 BIT(NL80211_CHAN_WIDTH_80) | 48 BIT(NL80211_CHAN_WIDTH_160), 49 }; 50 51 static const struct ieee80211_iface_limit if_limits[] = { 52 { 53 .max = 16, 54 .types = BIT(NL80211_IFTYPE_AP) 55 #ifdef CONFIG_MAC80211_MESH 56 | BIT(NL80211_IFTYPE_MESH_POINT) 57 #endif 58 }, { 59 .max = MT7996_MAX_INTERFACES, 60 .types = BIT(NL80211_IFTYPE_STATION) 61 } 62 }; 63 64 static const struct ieee80211_iface_combination if_comb = { 65 .limits = if_limits, 66 .n_limits = ARRAY_SIZE(if_limits), 67 .max_interfaces = MT7996_MAX_INTERFACES, 68 .num_different_channels = 1, 69 .beacon_int_infra_match = true, 70 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 71 BIT(NL80211_CHAN_WIDTH_20) | 72 BIT(NL80211_CHAN_WIDTH_40) | 73 BIT(NL80211_CHAN_WIDTH_80) | 74 BIT(NL80211_CHAN_WIDTH_160), 75 .beacon_int_min_gcd = 100, 76 }; 77 78 static const u8 if_types_ext_capa_ap[] = { 79 [0] = WLAN_EXT_CAPA1_EXT_CHANNEL_SWITCHING, 80 [2] = WLAN_EXT_CAPA3_MULTI_BSSID_SUPPORT, 81 [7] = WLAN_EXT_CAPA8_OPMODE_NOTIF, 82 }; 83 84 static const struct wiphy_iftype_ext_capab iftypes_ext_capa[] = { 85 { 86 .iftype = NL80211_IFTYPE_AP, 87 .extended_capabilities = if_types_ext_capa_ap, 88 .extended_capabilities_mask = if_types_ext_capa_ap, 89 .extended_capabilities_len = sizeof(if_types_ext_capa_ap), 90 .eml_capabilities = IEEE80211_EML_CAP_EMLSR_SUPP, 91 .mld_capa_and_ops = 92 FIELD_PREP_CONST(IEEE80211_MLD_CAP_OP_MAX_SIMUL_LINKS, 93 MT7996_MAX_RADIOS - 1), 94 }, { 95 .iftype = NL80211_IFTYPE_STATION, 96 .extended_capabilities = if_types_ext_capa_ap, 97 .extended_capabilities_mask = if_types_ext_capa_ap, 98 .extended_capabilities_len = sizeof(if_types_ext_capa_ap), 99 .mld_capa_and_ops = 100 FIELD_PREP_CONST(IEEE80211_MLD_CAP_OP_FREQ_SEP_TYPE_IND, 1) | 101 FIELD_PREP_CONST(IEEE80211_MLD_CAP_OP_MAX_SIMUL_LINKS, 102 MT7996_MAX_RADIOS - 1), 103 }, 104 }; 105 106 static ssize_t mt7996_thermal_temp_show(struct device *dev, 107 struct device_attribute *attr, 108 char *buf) 109 { 110 struct mt7996_phy *phy = dev_get_drvdata(dev); 111 int i = to_sensor_dev_attr(attr)->index; 112 int temperature; 113 114 switch (i) { 115 case 0: 116 temperature = mt7996_mcu_get_temperature(phy); 117 if (temperature < 0) 118 return temperature; 119 /* display in millidegree celcius */ 120 return sprintf(buf, "%u\n", temperature * 1000); 121 case 1: 122 case 2: 123 return sprintf(buf, "%u\n", 124 phy->throttle_temp[i - 1] * 1000); 125 case 3: 126 return sprintf(buf, "%hhu\n", phy->throttle_state); 127 default: 128 return -EINVAL; 129 } 130 } 131 132 static ssize_t mt7996_thermal_temp_store(struct device *dev, 133 struct device_attribute *attr, 134 const char *buf, size_t count) 135 { 136 struct mt7996_phy *phy = dev_get_drvdata(dev); 137 int ret, i = to_sensor_dev_attr(attr)->index; 138 long val; 139 140 ret = kstrtol(buf, 10, &val); 141 if (ret < 0) 142 return ret; 143 144 mutex_lock(&phy->dev->mt76.mutex); 145 val = DIV_ROUND_CLOSEST(clamp_val(val, 40 * 1000, 130 * 1000), 1000); 146 147 /* add a safety margin ~10 */ 148 if ((i - 1 == MT7996_CRIT_TEMP_IDX && 149 val > phy->throttle_temp[MT7996_MAX_TEMP_IDX] - 10) || 150 (i - 1 == MT7996_MAX_TEMP_IDX && 151 val - 10 < phy->throttle_temp[MT7996_CRIT_TEMP_IDX])) { 152 dev_err(phy->dev->mt76.dev, 153 "temp1_max shall be 10 degrees higher than temp1_crit."); 154 mutex_unlock(&phy->dev->mt76.mutex); 155 return -EINVAL; 156 } 157 158 phy->throttle_temp[i - 1] = val; 159 mutex_unlock(&phy->dev->mt76.mutex); 160 161 ret = mt7996_mcu_set_thermal_protect(phy, true); 162 if (ret) 163 return ret; 164 165 return count; 166 } 167 168 static SENSOR_DEVICE_ATTR_RO(temp1_input, mt7996_thermal_temp, 0); 169 static SENSOR_DEVICE_ATTR_RW(temp1_crit, mt7996_thermal_temp, 1); 170 static SENSOR_DEVICE_ATTR_RW(temp1_max, mt7996_thermal_temp, 2); 171 static SENSOR_DEVICE_ATTR_RO(throttle1, mt7996_thermal_temp, 3); 172 173 static struct attribute *mt7996_hwmon_attrs[] = { 174 &sensor_dev_attr_temp1_input.dev_attr.attr, 175 &sensor_dev_attr_temp1_crit.dev_attr.attr, 176 &sensor_dev_attr_temp1_max.dev_attr.attr, 177 &sensor_dev_attr_throttle1.dev_attr.attr, 178 NULL, 179 }; 180 ATTRIBUTE_GROUPS(mt7996_hwmon); 181 182 static int 183 mt7996_thermal_get_max_throttle_state(struct thermal_cooling_device *cdev, 184 unsigned long *state) 185 { 186 *state = MT7996_CDEV_THROTTLE_MAX; 187 188 return 0; 189 } 190 191 static int 192 mt7996_thermal_get_cur_throttle_state(struct thermal_cooling_device *cdev, 193 unsigned long *state) 194 { 195 struct mt7996_phy *phy = cdev->devdata; 196 197 *state = phy->cdev_state; 198 199 return 0; 200 } 201 202 static int 203 mt7996_thermal_set_cur_throttle_state(struct thermal_cooling_device *cdev, 204 unsigned long state) 205 { 206 struct mt7996_phy *phy = cdev->devdata; 207 u8 throttling = MT7996_THERMAL_THROTTLE_MAX - state; 208 int ret; 209 210 if (state > MT7996_CDEV_THROTTLE_MAX) { 211 dev_err(phy->dev->mt76.dev, 212 "please specify a valid throttling state\n"); 213 return -EINVAL; 214 } 215 216 if (state == phy->cdev_state) 217 return 0; 218 219 /* cooling_device convention: 0 = no cooling, more = more cooling 220 * mcu convention: 1 = max cooling, more = less cooling 221 */ 222 ret = mt7996_mcu_set_thermal_throttling(phy, throttling); 223 if (ret) 224 return ret; 225 226 phy->cdev_state = state; 227 228 return 0; 229 } 230 231 static const struct thermal_cooling_device_ops mt7996_thermal_ops = { 232 .get_max_state = mt7996_thermal_get_max_throttle_state, 233 .get_cur_state = mt7996_thermal_get_cur_throttle_state, 234 .set_cur_state = mt7996_thermal_set_cur_throttle_state, 235 }; 236 237 static void mt7996_unregister_thermal(struct mt7996_phy *phy) 238 { 239 struct wiphy *wiphy = phy->mt76->hw->wiphy; 240 char name[sizeof("cooling_deviceXXX")]; 241 242 if (!phy->cdev) 243 return; 244 245 snprintf(name, sizeof(name), "cooling_device%d", phy->mt76->band_idx); 246 sysfs_remove_link(&wiphy->dev.kobj, name); 247 thermal_cooling_device_unregister(phy->cdev); 248 } 249 250 static int mt7996_thermal_init(struct mt7996_phy *phy) 251 { 252 struct wiphy *wiphy = phy->mt76->hw->wiphy; 253 char cname[sizeof("cooling_deviceXXX")]; 254 struct thermal_cooling_device *cdev; 255 struct device *hwmon; 256 const char *name; 257 258 name = devm_kasprintf(&wiphy->dev, GFP_KERNEL, "mt7996_%s.%d", 259 wiphy_name(wiphy), phy->mt76->band_idx); 260 if (!name) 261 return -ENOMEM; 262 263 snprintf(cname, sizeof(cname), "cooling_device%d", phy->mt76->band_idx); 264 265 cdev = thermal_cooling_device_register(name, phy, &mt7996_thermal_ops); 266 if (!IS_ERR(cdev)) { 267 if (sysfs_create_link(&wiphy->dev.kobj, &cdev->device.kobj, 268 cname) < 0) 269 thermal_cooling_device_unregister(cdev); 270 else 271 phy->cdev = cdev; 272 } 273 274 /* initialize critical/maximum high temperature */ 275 phy->throttle_temp[MT7996_CRIT_TEMP_IDX] = MT7996_CRIT_TEMP; 276 phy->throttle_temp[MT7996_MAX_TEMP_IDX] = MT7996_MAX_TEMP; 277 278 if (!IS_REACHABLE(CONFIG_HWMON)) 279 return 0; 280 281 hwmon = devm_hwmon_device_register_with_groups(&wiphy->dev, name, phy, 282 mt7996_hwmon_groups); 283 284 if (IS_ERR(hwmon)) 285 return PTR_ERR(hwmon); 286 287 return 0; 288 } 289 290 static void mt7996_led_set_config(struct led_classdev *led_cdev, 291 u8 delay_on, u8 delay_off) 292 { 293 struct mt7996_dev *dev; 294 struct mt76_phy *mphy; 295 u32 val; 296 297 mphy = container_of(led_cdev, struct mt76_phy, leds.cdev); 298 dev = container_of(mphy->dev, struct mt7996_dev, mt76); 299 300 /* select TX blink mode, 2: only data frames */ 301 mt76_rmw_field(dev, MT_TMAC_TCR0(mphy->band_idx), MT_TMAC_TCR0_TX_BLINK, 2); 302 303 /* enable LED */ 304 mt76_wr(dev, MT_LED_EN(mphy->band_idx), 1); 305 306 /* set LED Tx blink on/off time */ 307 val = FIELD_PREP(MT_LED_TX_BLINK_ON_MASK, delay_on) | 308 FIELD_PREP(MT_LED_TX_BLINK_OFF_MASK, delay_off); 309 mt76_wr(dev, MT_LED_TX_BLINK(mphy->band_idx), val); 310 311 /* turn LED off */ 312 if (delay_off == 0xff && delay_on == 0x0) { 313 val = MT_LED_CTRL_POLARITY | MT_LED_CTRL_KICK; 314 } else { 315 /* control LED */ 316 val = MT_LED_CTRL_BLINK_MODE | MT_LED_CTRL_KICK; 317 if (mphy->band_idx == MT_BAND1) 318 val |= MT_LED_CTRL_BLINK_BAND_SEL; 319 } 320 321 if (mphy->leds.al) 322 val |= MT_LED_CTRL_POLARITY; 323 324 mt76_wr(dev, MT_LED_CTRL(mphy->band_idx), val); 325 mt76_clear(dev, MT_LED_CTRL(mphy->band_idx), MT_LED_CTRL_KICK); 326 } 327 328 static int mt7996_led_set_blink(struct led_classdev *led_cdev, 329 unsigned long *delay_on, 330 unsigned long *delay_off) 331 { 332 u16 delta_on = 0, delta_off = 0; 333 334 #define HW_TICK 10 335 #define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK) 336 337 if (*delay_on) 338 delta_on = TO_HW_TICK(*delay_on); 339 if (*delay_off) 340 delta_off = TO_HW_TICK(*delay_off); 341 342 mt7996_led_set_config(led_cdev, delta_on, delta_off); 343 344 return 0; 345 } 346 347 static void mt7996_led_set_brightness(struct led_classdev *led_cdev, 348 enum led_brightness brightness) 349 { 350 if (!brightness) 351 mt7996_led_set_config(led_cdev, 0, 0xff); 352 else 353 mt7996_led_set_config(led_cdev, 0xff, 0); 354 } 355 356 static void __mt7996_init_txpower(struct mt7996_phy *phy, 357 struct ieee80211_supported_band *sband) 358 { 359 struct mt7996_dev *dev = phy->dev; 360 int i, n_chains = hweight16(phy->mt76->chainmask); 361 int path_delta = mt76_tx_power_path_delta(n_chains); 362 int pwr_delta = mt7996_eeprom_get_power_delta(dev, sband->band); 363 struct mt76_power_limits limits; 364 365 for (i = 0; i < sband->n_channels; i++) { 366 struct ieee80211_channel *chan = &sband->channels[i]; 367 int target_power = mt7996_eeprom_get_target_power(dev, chan); 368 369 target_power += pwr_delta; 370 target_power = mt76_get_rate_power_limits(phy->mt76, chan, 371 &limits, 372 target_power); 373 target_power += path_delta; 374 target_power = DIV_ROUND_UP(target_power, 2); 375 chan->max_power = min_t(int, chan->max_reg_power, 376 target_power); 377 chan->orig_mpwr = target_power; 378 } 379 } 380 381 void mt7996_init_txpower(struct mt7996_phy *phy) 382 { 383 if (!phy) 384 return; 385 386 if (phy->mt76->cap.has_2ghz) 387 __mt7996_init_txpower(phy, &phy->mt76->sband_2g.sband); 388 if (phy->mt76->cap.has_5ghz) 389 __mt7996_init_txpower(phy, &phy->mt76->sband_5g.sband); 390 if (phy->mt76->cap.has_6ghz) 391 __mt7996_init_txpower(phy, &phy->mt76->sband_6g.sband); 392 } 393 394 static void 395 mt7996_regd_notifier(struct wiphy *wiphy, 396 struct regulatory_request *request) 397 { 398 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 399 struct mt7996_dev *dev = mt7996_hw_dev(hw); 400 struct mt7996_phy *phy; 401 402 memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2)); 403 dev->mt76.region = request->dfs_region; 404 405 mt7996_for_each_phy(dev, phy) { 406 if (dev->mt76.region == NL80211_DFS_UNSET) 407 mt7996_mcu_rdd_background_enable(phy, NULL); 408 409 mt7996_init_txpower(phy); 410 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN; 411 mt7996_dfs_init_radar_detector(phy); 412 } 413 } 414 415 static void 416 mt7996_init_wiphy_band(struct ieee80211_hw *hw, struct mt7996_phy *phy) 417 { 418 struct mt7996_dev *dev = phy->dev; 419 struct wiphy *wiphy = hw->wiphy; 420 int n_radios = hw->wiphy->n_radio; 421 struct wiphy_radio_freq_range *freq = &dev->radio_freqs[n_radios]; 422 struct wiphy_radio *radio = &dev->radios[n_radios]; 423 424 phy->slottime = 9; 425 phy->beacon_rate = -1; 426 phy->rxfilter = MT_WF_RFCR_DROP_OTHER_UC; 427 428 if (phy->mt76->cap.has_2ghz) { 429 phy->mt76->sband_2g.sband.ht_cap.cap |= 430 IEEE80211_HT_CAP_LDPC_CODING | 431 IEEE80211_HT_CAP_MAX_AMSDU; 432 phy->mt76->sband_2g.sband.ht_cap.ampdu_density = 433 IEEE80211_HT_MPDU_DENSITY_2; 434 freq->start_freq = 2400000; 435 freq->end_freq = 2500000; 436 } else if (phy->mt76->cap.has_5ghz) { 437 phy->mt76->sband_5g.sband.ht_cap.cap |= 438 IEEE80211_HT_CAP_LDPC_CODING | 439 IEEE80211_HT_CAP_MAX_AMSDU; 440 441 phy->mt76->sband_5g.sband.vht_cap.cap |= 442 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 443 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 444 IEEE80211_VHT_CAP_SHORT_GI_160 | 445 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ; 446 phy->mt76->sband_5g.sband.ht_cap.ampdu_density = 447 IEEE80211_HT_MPDU_DENSITY_1; 448 449 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 450 freq->start_freq = 5000000; 451 freq->end_freq = 5900000; 452 } else if (phy->mt76->cap.has_6ghz) { 453 freq->start_freq = 5900000; 454 freq->end_freq = 7200000; 455 } else { 456 return; 457 } 458 459 dev->radio_phy[n_radios] = phy; 460 radio->freq_range = freq; 461 radio->n_freq_range = 1; 462 radio->iface_combinations = &if_comb; 463 radio->n_iface_combinations = 1; 464 memcpy(dev->radio_addrs[n_radios].addr, phy->mt76->macaddr, ETH_ALEN); 465 hw->wiphy->n_addresses++; 466 hw->wiphy->n_radio++; 467 468 wiphy->available_antennas_rx |= phy->mt76->chainmask; 469 wiphy->available_antennas_tx |= phy->mt76->chainmask; 470 471 mt76_set_stream_caps(phy->mt76, true); 472 mt7996_set_stream_vht_txbf_caps(phy); 473 mt7996_set_stream_he_eht_caps(phy); 474 mt7996_init_txpower(phy); 475 } 476 477 static void 478 mt7996_init_wiphy(struct ieee80211_hw *hw, struct mtk_wed_device *wed) 479 { 480 struct mt7996_dev *dev = mt7996_hw_dev(hw); 481 struct mt76_dev *mdev = &dev->mt76; 482 struct wiphy *wiphy = hw->wiphy; 483 u16 max_subframes = dev->has_eht ? IEEE80211_MAX_AMPDU_BUF_EHT : 484 IEEE80211_MAX_AMPDU_BUF_HE; 485 486 hw->queues = 4; 487 hw->max_rx_aggregation_subframes = max_subframes; 488 hw->max_tx_aggregation_subframes = max_subframes; 489 if (is_mt7990(mdev) && dev->has_eht) 490 hw->max_tx_aggregation_subframes = 512; 491 492 hw->netdev_features = NETIF_F_RXCSUM; 493 if (mtk_wed_device_active(wed) || mt76_npu_device_active(mdev)) 494 hw->netdev_features |= NETIF_F_HW_TC; 495 496 hw->radiotap_timestamp.units_pos = 497 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US; 498 499 hw->sta_data_size = sizeof(struct mt7996_sta); 500 hw->vif_data_size = sizeof(struct mt7996_vif); 501 hw->chanctx_data_size = sizeof(struct mt76_chanctx); 502 503 wiphy->iface_combinations = is_mt7996(&dev->mt76) ? &if_comb_global : 504 &if_comb_global_7992; 505 wiphy->n_iface_combinations = 1; 506 507 wiphy->radio = dev->radios; 508 wiphy->addresses = dev->radio_addrs; 509 510 wiphy->reg_notifier = mt7996_regd_notifier; 511 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH | 512 WIPHY_FLAG_SUPPORTS_MLO; 513 wiphy->mbssid_max_interfaces = 16; 514 wiphy->iftype_ext_capab = iftypes_ext_capa; 515 wiphy->num_iftype_ext_capab = ARRAY_SIZE(iftypes_ext_capa); 516 517 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR); 518 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS); 519 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY); 520 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT); 521 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT); 522 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE); 523 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP); 524 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY); 525 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT); 526 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 527 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_MU_MIMO_AIR_SNIFFER); 528 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL); 529 530 if (mt7996_eeprom_has_background_radar(dev) && 531 (!mdev->dev->of_node || 532 !of_property_read_bool(mdev->dev->of_node, 533 "mediatek,disable-radar-background"))) 534 wiphy_ext_feature_set(wiphy, 535 NL80211_EXT_FEATURE_RADAR_BACKGROUND); 536 537 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 538 ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD); 539 ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD); 540 ieee80211_hw_set(hw, NO_VIRTUAL_MONITOR); 541 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 542 ieee80211_hw_set(hw, CHANCTX_STA_CSA); 543 ieee80211_hw_set(hw, CONNECTION_MONITOR); 544 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 545 546 hw->max_tx_fragments = 4; 547 wiphy->txq_memory_limit = 32 << 20; /* 32 MiB */ 548 549 /* init led callbacks */ 550 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 551 dev->mphy.leds.cdev.brightness_set = mt7996_led_set_brightness; 552 dev->mphy.leds.cdev.blink_set = mt7996_led_set_blink; 553 } 554 555 wiphy->max_scan_ssids = 4; 556 wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN; 557 558 mt7996_init_wiphy_band(hw, &dev->phy); 559 } 560 561 static void 562 mt7996_mac_init_band(struct mt7996_dev *dev, u8 band) 563 { 564 u32 mask, set; 565 566 if (!mt7996_band_valid(dev, band)) 567 return; 568 569 /* clear estimated value of EIFS for Rx duration & OBSS time */ 570 mt76_wr(dev, MT_WF_RMAC_RSVD0(band), MT_WF_RMAC_RSVD0_EIFS_CLR); 571 572 /* clear backoff time for Rx duration */ 573 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME1(band), 574 MT_WF_RMAC_MIB_NONQOSD_BACKOFF); 575 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME3(band), 576 MT_WF_RMAC_MIB_QOS01_BACKOFF); 577 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME4(band), 578 MT_WF_RMAC_MIB_QOS23_BACKOFF); 579 580 /* clear backoff time for Tx duration */ 581 mt76_clear(dev, MT_WTBLOFF_ACR(band), 582 MT_WTBLOFF_ADM_BACKOFFTIME); 583 584 /* clear backoff time and set software compensation for OBSS time */ 585 mask = MT_WF_RMAC_MIB_OBSS_BACKOFF | MT_WF_RMAC_MIB_ED_OFFSET; 586 set = FIELD_PREP(MT_WF_RMAC_MIB_OBSS_BACKOFF, 0) | 587 FIELD_PREP(MT_WF_RMAC_MIB_ED_OFFSET, 4); 588 mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set); 589 590 /* filter out non-resp frames and get instanstaeous signal reporting */ 591 mask = MT_WTBLOFF_RSCR_RCPI_MODE | MT_WTBLOFF_RSCR_RCPI_PARAM; 592 set = FIELD_PREP(MT_WTBLOFF_RSCR_RCPI_MODE, 0) | 593 FIELD_PREP(MT_WTBLOFF_RSCR_RCPI_PARAM, 0x3); 594 mt76_rmw(dev, MT_WTBLOFF_RSCR(band), mask, set); 595 596 /* MT_TXD5_TX_STATUS_HOST (MPDU format) has higher priority than 597 * MT_AGG_ACR_PPDU_TXS2H (PPDU format) even though ACR bit is set. 598 */ 599 mt76_set(dev, MT_AGG_ACR4(band), MT_AGG_ACR_PPDU_TXS2H); 600 601 if (!is_mt7996(&dev->mt76)) 602 mt7996_mcu_set_bssid_mapping_addr(&dev->mt76, band); 603 } 604 605 static void mt7996_mac_init_basic_rates(struct mt7996_dev *dev) 606 { 607 int i; 608 609 for (i = 0; i < ARRAY_SIZE(mt76_rates); i++) { 610 u16 rate = mt76_rates[i].hw_value; 611 /* odd index for driver, even index for firmware */ 612 u16 idx = MT7996_BASIC_RATES_TBL + 2 * i; 613 614 rate = FIELD_PREP(MT_TX_RATE_MODE, rate >> 8) | 615 FIELD_PREP(MT_TX_RATE_IDX, rate & GENMASK(7, 0)); 616 mt7996_mcu_set_fixed_rate_table(&dev->phy, idx, rate, false); 617 } 618 } 619 620 void mt7996_mac_init(struct mt7996_dev *dev) 621 { 622 #define HIF_TXD_V2_1 0x21 623 int i, rx_path_type; 624 625 mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT); 626 627 for (i = 0; i < mt7996_wtbl_size(dev); i++) 628 mt7996_mac_wtbl_update(dev, i, 629 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 630 631 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 632 i = dev->mphy.leds.pin ? MT_LED_GPIO_MUX3 : MT_LED_GPIO_MUX2; 633 mt76_rmw_field(dev, i, MT_LED_GPIO_SEL_MASK, 4); 634 } 635 636 /* rro module init */ 637 if (dev->hif2) { 638 if (mt76_npu_device_active(&dev->mt76)) 639 rx_path_type = is_mt7996(&dev->mt76) ? 6 : 8; 640 else 641 rx_path_type = is_mt7996(&dev->mt76) ? 2 : 7; 642 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 643 rx_path_type); 644 } else { 645 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 0); 646 } 647 648 if (mt7996_has_hwrro(dev)) { 649 u16 timeout; 650 651 timeout = mt76_rr(dev, MT_HW_REV) == MT_HW_REV1 ? 512 : 128; 652 mt7996_mcu_set_rro(dev, UNI_RRO_SET_FLUSH_TIMEOUT, timeout); 653 mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 654 is_mt7996(&dev->mt76) ? 1 : 2); 655 mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 656 !is_mt7996(&dev->mt76)); 657 } else { 658 mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 3); 659 mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 1); 660 } 661 662 mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), 663 MCU_WA_PARAM_HW_PATH_HIF_VER, 664 HIF_TXD_V2_1, 0); 665 666 for (i = MT_BAND0; i <= MT_BAND2; i++) 667 mt7996_mac_init_band(dev, i); 668 669 mt7996_mac_init_basic_rates(dev); 670 } 671 672 int mt7996_txbf_init(struct mt7996_dev *dev) 673 { 674 int ret; 675 676 if (mt7996_band_valid(dev, MT_BAND1) || 677 mt7996_band_valid(dev, MT_BAND2)) { 678 ret = mt7996_mcu_set_txbf(dev, BF_MOD_EN_CTRL); 679 if (ret) 680 return ret; 681 } 682 683 /* trigger sounding packets */ 684 ret = mt7996_mcu_set_txbf(dev, BF_SOUNDING_ON); 685 if (ret) 686 return ret; 687 688 /* enable eBF */ 689 return mt7996_mcu_set_txbf(dev, BF_HW_EN_UPDATE); 690 } 691 692 static int mt7996_register_phy(struct mt7996_dev *dev, enum mt76_band_id band) 693 { 694 struct mt7996_phy *phy; 695 struct mt76_phy *mphy; 696 u32 mac_ofs, hif1_ofs = 0; 697 int ret; 698 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 699 700 if (!mt7996_band_valid(dev, band)) 701 return 0; 702 703 if (dev->hif2 && 704 ((is_mt7992(&dev->mt76) && band == MT_BAND1) || 705 (is_mt7996(&dev->mt76) && band == MT_BAND2 && 706 !mt76_npu_device_active(&dev->mt76)))) { 707 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); 708 wed = &dev->mt76.mmio.wed_hif2; 709 } 710 711 mphy = mt76_alloc_radio_phy(&dev->mt76, sizeof(*phy), band); 712 if (!mphy) 713 return -ENOMEM; 714 715 phy = mphy->priv; 716 phy->dev = dev; 717 phy->mt76 = mphy; 718 mphy->dev->phys[band] = mphy; 719 720 INIT_DELAYED_WORK(&mphy->mac_work, mt7996_mac_work); 721 722 ret = mt7996_eeprom_parse_hw_cap(dev, phy); 723 if (ret) 724 goto error; 725 726 mac_ofs = band == MT_BAND2 ? MT_EE_MAC_ADDR3 : MT_EE_MAC_ADDR2; 727 memcpy(mphy->macaddr, dev->mt76.eeprom.data + mac_ofs, ETH_ALEN); 728 /* Make the extra PHY MAC address local without overlapping with 729 * the usual MAC address allocation scheme on multiple virtual interfaces 730 */ 731 if (!is_valid_ether_addr(mphy->macaddr)) { 732 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR, 733 ETH_ALEN); 734 mphy->macaddr[0] |= 2; 735 mphy->macaddr[0] ^= BIT(7); 736 if (band == MT_BAND2) 737 mphy->macaddr[0] ^= BIT(6); 738 } 739 ret = mt76_eeprom_override(mphy); 740 if (ret) 741 goto error; 742 743 /* init wiphy according to mphy and phy */ 744 mt7996_init_wiphy_band(mphy->hw, phy); 745 746 if (is_mt7996(&dev->mt76) && 747 ((band == MT_BAND1 && !dev->hif2) || 748 (band == MT_BAND2 && mt76_npu_device_active(&dev->mt76)))) { 749 int i; 750 751 for (i = 0; i <= MT_TXQ_PSD; i++) 752 mphy->q_tx[i] = dev->mt76.phys[band - 1]->q_tx[0]; 753 } else { 754 int size = is_mt7996(&dev->mt76) && 755 mt76_npu_device_active(&dev->mt76) 756 ? MT7996_NPU_TX_RING_SIZE / 2 : MT7996_TX_RING_SIZE; 757 758 ret = mt7996_init_tx_queues(mphy->priv, MT_TXQ_ID(band), size, 759 MT_TXQ_RING_BASE(band) + hif1_ofs, 760 wed); 761 if (ret) 762 goto error; 763 } 764 765 ret = mt76_register_phy(mphy, true, mt76_rates, 766 ARRAY_SIZE(mt76_rates)); 767 if (ret) 768 goto error; 769 770 if (wed == &dev->mt76.mmio.wed_hif2 && mtk_wed_device_active(wed)) { 771 mt76_wr(dev, MT_INT_PCIE1_MASK_CSR, MT_INT_TX_RX_DONE_EXT); 772 mtk_wed_device_start(&dev->mt76.mmio.wed_hif2, 773 MT_INT_TX_RX_DONE_EXT); 774 } 775 776 return 0; 777 778 error: 779 mphy->dev->phys[band] = NULL; 780 return ret; 781 } 782 783 static void 784 mt7996_unregister_phy(struct mt7996_phy *phy) 785 { 786 if (phy) 787 mt7996_unregister_thermal(phy); 788 } 789 790 static void mt7996_init_work(struct work_struct *work) 791 { 792 struct mt7996_dev *dev = container_of(work, struct mt7996_dev, 793 init_work); 794 795 mt7996_mcu_set_eeprom(dev); 796 mt7996_mac_init(dev); 797 mt7996_txbf_init(dev); 798 799 if (!is_mt7990(&dev->mt76)) 800 mt7996_mcu_set_dup_wtbl(dev); 801 } 802 803 void mt7996_wfsys_reset(struct mt7996_dev *dev) 804 { 805 if (!is_mt7990(&dev->mt76)) { 806 mt76_set(dev, MT_WF_SUBSYS_RST, 0x1); 807 msleep(20); 808 809 mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1); 810 msleep(20); 811 812 return; 813 } 814 815 if (!dev->recovery.hw_full_reset) 816 return; 817 818 mt76_set(dev, MT_WF_SUBSYS_RST, 819 MT_WF_SUBSYS_RST_WHOLE_PATH_RST_REVERT | 820 MT_WF_SUBSYS_RST_BYPASS_WFDMA_SLP_PROT | 821 MT_WF_SUBSYS_RST_BYPASS_WFDMA2_SLP_PROT); 822 mt76_rmw(dev, MT_WF_SUBSYS_RST, 823 MT_WF_SUBSYS_RST_WHOLE_PATH_RST_REVERT_CYCLE, 824 u32_encode_bits(0x20, MT_WF_SUBSYS_RST_WHOLE_PATH_RST_REVERT_CYCLE)); 825 mt76_clear(dev, MT_WF_L05_RST, MT_WF_L05_RST_WF_RST_MASK); 826 mt76_set(dev, MT_WF_SUBSYS_RST, MT_WF_SUBSYS_RST_WHOLE_PATH_RST); 827 msleep(20); 828 829 if (mt76_poll(dev, MT_WF_L05_RST, MT_WF_L05_RST_WF_RST_MASK, 0x1a, 1000)) 830 return; 831 832 dev_err(dev->mt76.dev, "wfsys reset fail\n"); 833 } 834 835 static void mt7996_rro_hw_init_v3(struct mt7996_dev *dev) 836 { 837 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 838 u32 session_id; 839 840 if (dev->mt76.hwrro_mode == MT76_HWRRO_V3_1) 841 return; 842 843 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 844 if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed)) { 845 wed->wlan.ind_cmd.win_size = 846 ffs(MT7996_RRO_WINDOW_MAX_LEN) - 6; 847 if (is_mt7996(&dev->mt76)) 848 wed->wlan.ind_cmd.particular_sid = 849 MT7996_RRO_MAX_SESSION; 850 else 851 wed->wlan.ind_cmd.particular_sid = 1; 852 wed->wlan.ind_cmd.particular_se_phys = 853 dev->wed_rro.session.phy_addr; 854 wed->wlan.ind_cmd.se_group_nums = MT7996_RRO_ADDR_ELEM_LEN; 855 wed->wlan.ind_cmd.ack_sn_addr = MT_RRO_ACK_SN_CTRL; 856 } 857 #endif /* CONFIG_NET_MEDIATEK_SOC_WED */ 858 859 if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed)) { 860 mt76_wr(dev, MT_RRO_IND_CMD_SIGNATURE_BASE0, 0x15010e00); 861 mt76_set(dev, MT_RRO_IND_CMD_SIGNATURE_BASE1, 862 MT_RRO_IND_CMD_SIGNATURE_BASE1_EN); 863 } else { 864 mt76_wr(dev, MT_RRO_IND_CMD_SIGNATURE_BASE0, 0); 865 mt76_wr(dev, MT_RRO_IND_CMD_SIGNATURE_BASE1, 0); 866 } 867 868 /* particular session configure */ 869 /* use max session idx + 1 as particular session id */ 870 mt76_wr(dev, MT_RRO_PARTICULAR_CFG0, dev->wed_rro.session.phy_addr); 871 872 session_id = is_mt7996(&dev->mt76) ? MT7996_RRO_MAX_SESSION : 1; 873 mt76_wr(dev, MT_RRO_PARTICULAR_CFG1, 874 MT_RRO_PARTICULAR_CONFG_EN | 875 FIELD_PREP(MT_RRO_PARTICULAR_SID, session_id)); 876 } 877 878 void mt7996_rro_hw_init(struct mt7996_dev *dev) 879 { 880 u32 reg = MT_RRO_ADDR_ELEM_SEG_ADDR0; 881 int i; 882 883 if (!mt7996_has_hwrro(dev)) 884 return; 885 886 INIT_LIST_HEAD(&dev->wed_rro.page_cache); 887 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.page_map); i++) 888 INIT_LIST_HEAD(&dev->wed_rro.page_map[i]); 889 890 if (!is_mt7996(&dev->mt76)) { 891 reg = MT_RRO_MSDU_PG_SEG_ADDR0; 892 893 if (dev->mt76.hwrro_mode == MT76_HWRRO_V3_1) { 894 mt76_clear(dev, MT_RRO_3_0_EMU_CONF, 895 MT_RRO_3_0_EMU_CONF_EN_MASK); 896 mt76_set(dev, MT_RRO_3_1_GLOBAL_CONFIG, 897 MT_RRO_3_1_GLOBAL_CONFIG_RXDMAD_SEL); 898 if (!mtk_wed_device_active(&dev->mt76.mmio.wed) && 899 !mt76_npu_device_active(&dev->mt76)) { 900 mt76_set(dev, MT_RRO_3_1_GLOBAL_CONFIG, 901 MT_RRO_3_1_GLOBAL_CONFIG_RX_DIDX_WR_EN | 902 MT_RRO_3_1_GLOBAL_CONFIG_RX_CIDX_RD_EN); 903 mt76_wr(dev, MT_RRO_RX_RING_AP_CIDX_ADDR, 904 dev->wed_rro.emi_rings_cpu.phy_addr >> 4); 905 mt76_wr(dev, MT_RRO_RX_RING_AP_DIDX_ADDR, 906 dev->wed_rro.emi_rings_dma.phy_addr >> 4); 907 } 908 } else { 909 /* set emul 3.0 function */ 910 mt76_set(dev, MT_RRO_3_0_EMU_CONF, MT_RRO_3_0_EMU_CONF_EN_MASK); 911 912 mt76_wr(dev, MT_RRO_ADDR_ARRAY_BASE0, 913 dev->wed_rro.addr_elem[0].phy_addr); 914 } 915 916 mt76_set(dev, MT_RRO_3_1_GLOBAL_CONFIG, 917 MT_RRO_3_1_GLOBAL_CONFIG_INTERLEAVE_EN); 918 919 /* setup Msdu page address */ 920 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.msdu_pg); i++) { 921 mt76_wr(dev, reg, 922 dev->wed_rro.msdu_pg[i].phy_addr >> 4); 923 reg += 4; 924 } 925 } else { 926 /* TODO: remove line after WM has set */ 927 mt76_clear(dev, WF_RRO_AXI_MST_CFG, 928 WF_RRO_AXI_MST_CFG_DIDX_OK); 929 930 /* setup BA bitmap cache address */ 931 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE0, 932 dev->wed_rro.ba_bitmap[0].phy_addr); 933 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE1, 0); 934 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT0, 935 dev->wed_rro.ba_bitmap[1].phy_addr); 936 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT1, 0); 937 938 /* Setup Address element address */ 939 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) { 940 mt76_wr(dev, reg, 941 dev->wed_rro.addr_elem[i].phy_addr >> 4); 942 reg += 4; 943 } 944 945 /* Setup Address element address - separate address segment 946 * mode. 947 */ 948 mt76_wr(dev, MT_RRO_ADDR_ARRAY_BASE1, 949 MT_RRO_ADDR_ARRAY_ELEM_ADDR_SEG_MODE); 950 } 951 952 mt7996_rro_hw_init_v3(dev); 953 954 /* interrupt enable */ 955 mt76_wr(dev, MT_RRO_HOST_INT_ENA, 956 MT_RRO_HOST_INT_ENA_HOST_RRO_DONE_ENA); 957 } 958 959 static int mt7996_wed_rro_init(struct mt7996_dev *dev) 960 { 961 u32 val = FIELD_PREP(WED_RRO_ADDR_SIGNATURE_MASK, 0xff); 962 struct mt7996_wed_rro_addr *addr; 963 void *ptr; 964 int i; 965 966 if (!mt7996_has_hwrro(dev)) 967 return 0; 968 969 if (dev->mt76.hwrro_mode == MT76_HWRRO_V3) { 970 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.ba_bitmap); i++) { 971 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 972 MT7996_RRO_BA_BITMAP_CR_SIZE, 973 &dev->wed_rro.ba_bitmap[i].phy_addr, 974 GFP_KERNEL); 975 if (!ptr) 976 return -ENOMEM; 977 978 dev->wed_rro.ba_bitmap[i].ptr = ptr; 979 } 980 } 981 982 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) { 983 int j; 984 985 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 986 MT7996_RRO_WINDOW_MAX_SIZE * sizeof(*addr), 987 &dev->wed_rro.addr_elem[i].phy_addr, 988 GFP_KERNEL); 989 if (!ptr) 990 return -ENOMEM; 991 992 dev->wed_rro.addr_elem[i].ptr = ptr; 993 memset(dev->wed_rro.addr_elem[i].ptr, 0, 994 MT7996_RRO_WINDOW_MAX_SIZE * sizeof(*addr)); 995 996 addr = dev->wed_rro.addr_elem[i].ptr; 997 for (j = 0; j < MT7996_RRO_WINDOW_MAX_SIZE; j++) { 998 addr->data = cpu_to_le32(val); 999 addr++; 1000 } 1001 1002 if (is_mt7996(&dev->mt76) && 1003 mt76_npu_device_active(&dev->mt76)) 1004 mt76_npu_send_txrx_addr(&dev->mt76, 0, i, 1005 dev->wed_rro.addr_elem[i].phy_addr, 1006 0, 0); 1007 1008 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 1009 if (mtk_wed_device_active(&dev->mt76.mmio.wed) && 1010 mtk_wed_get_rx_capa(&dev->mt76.mmio.wed)) { 1011 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 1012 1013 wed->wlan.ind_cmd.addr_elem_phys[i] = 1014 dev->wed_rro.addr_elem[i].phy_addr; 1015 } 1016 #endif /* CONFIG_NET_MEDIATEK_SOC_WED */ 1017 } 1018 1019 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.msdu_pg); i++) { 1020 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 1021 MT7996_RRO_MSDU_PG_SIZE_PER_CR, 1022 &dev->wed_rro.msdu_pg[i].phy_addr, 1023 GFP_KERNEL); 1024 if (!ptr) 1025 return -ENOMEM; 1026 1027 dev->wed_rro.msdu_pg[i].ptr = ptr; 1028 1029 memset(dev->wed_rro.msdu_pg[i].ptr, 0, 1030 MT7996_RRO_MSDU_PG_SIZE_PER_CR); 1031 } 1032 1033 if (!mtk_wed_device_active(&dev->mt76.mmio.wed) && 1034 dev->mt76.hwrro_mode == MT76_HWRRO_V3_1) { 1035 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 1036 sizeof(*dev->wed_rro.emi_rings_cpu.ptr), 1037 &dev->wed_rro.emi_rings_cpu.phy_addr, 1038 GFP_KERNEL); 1039 if (!ptr) 1040 return -ENOMEM; 1041 1042 dev->wed_rro.emi_rings_cpu.ptr = ptr; 1043 1044 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 1045 sizeof(*dev->wed_rro.emi_rings_dma.ptr), 1046 &dev->wed_rro.emi_rings_dma.phy_addr, 1047 GFP_KERNEL); 1048 if (!ptr) 1049 return -ENOMEM; 1050 1051 dev->wed_rro.emi_rings_dma.ptr = ptr; 1052 } 1053 1054 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 1055 MT7996_RRO_WINDOW_MAX_LEN * sizeof(*addr), 1056 &dev->wed_rro.session.phy_addr, 1057 GFP_KERNEL); 1058 if (!ptr) 1059 return -ENOMEM; 1060 1061 dev->wed_rro.session.ptr = ptr; 1062 addr = dev->wed_rro.session.ptr; 1063 for (i = 0; i < MT7996_RRO_WINDOW_MAX_LEN; i++) { 1064 addr->data = cpu_to_le32(val); 1065 addr++; 1066 } 1067 1068 if (is_mt7996(&dev->mt76) && mt76_npu_device_active(&dev->mt76)) 1069 mt76_npu_send_txrx_addr(&dev->mt76, 1, 0, 1070 dev->wed_rro.session.phy_addr, 0, 0); 1071 1072 mt7996_rro_hw_init(dev); 1073 1074 return mt7996_dma_rro_init(dev); 1075 } 1076 1077 static void mt7996_wed_rro_free(struct mt7996_dev *dev) 1078 { 1079 int i; 1080 1081 if (!mt7996_has_hwrro(dev)) 1082 return; 1083 1084 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.ba_bitmap); i++) { 1085 if (!dev->wed_rro.ba_bitmap[i].ptr) 1086 continue; 1087 1088 dmam_free_coherent(dev->mt76.dma_dev, 1089 MT7996_RRO_BA_BITMAP_CR_SIZE, 1090 dev->wed_rro.ba_bitmap[i].ptr, 1091 dev->wed_rro.ba_bitmap[i].phy_addr); 1092 } 1093 1094 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) { 1095 if (!dev->wed_rro.addr_elem[i].ptr) 1096 continue; 1097 1098 dmam_free_coherent(dev->mt76.dma_dev, 1099 MT7996_RRO_WINDOW_MAX_SIZE * 1100 sizeof(struct mt7996_wed_rro_addr), 1101 dev->wed_rro.addr_elem[i].ptr, 1102 dev->wed_rro.addr_elem[i].phy_addr); 1103 } 1104 1105 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.msdu_pg); i++) { 1106 if (!dev->wed_rro.msdu_pg[i].ptr) 1107 continue; 1108 1109 dmam_free_coherent(dev->mt76.dma_dev, 1110 MT7996_RRO_MSDU_PG_SIZE_PER_CR, 1111 dev->wed_rro.msdu_pg[i].ptr, 1112 dev->wed_rro.msdu_pg[i].phy_addr); 1113 } 1114 1115 if (dev->wed_rro.emi_rings_cpu.ptr) 1116 dmam_free_coherent(dev->mt76.dma_dev, 1117 sizeof(*dev->wed_rro.emi_rings_cpu.ptr), 1118 dev->wed_rro.emi_rings_cpu.ptr, 1119 dev->wed_rro.emi_rings_cpu.phy_addr); 1120 1121 if (dev->wed_rro.emi_rings_dma.ptr) 1122 dmam_free_coherent(dev->mt76.dma_dev, 1123 sizeof(*dev->wed_rro.emi_rings_dma.ptr), 1124 dev->wed_rro.emi_rings_dma.ptr, 1125 dev->wed_rro.emi_rings_dma.phy_addr); 1126 1127 if (!dev->wed_rro.session.ptr) 1128 return; 1129 1130 dmam_free_coherent(dev->mt76.dma_dev, 1131 MT7996_RRO_WINDOW_MAX_LEN * 1132 sizeof(struct mt7996_wed_rro_addr), 1133 dev->wed_rro.session.ptr, 1134 dev->wed_rro.session.phy_addr); 1135 } 1136 1137 static void mt7996_wed_rro_work(struct work_struct *work) 1138 { 1139 u32 val = FIELD_PREP(WED_RRO_ADDR_SIGNATURE_MASK, 0xff); 1140 struct mt7996_dev *dev; 1141 LIST_HEAD(list); 1142 1143 dev = (struct mt7996_dev *)container_of(work, struct mt7996_dev, 1144 wed_rro.work); 1145 1146 spin_lock_bh(&dev->wed_rro.lock); 1147 list_splice_init(&dev->wed_rro.poll_list, &list); 1148 spin_unlock_bh(&dev->wed_rro.lock); 1149 1150 while (!list_empty(&list)) { 1151 struct mt7996_wed_rro_session_id *e; 1152 int i; 1153 1154 e = list_first_entry(&list, struct mt7996_wed_rro_session_id, 1155 list); 1156 list_del_init(&e->list); 1157 1158 if (mt76_npu_device_active(&dev->mt76)) { 1159 if (is_mt7996(&dev->mt76)) 1160 mt76_npu_send_txrx_addr(&dev->mt76, 3, e->id, 1161 0, 0, 0); 1162 goto reset_session; 1163 } 1164 1165 for (i = 0; i < MT7996_RRO_WINDOW_MAX_LEN; i++) { 1166 void *ptr = dev->wed_rro.session.ptr; 1167 struct mt7996_wed_rro_addr *elem; 1168 u32 idx, elem_id = i; 1169 1170 if (e->id == MT7996_RRO_MAX_SESSION) 1171 goto reset; 1172 1173 idx = e->id / MT7996_RRO_BA_BITMAP_SESSION_SIZE; 1174 if (idx >= ARRAY_SIZE(dev->wed_rro.addr_elem)) 1175 goto out; 1176 1177 ptr = dev->wed_rro.addr_elem[idx].ptr; 1178 elem_id += 1179 (e->id % MT7996_RRO_BA_BITMAP_SESSION_SIZE) * 1180 MT7996_RRO_WINDOW_MAX_LEN; 1181 reset: 1182 elem = ptr + elem_id * sizeof(*elem); 1183 elem->data |= cpu_to_le32(val); 1184 } 1185 reset_session: 1186 mt7996_mcu_wed_rro_reset_sessions(dev, e->id); 1187 out: 1188 kfree(e); 1189 } 1190 } 1191 1192 static int mt7996_variant_type_init(struct mt7996_dev *dev) 1193 { 1194 u32 val = mt76_rr(dev, MT_PAD_GPIO); 1195 u8 var_type; 1196 1197 switch (mt76_chip(&dev->mt76)) { 1198 case MT7996_DEVICE_ID: 1199 if (val & MT_PAD_GPIO_2ADIE_TBTC) 1200 var_type = MT7996_VAR_TYPE_233; 1201 else 1202 var_type = MT7996_VAR_TYPE_444; 1203 break; 1204 case MT7992_DEVICE_ID: 1205 if (val & MT_PAD_GPIO_ADIE_SINGLE) 1206 var_type = MT7992_VAR_TYPE_23; 1207 else if (u32_get_bits(val, MT_PAD_GPIO_ADIE_COMB_7992)) 1208 var_type = MT7992_VAR_TYPE_44; 1209 else 1210 var_type = MT7992_VAR_TYPE_24; 1211 break; 1212 case MT7990_DEVICE_ID: 1213 var_type = MT7990_VAR_TYPE_23; 1214 break; 1215 default: 1216 return -EINVAL; 1217 } 1218 1219 dev->var.type = var_type; 1220 return 0; 1221 } 1222 1223 static int mt7996_variant_fem_init(struct mt7996_dev *dev) 1224 { 1225 #define MT7976C_EFUSE_OFFSET 0x470 1226 u8 buf[MT7996_EEPROM_BLOCK_SIZE], idx, adie_idx, adie_comb; 1227 u32 regval, val = mt76_rr(dev, MT_PAD_GPIO); 1228 u16 adie_id, adie_ver; 1229 bool is_7976c; 1230 int ret; 1231 1232 if (is_mt7992(&dev->mt76)) { 1233 adie_idx = (val & MT_PAD_GPIO_ADIE_SINGLE) ? 0 : 1; 1234 adie_comb = u32_get_bits(val, MT_PAD_GPIO_ADIE_COMB_7992); 1235 } else { 1236 adie_idx = 0; 1237 adie_comb = u32_get_bits(val, MT_PAD_GPIO_ADIE_COMB); 1238 } 1239 1240 ret = mt7996_mcu_rf_regval(dev, MT_ADIE_CHIP_ID(adie_idx), ®val, false); 1241 if (ret) 1242 return ret; 1243 1244 ret = mt7996_mcu_get_eeprom(dev, MT7976C_EFUSE_OFFSET, buf, sizeof(buf), 1245 EEPROM_MODE_EFUSE); 1246 if (ret && ret != -EINVAL) 1247 return ret; 1248 1249 adie_ver = u32_get_bits(regval, MT_ADIE_VERSION_MASK); 1250 idx = MT7976C_EFUSE_OFFSET % MT7996_EEPROM_BLOCK_SIZE; 1251 is_7976c = adie_ver == 0x8a10 || adie_ver == 0x8b00 || 1252 adie_ver == 0x8c10 || (!ret && buf[idx] == 0xc); 1253 1254 adie_id = u32_get_bits(regval, MT_ADIE_CHIP_ID_MASK); 1255 if (adie_id == 0x7975 || adie_id == 0x7979 || 1256 (adie_id == 0x7976 && is_7976c)) 1257 dev->var.fem = MT7996_FEM_INT; 1258 else if (adie_id == 0x7977 && adie_comb == 1) 1259 dev->var.fem = MT7996_FEM_MIX; 1260 else 1261 dev->var.fem = MT7996_FEM_EXT; 1262 1263 return 0; 1264 } 1265 1266 static int mt7996_init_hardware(struct mt7996_dev *dev) 1267 { 1268 int ret, idx; 1269 1270 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 1271 if (is_mt7992(&dev->mt76)) { 1272 mt76_rmw(dev, MT_AFE_CTL_BAND_PLL_03(MT_BAND0), MT_AFE_CTL_BAND_PLL_03_MSB_EN, 0); 1273 mt76_rmw(dev, MT_AFE_CTL_BAND_PLL_03(MT_BAND1), MT_AFE_CTL_BAND_PLL_03_MSB_EN, 0); 1274 } 1275 1276 INIT_WORK(&dev->init_work, mt7996_init_work); 1277 INIT_WORK(&dev->wed_rro.work, mt7996_wed_rro_work); 1278 INIT_LIST_HEAD(&dev->wed_rro.poll_list); 1279 spin_lock_init(&dev->wed_rro.lock); 1280 1281 ret = mt7996_variant_type_init(dev); 1282 if (ret) 1283 return ret; 1284 1285 ret = mt7996_dma_init(dev); 1286 if (ret) 1287 return ret; 1288 1289 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state); 1290 1291 ret = mt7996_mcu_init(dev); 1292 if (ret) 1293 return ret; 1294 1295 ret = mt7996_wed_rro_init(dev); 1296 if (ret) 1297 return ret; 1298 1299 ret = mt7996_variant_fem_init(dev); 1300 if (ret) 1301 return ret; 1302 1303 ret = mt7996_eeprom_init(dev); 1304 if (ret < 0) 1305 return ret; 1306 1307 /* Beacon and mgmt frames should occupy wcid 0 */ 1308 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7996_WTBL_STA); 1309 if (idx) 1310 return -ENOSPC; 1311 1312 dev->mt76.global_wcid.idx = idx; 1313 dev->mt76.global_wcid.hw_key_idx = -1; 1314 dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET; 1315 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid); 1316 1317 return 0; 1318 } 1319 1320 void mt7996_set_stream_vht_txbf_caps(struct mt7996_phy *phy) 1321 { 1322 int sts; 1323 u32 *cap; 1324 1325 if (!phy->mt76->cap.has_5ghz) 1326 return; 1327 1328 sts = hweight16(phy->mt76->chainmask); 1329 cap = &phy->mt76->sband_5g.sband.vht_cap.cap; 1330 1331 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 1332 IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE; 1333 1334 if (is_mt7992(phy->mt76->dev)) 1335 *cap |= FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 4); 1336 else 1337 *cap |= FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 3); 1338 1339 *cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK | 1340 IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 1341 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE); 1342 1343 if (sts < 2) 1344 return; 1345 1346 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 1347 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE | 1348 FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, sts - 1); 1349 } 1350 1351 static void 1352 mt7996_set_stream_he_txbf_caps(struct mt7996_phy *phy, 1353 struct ieee80211_sta_he_cap *he_cap, int vif, 1354 enum nl80211_band band) 1355 { 1356 struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem; 1357 int sts = hweight16(phy->mt76->chainmask); 1358 bool non_2g = band != NL80211_BAND_2GHZ; 1359 u8 c; 1360 1361 #ifdef CONFIG_MAC80211_MESH 1362 if (vif == NL80211_IFTYPE_MESH_POINT) 1363 return; 1364 #endif 1365 1366 elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 1367 elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 1368 1369 c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK | 1370 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK; 1371 elem->phy_cap_info[5] &= ~c; 1372 1373 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 1374 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 1375 elem->phy_cap_info[6] &= ~c; 1376 1377 elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK; 1378 1379 c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 1380 IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO; 1381 elem->phy_cap_info[2] |= c; 1382 1383 c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE; 1384 1385 if (is_mt7992(phy->mt76->dev)) 1386 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_5 | 1387 (IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_5 * non_2g); 1388 else 1389 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4 | 1390 (IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4 * non_2g); 1391 1392 elem->phy_cap_info[4] |= c; 1393 1394 /* do not support NG16 due to spec D4.0 changes subcarrier idx */ 1395 c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 1396 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU; 1397 1398 if (vif == NL80211_IFTYPE_STATION) 1399 c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO; 1400 1401 elem->phy_cap_info[6] |= c; 1402 1403 if (sts < 2) 1404 return; 1405 1406 /* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */ 1407 elem->phy_cap_info[7] |= min_t(int, sts - 1, 2) << 3; 1408 1409 if (!(vif == NL80211_IFTYPE_AP || vif == NL80211_IFTYPE_STATION)) 1410 return; 1411 1412 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 1413 1414 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 1415 sts - 1) | 1416 (FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK, 1417 sts - 1) * non_2g); 1418 1419 elem->phy_cap_info[5] |= c; 1420 1421 if (vif != NL80211_IFTYPE_AP) 1422 return; 1423 1424 elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 1425 1426 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 1427 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 1428 elem->phy_cap_info[6] |= c; 1429 1430 c = 0; 1431 if (non_2g) 1432 c |= IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ | 1433 IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ; 1434 elem->phy_cap_info[7] |= c; 1435 } 1436 1437 static void 1438 mt7996_init_he_caps(struct mt7996_phy *phy, enum nl80211_band band, 1439 struct ieee80211_sband_iftype_data *data, 1440 enum nl80211_iftype iftype) 1441 { 1442 struct ieee80211_sta_he_cap *he_cap = &data->he_cap; 1443 struct ieee80211_he_cap_elem *he_cap_elem = &he_cap->he_cap_elem; 1444 struct ieee80211_he_mcs_nss_supp *he_mcs = &he_cap->he_mcs_nss_supp; 1445 int i, nss = hweight8(phy->mt76->antenna_mask); 1446 u16 mcs_map = 0; 1447 1448 for (i = 0; i < 8; i++) { 1449 if (i < nss) 1450 mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 1451 else 1452 mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 1453 } 1454 1455 he_cap->has_he = true; 1456 1457 he_cap_elem->mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; 1458 he_cap_elem->mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 1459 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3; 1460 he_cap_elem->mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 1461 1462 if (band == NL80211_BAND_2GHZ) 1463 he_cap_elem->phy_cap_info[0] = 1464 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 1465 else 1466 he_cap_elem->phy_cap_info[0] = 1467 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 1468 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 1469 1470 he_cap_elem->phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD; 1471 he_cap_elem->phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 1472 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ; 1473 1474 he_cap_elem->phy_cap_info[7] = 1475 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI; 1476 1477 switch (iftype) { 1478 case NL80211_IFTYPE_AP: 1479 he_cap_elem->mac_cap_info[0] |= IEEE80211_HE_MAC_CAP0_TWT_RES; 1480 he_cap_elem->mac_cap_info[2] |= IEEE80211_HE_MAC_CAP2_BSR; 1481 he_cap_elem->mac_cap_info[4] |= IEEE80211_HE_MAC_CAP4_BQR; 1482 he_cap_elem->mac_cap_info[5] |= 1483 IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX; 1484 he_cap_elem->phy_cap_info[3] |= 1485 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1486 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1487 he_cap_elem->phy_cap_info[6] |= 1488 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1489 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1490 he_cap_elem->phy_cap_info[9] |= 1491 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1492 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU; 1493 break; 1494 case NL80211_IFTYPE_STATION: 1495 he_cap_elem->mac_cap_info[1] |= 1496 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 1497 1498 if (band == NL80211_BAND_2GHZ) 1499 he_cap_elem->phy_cap_info[0] |= 1500 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G; 1501 else 1502 he_cap_elem->phy_cap_info[0] |= 1503 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G; 1504 1505 he_cap_elem->phy_cap_info[1] |= 1506 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 1507 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 1508 he_cap_elem->phy_cap_info[3] |= 1509 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1510 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1511 he_cap_elem->phy_cap_info[6] |= 1512 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB | 1513 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1514 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1515 he_cap_elem->phy_cap_info[7] |= 1516 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP; 1517 he_cap_elem->phy_cap_info[8] |= 1518 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 1519 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 1520 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU | 1521 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484; 1522 he_cap_elem->phy_cap_info[9] |= 1523 IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 1524 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK | 1525 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1526 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 1527 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 1528 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB; 1529 break; 1530 default: 1531 break; 1532 } 1533 1534 he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map); 1535 he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map); 1536 he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map); 1537 he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map); 1538 1539 mt7996_set_stream_he_txbf_caps(phy, he_cap, iftype, band); 1540 1541 memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres)); 1542 if (he_cap_elem->phy_cap_info[6] & 1543 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) { 1544 mt76_connac_gen_ppe_thresh(he_cap->ppe_thres, nss, band); 1545 } else { 1546 he_cap_elem->phy_cap_info[9] |= 1547 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 1548 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 1549 } 1550 1551 if (band == NL80211_BAND_6GHZ) { 1552 u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS | 1553 IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS; 1554 1555 cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_0_5, 1556 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 1557 u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 1558 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 1559 u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 1560 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 1561 1562 data->he_6ghz_capa.capa = cpu_to_le16(cap); 1563 } 1564 } 1565 1566 static void 1567 mt7996_init_eht_caps(struct mt7996_phy *phy, enum nl80211_band band, 1568 struct ieee80211_sband_iftype_data *data, 1569 enum nl80211_iftype iftype) 1570 { 1571 struct ieee80211_sta_eht_cap *eht_cap = &data->eht_cap; 1572 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem = &eht_cap->eht_cap_elem; 1573 struct ieee80211_eht_mcs_nss_supp *eht_nss = &eht_cap->eht_mcs_nss_supp; 1574 int nss = hweight8(phy->mt76->antenna_mask); 1575 int sts = hweight16(phy->mt76->chainmask); 1576 u8 val; 1577 1578 if (!phy->dev->has_eht) 1579 return; 1580 1581 eht_cap->has_eht = true; 1582 1583 eht_cap_elem->mac_cap_info[0] = 1584 IEEE80211_EHT_MAC_CAP0_OM_CONTROL | 1585 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_11454, 1586 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK); 1587 1588 eht_cap_elem->mac_cap_info[1] |= 1589 IEEE80211_EHT_MAC_CAP1_MAX_AMPDU_LEN_MASK; 1590 1591 eht_cap_elem->phy_cap_info[0] = 1592 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI | 1593 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMER | 1594 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE; 1595 1596 /* Set the maximum capability regardless of the antenna configuration. */ 1597 val = is_mt7992(phy->mt76->dev) ? 4 : 3; 1598 eht_cap_elem->phy_cap_info[0] |= 1599 u8_encode_bits(u8_get_bits(val, BIT(0)), 1600 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK); 1601 1602 eht_cap_elem->phy_cap_info[1] = 1603 u8_encode_bits(u8_get_bits(val, GENMASK(2, 1)), 1604 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK); 1605 1606 eht_cap_elem->phy_cap_info[2] = 1607 u8_encode_bits(sts - 1, IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_80MHZ_MASK); 1608 1609 if (band != NL80211_BAND_2GHZ) { 1610 eht_cap_elem->phy_cap_info[1] |= 1611 u8_encode_bits(val, 1612 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK); 1613 1614 eht_cap_elem->phy_cap_info[2] |= 1615 u8_encode_bits(sts - 1, 1616 IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_160MHZ_MASK); 1617 } 1618 1619 if (band == NL80211_BAND_6GHZ) { 1620 eht_cap_elem->phy_cap_info[0] |= 1621 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ; 1622 1623 eht_cap_elem->phy_cap_info[1] |= 1624 u8_encode_bits(val, 1625 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK); 1626 1627 eht_cap_elem->phy_cap_info[2] |= 1628 u8_encode_bits(sts - 1, 1629 IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_320MHZ_MASK); 1630 } 1631 1632 eht_cap_elem->phy_cap_info[3] = 1633 IEEE80211_EHT_PHY_CAP3_NG_16_SU_FEEDBACK | 1634 IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK | 1635 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK | 1636 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK; 1637 1638 eht_cap_elem->phy_cap_info[4] = 1639 IEEE80211_EHT_PHY_CAP4_EHT_MU_PPDU_4_EHT_LTF_08_GI | 1640 u8_encode_bits(min_t(int, sts - 1, 2), 1641 IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK); 1642 1643 eht_cap_elem->phy_cap_info[5] = 1644 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_16US, 1645 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK) | 1646 u8_encode_bits(u8_get_bits(1, GENMASK(1, 0)), 1647 IEEE80211_EHT_PHY_CAP5_MAX_NUM_SUPP_EHT_LTF_MASK); 1648 1649 eht_cap_elem->phy_cap_info[6] = IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK; 1650 if (band != NL80211_BAND_6GHZ) { 1651 eht_cap_elem->phy_cap_info[6] &= 1652 ~IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_320MHZ; 1653 1654 if (band != NL80211_BAND_5GHZ) 1655 eht_cap_elem->phy_cap_info[6] &= 1656 ~(IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_160MHZ | 1657 IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_80MHZ); 1658 } 1659 1660 val = u8_encode_bits(nss, IEEE80211_EHT_MCS_NSS_RX) | 1661 u8_encode_bits(nss, IEEE80211_EHT_MCS_NSS_TX); 1662 #define SET_EHT_MAX_NSS(_bw, _val) do { \ 1663 eht_nss->bw._##_bw.rx_tx_mcs9_max_nss = _val; \ 1664 eht_nss->bw._##_bw.rx_tx_mcs11_max_nss = _val; \ 1665 eht_nss->bw._##_bw.rx_tx_mcs13_max_nss = _val; \ 1666 } while (0) 1667 1668 SET_EHT_MAX_NSS(80, val); 1669 SET_EHT_MAX_NSS(160, val); 1670 if (band == NL80211_BAND_6GHZ) 1671 SET_EHT_MAX_NSS(320, val); 1672 #undef SET_EHT_MAX_NSS 1673 1674 if (iftype != NL80211_IFTYPE_AP) 1675 return; 1676 1677 eht_cap_elem->phy_cap_info[3] |= 1678 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK | 1679 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK; 1680 1681 eht_cap_elem->phy_cap_info[7] = 1682 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_80MHZ | 1683 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_80MHZ; 1684 1685 if (band == NL80211_BAND_2GHZ) 1686 return; 1687 1688 eht_cap_elem->phy_cap_info[7] |= 1689 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_160MHZ | 1690 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_160MHZ; 1691 1692 if (band != NL80211_BAND_6GHZ) 1693 return; 1694 1695 eht_cap_elem->phy_cap_info[7] |= 1696 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_320MHZ | 1697 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_320MHZ; 1698 } 1699 1700 static void 1701 __mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy, 1702 struct ieee80211_supported_band *sband, 1703 enum nl80211_band band) 1704 { 1705 struct ieee80211_sband_iftype_data *data = phy->iftype[band]; 1706 int i, n = 0; 1707 1708 for (i = 0; i < NUM_NL80211_IFTYPES; i++) { 1709 switch (i) { 1710 case NL80211_IFTYPE_STATION: 1711 case NL80211_IFTYPE_AP: 1712 #ifdef CONFIG_MAC80211_MESH 1713 case NL80211_IFTYPE_MESH_POINT: 1714 #endif 1715 break; 1716 default: 1717 continue; 1718 } 1719 1720 data[n].types_mask = BIT(i); 1721 mt7996_init_he_caps(phy, band, &data[n], i); 1722 mt7996_init_eht_caps(phy, band, &data[n], i); 1723 1724 n++; 1725 } 1726 1727 _ieee80211_set_sband_iftype_data(sband, data, n); 1728 } 1729 1730 void mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy) 1731 { 1732 if (phy->mt76->cap.has_2ghz) 1733 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_2g.sband, 1734 NL80211_BAND_2GHZ); 1735 1736 if (phy->mt76->cap.has_5ghz) 1737 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_5g.sband, 1738 NL80211_BAND_5GHZ); 1739 1740 if (phy->mt76->cap.has_6ghz) 1741 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_6g.sband, 1742 NL80211_BAND_6GHZ); 1743 } 1744 1745 int mt7996_register_device(struct mt7996_dev *dev) 1746 { 1747 struct ieee80211_hw *hw = mt76_hw(dev); 1748 struct mt7996_phy *phy; 1749 int ret; 1750 1751 dev->phy.dev = dev; 1752 dev->phy.mt76 = &dev->mt76.phy; 1753 dev->mt76.phy.priv = &dev->phy; 1754 INIT_WORK(&dev->rc_work, mt7996_mac_sta_rc_work); 1755 INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7996_mac_work); 1756 INIT_LIST_HEAD(&dev->sta_rc_list); 1757 INIT_LIST_HEAD(&dev->twt_list); 1758 1759 init_waitqueue_head(&dev->reset_wait); 1760 INIT_WORK(&dev->reset_work, mt7996_mac_reset_work); 1761 INIT_WORK(&dev->dump_work, mt7996_mac_dump_work); 1762 mutex_init(&dev->dump_mutex); 1763 1764 ret = mt7996_init_hardware(dev); 1765 if (ret) 1766 return ret; 1767 1768 mt7996_init_wiphy(hw, &dev->mt76.mmio.wed); 1769 1770 ret = mt7996_register_phy(dev, MT_BAND1); 1771 if (ret) 1772 return ret; 1773 1774 ret = mt7996_register_phy(dev, MT_BAND2); 1775 if (ret) 1776 return ret; 1777 1778 ret = mt7996_npu_hw_init(dev); 1779 if (ret) 1780 return ret; 1781 1782 mt7996_dma_rro_start(dev); 1783 1784 ret = mt76_register_device(&dev->mt76, true, mt76_rates, 1785 ARRAY_SIZE(mt76_rates)); 1786 if (ret) 1787 return ret; 1788 1789 mt7996_for_each_phy(dev, phy) 1790 mt7996_thermal_init(phy); 1791 1792 ieee80211_queue_work(mt76_hw(dev), &dev->init_work); 1793 1794 dev->recovery.hw_init_done = true; 1795 1796 ret = mt7996_init_debugfs(dev); 1797 if (ret) 1798 goto error; 1799 1800 ret = mt7996_coredump_register(dev); 1801 if (ret) 1802 goto error; 1803 1804 return 0; 1805 1806 error: 1807 cancel_work_sync(&dev->init_work); 1808 1809 return ret; 1810 } 1811 1812 void mt7996_unregister_device(struct mt7996_dev *dev) 1813 { 1814 int i; 1815 1816 cancel_work_sync(&dev->dump_work); 1817 cancel_work_sync(&dev->wed_rro.work); 1818 cancel_work_sync(&dev->reset_work); 1819 cancel_work_sync(&dev->rc_work); 1820 mt7996_unregister_phy(mt7996_phy3(dev)); 1821 mt7996_unregister_phy(mt7996_phy2(dev)); 1822 mt7996_unregister_thermal(&dev->phy); 1823 mt7996_coredump_unregister(dev); 1824 mt76_unregister_device(&dev->mt76); 1825 mt7996_wed_rro_free(dev); 1826 for (i = 0; i < ARRAY_SIZE(dev->mt76.napi); i++) { 1827 if (dev->mt76.napi[i].dev) 1828 napi_disable(&dev->mt76.napi[i]); 1829 } 1830 mt7996_mcu_exit(dev); 1831 mt7996_tx_token_put(dev); 1832 mt7996_dma_cleanup(dev); 1833 if (mt7996_has_hwrro(dev) && 1834 !mtk_wed_device_active(&dev->mt76.mmio.wed)) 1835 mt7996_rro_msdu_page_map_free(dev); 1836 tasklet_disable(&dev->mt76.irq_tasklet); 1837 1838 mt76_free_device(&dev->mt76); 1839 } 1840