1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #include <linux/of.h> 10 #include <linux/of_mdio.h> 11 #include <linux/of_net.h> 12 #include <linux/of_address.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/platform_device.h> 15 #include <linux/regmap.h> 16 #include <linux/clk.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/if_vlan.h> 19 #include <linux/reset.h> 20 #include <linux/tcp.h> 21 #include <linux/interrupt.h> 22 #include <linux/pinctrl/devinfo.h> 23 #include <linux/phylink.h> 24 #include <linux/pcs/pcs-mtk-lynxi.h> 25 #include <linux/jhash.h> 26 #include <linux/bitfield.h> 27 #include <net/dsa.h> 28 #include <net/dst_metadata.h> 29 #include <net/netdev_lock.h> 30 #include <net/page_pool/helpers.h> 31 #include <linux/genalloc.h> 32 33 #include "mtk_eth_soc.h" 34 #include "mtk_wed.h" 35 36 static int mtk_msg_level = -1; 37 module_param_named(msg_level, mtk_msg_level, int, 0); 38 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 39 40 #define MTK_ETHTOOL_STAT(x) { #x, \ 41 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 42 43 #define MTK_ETHTOOL_XDP_STAT(x) { #x, \ 44 offsetof(struct mtk_hw_stats, xdp_stats.x) / \ 45 sizeof(u64) } 46 47 static const struct mtk_reg_map mtk_reg_map = { 48 .tx_irq_mask = 0x1a1c, 49 .tx_irq_status = 0x1a18, 50 .pdma = { 51 .rx_ptr = 0x0900, 52 .rx_cnt_cfg = 0x0904, 53 .pcrx_ptr = 0x0908, 54 .glo_cfg = 0x0a04, 55 .rst_idx = 0x0a08, 56 .delay_irq = 0x0a0c, 57 .irq_status = 0x0a20, 58 .irq_mask = 0x0a28, 59 .adma_rx_dbg0 = 0x0a38, 60 .int_grp = 0x0a50, 61 }, 62 .qdma = { 63 .qtx_cfg = 0x1800, 64 .qtx_sch = 0x1804, 65 .rx_ptr = 0x1900, 66 .rx_cnt_cfg = 0x1904, 67 .qcrx_ptr = 0x1908, 68 .glo_cfg = 0x1a04, 69 .rst_idx = 0x1a08, 70 .delay_irq = 0x1a0c, 71 .fc_th = 0x1a10, 72 .tx_sch_rate = 0x1a14, 73 .int_grp = 0x1a20, 74 .hred = 0x1a44, 75 .ctx_ptr = 0x1b00, 76 .dtx_ptr = 0x1b04, 77 .crx_ptr = 0x1b10, 78 .drx_ptr = 0x1b14, 79 .fq_head = 0x1b20, 80 .fq_tail = 0x1b24, 81 .fq_count = 0x1b28, 82 .fq_blen = 0x1b2c, 83 }, 84 .gdm1_cnt = 0x2400, 85 .gdma_to_ppe = { 86 [0] = 0x4444, 87 }, 88 .ppe_base = 0x0c00, 89 .wdma_base = { 90 [0] = 0x2800, 91 [1] = 0x2c00, 92 }, 93 .pse_iq_sta = 0x0110, 94 .pse_oq_sta = 0x0118, 95 }; 96 97 static const struct mtk_reg_map mt7628_reg_map = { 98 .tx_irq_mask = 0x0a28, 99 .tx_irq_status = 0x0a20, 100 .pdma = { 101 .rx_ptr = 0x0900, 102 .rx_cnt_cfg = 0x0904, 103 .pcrx_ptr = 0x0908, 104 .glo_cfg = 0x0a04, 105 .rst_idx = 0x0a08, 106 .delay_irq = 0x0a0c, 107 .irq_status = 0x0a20, 108 .irq_mask = 0x0a28, 109 .int_grp = 0x0a50, 110 }, 111 }; 112 113 static const struct mtk_reg_map mt7986_reg_map = { 114 .tx_irq_mask = 0x461c, 115 .tx_irq_status = 0x4618, 116 .pdma = { 117 .rx_ptr = 0x4100, 118 .rx_cnt_cfg = 0x4104, 119 .pcrx_ptr = 0x4108, 120 .glo_cfg = 0x4204, 121 .rst_idx = 0x4208, 122 .delay_irq = 0x420c, 123 .irq_status = 0x4220, 124 .irq_mask = 0x4228, 125 .adma_rx_dbg0 = 0x4238, 126 .int_grp = 0x4250, 127 }, 128 .qdma = { 129 .qtx_cfg = 0x4400, 130 .qtx_sch = 0x4404, 131 .rx_ptr = 0x4500, 132 .rx_cnt_cfg = 0x4504, 133 .qcrx_ptr = 0x4508, 134 .glo_cfg = 0x4604, 135 .rst_idx = 0x4608, 136 .delay_irq = 0x460c, 137 .fc_th = 0x4610, 138 .int_grp = 0x4620, 139 .hred = 0x4644, 140 .ctx_ptr = 0x4700, 141 .dtx_ptr = 0x4704, 142 .crx_ptr = 0x4710, 143 .drx_ptr = 0x4714, 144 .fq_head = 0x4720, 145 .fq_tail = 0x4724, 146 .fq_count = 0x4728, 147 .fq_blen = 0x472c, 148 .tx_sch_rate = 0x4798, 149 }, 150 .gdm1_cnt = 0x1c00, 151 .gdma_to_ppe = { 152 [0] = 0x3333, 153 [1] = 0x4444, 154 }, 155 .ppe_base = 0x2000, 156 .wdma_base = { 157 [0] = 0x4800, 158 [1] = 0x4c00, 159 }, 160 .pse_iq_sta = 0x0180, 161 .pse_oq_sta = 0x01a0, 162 }; 163 164 static const struct mtk_reg_map mt7988_reg_map = { 165 .tx_irq_mask = 0x461c, 166 .tx_irq_status = 0x4618, 167 .pdma = { 168 .rx_ptr = 0x6900, 169 .rx_cnt_cfg = 0x6904, 170 .pcrx_ptr = 0x6908, 171 .glo_cfg = 0x6a04, 172 .rst_idx = 0x6a08, 173 .delay_irq = 0x6a0c, 174 .irq_status = 0x6a20, 175 .irq_mask = 0x6a28, 176 .adma_rx_dbg0 = 0x6a38, 177 .int_grp = 0x6a50, 178 }, 179 .qdma = { 180 .qtx_cfg = 0x4400, 181 .qtx_sch = 0x4404, 182 .rx_ptr = 0x4500, 183 .rx_cnt_cfg = 0x4504, 184 .qcrx_ptr = 0x4508, 185 .glo_cfg = 0x4604, 186 .rst_idx = 0x4608, 187 .delay_irq = 0x460c, 188 .fc_th = 0x4610, 189 .int_grp = 0x4620, 190 .hred = 0x4644, 191 .ctx_ptr = 0x4700, 192 .dtx_ptr = 0x4704, 193 .crx_ptr = 0x4710, 194 .drx_ptr = 0x4714, 195 .fq_head = 0x4720, 196 .fq_tail = 0x4724, 197 .fq_count = 0x4728, 198 .fq_blen = 0x472c, 199 .tx_sch_rate = 0x4798, 200 }, 201 .gdm1_cnt = 0x1c00, 202 .gdma_to_ppe = { 203 [0] = 0x3333, 204 [1] = 0x4444, 205 [2] = 0xcccc, 206 }, 207 .ppe_base = 0x2000, 208 .wdma_base = { 209 [0] = 0x4800, 210 [1] = 0x4c00, 211 [2] = 0x5000, 212 }, 213 .pse_iq_sta = 0x0180, 214 .pse_oq_sta = 0x01a0, 215 }; 216 217 /* strings used by ethtool */ 218 static const struct mtk_ethtool_stats { 219 char str[ETH_GSTRING_LEN]; 220 u32 offset; 221 } mtk_ethtool_stats[] = { 222 MTK_ETHTOOL_STAT(tx_bytes), 223 MTK_ETHTOOL_STAT(tx_packets), 224 MTK_ETHTOOL_STAT(tx_skip), 225 MTK_ETHTOOL_STAT(tx_collisions), 226 MTK_ETHTOOL_STAT(rx_bytes), 227 MTK_ETHTOOL_STAT(rx_packets), 228 MTK_ETHTOOL_STAT(rx_overflow), 229 MTK_ETHTOOL_STAT(rx_fcs_errors), 230 MTK_ETHTOOL_STAT(rx_short_errors), 231 MTK_ETHTOOL_STAT(rx_long_errors), 232 MTK_ETHTOOL_STAT(rx_checksum_errors), 233 MTK_ETHTOOL_STAT(rx_flow_control_packets), 234 MTK_ETHTOOL_XDP_STAT(rx_xdp_redirect), 235 MTK_ETHTOOL_XDP_STAT(rx_xdp_pass), 236 MTK_ETHTOOL_XDP_STAT(rx_xdp_drop), 237 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx), 238 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx_errors), 239 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit), 240 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit_errors), 241 }; 242 243 static const char * const mtk_clks_source_name[] = { 244 "ethif", 245 "sgmiitop", 246 "esw", 247 "gp0", 248 "gp1", 249 "gp2", 250 "gp3", 251 "xgp1", 252 "xgp2", 253 "xgp3", 254 "crypto", 255 "fe", 256 "trgpll", 257 "sgmii_tx250m", 258 "sgmii_rx250m", 259 "sgmii_cdr_ref", 260 "sgmii_cdr_fb", 261 "sgmii2_tx250m", 262 "sgmii2_rx250m", 263 "sgmii2_cdr_ref", 264 "sgmii2_cdr_fb", 265 "sgmii_ck", 266 "eth2pll", 267 "wocpu0", 268 "wocpu1", 269 "netsys0", 270 "netsys1", 271 "ethwarp_wocpu2", 272 "ethwarp_wocpu1", 273 "ethwarp_wocpu0", 274 "top_sgm0_sel", 275 "top_sgm1_sel", 276 "top_eth_gmii_sel", 277 "top_eth_refck_50m_sel", 278 "top_eth_sys_200m_sel", 279 "top_eth_sys_sel", 280 "top_eth_xgmii_sel", 281 "top_eth_mii_sel", 282 "top_netsys_sel", 283 "top_netsys_500m_sel", 284 "top_netsys_pao_2x_sel", 285 "top_netsys_sync_250m_sel", 286 "top_netsys_ppefb_250m_sel", 287 "top_netsys_warp_sel", 288 }; 289 290 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 291 { 292 __raw_writel(val, eth->base + reg); 293 } 294 295 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 296 { 297 return __raw_readl(eth->base + reg); 298 } 299 300 u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg) 301 { 302 u32 val; 303 304 val = mtk_r32(eth, reg); 305 val &= ~mask; 306 val |= set; 307 mtk_w32(eth, val, reg); 308 return reg; 309 } 310 311 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 312 { 313 unsigned long t_start = jiffies; 314 315 while (1) { 316 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 317 return 0; 318 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 319 break; 320 cond_resched(); 321 } 322 323 dev_err(eth->dev, "mdio: MDIO timeout\n"); 324 return -ETIMEDOUT; 325 } 326 327 static int _mtk_mdio_write_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg, 328 u32 write_data) 329 { 330 int ret; 331 332 ret = mtk_mdio_busy_wait(eth); 333 if (ret < 0) 334 return ret; 335 336 mtk_w32(eth, PHY_IAC_ACCESS | 337 PHY_IAC_START_C22 | 338 PHY_IAC_CMD_WRITE | 339 PHY_IAC_REG(phy_reg) | 340 PHY_IAC_ADDR(phy_addr) | 341 PHY_IAC_DATA(write_data), 342 MTK_PHY_IAC); 343 344 ret = mtk_mdio_busy_wait(eth); 345 if (ret < 0) 346 return ret; 347 348 return 0; 349 } 350 351 static int _mtk_mdio_write_c45(struct mtk_eth *eth, u32 phy_addr, 352 u32 devad, u32 phy_reg, u32 write_data) 353 { 354 int ret; 355 356 ret = mtk_mdio_busy_wait(eth); 357 if (ret < 0) 358 return ret; 359 360 mtk_w32(eth, PHY_IAC_ACCESS | 361 PHY_IAC_START_C45 | 362 PHY_IAC_CMD_C45_ADDR | 363 PHY_IAC_REG(devad) | 364 PHY_IAC_ADDR(phy_addr) | 365 PHY_IAC_DATA(phy_reg), 366 MTK_PHY_IAC); 367 368 ret = mtk_mdio_busy_wait(eth); 369 if (ret < 0) 370 return ret; 371 372 mtk_w32(eth, PHY_IAC_ACCESS | 373 PHY_IAC_START_C45 | 374 PHY_IAC_CMD_WRITE | 375 PHY_IAC_REG(devad) | 376 PHY_IAC_ADDR(phy_addr) | 377 PHY_IAC_DATA(write_data), 378 MTK_PHY_IAC); 379 380 ret = mtk_mdio_busy_wait(eth); 381 if (ret < 0) 382 return ret; 383 384 return 0; 385 } 386 387 static int _mtk_mdio_read_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg) 388 { 389 int ret; 390 391 ret = mtk_mdio_busy_wait(eth); 392 if (ret < 0) 393 return ret; 394 395 mtk_w32(eth, PHY_IAC_ACCESS | 396 PHY_IAC_START_C22 | 397 PHY_IAC_CMD_C22_READ | 398 PHY_IAC_REG(phy_reg) | 399 PHY_IAC_ADDR(phy_addr), 400 MTK_PHY_IAC); 401 402 ret = mtk_mdio_busy_wait(eth); 403 if (ret < 0) 404 return ret; 405 406 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; 407 } 408 409 static int _mtk_mdio_read_c45(struct mtk_eth *eth, u32 phy_addr, 410 u32 devad, u32 phy_reg) 411 { 412 int ret; 413 414 ret = mtk_mdio_busy_wait(eth); 415 if (ret < 0) 416 return ret; 417 418 mtk_w32(eth, PHY_IAC_ACCESS | 419 PHY_IAC_START_C45 | 420 PHY_IAC_CMD_C45_ADDR | 421 PHY_IAC_REG(devad) | 422 PHY_IAC_ADDR(phy_addr) | 423 PHY_IAC_DATA(phy_reg), 424 MTK_PHY_IAC); 425 426 ret = mtk_mdio_busy_wait(eth); 427 if (ret < 0) 428 return ret; 429 430 mtk_w32(eth, PHY_IAC_ACCESS | 431 PHY_IAC_START_C45 | 432 PHY_IAC_CMD_C45_READ | 433 PHY_IAC_REG(devad) | 434 PHY_IAC_ADDR(phy_addr), 435 MTK_PHY_IAC); 436 437 ret = mtk_mdio_busy_wait(eth); 438 if (ret < 0) 439 return ret; 440 441 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; 442 } 443 444 static int mtk_mdio_write_c22(struct mii_bus *bus, int phy_addr, 445 int phy_reg, u16 val) 446 { 447 struct mtk_eth *eth = bus->priv; 448 449 return _mtk_mdio_write_c22(eth, phy_addr, phy_reg, val); 450 } 451 452 static int mtk_mdio_write_c45(struct mii_bus *bus, int phy_addr, 453 int devad, int phy_reg, u16 val) 454 { 455 struct mtk_eth *eth = bus->priv; 456 457 return _mtk_mdio_write_c45(eth, phy_addr, devad, phy_reg, val); 458 } 459 460 static int mtk_mdio_read_c22(struct mii_bus *bus, int phy_addr, int phy_reg) 461 { 462 struct mtk_eth *eth = bus->priv; 463 464 return _mtk_mdio_read_c22(eth, phy_addr, phy_reg); 465 } 466 467 static int mtk_mdio_read_c45(struct mii_bus *bus, int phy_addr, int devad, 468 int phy_reg) 469 { 470 struct mtk_eth *eth = bus->priv; 471 472 return _mtk_mdio_read_c45(eth, phy_addr, devad, phy_reg); 473 } 474 475 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth, 476 phy_interface_t interface) 477 { 478 u32 val; 479 480 val = (interface == PHY_INTERFACE_MODE_TRGMII) ? 481 ETHSYS_TRGMII_MT7621_DDR_PLL : 0; 482 483 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 484 ETHSYS_TRGMII_MT7621_MASK, val); 485 486 return 0; 487 } 488 489 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, 490 phy_interface_t interface) 491 { 492 int ret; 493 494 if (interface == PHY_INTERFACE_MODE_TRGMII) { 495 mtk_w32(eth, TRGMII_MODE, INTF_MODE); 496 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], 500000000); 497 if (ret) 498 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 499 return; 500 } 501 502 dev_err(eth->dev, "Missing PLL configuration, ethernet may not work\n"); 503 } 504 505 static void mtk_setup_bridge_switch(struct mtk_eth *eth) 506 { 507 /* Force Port1 XGMAC Link Up */ 508 mtk_m32(eth, 0, MTK_XGMAC_FORCE_MODE(MTK_GMAC1_ID), 509 MTK_XGMAC_STS(MTK_GMAC1_ID)); 510 511 /* Adjust GSW bridge IPG to 11 */ 512 mtk_m32(eth, GSWTX_IPG_MASK | GSWRX_IPG_MASK, 513 (GSW_IPG_11 << GSWTX_IPG_SHIFT) | 514 (GSW_IPG_11 << GSWRX_IPG_SHIFT), 515 MTK_GSW_CFG); 516 } 517 518 static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config, 519 phy_interface_t interface) 520 { 521 struct mtk_mac *mac = container_of(config, struct mtk_mac, 522 phylink_config); 523 struct mtk_eth *eth = mac->hw; 524 unsigned int sid; 525 526 if (interface == PHY_INTERFACE_MODE_SGMII || 527 phy_interface_mode_is_8023z(interface)) { 528 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? 529 0 : mac->id; 530 531 return eth->sgmii_pcs[sid]; 532 } 533 534 return NULL; 535 } 536 537 static int mtk_mac_prepare(struct phylink_config *config, unsigned int mode, 538 phy_interface_t iface) 539 { 540 struct mtk_mac *mac = container_of(config, struct mtk_mac, 541 phylink_config); 542 struct mtk_eth *eth = mac->hw; 543 544 if (mtk_interface_mode_is_xgmii(eth, iface) && 545 mac->id != MTK_GMAC1_ID) { 546 mtk_m32(mac->hw, XMAC_MCR_TRX_DISABLE, 547 XMAC_MCR_TRX_DISABLE, MTK_XMAC_MCR(mac->id)); 548 549 mtk_m32(mac->hw, MTK_XGMAC_FORCE_MODE(mac->id) | 550 MTK_XGMAC_FORCE_LINK(mac->id), 551 MTK_XGMAC_FORCE_MODE(mac->id), MTK_XGMAC_STS(mac->id)); 552 } 553 554 return 0; 555 } 556 557 static void mtk_mac_config(struct phylink_config *config, unsigned int mode, 558 const struct phylink_link_state *state) 559 { 560 struct mtk_mac *mac = container_of(config, struct mtk_mac, 561 phylink_config); 562 struct mtk_eth *eth = mac->hw; 563 int val, ge_mode, err = 0; 564 u32 i; 565 566 if (mac->interface != state->interface) { 567 /* Setup soc pin functions */ 568 switch (state->interface) { 569 case PHY_INTERFACE_MODE_TRGMII: 570 case PHY_INTERFACE_MODE_RGMII_TXID: 571 case PHY_INTERFACE_MODE_RGMII_RXID: 572 case PHY_INTERFACE_MODE_RGMII_ID: 573 case PHY_INTERFACE_MODE_RGMII: 574 case PHY_INTERFACE_MODE_MII: 575 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) { 576 err = mtk_gmac_rgmii_path_setup(eth, mac->id); 577 if (err) 578 goto init_err; 579 } 580 break; 581 case PHY_INTERFACE_MODE_1000BASEX: 582 case PHY_INTERFACE_MODE_2500BASEX: 583 case PHY_INTERFACE_MODE_SGMII: 584 err = mtk_gmac_sgmii_path_setup(eth, mac->id); 585 if (err) 586 goto init_err; 587 break; 588 case PHY_INTERFACE_MODE_GMII: 589 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) { 590 err = mtk_gmac_gephy_path_setup(eth, mac->id); 591 if (err) 592 goto init_err; 593 } 594 break; 595 case PHY_INTERFACE_MODE_INTERNAL: 596 if (mac->id == MTK_GMAC2_ID && 597 MTK_HAS_CAPS(eth->soc->caps, MTK_2P5GPHY)) { 598 err = mtk_gmac_2p5gphy_path_setup(eth, mac->id); 599 if (err) 600 goto init_err; 601 } 602 break; 603 default: 604 goto err_phy; 605 } 606 607 /* Setup clock for 1st gmac */ 608 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII && 609 !phy_interface_mode_is_8023z(state->interface) && 610 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) { 611 if (MTK_HAS_CAPS(mac->hw->soc->caps, 612 MTK_TRGMII_MT7621_CLK)) { 613 if (mt7621_gmac0_rgmii_adjust(mac->hw, 614 state->interface)) 615 goto err_phy; 616 } else { 617 mtk_gmac0_rgmii_adjust(mac->hw, 618 state->interface); 619 620 /* mt7623_pad_clk_setup */ 621 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 622 mtk_w32(mac->hw, 623 TD_DM_DRVP(8) | TD_DM_DRVN(8), 624 TRGMII_TD_ODT(i)); 625 626 /* Assert/release MT7623 RXC reset */ 627 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL, 628 TRGMII_RCK_CTRL); 629 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL); 630 } 631 } 632 633 switch (state->interface) { 634 case PHY_INTERFACE_MODE_MII: 635 case PHY_INTERFACE_MODE_GMII: 636 ge_mode = 1; 637 break; 638 default: 639 ge_mode = 0; 640 break; 641 } 642 643 /* put the gmac into the right mode */ 644 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 645 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 646 val |= SYSCFG0_GE_MODE(ge_mode, mac->id); 647 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 648 649 mac->interface = state->interface; 650 } 651 652 /* SGMII */ 653 if (state->interface == PHY_INTERFACE_MODE_SGMII || 654 phy_interface_mode_is_8023z(state->interface)) { 655 /* The path GMAC to SGMII will be enabled once the SGMIISYS is 656 * being setup done. 657 */ 658 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 659 660 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 661 SYSCFG0_SGMII_MASK, 662 ~(u32)SYSCFG0_SGMII_MASK); 663 664 /* Save the syscfg0 value for mac_finish */ 665 mac->syscfg0 = val; 666 } else if (phylink_autoneg_inband(mode)) { 667 dev_err(eth->dev, 668 "In-band mode not supported in non SGMII mode!\n"); 669 return; 670 } 671 672 /* Setup gmac */ 673 if (mtk_interface_mode_is_xgmii(eth, state->interface)) { 674 mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id)); 675 mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id)); 676 677 if (mac->id == MTK_GMAC1_ID) 678 mtk_setup_bridge_switch(eth); 679 } 680 681 return; 682 683 err_phy: 684 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__, 685 mac->id, phy_modes(state->interface)); 686 return; 687 688 init_err: 689 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__, 690 mac->id, phy_modes(state->interface), err); 691 } 692 693 static int mtk_mac_finish(struct phylink_config *config, unsigned int mode, 694 phy_interface_t interface) 695 { 696 struct mtk_mac *mac = container_of(config, struct mtk_mac, 697 phylink_config); 698 struct mtk_eth *eth = mac->hw; 699 u32 mcr_cur, mcr_new; 700 701 /* Enable SGMII */ 702 if (interface == PHY_INTERFACE_MODE_SGMII || 703 phy_interface_mode_is_8023z(interface)) 704 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 705 SYSCFG0_SGMII_MASK, mac->syscfg0); 706 707 /* Setup gmac */ 708 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 709 mcr_new = mcr_cur; 710 mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE | 711 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_RX_FIFO_CLR_DIS; 712 713 /* Only update control register when needed! */ 714 if (mcr_new != mcr_cur) 715 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 716 717 return 0; 718 } 719 720 static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode, 721 phy_interface_t interface) 722 { 723 struct mtk_mac *mac = container_of(config, struct mtk_mac, 724 phylink_config); 725 726 if (!mtk_interface_mode_is_xgmii(mac->hw, interface)) { 727 /* GMAC modes */ 728 mtk_m32(mac->hw, 729 MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK, 0, 730 MTK_MAC_MCR(mac->id)); 731 } else if (mac->id != MTK_GMAC1_ID) { 732 /* XGMAC except for built-in switch */ 733 mtk_m32(mac->hw, XMAC_MCR_TRX_DISABLE, XMAC_MCR_TRX_DISABLE, 734 MTK_XMAC_MCR(mac->id)); 735 mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id), 0, 736 MTK_XGMAC_STS(mac->id)); 737 } 738 } 739 740 static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx, 741 int speed) 742 { 743 const struct mtk_soc_data *soc = eth->soc; 744 u32 ofs, val; 745 746 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 747 return; 748 749 val = MTK_QTX_SCH_MIN_RATE_EN | 750 /* minimum: 10 Mbps */ 751 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | 752 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | 753 MTK_QTX_SCH_LEAKY_BUCKET_SIZE; 754 if (mtk_is_netsys_v1(eth)) 755 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; 756 757 if (IS_ENABLED(CONFIG_SOC_MT7621)) { 758 switch (speed) { 759 case SPEED_10: 760 val |= MTK_QTX_SCH_MAX_RATE_EN | 761 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) | 762 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 2) | 763 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 764 break; 765 case SPEED_100: 766 val |= MTK_QTX_SCH_MAX_RATE_EN | 767 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) | 768 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 3) | 769 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 770 break; 771 case SPEED_1000: 772 val |= MTK_QTX_SCH_MAX_RATE_EN | 773 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 105) | 774 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) | 775 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10); 776 break; 777 default: 778 break; 779 } 780 } else { 781 switch (speed) { 782 case SPEED_10: 783 val |= MTK_QTX_SCH_MAX_RATE_EN | 784 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) | 785 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) | 786 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 787 break; 788 case SPEED_100: 789 val |= MTK_QTX_SCH_MAX_RATE_EN | 790 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) | 791 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5) | 792 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 793 break; 794 case SPEED_1000: 795 val |= MTK_QTX_SCH_MAX_RATE_EN | 796 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) | 797 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 6) | 798 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10); 799 break; 800 default: 801 break; 802 } 803 } 804 805 ofs = MTK_QTX_OFFSET * idx; 806 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); 807 } 808 809 static void mtk_gdm_mac_link_up(struct mtk_mac *mac, 810 struct phy_device *phy, 811 unsigned int mode, phy_interface_t interface, 812 int speed, int duplex, bool tx_pause, 813 bool rx_pause) 814 { 815 u32 mcr; 816 817 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 818 mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 | 819 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC | 820 MAC_MCR_FORCE_RX_FC); 821 822 /* Configure speed */ 823 mac->speed = speed; 824 switch (speed) { 825 case SPEED_2500: 826 case SPEED_1000: 827 mcr |= MAC_MCR_SPEED_1000; 828 break; 829 case SPEED_100: 830 mcr |= MAC_MCR_SPEED_100; 831 break; 832 } 833 834 /* Configure duplex */ 835 if (duplex == DUPLEX_FULL) 836 mcr |= MAC_MCR_FORCE_DPX; 837 838 /* Configure pause modes - phylink will avoid these for half duplex */ 839 if (tx_pause) 840 mcr |= MAC_MCR_FORCE_TX_FC; 841 if (rx_pause) 842 mcr |= MAC_MCR_FORCE_RX_FC; 843 844 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK; 845 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 846 } 847 848 static void mtk_xgdm_mac_link_up(struct mtk_mac *mac, 849 struct phy_device *phy, 850 unsigned int mode, phy_interface_t interface, 851 int speed, int duplex, bool tx_pause, 852 bool rx_pause) 853 { 854 u32 mcr; 855 856 if (mac->id == MTK_GMAC1_ID) 857 return; 858 859 /* Eliminate the interference(before link-up) caused by PHY noise */ 860 mtk_m32(mac->hw, XMAC_LOGIC_RST, 0, MTK_XMAC_LOGIC_RST(mac->id)); 861 mdelay(20); 862 mtk_m32(mac->hw, XMAC_GLB_CNTCLR, XMAC_GLB_CNTCLR, 863 MTK_XMAC_CNT_CTRL(mac->id)); 864 865 mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id), 866 MTK_XGMAC_FORCE_LINK(mac->id), MTK_XGMAC_STS(mac->id)); 867 868 mcr = mtk_r32(mac->hw, MTK_XMAC_MCR(mac->id)); 869 mcr &= ~(XMAC_MCR_FORCE_TX_FC | XMAC_MCR_FORCE_RX_FC | 870 XMAC_MCR_TRX_DISABLE); 871 /* Configure pause modes - 872 * phylink will avoid these for half duplex 873 */ 874 if (tx_pause) 875 mcr |= XMAC_MCR_FORCE_TX_FC; 876 if (rx_pause) 877 mcr |= XMAC_MCR_FORCE_RX_FC; 878 879 mtk_w32(mac->hw, mcr, MTK_XMAC_MCR(mac->id)); 880 } 881 882 static void mtk_mac_link_up(struct phylink_config *config, 883 struct phy_device *phy, 884 unsigned int mode, phy_interface_t interface, 885 int speed, int duplex, bool tx_pause, bool rx_pause) 886 { 887 struct mtk_mac *mac = container_of(config, struct mtk_mac, 888 phylink_config); 889 890 if (mtk_interface_mode_is_xgmii(mac->hw, interface)) 891 mtk_xgdm_mac_link_up(mac, phy, mode, interface, speed, duplex, 892 tx_pause, rx_pause); 893 else 894 mtk_gdm_mac_link_up(mac, phy, mode, interface, speed, duplex, 895 tx_pause, rx_pause); 896 } 897 898 static void mtk_mac_disable_tx_lpi(struct phylink_config *config) 899 { 900 struct mtk_mac *mac = container_of(config, struct mtk_mac, 901 phylink_config); 902 struct mtk_eth *eth = mac->hw; 903 904 mtk_m32(eth, MAC_MCR_EEE100M | MAC_MCR_EEE1G, 0, MTK_MAC_MCR(mac->id)); 905 } 906 907 static int mtk_mac_enable_tx_lpi(struct phylink_config *config, u32 timer, 908 bool tx_clk_stop) 909 { 910 struct mtk_mac *mac = container_of(config, struct mtk_mac, 911 phylink_config); 912 struct mtk_eth *eth = mac->hw; 913 u32 val; 914 915 if (mtk_interface_mode_is_xgmii(eth, mac->interface)) 916 return -EOPNOTSUPP; 917 918 /* Tx idle timer in ms */ 919 timer = DIV_ROUND_UP(timer, 1000); 920 921 /* If the timer is zero, then set LPI_MODE, which allows the 922 * system to enter LPI mode immediately rather than waiting for 923 * the LPI threshold. 924 */ 925 if (!timer) 926 val = MAC_EEE_LPI_MODE; 927 else if (FIELD_FIT(MAC_EEE_LPI_TXIDLE_THD, timer)) 928 val = FIELD_PREP(MAC_EEE_LPI_TXIDLE_THD, timer); 929 else 930 val = MAC_EEE_LPI_TXIDLE_THD; 931 932 if (tx_clk_stop) 933 val |= MAC_EEE_CKG_TXIDLE; 934 935 /* PHY Wake-up time, this field does not have a reset value, so use the 936 * reset value from MT7531 (36us for 100M and 17us for 1000M). 937 */ 938 val |= FIELD_PREP(MAC_EEE_WAKEUP_TIME_1000, 17) | 939 FIELD_PREP(MAC_EEE_WAKEUP_TIME_100, 36); 940 941 mtk_w32(eth, val, MTK_MAC_EEECR(mac->id)); 942 mtk_m32(eth, 0, MAC_MCR_EEE100M | MAC_MCR_EEE1G, MTK_MAC_MCR(mac->id)); 943 944 return 0; 945 } 946 947 static const struct phylink_mac_ops mtk_phylink_ops = { 948 .mac_prepare = mtk_mac_prepare, 949 .mac_select_pcs = mtk_mac_select_pcs, 950 .mac_config = mtk_mac_config, 951 .mac_finish = mtk_mac_finish, 952 .mac_link_down = mtk_mac_link_down, 953 .mac_link_up = mtk_mac_link_up, 954 .mac_disable_tx_lpi = mtk_mac_disable_tx_lpi, 955 .mac_enable_tx_lpi = mtk_mac_enable_tx_lpi, 956 }; 957 958 static void rt5350_mac_config(struct phylink_config *config, unsigned int mode, 959 const struct phylink_link_state *state) 960 { 961 } 962 963 static void rt5350_mac_link_down(struct phylink_config *config, unsigned int mode, 964 phy_interface_t interface) 965 { 966 } 967 968 static void rt5350_mac_link_up(struct phylink_config *config, 969 struct phy_device *phy, 970 unsigned int mode, phy_interface_t interface, 971 int speed, int duplex, bool tx_pause, bool rx_pause) 972 { 973 } 974 975 /* MT76x8 (rt5350-eth) does not expose any MAC control registers */ 976 static const struct phylink_mac_ops rt5350_phylink_ops = { 977 .mac_config = rt5350_mac_config, 978 .mac_link_down = rt5350_mac_link_down, 979 .mac_link_up = rt5350_mac_link_up, 980 }; 981 982 static void mtk_mdio_config(struct mtk_eth *eth) 983 { 984 u32 val; 985 986 /* Configure MDC Divider */ 987 val = FIELD_PREP(PPSC_MDC_CFG, eth->mdc_divider); 988 989 /* Configure MDC Turbo Mode */ 990 if (mtk_is_netsys_v3_or_greater(eth)) 991 mtk_m32(eth, 0, MISC_MDC_TURBO, MTK_MAC_MISC_V3); 992 else 993 val |= PPSC_MDC_TURBO; 994 995 mtk_m32(eth, PPSC_MDC_CFG, val, MTK_PPSC); 996 } 997 998 static int mtk_mdio_init(struct mtk_eth *eth) 999 { 1000 unsigned int max_clk = 2500000; 1001 struct device_node *mii_np; 1002 int ret; 1003 u32 val; 1004 1005 mii_np = of_get_available_child_by_name(eth->dev->of_node, "mdio-bus"); 1006 if (!mii_np) { 1007 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 1008 return -ENODEV; 1009 } 1010 1011 eth->mii_bus = devm_mdiobus_alloc(eth->dev); 1012 if (!eth->mii_bus) { 1013 ret = -ENOMEM; 1014 goto err_put_node; 1015 } 1016 1017 eth->mii_bus->name = "mdio"; 1018 eth->mii_bus->read = mtk_mdio_read_c22; 1019 eth->mii_bus->write = mtk_mdio_write_c22; 1020 eth->mii_bus->read_c45 = mtk_mdio_read_c45; 1021 eth->mii_bus->write_c45 = mtk_mdio_write_c45; 1022 eth->mii_bus->priv = eth; 1023 eth->mii_bus->parent = eth->dev; 1024 1025 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); 1026 1027 if (!of_property_read_u32(mii_np, "clock-frequency", &val)) { 1028 if (val > MDC_MAX_FREQ || val < MDC_MAX_FREQ / MDC_MAX_DIVIDER) { 1029 dev_err(eth->dev, "MDIO clock frequency out of range"); 1030 ret = -EINVAL; 1031 goto err_put_node; 1032 } 1033 max_clk = val; 1034 } 1035 eth->mdc_divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63); 1036 mtk_mdio_config(eth); 1037 dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / eth->mdc_divider); 1038 ret = of_mdiobus_register(eth->mii_bus, mii_np); 1039 1040 err_put_node: 1041 of_node_put(mii_np); 1042 return ret; 1043 } 1044 1045 static void mtk_mdio_cleanup(struct mtk_eth *eth) 1046 { 1047 if (!eth->mii_bus) 1048 return; 1049 1050 mdiobus_unregister(eth->mii_bus); 1051 } 1052 1053 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) 1054 { 1055 unsigned long flags; 1056 u32 val; 1057 1058 spin_lock_irqsave(ð->tx_irq_lock, flags); 1059 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); 1060 mtk_w32(eth, val & ~mask, eth->soc->reg_map->tx_irq_mask); 1061 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 1062 } 1063 1064 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) 1065 { 1066 unsigned long flags; 1067 u32 val; 1068 1069 spin_lock_irqsave(ð->tx_irq_lock, flags); 1070 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); 1071 mtk_w32(eth, val | mask, eth->soc->reg_map->tx_irq_mask); 1072 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 1073 } 1074 1075 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) 1076 { 1077 unsigned long flags; 1078 u32 val; 1079 1080 spin_lock_irqsave(ð->rx_irq_lock, flags); 1081 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); 1082 mtk_w32(eth, val & ~mask, eth->soc->reg_map->pdma.irq_mask); 1083 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 1084 } 1085 1086 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) 1087 { 1088 unsigned long flags; 1089 u32 val; 1090 1091 spin_lock_irqsave(ð->rx_irq_lock, flags); 1092 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); 1093 mtk_w32(eth, val | mask, eth->soc->reg_map->pdma.irq_mask); 1094 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 1095 } 1096 1097 static int mtk_set_mac_address(struct net_device *dev, void *p) 1098 { 1099 int ret = eth_mac_addr(dev, p); 1100 struct mtk_mac *mac = netdev_priv(dev); 1101 struct mtk_eth *eth = mac->hw; 1102 const char *macaddr = dev->dev_addr; 1103 1104 if (ret) 1105 return ret; 1106 1107 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 1108 return -EBUSY; 1109 1110 spin_lock_bh(&mac->hw->page_lock); 1111 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 1112 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 1113 MT7628_SDM_MAC_ADRH); 1114 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 1115 (macaddr[4] << 8) | macaddr[5], 1116 MT7628_SDM_MAC_ADRL); 1117 } else { 1118 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 1119 MTK_GDMA_MAC_ADRH(mac->id)); 1120 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 1121 (macaddr[4] << 8) | macaddr[5], 1122 MTK_GDMA_MAC_ADRL(mac->id)); 1123 } 1124 spin_unlock_bh(&mac->hw->page_lock); 1125 1126 return 0; 1127 } 1128 1129 void mtk_stats_update_mac(struct mtk_mac *mac) 1130 { 1131 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1132 struct mtk_eth *eth = mac->hw; 1133 1134 u64_stats_update_begin(&hw_stats->syncp); 1135 1136 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 1137 hw_stats->tx_packets += mtk_r32(mac->hw, MT7628_SDM_TPCNT); 1138 hw_stats->tx_bytes += mtk_r32(mac->hw, MT7628_SDM_TBCNT); 1139 hw_stats->rx_packets += mtk_r32(mac->hw, MT7628_SDM_RPCNT); 1140 hw_stats->rx_bytes += mtk_r32(mac->hw, MT7628_SDM_RBCNT); 1141 hw_stats->rx_checksum_errors += 1142 mtk_r32(mac->hw, MT7628_SDM_CS_ERR); 1143 } else { 1144 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 1145 unsigned int offs = hw_stats->reg_offset; 1146 u64 stats; 1147 1148 hw_stats->rx_bytes += mtk_r32(mac->hw, reg_map->gdm1_cnt + offs); 1149 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x4 + offs); 1150 if (stats) 1151 hw_stats->rx_bytes += (stats << 32); 1152 hw_stats->rx_packets += 1153 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x8 + offs); 1154 hw_stats->rx_overflow += 1155 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x10 + offs); 1156 hw_stats->rx_fcs_errors += 1157 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x14 + offs); 1158 hw_stats->rx_short_errors += 1159 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x18 + offs); 1160 hw_stats->rx_long_errors += 1161 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x1c + offs); 1162 hw_stats->rx_checksum_errors += 1163 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs); 1164 hw_stats->rx_flow_control_packets += 1165 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs); 1166 1167 if (mtk_is_netsys_v3_or_greater(eth)) { 1168 hw_stats->tx_skip += 1169 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x50 + offs); 1170 hw_stats->tx_collisions += 1171 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x54 + offs); 1172 hw_stats->tx_bytes += 1173 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x40 + offs); 1174 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x44 + offs); 1175 if (stats) 1176 hw_stats->tx_bytes += (stats << 32); 1177 hw_stats->tx_packets += 1178 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x48 + offs); 1179 } else { 1180 hw_stats->tx_skip += 1181 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs); 1182 hw_stats->tx_collisions += 1183 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs); 1184 hw_stats->tx_bytes += 1185 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs); 1186 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs); 1187 if (stats) 1188 hw_stats->tx_bytes += (stats << 32); 1189 hw_stats->tx_packets += 1190 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs); 1191 } 1192 } 1193 1194 u64_stats_update_end(&hw_stats->syncp); 1195 } 1196 1197 static void mtk_stats_update(struct mtk_eth *eth) 1198 { 1199 int i; 1200 1201 for (i = 0; i < MTK_MAX_DEVS; i++) { 1202 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 1203 continue; 1204 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 1205 mtk_stats_update_mac(eth->mac[i]); 1206 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 1207 } 1208 } 1209 } 1210 1211 static void mtk_get_stats64(struct net_device *dev, 1212 struct rtnl_link_stats64 *storage) 1213 { 1214 struct mtk_mac *mac = netdev_priv(dev); 1215 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1216 unsigned int start; 1217 1218 if (netif_running(dev) && netif_device_present(dev)) { 1219 if (spin_trylock_bh(&hw_stats->stats_lock)) { 1220 mtk_stats_update_mac(mac); 1221 spin_unlock_bh(&hw_stats->stats_lock); 1222 } 1223 } 1224 1225 do { 1226 start = u64_stats_fetch_begin(&hw_stats->syncp); 1227 storage->rx_packets = hw_stats->rx_packets; 1228 storage->tx_packets = hw_stats->tx_packets; 1229 storage->rx_bytes = hw_stats->rx_bytes; 1230 storage->tx_bytes = hw_stats->tx_bytes; 1231 storage->collisions = hw_stats->tx_collisions; 1232 storage->rx_length_errors = hw_stats->rx_short_errors + 1233 hw_stats->rx_long_errors; 1234 storage->rx_over_errors = hw_stats->rx_overflow; 1235 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 1236 storage->rx_errors = hw_stats->rx_checksum_errors; 1237 storage->tx_aborted_errors = hw_stats->tx_skip; 1238 } while (u64_stats_fetch_retry(&hw_stats->syncp, start)); 1239 1240 storage->tx_errors = dev->stats.tx_errors; 1241 storage->rx_dropped = dev->stats.rx_dropped; 1242 storage->tx_dropped = dev->stats.tx_dropped; 1243 } 1244 1245 static inline int mtk_max_frag_size(int mtu) 1246 { 1247 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 1248 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH_2K) 1249 mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 1250 1251 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 1252 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 1253 } 1254 1255 static inline int mtk_max_buf_size(int frag_size) 1256 { 1257 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 1258 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 1259 1260 WARN_ON(buf_size < MTK_MAX_RX_LENGTH_2K); 1261 1262 return buf_size; 1263 } 1264 1265 static bool mtk_rx_get_desc(struct mtk_eth *eth, struct mtk_rx_dma_v2 *rxd, 1266 struct mtk_rx_dma_v2 *dma_rxd) 1267 { 1268 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 1269 if (!(rxd->rxd2 & RX_DMA_DONE)) 1270 return false; 1271 1272 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 1273 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 1274 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 1275 if (mtk_is_netsys_v3_or_greater(eth)) { 1276 rxd->rxd5 = READ_ONCE(dma_rxd->rxd5); 1277 rxd->rxd6 = READ_ONCE(dma_rxd->rxd6); 1278 } 1279 1280 return true; 1281 } 1282 1283 static void *mtk_max_lro_buf_alloc(gfp_t gfp_mask) 1284 { 1285 unsigned int size = mtk_max_frag_size(MTK_MAX_LRO_RX_LENGTH); 1286 unsigned long data; 1287 1288 data = __get_free_pages(gfp_mask | __GFP_COMP | __GFP_NOWARN, 1289 get_order(size)); 1290 1291 return (void *)data; 1292 } 1293 1294 static void *mtk_dma_ring_alloc(struct mtk_eth *eth, size_t size, 1295 dma_addr_t *dma_handle, bool use_sram) 1296 { 1297 void *dma_ring; 1298 1299 if (use_sram && eth->sram_pool) { 1300 dma_ring = (void *)gen_pool_alloc(eth->sram_pool, size); 1301 if (!dma_ring) 1302 return dma_ring; 1303 *dma_handle = gen_pool_virt_to_phys(eth->sram_pool, 1304 (unsigned long)dma_ring); 1305 } else { 1306 dma_ring = dma_alloc_coherent(eth->dma_dev, size, dma_handle, 1307 GFP_KERNEL); 1308 } 1309 1310 return dma_ring; 1311 } 1312 1313 static void mtk_dma_ring_free(struct mtk_eth *eth, size_t size, void *dma_ring, 1314 dma_addr_t dma_handle, bool in_sram) 1315 { 1316 if (in_sram && eth->sram_pool) 1317 gen_pool_free(eth->sram_pool, (unsigned long)dma_ring, size); 1318 else 1319 dma_free_coherent(eth->dma_dev, size, dma_ring, dma_handle); 1320 } 1321 1322 /* the qdma core needs scratch memory to be setup */ 1323 static int mtk_init_fq_dma(struct mtk_eth *eth) 1324 { 1325 const struct mtk_soc_data *soc = eth->soc; 1326 dma_addr_t phy_ring_tail; 1327 int cnt = soc->tx.fq_dma_size; 1328 dma_addr_t dma_addr; 1329 int i, j, len; 1330 1331 eth->scratch_ring = mtk_dma_ring_alloc(eth, cnt * soc->tx.desc_size, 1332 ð->phy_scratch_ring, true); 1333 1334 if (unlikely(!eth->scratch_ring)) 1335 return -ENOMEM; 1336 1337 phy_ring_tail = eth->phy_scratch_ring + soc->tx.desc_size * (cnt - 1); 1338 1339 for (j = 0; j < DIV_ROUND_UP(soc->tx.fq_dma_size, MTK_FQ_DMA_LENGTH); j++) { 1340 len = min_t(int, cnt - j * MTK_FQ_DMA_LENGTH, MTK_FQ_DMA_LENGTH); 1341 eth->scratch_head[j] = kcalloc(len, MTK_QDMA_PAGE_SIZE, GFP_KERNEL); 1342 1343 if (unlikely(!eth->scratch_head[j])) 1344 return -ENOMEM; 1345 1346 dma_addr = dma_map_single(eth->dma_dev, 1347 eth->scratch_head[j], len * MTK_QDMA_PAGE_SIZE, 1348 DMA_FROM_DEVICE); 1349 1350 if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) 1351 return -ENOMEM; 1352 1353 for (i = 0; i < len; i++) { 1354 struct mtk_tx_dma_v2 *txd; 1355 1356 txd = eth->scratch_ring + (j * MTK_FQ_DMA_LENGTH + i) * soc->tx.desc_size; 1357 txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE; 1358 if (j * MTK_FQ_DMA_LENGTH + i < cnt) 1359 txd->txd2 = eth->phy_scratch_ring + 1360 (j * MTK_FQ_DMA_LENGTH + i + 1) * soc->tx.desc_size; 1361 1362 txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); 1363 if (MTK_HAS_CAPS(soc->caps, MTK_36BIT_DMA)) 1364 txd->txd3 |= TX_DMA_PREP_ADDR64(dma_addr + i * MTK_QDMA_PAGE_SIZE); 1365 1366 txd->txd4 = 0; 1367 if (mtk_is_netsys_v2_or_greater(eth)) { 1368 txd->txd5 = 0; 1369 txd->txd6 = 0; 1370 txd->txd7 = 0; 1371 txd->txd8 = 0; 1372 } 1373 } 1374 } 1375 1376 mtk_w32(eth, eth->phy_scratch_ring, soc->reg_map->qdma.fq_head); 1377 mtk_w32(eth, phy_ring_tail, soc->reg_map->qdma.fq_tail); 1378 mtk_w32(eth, (cnt << 16) | cnt, soc->reg_map->qdma.fq_count); 1379 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, soc->reg_map->qdma.fq_blen); 1380 1381 return 0; 1382 } 1383 1384 static void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 1385 { 1386 return ring->dma + (desc - ring->phys); 1387 } 1388 1389 static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 1390 void *txd, u32 txd_size) 1391 { 1392 int idx = (txd - ring->dma) / txd_size; 1393 1394 return &ring->buf[idx]; 1395 } 1396 1397 static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring, 1398 struct mtk_tx_dma *dma) 1399 { 1400 return ring->dma_pdma - (struct mtk_tx_dma *)ring->dma + dma; 1401 } 1402 1403 static int txd_to_idx(struct mtk_tx_ring *ring, void *dma, u32 txd_size) 1404 { 1405 return (dma - ring->dma) / txd_size; 1406 } 1407 1408 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 1409 struct xdp_frame_bulk *bq, bool napi) 1410 { 1411 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1412 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 1413 dma_unmap_single(eth->dma_dev, 1414 dma_unmap_addr(tx_buf, dma_addr0), 1415 dma_unmap_len(tx_buf, dma_len0), 1416 DMA_TO_DEVICE); 1417 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 1418 dma_unmap_page(eth->dma_dev, 1419 dma_unmap_addr(tx_buf, dma_addr0), 1420 dma_unmap_len(tx_buf, dma_len0), 1421 DMA_TO_DEVICE); 1422 } 1423 } else { 1424 if (dma_unmap_len(tx_buf, dma_len0)) { 1425 dma_unmap_page(eth->dma_dev, 1426 dma_unmap_addr(tx_buf, dma_addr0), 1427 dma_unmap_len(tx_buf, dma_len0), 1428 DMA_TO_DEVICE); 1429 } 1430 1431 if (dma_unmap_len(tx_buf, dma_len1)) { 1432 dma_unmap_page(eth->dma_dev, 1433 dma_unmap_addr(tx_buf, dma_addr1), 1434 dma_unmap_len(tx_buf, dma_len1), 1435 DMA_TO_DEVICE); 1436 } 1437 } 1438 1439 if (tx_buf->data && tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 1440 if (tx_buf->type == MTK_TYPE_SKB) { 1441 struct sk_buff *skb = tx_buf->data; 1442 1443 if (napi) 1444 napi_consume_skb(skb, napi); 1445 else 1446 dev_kfree_skb_any(skb); 1447 } else { 1448 struct xdp_frame *xdpf = tx_buf->data; 1449 1450 if (napi && tx_buf->type == MTK_TYPE_XDP_TX) 1451 xdp_return_frame_rx_napi(xdpf); 1452 else if (bq) 1453 xdp_return_frame_bulk(xdpf, bq); 1454 else 1455 xdp_return_frame(xdpf); 1456 } 1457 } 1458 tx_buf->flags = 0; 1459 tx_buf->data = NULL; 1460 } 1461 1462 static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 1463 struct mtk_tx_dma *txd, dma_addr_t mapped_addr, 1464 size_t size, int idx) 1465 { 1466 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1467 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 1468 dma_unmap_len_set(tx_buf, dma_len0, size); 1469 } else { 1470 if (idx & 1) { 1471 txd->txd3 = mapped_addr; 1472 txd->txd2 |= TX_DMA_PLEN1(size); 1473 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr); 1474 dma_unmap_len_set(tx_buf, dma_len1, size); 1475 } else { 1476 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1477 txd->txd1 = mapped_addr; 1478 txd->txd2 = TX_DMA_PLEN0(size); 1479 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 1480 dma_unmap_len_set(tx_buf, dma_len0, size); 1481 } 1482 } 1483 } 1484 1485 static void mtk_tx_set_dma_desc_v1(struct net_device *dev, void *txd, 1486 struct mtk_tx_dma_desc_info *info) 1487 { 1488 struct mtk_mac *mac = netdev_priv(dev); 1489 struct mtk_eth *eth = mac->hw; 1490 struct mtk_tx_dma *desc = txd; 1491 u32 data; 1492 1493 WRITE_ONCE(desc->txd1, info->addr); 1494 1495 data = TX_DMA_SWC | TX_DMA_PLEN0(info->size) | 1496 FIELD_PREP(TX_DMA_PQID, info->qid); 1497 if (info->last) 1498 data |= TX_DMA_LS0; 1499 WRITE_ONCE(desc->txd3, data); 1500 1501 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT; /* forward port */ 1502 if (info->first) { 1503 if (info->gso) 1504 data |= TX_DMA_TSO; 1505 /* tx checksum offload */ 1506 if (info->csum) 1507 data |= TX_DMA_CHKSUM; 1508 /* vlan header offload */ 1509 if (info->vlan) 1510 data |= TX_DMA_INS_VLAN | info->vlan_tci; 1511 } 1512 WRITE_ONCE(desc->txd4, data); 1513 } 1514 1515 static void mtk_tx_set_dma_desc_v2(struct net_device *dev, void *txd, 1516 struct mtk_tx_dma_desc_info *info) 1517 { 1518 struct mtk_mac *mac = netdev_priv(dev); 1519 struct mtk_tx_dma_v2 *desc = txd; 1520 struct mtk_eth *eth = mac->hw; 1521 u32 data; 1522 1523 WRITE_ONCE(desc->txd1, info->addr); 1524 1525 data = TX_DMA_PLEN0(info->size); 1526 if (info->last) 1527 data |= TX_DMA_LS0; 1528 1529 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) 1530 data |= TX_DMA_PREP_ADDR64(info->addr); 1531 1532 WRITE_ONCE(desc->txd3, data); 1533 1534 /* set forward port */ 1535 switch (mac->id) { 1536 case MTK_GMAC1_ID: 1537 data = PSE_GDM1_PORT << TX_DMA_FPORT_SHIFT_V2; 1538 break; 1539 case MTK_GMAC2_ID: 1540 data = PSE_GDM2_PORT << TX_DMA_FPORT_SHIFT_V2; 1541 break; 1542 case MTK_GMAC3_ID: 1543 data = PSE_GDM3_PORT << TX_DMA_FPORT_SHIFT_V2; 1544 break; 1545 } 1546 1547 data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); 1548 WRITE_ONCE(desc->txd4, data); 1549 1550 data = 0; 1551 if (info->first) { 1552 if (info->gso) 1553 data |= TX_DMA_TSO_V2; 1554 /* tx checksum offload */ 1555 if (info->csum) 1556 data |= TX_DMA_CHKSUM_V2; 1557 if (mtk_is_netsys_v3_or_greater(eth) && netdev_uses_dsa(dev)) 1558 data |= TX_DMA_SPTAG_V3; 1559 } 1560 WRITE_ONCE(desc->txd5, data); 1561 1562 data = 0; 1563 if (info->first && info->vlan) 1564 data |= TX_DMA_INS_VLAN_V2 | info->vlan_tci; 1565 WRITE_ONCE(desc->txd6, data); 1566 1567 WRITE_ONCE(desc->txd7, 0); 1568 WRITE_ONCE(desc->txd8, 0); 1569 } 1570 1571 static void mtk_tx_set_dma_desc(struct net_device *dev, void *txd, 1572 struct mtk_tx_dma_desc_info *info) 1573 { 1574 struct mtk_mac *mac = netdev_priv(dev); 1575 struct mtk_eth *eth = mac->hw; 1576 1577 if (mtk_is_netsys_v2_or_greater(eth)) 1578 mtk_tx_set_dma_desc_v2(dev, txd, info); 1579 else 1580 mtk_tx_set_dma_desc_v1(dev, txd, info); 1581 } 1582 1583 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 1584 int tx_num, struct mtk_tx_ring *ring, bool gso) 1585 { 1586 struct mtk_tx_dma_desc_info txd_info = { 1587 .size = skb_headlen(skb), 1588 .gso = gso, 1589 .csum = skb->ip_summed == CHECKSUM_PARTIAL, 1590 .vlan = skb_vlan_tag_present(skb), 1591 .qid = skb_get_queue_mapping(skb), 1592 .vlan_tci = skb_vlan_tag_get(skb), 1593 .first = true, 1594 .last = !skb_is_nonlinear(skb), 1595 }; 1596 struct netdev_queue *txq; 1597 struct mtk_mac *mac = netdev_priv(dev); 1598 struct mtk_eth *eth = mac->hw; 1599 const struct mtk_soc_data *soc = eth->soc; 1600 struct mtk_tx_dma *itxd, *txd; 1601 struct mtk_tx_dma *itxd_pdma, *txd_pdma; 1602 struct mtk_tx_buf *itx_buf, *tx_buf; 1603 int i, n_desc = 1; 1604 int queue = skb_get_queue_mapping(skb); 1605 int k = 0; 1606 1607 txq = netdev_get_tx_queue(dev, queue); 1608 itxd = ring->next_free; 1609 itxd_pdma = qdma_to_pdma(ring, itxd); 1610 if (itxd == ring->last_free) 1611 return -ENOMEM; 1612 1613 itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size); 1614 memset(itx_buf, 0, sizeof(*itx_buf)); 1615 1616 txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size, 1617 DMA_TO_DEVICE); 1618 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) 1619 return -ENOMEM; 1620 1621 mtk_tx_set_dma_desc(dev, itxd, &txd_info); 1622 1623 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 1624 itx_buf->mac_id = mac->id; 1625 setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size, 1626 k++); 1627 1628 /* TX SG offload */ 1629 txd = itxd; 1630 txd_pdma = qdma_to_pdma(ring, txd); 1631 1632 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1633 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1634 unsigned int offset = 0; 1635 int frag_size = skb_frag_size(frag); 1636 1637 while (frag_size) { 1638 bool new_desc = true; 1639 1640 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || 1641 (i & 0x1)) { 1642 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 1643 txd_pdma = qdma_to_pdma(ring, txd); 1644 if (txd == ring->last_free) 1645 goto err_dma; 1646 1647 n_desc++; 1648 } else { 1649 new_desc = false; 1650 } 1651 1652 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); 1653 txd_info.size = min_t(unsigned int, frag_size, 1654 soc->tx.dma_max_len); 1655 txd_info.qid = queue; 1656 txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 && 1657 !(frag_size - txd_info.size); 1658 txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag, 1659 offset, txd_info.size, 1660 DMA_TO_DEVICE); 1661 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) 1662 goto err_dma; 1663 1664 mtk_tx_set_dma_desc(dev, txd, &txd_info); 1665 1666 tx_buf = mtk_desc_to_tx_buf(ring, txd, 1667 soc->tx.desc_size); 1668 if (new_desc) 1669 memset(tx_buf, 0, sizeof(*tx_buf)); 1670 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1671 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 1672 tx_buf->mac_id = mac->id; 1673 1674 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr, 1675 txd_info.size, k++); 1676 1677 frag_size -= txd_info.size; 1678 offset += txd_info.size; 1679 } 1680 } 1681 1682 /* store skb to cleanup */ 1683 itx_buf->type = MTK_TYPE_SKB; 1684 itx_buf->data = skb; 1685 1686 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1687 if (k & 0x1) 1688 txd_pdma->txd2 |= TX_DMA_LS0; 1689 else 1690 txd_pdma->txd2 |= TX_DMA_LS1; 1691 } 1692 1693 netdev_tx_sent_queue(txq, skb->len); 1694 skb_tx_timestamp(skb); 1695 1696 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1697 atomic_sub(n_desc, &ring->free_count); 1698 1699 /* make sure that all changes to the dma ring are flushed before we 1700 * continue 1701 */ 1702 wmb(); 1703 1704 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1705 if (netif_xmit_stopped(txq) || !netdev_xmit_more()) 1706 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); 1707 } else { 1708 int next_idx; 1709 1710 next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->tx.desc_size), 1711 ring->dma_size); 1712 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0); 1713 } 1714 1715 return 0; 1716 1717 err_dma: 1718 do { 1719 tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size); 1720 1721 /* unmap dma */ 1722 mtk_tx_unmap(eth, tx_buf, NULL, false); 1723 1724 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1725 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 1726 itxd_pdma->txd2 = TX_DMA_DESP2_DEF; 1727 1728 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 1729 itxd_pdma = qdma_to_pdma(ring, itxd); 1730 } while (itxd != txd); 1731 1732 return -ENOMEM; 1733 } 1734 1735 static int mtk_cal_txd_req(struct mtk_eth *eth, struct sk_buff *skb) 1736 { 1737 int i, nfrags = 1; 1738 skb_frag_t *frag; 1739 1740 if (skb_is_gso(skb)) { 1741 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1742 frag = &skb_shinfo(skb)->frags[i]; 1743 nfrags += DIV_ROUND_UP(skb_frag_size(frag), 1744 eth->soc->tx.dma_max_len); 1745 } 1746 } else { 1747 nfrags += skb_shinfo(skb)->nr_frags; 1748 } 1749 1750 return nfrags; 1751 } 1752 1753 static int mtk_queue_stopped(struct mtk_eth *eth) 1754 { 1755 int i; 1756 1757 for (i = 0; i < MTK_MAX_DEVS; i++) { 1758 if (!eth->netdev[i]) 1759 continue; 1760 if (netif_queue_stopped(eth->netdev[i])) 1761 return 1; 1762 } 1763 1764 return 0; 1765 } 1766 1767 static void mtk_wake_queue(struct mtk_eth *eth) 1768 { 1769 int i; 1770 1771 for (i = 0; i < MTK_MAX_DEVS; i++) { 1772 if (!eth->netdev[i]) 1773 continue; 1774 netif_tx_wake_all_queues(eth->netdev[i]); 1775 } 1776 } 1777 1778 static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 1779 { 1780 struct mtk_mac *mac = netdev_priv(dev); 1781 struct mtk_eth *eth = mac->hw; 1782 struct mtk_tx_ring *ring = ð->tx_ring; 1783 struct net_device_stats *stats = &dev->stats; 1784 bool gso = false; 1785 int tx_num; 1786 1787 if (skb_vlan_tag_present(skb) && 1788 !eth_proto_is_802_3(eth_hdr(skb)->h_proto)) { 1789 skb = __vlan_hwaccel_push_inside(skb); 1790 if (!skb) 1791 goto dropped; 1792 } 1793 1794 /* normally we can rely on the stack not calling this more than once, 1795 * however we have 2 queues running on the same ring so we need to lock 1796 * the ring access 1797 */ 1798 spin_lock(ð->page_lock); 1799 1800 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1801 goto drop; 1802 1803 tx_num = mtk_cal_txd_req(eth, skb); 1804 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 1805 netif_tx_stop_all_queues(dev); 1806 netif_err(eth, tx_queued, dev, 1807 "Tx Ring full when queue awake!\n"); 1808 spin_unlock(ð->page_lock); 1809 return NETDEV_TX_BUSY; 1810 } 1811 1812 /* TSO: fill MSS info in tcp checksum field */ 1813 if (skb_is_gso(skb)) { 1814 if (skb_cow_head(skb, 0)) { 1815 netif_warn(eth, tx_err, dev, 1816 "GSO expand head fail.\n"); 1817 goto drop; 1818 } 1819 1820 if (skb_shinfo(skb)->gso_type & 1821 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 1822 gso = true; 1823 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 1824 } 1825 } 1826 1827 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 1828 goto drop; 1829 1830 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 1831 netif_tx_stop_all_queues(dev); 1832 1833 spin_unlock(ð->page_lock); 1834 1835 return NETDEV_TX_OK; 1836 1837 drop: 1838 spin_unlock(ð->page_lock); 1839 dev_kfree_skb_any(skb); 1840 dropped: 1841 stats->tx_dropped++; 1842 return NETDEV_TX_OK; 1843 } 1844 1845 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) 1846 { 1847 int i; 1848 struct mtk_rx_ring *ring; 1849 int idx; 1850 1851 if (!eth->hwlro) 1852 return ð->rx_ring[0]; 1853 1854 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1855 struct mtk_rx_dma *rxd; 1856 1857 ring = ð->rx_ring[i]; 1858 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1859 rxd = ring->dma + idx * eth->soc->rx.desc_size; 1860 if (rxd->rxd2 & RX_DMA_DONE) { 1861 ring->calc_idx_update = true; 1862 return ring; 1863 } 1864 } 1865 1866 return NULL; 1867 } 1868 1869 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) 1870 { 1871 struct mtk_rx_ring *ring; 1872 int i; 1873 1874 if (!eth->hwlro) { 1875 ring = ð->rx_ring[0]; 1876 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1877 } else { 1878 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1879 ring = ð->rx_ring[i]; 1880 if (ring->calc_idx_update) { 1881 ring->calc_idx_update = false; 1882 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1883 } 1884 } 1885 } 1886 } 1887 1888 static bool mtk_page_pool_enabled(struct mtk_eth *eth) 1889 { 1890 return mtk_is_netsys_v2_or_greater(eth); 1891 } 1892 1893 static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth, 1894 struct xdp_rxq_info *xdp_q, 1895 int id, int size) 1896 { 1897 struct page_pool_params pp_params = { 1898 .order = 0, 1899 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 1900 .pool_size = size, 1901 .nid = NUMA_NO_NODE, 1902 .dev = eth->dma_dev, 1903 .offset = MTK_PP_HEADROOM, 1904 .max_len = MTK_PP_MAX_BUF_SIZE, 1905 }; 1906 struct page_pool *pp; 1907 int err; 1908 1909 pp_params.dma_dir = rcu_access_pointer(eth->prog) ? DMA_BIDIRECTIONAL 1910 : DMA_FROM_DEVICE; 1911 pp = page_pool_create(&pp_params); 1912 if (IS_ERR(pp)) 1913 return pp; 1914 1915 err = __xdp_rxq_info_reg(xdp_q, eth->dummy_dev, id, 1916 eth->rx_napi.napi_id, PAGE_SIZE); 1917 if (err < 0) 1918 goto err_free_pp; 1919 1920 err = xdp_rxq_info_reg_mem_model(xdp_q, MEM_TYPE_PAGE_POOL, pp); 1921 if (err) 1922 goto err_unregister_rxq; 1923 1924 return pp; 1925 1926 err_unregister_rxq: 1927 xdp_rxq_info_unreg(xdp_q); 1928 err_free_pp: 1929 page_pool_destroy(pp); 1930 1931 return ERR_PTR(err); 1932 } 1933 1934 static void *mtk_page_pool_get_buff(struct page_pool *pp, dma_addr_t *dma_addr, 1935 gfp_t gfp_mask) 1936 { 1937 struct page *page; 1938 1939 page = page_pool_alloc_pages(pp, gfp_mask | __GFP_NOWARN); 1940 if (!page) 1941 return NULL; 1942 1943 *dma_addr = page_pool_get_dma_addr(page) + MTK_PP_HEADROOM; 1944 return page_address(page); 1945 } 1946 1947 static void mtk_rx_put_buff(struct mtk_rx_ring *ring, void *data, bool napi) 1948 { 1949 if (ring->page_pool) 1950 page_pool_put_full_page(ring->page_pool, 1951 virt_to_head_page(data), napi); 1952 else 1953 skb_free_frag(data); 1954 } 1955 1956 static int mtk_xdp_frame_map(struct mtk_eth *eth, struct net_device *dev, 1957 struct mtk_tx_dma_desc_info *txd_info, 1958 struct mtk_tx_dma *txd, struct mtk_tx_buf *tx_buf, 1959 void *data, u16 headroom, int index, bool dma_map) 1960 { 1961 struct mtk_tx_ring *ring = ð->tx_ring; 1962 struct mtk_mac *mac = netdev_priv(dev); 1963 struct mtk_tx_dma *txd_pdma; 1964 1965 if (dma_map) { /* ndo_xdp_xmit */ 1966 txd_info->addr = dma_map_single(eth->dma_dev, data, 1967 txd_info->size, DMA_TO_DEVICE); 1968 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info->addr))) 1969 return -ENOMEM; 1970 1971 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 1972 } else { 1973 struct page *page = virt_to_head_page(data); 1974 1975 txd_info->addr = page_pool_get_dma_addr(page) + 1976 sizeof(struct xdp_frame) + headroom; 1977 dma_sync_single_for_device(eth->dma_dev, txd_info->addr, 1978 txd_info->size, DMA_BIDIRECTIONAL); 1979 } 1980 mtk_tx_set_dma_desc(dev, txd, txd_info); 1981 1982 tx_buf->mac_id = mac->id; 1983 tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX; 1984 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1985 1986 txd_pdma = qdma_to_pdma(ring, txd); 1987 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info->addr, txd_info->size, 1988 index); 1989 1990 return 0; 1991 } 1992 1993 static int mtk_xdp_submit_frame(struct mtk_eth *eth, struct xdp_frame *xdpf, 1994 struct net_device *dev, bool dma_map) 1995 { 1996 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 1997 const struct mtk_soc_data *soc = eth->soc; 1998 struct mtk_tx_ring *ring = ð->tx_ring; 1999 struct mtk_mac *mac = netdev_priv(dev); 2000 struct mtk_tx_dma_desc_info txd_info = { 2001 .size = xdpf->len, 2002 .first = true, 2003 .last = !xdp_frame_has_frags(xdpf), 2004 .qid = mac->id, 2005 }; 2006 int err, index = 0, n_desc = 1, nr_frags; 2007 struct mtk_tx_buf *htx_buf, *tx_buf; 2008 struct mtk_tx_dma *htxd, *txd; 2009 void *data = xdpf->data; 2010 2011 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 2012 return -EBUSY; 2013 2014 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 2015 if (unlikely(atomic_read(&ring->free_count) <= 1 + nr_frags)) 2016 return -EBUSY; 2017 2018 spin_lock(ð->page_lock); 2019 2020 txd = ring->next_free; 2021 if (txd == ring->last_free) { 2022 spin_unlock(ð->page_lock); 2023 return -ENOMEM; 2024 } 2025 htxd = txd; 2026 2027 tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->tx.desc_size); 2028 memset(tx_buf, 0, sizeof(*tx_buf)); 2029 htx_buf = tx_buf; 2030 2031 for (;;) { 2032 err = mtk_xdp_frame_map(eth, dev, &txd_info, txd, tx_buf, 2033 data, xdpf->headroom, index, dma_map); 2034 if (err < 0) 2035 goto unmap; 2036 2037 if (txd_info.last) 2038 break; 2039 2040 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || (index & 0x1)) { 2041 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 2042 if (txd == ring->last_free) 2043 goto unmap; 2044 2045 tx_buf = mtk_desc_to_tx_buf(ring, txd, 2046 soc->tx.desc_size); 2047 memset(tx_buf, 0, sizeof(*tx_buf)); 2048 n_desc++; 2049 } 2050 2051 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); 2052 txd_info.size = skb_frag_size(&sinfo->frags[index]); 2053 txd_info.last = index + 1 == nr_frags; 2054 txd_info.qid = mac->id; 2055 data = skb_frag_address(&sinfo->frags[index]); 2056 2057 index++; 2058 } 2059 /* store xdpf for cleanup */ 2060 htx_buf->data = xdpf; 2061 2062 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 2063 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, txd); 2064 2065 if (index & 1) 2066 txd_pdma->txd2 |= TX_DMA_LS0; 2067 else 2068 txd_pdma->txd2 |= TX_DMA_LS1; 2069 } 2070 2071 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 2072 atomic_sub(n_desc, &ring->free_count); 2073 2074 /* make sure that all changes to the dma ring are flushed before we 2075 * continue 2076 */ 2077 wmb(); 2078 2079 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 2080 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); 2081 } else { 2082 int idx; 2083 2084 idx = txd_to_idx(ring, txd, soc->tx.desc_size); 2085 mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size), 2086 MT7628_TX_CTX_IDX0); 2087 } 2088 2089 spin_unlock(ð->page_lock); 2090 2091 return 0; 2092 2093 unmap: 2094 while (htxd != txd) { 2095 tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->tx.desc_size); 2096 mtk_tx_unmap(eth, tx_buf, NULL, false); 2097 2098 htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 2099 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 2100 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, htxd); 2101 2102 txd_pdma->txd2 = TX_DMA_DESP2_DEF; 2103 } 2104 2105 htxd = mtk_qdma_phys_to_virt(ring, htxd->txd2); 2106 } 2107 2108 spin_unlock(ð->page_lock); 2109 2110 return err; 2111 } 2112 2113 static int mtk_xdp_xmit(struct net_device *dev, int num_frame, 2114 struct xdp_frame **frames, u32 flags) 2115 { 2116 struct mtk_mac *mac = netdev_priv(dev); 2117 struct mtk_hw_stats *hw_stats = mac->hw_stats; 2118 struct mtk_eth *eth = mac->hw; 2119 int i, nxmit = 0; 2120 2121 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2122 return -EINVAL; 2123 2124 for (i = 0; i < num_frame; i++) { 2125 if (mtk_xdp_submit_frame(eth, frames[i], dev, true)) 2126 break; 2127 nxmit++; 2128 } 2129 2130 u64_stats_update_begin(&hw_stats->syncp); 2131 hw_stats->xdp_stats.tx_xdp_xmit += nxmit; 2132 hw_stats->xdp_stats.tx_xdp_xmit_errors += num_frame - nxmit; 2133 u64_stats_update_end(&hw_stats->syncp); 2134 2135 return nxmit; 2136 } 2137 2138 static u32 mtk_xdp_run(struct mtk_eth *eth, struct mtk_rx_ring *ring, 2139 struct xdp_buff *xdp, struct net_device *dev) 2140 { 2141 struct mtk_mac *mac = netdev_priv(dev); 2142 struct mtk_hw_stats *hw_stats = mac->hw_stats; 2143 u64 *count = &hw_stats->xdp_stats.rx_xdp_drop; 2144 struct bpf_prog *prog; 2145 u32 act = XDP_PASS; 2146 2147 rcu_read_lock(); 2148 2149 prog = rcu_dereference(eth->prog); 2150 if (!prog) 2151 goto out; 2152 2153 act = bpf_prog_run_xdp(prog, xdp); 2154 switch (act) { 2155 case XDP_PASS: 2156 count = &hw_stats->xdp_stats.rx_xdp_pass; 2157 goto update_stats; 2158 case XDP_REDIRECT: 2159 if (unlikely(xdp_do_redirect(dev, xdp, prog))) { 2160 act = XDP_DROP; 2161 break; 2162 } 2163 2164 count = &hw_stats->xdp_stats.rx_xdp_redirect; 2165 goto update_stats; 2166 case XDP_TX: { 2167 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 2168 2169 if (!xdpf || mtk_xdp_submit_frame(eth, xdpf, dev, false)) { 2170 count = &hw_stats->xdp_stats.rx_xdp_tx_errors; 2171 act = XDP_DROP; 2172 break; 2173 } 2174 2175 count = &hw_stats->xdp_stats.rx_xdp_tx; 2176 goto update_stats; 2177 } 2178 default: 2179 bpf_warn_invalid_xdp_action(dev, prog, act); 2180 fallthrough; 2181 case XDP_ABORTED: 2182 trace_xdp_exception(dev, prog, act); 2183 fallthrough; 2184 case XDP_DROP: 2185 break; 2186 } 2187 2188 page_pool_put_full_page(ring->page_pool, 2189 virt_to_head_page(xdp->data), true); 2190 2191 update_stats: 2192 u64_stats_update_begin(&hw_stats->syncp); 2193 *count = *count + 1; 2194 u64_stats_update_end(&hw_stats->syncp); 2195 out: 2196 rcu_read_unlock(); 2197 2198 return act; 2199 } 2200 2201 static int mtk_poll_rx(struct napi_struct *napi, int budget, 2202 struct mtk_eth *eth) 2203 { 2204 struct dim_sample dim_sample = {}; 2205 struct mtk_rx_ring *ring; 2206 bool xdp_flush = false; 2207 int idx; 2208 struct sk_buff *skb; 2209 u64 addr64 = 0; 2210 u8 *data, *new_data; 2211 struct mtk_rx_dma_v2 *rxd, trxd; 2212 int done = 0, bytes = 0; 2213 dma_addr_t dma_addr = DMA_MAPPING_ERROR; 2214 int ppe_idx = 0; 2215 2216 while (done < budget) { 2217 unsigned int pktlen, *rxdcsum; 2218 struct net_device *netdev; 2219 u32 hash, reason; 2220 int mac = 0; 2221 2222 ring = mtk_get_rx_ring(eth); 2223 if (unlikely(!ring)) 2224 goto rx_done; 2225 2226 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 2227 rxd = ring->dma + idx * eth->soc->rx.desc_size; 2228 data = ring->data[idx]; 2229 2230 if (!mtk_rx_get_desc(eth, &trxd, rxd)) 2231 break; 2232 2233 /* find out which mac the packet come from. values start at 1 */ 2234 if (mtk_is_netsys_v3_or_greater(eth)) { 2235 u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5); 2236 2237 switch (val) { 2238 case PSE_GDM1_PORT: 2239 case PSE_GDM2_PORT: 2240 mac = val - 1; 2241 break; 2242 case PSE_GDM3_PORT: 2243 mac = MTK_GMAC3_ID; 2244 break; 2245 default: 2246 break; 2247 } 2248 } else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 2249 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) { 2250 mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1; 2251 } 2252 2253 if (unlikely(mac < 0 || mac >= MTK_MAX_DEVS || 2254 !eth->netdev[mac])) 2255 goto release_desc; 2256 2257 netdev = eth->netdev[mac]; 2258 ppe_idx = eth->mac[mac]->ppe_idx; 2259 2260 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 2261 goto release_desc; 2262 2263 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 2264 2265 /* alloc new buffer */ 2266 if (ring->page_pool) { 2267 struct page *page = virt_to_head_page(data); 2268 struct xdp_buff xdp; 2269 u32 ret, metasize; 2270 2271 new_data = mtk_page_pool_get_buff(ring->page_pool, 2272 &dma_addr, 2273 GFP_ATOMIC); 2274 if (unlikely(!new_data)) { 2275 netdev->stats.rx_dropped++; 2276 goto release_desc; 2277 } 2278 2279 dma_sync_single_for_cpu(eth->dma_dev, 2280 page_pool_get_dma_addr(page) + MTK_PP_HEADROOM, 2281 pktlen, page_pool_get_dma_dir(ring->page_pool)); 2282 2283 xdp_init_buff(&xdp, PAGE_SIZE, &ring->xdp_q); 2284 xdp_prepare_buff(&xdp, data, MTK_PP_HEADROOM, pktlen, 2285 true); 2286 xdp_buff_clear_frags_flag(&xdp); 2287 2288 ret = mtk_xdp_run(eth, ring, &xdp, netdev); 2289 if (ret == XDP_REDIRECT) 2290 xdp_flush = true; 2291 2292 if (ret != XDP_PASS) 2293 goto skip_rx; 2294 2295 skb = build_skb(data, PAGE_SIZE); 2296 if (unlikely(!skb)) { 2297 page_pool_put_full_page(ring->page_pool, 2298 page, true); 2299 netdev->stats.rx_dropped++; 2300 goto skip_rx; 2301 } 2302 2303 skb_reserve(skb, xdp.data - xdp.data_hard_start); 2304 skb_put(skb, xdp.data_end - xdp.data); 2305 metasize = xdp.data - xdp.data_meta; 2306 if (metasize) 2307 skb_metadata_set(skb, metasize); 2308 skb_mark_for_recycle(skb); 2309 } else { 2310 if (ring->frag_size <= PAGE_SIZE) 2311 new_data = napi_alloc_frag(ring->frag_size); 2312 else 2313 new_data = mtk_max_lro_buf_alloc(GFP_ATOMIC); 2314 2315 if (unlikely(!new_data)) { 2316 netdev->stats.rx_dropped++; 2317 goto release_desc; 2318 } 2319 2320 dma_addr = dma_map_single(eth->dma_dev, 2321 new_data + NET_SKB_PAD + eth->ip_align, 2322 ring->buf_size, DMA_FROM_DEVICE); 2323 if (unlikely(dma_mapping_error(eth->dma_dev, 2324 dma_addr))) { 2325 skb_free_frag(new_data); 2326 netdev->stats.rx_dropped++; 2327 goto release_desc; 2328 } 2329 2330 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) 2331 addr64 = RX_DMA_GET_ADDR64(trxd.rxd2); 2332 2333 dma_unmap_single(eth->dma_dev, ((u64)trxd.rxd1 | addr64), 2334 ring->buf_size, DMA_FROM_DEVICE); 2335 2336 skb = build_skb(data, ring->frag_size); 2337 if (unlikely(!skb)) { 2338 netdev->stats.rx_dropped++; 2339 skb_free_frag(data); 2340 goto skip_rx; 2341 } 2342 2343 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 2344 skb_put(skb, pktlen); 2345 } 2346 2347 skb->dev = netdev; 2348 bytes += skb->len; 2349 2350 if (mtk_is_netsys_v3_or_greater(eth)) { 2351 reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5); 2352 hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY; 2353 if (hash != MTK_RXD5_FOE_ENTRY) 2354 skb_set_hash(skb, jhash_1word(hash, 0), 2355 PKT_HASH_TYPE_L4); 2356 rxdcsum = &trxd.rxd3; 2357 } else { 2358 reason = FIELD_GET(MTK_RXD4_PPE_CPU_REASON, trxd.rxd4); 2359 hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY; 2360 if (hash != MTK_RXD4_FOE_ENTRY) 2361 skb_set_hash(skb, jhash_1word(hash, 0), 2362 PKT_HASH_TYPE_L4); 2363 rxdcsum = &trxd.rxd4; 2364 } 2365 2366 if (*rxdcsum & eth->soc->rx.dma_l4_valid) 2367 skb->ip_summed = CHECKSUM_UNNECESSARY; 2368 else 2369 skb_checksum_none_assert(skb); 2370 skb->protocol = eth_type_trans(skb, netdev); 2371 2372 /* When using VLAN untagging in combination with DSA, the 2373 * hardware treats the MTK special tag as a VLAN and untags it. 2374 */ 2375 if (mtk_is_netsys_v1(eth) && (trxd.rxd2 & RX_DMA_VTAG) && 2376 netdev_uses_dsa(netdev)) { 2377 unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0); 2378 2379 if (port < ARRAY_SIZE(eth->dsa_meta) && 2380 eth->dsa_meta[port]) 2381 skb_dst_set_noref(skb, ð->dsa_meta[port]->dst); 2382 } 2383 2384 if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) 2385 mtk_ppe_check_skb(eth->ppe[ppe_idx], skb, hash); 2386 2387 skb_record_rx_queue(skb, 0); 2388 napi_gro_receive(napi, skb); 2389 2390 skip_rx: 2391 ring->data[idx] = new_data; 2392 rxd->rxd1 = (unsigned int)dma_addr; 2393 release_desc: 2394 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) { 2395 if (unlikely(dma_addr == DMA_MAPPING_ERROR)) 2396 addr64 = FIELD_GET(RX_DMA_ADDR64_MASK, 2397 rxd->rxd2); 2398 else 2399 addr64 = RX_DMA_PREP_ADDR64(dma_addr); 2400 } 2401 2402 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2403 rxd->rxd2 = RX_DMA_LSO; 2404 else 2405 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size) | addr64; 2406 2407 ring->calc_idx = idx; 2408 done++; 2409 } 2410 2411 rx_done: 2412 if (done) { 2413 /* make sure that all changes to the dma ring are flushed before 2414 * we continue 2415 */ 2416 wmb(); 2417 mtk_update_rx_cpu_idx(eth); 2418 } 2419 2420 eth->rx_packets += done; 2421 eth->rx_bytes += bytes; 2422 dim_update_sample(eth->rx_events, eth->rx_packets, eth->rx_bytes, 2423 &dim_sample); 2424 net_dim(ð->rx_dim, &dim_sample); 2425 2426 if (xdp_flush) 2427 xdp_do_flush(); 2428 2429 return done; 2430 } 2431 2432 struct mtk_poll_state { 2433 struct netdev_queue *txq; 2434 unsigned int total; 2435 unsigned int done; 2436 unsigned int bytes; 2437 }; 2438 2439 static void 2440 mtk_poll_tx_done(struct mtk_eth *eth, struct mtk_poll_state *state, u8 mac, 2441 struct sk_buff *skb) 2442 { 2443 struct netdev_queue *txq; 2444 struct net_device *dev; 2445 unsigned int bytes = skb->len; 2446 2447 state->total++; 2448 eth->tx_packets++; 2449 eth->tx_bytes += bytes; 2450 2451 dev = eth->netdev[mac]; 2452 if (!dev) 2453 return; 2454 2455 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); 2456 if (state->txq == txq) { 2457 state->done++; 2458 state->bytes += bytes; 2459 return; 2460 } 2461 2462 if (state->txq) 2463 netdev_tx_completed_queue(state->txq, state->done, state->bytes); 2464 2465 state->txq = txq; 2466 state->done = 1; 2467 state->bytes = bytes; 2468 } 2469 2470 static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget, 2471 struct mtk_poll_state *state) 2472 { 2473 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2474 struct mtk_tx_ring *ring = ð->tx_ring; 2475 struct mtk_tx_buf *tx_buf; 2476 struct xdp_frame_bulk bq; 2477 struct mtk_tx_dma *desc; 2478 u32 cpu, dma; 2479 2480 cpu = ring->last_free_ptr; 2481 dma = mtk_r32(eth, reg_map->qdma.drx_ptr); 2482 2483 desc = mtk_qdma_phys_to_virt(ring, cpu); 2484 xdp_frame_bulk_init(&bq); 2485 2486 while ((cpu != dma) && budget) { 2487 u32 next_cpu = desc->txd2; 2488 2489 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 2490 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 2491 break; 2492 2493 tx_buf = mtk_desc_to_tx_buf(ring, desc, 2494 eth->soc->tx.desc_size); 2495 if (!tx_buf->data) 2496 break; 2497 2498 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 2499 if (tx_buf->type == MTK_TYPE_SKB) 2500 mtk_poll_tx_done(eth, state, tx_buf->mac_id, 2501 tx_buf->data); 2502 2503 budget--; 2504 } 2505 mtk_tx_unmap(eth, tx_buf, &bq, true); 2506 2507 ring->last_free = desc; 2508 atomic_inc(&ring->free_count); 2509 2510 cpu = next_cpu; 2511 } 2512 xdp_flush_frame_bulk(&bq); 2513 2514 ring->last_free_ptr = cpu; 2515 mtk_w32(eth, cpu, reg_map->qdma.crx_ptr); 2516 2517 return budget; 2518 } 2519 2520 static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget, 2521 struct mtk_poll_state *state) 2522 { 2523 struct mtk_tx_ring *ring = ð->tx_ring; 2524 struct mtk_tx_buf *tx_buf; 2525 struct xdp_frame_bulk bq; 2526 struct mtk_tx_dma *desc; 2527 u32 cpu, dma; 2528 2529 cpu = ring->cpu_idx; 2530 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0); 2531 xdp_frame_bulk_init(&bq); 2532 2533 while ((cpu != dma) && budget) { 2534 tx_buf = &ring->buf[cpu]; 2535 if (!tx_buf->data) 2536 break; 2537 2538 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 2539 if (tx_buf->type == MTK_TYPE_SKB) 2540 mtk_poll_tx_done(eth, state, 0, tx_buf->data); 2541 budget--; 2542 } 2543 mtk_tx_unmap(eth, tx_buf, &bq, true); 2544 2545 desc = ring->dma + cpu * eth->soc->tx.desc_size; 2546 ring->last_free = desc; 2547 atomic_inc(&ring->free_count); 2548 2549 cpu = NEXT_DESP_IDX(cpu, ring->dma_size); 2550 } 2551 xdp_flush_frame_bulk(&bq); 2552 2553 ring->cpu_idx = cpu; 2554 2555 return budget; 2556 } 2557 2558 static int mtk_poll_tx(struct mtk_eth *eth, int budget) 2559 { 2560 struct mtk_tx_ring *ring = ð->tx_ring; 2561 struct dim_sample dim_sample = {}; 2562 struct mtk_poll_state state = {}; 2563 2564 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2565 budget = mtk_poll_tx_qdma(eth, budget, &state); 2566 else 2567 budget = mtk_poll_tx_pdma(eth, budget, &state); 2568 2569 if (state.txq) 2570 netdev_tx_completed_queue(state.txq, state.done, state.bytes); 2571 2572 dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes, 2573 &dim_sample); 2574 net_dim(ð->tx_dim, &dim_sample); 2575 2576 if (mtk_queue_stopped(eth) && 2577 (atomic_read(&ring->free_count) > ring->thresh)) 2578 mtk_wake_queue(eth); 2579 2580 return state.total; 2581 } 2582 2583 static void mtk_handle_status_irq(struct mtk_eth *eth) 2584 { 2585 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 2586 2587 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 2588 mtk_stats_update(eth); 2589 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 2590 MTK_INT_STATUS2); 2591 } 2592 } 2593 2594 static int mtk_napi_tx(struct napi_struct *napi, int budget) 2595 { 2596 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 2597 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2598 int tx_done = 0; 2599 2600 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2601 mtk_handle_status_irq(eth); 2602 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->tx_irq_status); 2603 tx_done = mtk_poll_tx(eth, budget); 2604 2605 if (unlikely(netif_msg_intr(eth))) { 2606 dev_info(eth->dev, 2607 "done tx %d, intr 0x%08x/0x%x\n", tx_done, 2608 mtk_r32(eth, reg_map->tx_irq_status), 2609 mtk_r32(eth, reg_map->tx_irq_mask)); 2610 } 2611 2612 if (tx_done == budget) 2613 return budget; 2614 2615 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) 2616 return budget; 2617 2618 if (napi_complete_done(napi, tx_done)) 2619 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2620 2621 return tx_done; 2622 } 2623 2624 static int mtk_napi_rx(struct napi_struct *napi, int budget) 2625 { 2626 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 2627 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2628 int rx_done_total = 0; 2629 2630 mtk_handle_status_irq(eth); 2631 2632 do { 2633 int rx_done; 2634 2635 mtk_w32(eth, eth->soc->rx.irq_done_mask, 2636 reg_map->pdma.irq_status); 2637 rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth); 2638 rx_done_total += rx_done; 2639 2640 if (unlikely(netif_msg_intr(eth))) { 2641 dev_info(eth->dev, 2642 "done rx %d, intr 0x%08x/0x%x\n", rx_done, 2643 mtk_r32(eth, reg_map->pdma.irq_status), 2644 mtk_r32(eth, reg_map->pdma.irq_mask)); 2645 } 2646 2647 if (rx_done_total == budget) 2648 return budget; 2649 2650 } while (mtk_r32(eth, reg_map->pdma.irq_status) & 2651 eth->soc->rx.irq_done_mask); 2652 2653 if (napi_complete_done(napi, rx_done_total)) 2654 mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask); 2655 2656 return rx_done_total; 2657 } 2658 2659 static int mtk_tx_alloc(struct mtk_eth *eth) 2660 { 2661 const struct mtk_soc_data *soc = eth->soc; 2662 struct mtk_tx_ring *ring = ð->tx_ring; 2663 int i, sz = soc->tx.desc_size; 2664 struct mtk_tx_dma_v2 *txd; 2665 int ring_size; 2666 u32 ofs, val; 2667 2668 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 2669 ring_size = MTK_QDMA_RING_SIZE; 2670 else 2671 ring_size = soc->tx.dma_size; 2672 2673 ring->buf = kzalloc_objs(*ring->buf, ring_size); 2674 if (!ring->buf) 2675 goto no_tx_mem; 2676 2677 ring->dma = mtk_dma_ring_alloc(eth, ring_size * sz, &ring->phys, true); 2678 if (!ring->dma) 2679 goto no_tx_mem; 2680 2681 for (i = 0; i < ring_size; i++) { 2682 int next = (i + 1) % ring_size; 2683 u32 next_ptr = ring->phys + next * sz; 2684 2685 txd = ring->dma + i * sz; 2686 txd->txd2 = next_ptr; 2687 txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 2688 txd->txd4 = 0; 2689 if (mtk_is_netsys_v2_or_greater(eth)) { 2690 txd->txd5 = 0; 2691 txd->txd6 = 0; 2692 txd->txd7 = 0; 2693 txd->txd8 = 0; 2694 } 2695 } 2696 2697 /* On MT7688 (PDMA only) this driver uses the ring->dma structs 2698 * only as the framework. The real HW descriptors are the PDMA 2699 * descriptors in ring->dma_pdma. 2700 */ 2701 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 2702 ring->dma_pdma = dma_alloc_coherent(eth->dma_dev, ring_size * sz, 2703 &ring->phys_pdma, GFP_KERNEL); 2704 if (!ring->dma_pdma) 2705 goto no_tx_mem; 2706 2707 for (i = 0; i < ring_size; i++) { 2708 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF; 2709 ring->dma_pdma[i].txd4 = 0; 2710 } 2711 } 2712 2713 ring->dma_size = ring_size; 2714 atomic_set(&ring->free_count, ring_size - 2); 2715 ring->next_free = ring->dma; 2716 ring->last_free = (void *)txd; 2717 ring->last_free_ptr = (u32)(ring->phys + ((ring_size - 1) * sz)); 2718 ring->thresh = MAX_SKB_FRAGS; 2719 2720 /* make sure that all changes to the dma ring are flushed before we 2721 * continue 2722 */ 2723 wmb(); 2724 2725 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 2726 mtk_w32(eth, ring->phys, soc->reg_map->qdma.ctx_ptr); 2727 mtk_w32(eth, ring->phys, soc->reg_map->qdma.dtx_ptr); 2728 mtk_w32(eth, 2729 ring->phys + ((ring_size - 1) * sz), 2730 soc->reg_map->qdma.crx_ptr); 2731 mtk_w32(eth, ring->last_free_ptr, soc->reg_map->qdma.drx_ptr); 2732 2733 for (i = 0, ofs = 0; i < MTK_QDMA_NUM_QUEUES; i++) { 2734 val = (QDMA_RES_THRES << 8) | QDMA_RES_THRES; 2735 mtk_w32(eth, val, soc->reg_map->qdma.qtx_cfg + ofs); 2736 2737 val = MTK_QTX_SCH_MIN_RATE_EN | 2738 /* minimum: 10 Mbps */ 2739 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | 2740 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | 2741 MTK_QTX_SCH_LEAKY_BUCKET_SIZE; 2742 if (mtk_is_netsys_v1(eth)) 2743 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; 2744 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); 2745 ofs += MTK_QTX_OFFSET; 2746 } 2747 val = MTK_QDMA_TX_SCH_MAX_WFQ | (MTK_QDMA_TX_SCH_MAX_WFQ << 16); 2748 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate); 2749 if (mtk_is_netsys_v2_or_greater(eth)) 2750 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4); 2751 } else { 2752 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0); 2753 mtk_w32(eth, ring_size, MT7628_TX_MAX_CNT0); 2754 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0); 2755 mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx); 2756 } 2757 2758 return 0; 2759 2760 no_tx_mem: 2761 return -ENOMEM; 2762 } 2763 2764 static void mtk_tx_clean(struct mtk_eth *eth) 2765 { 2766 const struct mtk_soc_data *soc = eth->soc; 2767 struct mtk_tx_ring *ring = ð->tx_ring; 2768 int i; 2769 2770 if (ring->buf) { 2771 for (i = 0; i < ring->dma_size; i++) 2772 mtk_tx_unmap(eth, &ring->buf[i], NULL, false); 2773 kfree(ring->buf); 2774 ring->buf = NULL; 2775 } 2776 2777 if (ring->dma) { 2778 mtk_dma_ring_free(eth, ring->dma_size * soc->tx.desc_size, 2779 ring->dma, ring->phys, true); 2780 ring->dma = NULL; 2781 } 2782 2783 if (ring->dma_pdma) { 2784 dma_free_coherent(eth->dma_dev, 2785 ring->dma_size * soc->tx.desc_size, 2786 ring->dma_pdma, ring->phys_pdma); 2787 ring->dma_pdma = NULL; 2788 } 2789 } 2790 2791 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) 2792 { 2793 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2794 const struct mtk_soc_data *soc = eth->soc; 2795 struct mtk_rx_ring *ring; 2796 int rx_data_len, rx_dma_size; 2797 int i; 2798 2799 if (rx_flag == MTK_RX_FLAGS_QDMA) { 2800 if (ring_no) 2801 return -EINVAL; 2802 ring = ð->rx_ring_qdma; 2803 } else { 2804 ring = ð->rx_ring[ring_no]; 2805 } 2806 2807 if (rx_flag == MTK_RX_FLAGS_HWLRO) { 2808 rx_data_len = MTK_MAX_LRO_RX_LENGTH; 2809 rx_dma_size = MTK_HW_LRO_DMA_SIZE; 2810 } else { 2811 rx_data_len = ETH_DATA_LEN; 2812 rx_dma_size = soc->rx.dma_size; 2813 } 2814 2815 ring->frag_size = mtk_max_frag_size(rx_data_len); 2816 ring->buf_size = mtk_max_buf_size(ring->frag_size); 2817 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), 2818 GFP_KERNEL); 2819 if (!ring->data) 2820 return -ENOMEM; 2821 2822 if (mtk_page_pool_enabled(eth)) { 2823 struct page_pool *pp; 2824 2825 pp = mtk_create_page_pool(eth, &ring->xdp_q, ring_no, 2826 rx_dma_size); 2827 if (IS_ERR(pp)) 2828 return PTR_ERR(pp); 2829 2830 ring->page_pool = pp; 2831 } 2832 2833 ring->dma = mtk_dma_ring_alloc(eth, 2834 rx_dma_size * eth->soc->rx.desc_size, 2835 &ring->phys, 2836 rx_flag == MTK_RX_FLAGS_NORMAL); 2837 if (!ring->dma) 2838 return -ENOMEM; 2839 2840 for (i = 0; i < rx_dma_size; i++) { 2841 struct mtk_rx_dma_v2 *rxd; 2842 dma_addr_t dma_addr; 2843 void *data; 2844 2845 rxd = ring->dma + i * eth->soc->rx.desc_size; 2846 if (ring->page_pool) { 2847 data = mtk_page_pool_get_buff(ring->page_pool, 2848 &dma_addr, GFP_KERNEL); 2849 if (!data) 2850 return -ENOMEM; 2851 } else { 2852 if (ring->frag_size <= PAGE_SIZE) 2853 data = netdev_alloc_frag(ring->frag_size); 2854 else 2855 data = mtk_max_lro_buf_alloc(GFP_KERNEL); 2856 2857 if (!data) 2858 return -ENOMEM; 2859 2860 dma_addr = dma_map_single(eth->dma_dev, 2861 data + NET_SKB_PAD + eth->ip_align, 2862 ring->buf_size, DMA_FROM_DEVICE); 2863 if (unlikely(dma_mapping_error(eth->dma_dev, 2864 dma_addr))) { 2865 skb_free_frag(data); 2866 return -ENOMEM; 2867 } 2868 } 2869 rxd->rxd1 = (unsigned int)dma_addr; 2870 ring->data[i] = data; 2871 2872 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2873 rxd->rxd2 = RX_DMA_LSO; 2874 else 2875 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); 2876 2877 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) 2878 rxd->rxd2 |= RX_DMA_PREP_ADDR64(dma_addr); 2879 2880 rxd->rxd3 = 0; 2881 rxd->rxd4 = 0; 2882 if (mtk_is_netsys_v3_or_greater(eth)) { 2883 rxd->rxd5 = 0; 2884 rxd->rxd6 = 0; 2885 rxd->rxd7 = 0; 2886 rxd->rxd8 = 0; 2887 } 2888 } 2889 2890 ring->dma_size = rx_dma_size; 2891 ring->calc_idx_update = false; 2892 ring->calc_idx = rx_dma_size - 1; 2893 if (rx_flag == MTK_RX_FLAGS_QDMA) 2894 ring->crx_idx_reg = reg_map->qdma.qcrx_ptr + 2895 ring_no * MTK_QRX_OFFSET; 2896 else 2897 ring->crx_idx_reg = reg_map->pdma.pcrx_ptr + 2898 ring_no * MTK_QRX_OFFSET; 2899 /* make sure that all changes to the dma ring are flushed before we 2900 * continue 2901 */ 2902 wmb(); 2903 2904 if (rx_flag == MTK_RX_FLAGS_QDMA) { 2905 mtk_w32(eth, ring->phys, 2906 reg_map->qdma.rx_ptr + ring_no * MTK_QRX_OFFSET); 2907 mtk_w32(eth, rx_dma_size, 2908 reg_map->qdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); 2909 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), 2910 reg_map->qdma.rst_idx); 2911 } else { 2912 mtk_w32(eth, ring->phys, 2913 reg_map->pdma.rx_ptr + ring_no * MTK_QRX_OFFSET); 2914 mtk_w32(eth, rx_dma_size, 2915 reg_map->pdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); 2916 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), 2917 reg_map->pdma.rst_idx); 2918 } 2919 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 2920 2921 return 0; 2922 } 2923 2924 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring, bool in_sram) 2925 { 2926 u64 addr64 = 0; 2927 int i; 2928 2929 if (ring->data && ring->dma) { 2930 for (i = 0; i < ring->dma_size; i++) { 2931 struct mtk_rx_dma *rxd; 2932 2933 if (!ring->data[i]) 2934 continue; 2935 2936 rxd = ring->dma + i * eth->soc->rx.desc_size; 2937 if (!rxd->rxd1) 2938 continue; 2939 2940 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) 2941 addr64 = RX_DMA_GET_ADDR64(rxd->rxd2); 2942 2943 dma_unmap_single(eth->dma_dev, ((u64)rxd->rxd1 | addr64), 2944 ring->buf_size, DMA_FROM_DEVICE); 2945 mtk_rx_put_buff(ring, ring->data[i], false); 2946 } 2947 kfree(ring->data); 2948 ring->data = NULL; 2949 } 2950 2951 if (ring->dma) { 2952 mtk_dma_ring_free(eth, ring->dma_size * eth->soc->rx.desc_size, 2953 ring->dma, ring->phys, in_sram); 2954 ring->dma = NULL; 2955 } 2956 2957 if (ring->page_pool) { 2958 if (xdp_rxq_info_is_reg(&ring->xdp_q)) 2959 xdp_rxq_info_unreg(&ring->xdp_q); 2960 page_pool_destroy(ring->page_pool); 2961 ring->page_pool = NULL; 2962 } 2963 } 2964 2965 static int mtk_hwlro_rx_init(struct mtk_eth *eth) 2966 { 2967 int i; 2968 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; 2969 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; 2970 2971 /* set LRO rings to auto-learn modes */ 2972 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; 2973 2974 /* validate LRO ring */ 2975 ring_ctrl_dw2 |= MTK_RING_VLD; 2976 2977 /* set AGE timer (unit: 20us) */ 2978 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; 2979 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; 2980 2981 /* set max AGG timer (unit: 20us) */ 2982 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; 2983 2984 /* set max LRO AGG count */ 2985 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; 2986 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; 2987 2988 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 2989 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); 2990 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); 2991 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); 2992 } 2993 2994 /* IPv4 checksum update enable */ 2995 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; 2996 2997 /* switch priority comparison to packet count mode */ 2998 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; 2999 3000 /* bandwidth threshold setting */ 3001 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); 3002 3003 /* auto-learn score delta setting */ 3004 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); 3005 3006 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ 3007 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, 3008 MTK_PDMA_LRO_ALT_REFRESH_TIMER); 3009 3010 /* set HW LRO mode & the max aggregation count for rx packets */ 3011 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); 3012 3013 /* the minimal remaining room of SDL0 in RXD for lro aggregation */ 3014 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; 3015 3016 /* enable HW LRO */ 3017 lro_ctrl_dw0 |= MTK_LRO_EN; 3018 3019 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); 3020 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); 3021 3022 return 0; 3023 } 3024 3025 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) 3026 { 3027 int i; 3028 u32 val; 3029 3030 /* relinquish lro rings, flush aggregated packets */ 3031 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); 3032 3033 /* wait for relinquishments done */ 3034 for (i = 0; i < 10; i++) { 3035 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); 3036 if (val & MTK_LRO_RING_RELINQUISH_DONE) { 3037 msleep(20); 3038 continue; 3039 } 3040 break; 3041 } 3042 3043 /* invalidate lro rings */ 3044 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 3045 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); 3046 3047 /* disable HW LRO */ 3048 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); 3049 } 3050 3051 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) 3052 { 3053 u32 reg_val; 3054 3055 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 3056 3057 /* invalidate the IP setting */ 3058 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 3059 3060 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); 3061 3062 /* validate the IP setting */ 3063 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 3064 } 3065 3066 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) 3067 { 3068 u32 reg_val; 3069 3070 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 3071 3072 /* invalidate the IP setting */ 3073 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 3074 3075 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); 3076 } 3077 3078 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) 3079 { 3080 int cnt = 0; 3081 int i; 3082 3083 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 3084 if (mac->hwlro_ip[i]) 3085 cnt++; 3086 } 3087 3088 return cnt; 3089 } 3090 3091 static int mtk_hwlro_add_ipaddr(struct net_device *dev, 3092 struct ethtool_rxnfc *cmd) 3093 { 3094 struct ethtool_rx_flow_spec *fsp = 3095 (struct ethtool_rx_flow_spec *)&cmd->fs; 3096 struct mtk_mac *mac = netdev_priv(dev); 3097 struct mtk_eth *eth = mac->hw; 3098 int hwlro_idx; 3099 3100 if ((fsp->flow_type != TCP_V4_FLOW) || 3101 (!fsp->h_u.tcp_ip4_spec.ip4dst) || 3102 (fsp->location > 1)) 3103 return -EINVAL; 3104 3105 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); 3106 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 3107 3108 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 3109 3110 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); 3111 3112 return 0; 3113 } 3114 3115 static int mtk_hwlro_del_ipaddr(struct net_device *dev, 3116 struct ethtool_rxnfc *cmd) 3117 { 3118 struct ethtool_rx_flow_spec *fsp = 3119 (struct ethtool_rx_flow_spec *)&cmd->fs; 3120 struct mtk_mac *mac = netdev_priv(dev); 3121 struct mtk_eth *eth = mac->hw; 3122 int hwlro_idx; 3123 3124 if (fsp->location > 1) 3125 return -EINVAL; 3126 3127 mac->hwlro_ip[fsp->location] = 0; 3128 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 3129 3130 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 3131 3132 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 3133 3134 return 0; 3135 } 3136 3137 static void mtk_hwlro_netdev_disable(struct net_device *dev) 3138 { 3139 struct mtk_mac *mac = netdev_priv(dev); 3140 struct mtk_eth *eth = mac->hw; 3141 int i, hwlro_idx; 3142 3143 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 3144 mac->hwlro_ip[i] = 0; 3145 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; 3146 3147 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 3148 } 3149 3150 mac->hwlro_ip_cnt = 0; 3151 } 3152 3153 static int mtk_hwlro_get_fdir_entry(struct net_device *dev, 3154 struct ethtool_rxnfc *cmd) 3155 { 3156 struct mtk_mac *mac = netdev_priv(dev); 3157 struct ethtool_rx_flow_spec *fsp = 3158 (struct ethtool_rx_flow_spec *)&cmd->fs; 3159 3160 if (fsp->location >= ARRAY_SIZE(mac->hwlro_ip)) 3161 return -EINVAL; 3162 3163 /* only tcp dst ipv4 is meaningful, others are meaningless */ 3164 fsp->flow_type = TCP_V4_FLOW; 3165 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); 3166 fsp->m_u.tcp_ip4_spec.ip4dst = 0; 3167 3168 fsp->h_u.tcp_ip4_spec.ip4src = 0; 3169 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; 3170 fsp->h_u.tcp_ip4_spec.psrc = 0; 3171 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; 3172 fsp->h_u.tcp_ip4_spec.pdst = 0; 3173 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; 3174 fsp->h_u.tcp_ip4_spec.tos = 0; 3175 fsp->m_u.tcp_ip4_spec.tos = 0xff; 3176 3177 return 0; 3178 } 3179 3180 static int mtk_hwlro_get_fdir_all(struct net_device *dev, 3181 struct ethtool_rxnfc *cmd, 3182 u32 *rule_locs) 3183 { 3184 struct mtk_mac *mac = netdev_priv(dev); 3185 int cnt = 0; 3186 int i; 3187 3188 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 3189 if (cnt == cmd->rule_cnt) 3190 return -EMSGSIZE; 3191 3192 if (mac->hwlro_ip[i]) { 3193 rule_locs[cnt] = i; 3194 cnt++; 3195 } 3196 } 3197 3198 cmd->rule_cnt = cnt; 3199 3200 return 0; 3201 } 3202 3203 static netdev_features_t mtk_fix_features(struct net_device *dev, 3204 netdev_features_t features) 3205 { 3206 if (!(features & NETIF_F_LRO)) { 3207 struct mtk_mac *mac = netdev_priv(dev); 3208 int ip_cnt = mtk_hwlro_get_ip_cnt(mac); 3209 3210 if (ip_cnt) { 3211 netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); 3212 3213 features |= NETIF_F_LRO; 3214 } 3215 } 3216 3217 return features; 3218 } 3219 3220 static int mtk_set_features(struct net_device *dev, netdev_features_t features) 3221 { 3222 netdev_features_t diff = dev->features ^ features; 3223 3224 if ((diff & NETIF_F_LRO) && !(features & NETIF_F_LRO)) 3225 mtk_hwlro_netdev_disable(dev); 3226 3227 return 0; 3228 } 3229 3230 /* wait for DMA to finish whatever it is doing before we start using it again */ 3231 static int mtk_dma_busy_wait(struct mtk_eth *eth) 3232 { 3233 unsigned int reg; 3234 int ret; 3235 u32 val; 3236 3237 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3238 reg = eth->soc->reg_map->qdma.glo_cfg; 3239 else 3240 reg = eth->soc->reg_map->pdma.glo_cfg; 3241 3242 ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val, 3243 !(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)), 3244 5, MTK_DMA_BUSY_TIMEOUT_US); 3245 if (ret) 3246 dev_err(eth->dev, "DMA init timeout\n"); 3247 3248 return ret; 3249 } 3250 3251 static int mtk_dma_init(struct mtk_eth *eth) 3252 { 3253 int err; 3254 u32 i; 3255 3256 if (mtk_dma_busy_wait(eth)) 3257 return -EBUSY; 3258 3259 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3260 /* QDMA needs scratch memory for internal reordering of the 3261 * descriptors 3262 */ 3263 err = mtk_init_fq_dma(eth); 3264 if (err) 3265 return err; 3266 } 3267 3268 err = mtk_tx_alloc(eth); 3269 if (err) 3270 return err; 3271 3272 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3273 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); 3274 if (err) 3275 return err; 3276 } 3277 3278 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); 3279 if (err) 3280 return err; 3281 3282 if (eth->hwlro) { 3283 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 3284 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); 3285 if (err) 3286 return err; 3287 } 3288 err = mtk_hwlro_rx_init(eth); 3289 if (err) 3290 return err; 3291 } 3292 3293 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3294 /* Enable random early drop and set drop threshold 3295 * automatically 3296 */ 3297 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | 3298 FC_THRES_MIN, eth->soc->reg_map->qdma.fc_th); 3299 mtk_w32(eth, 0x0, eth->soc->reg_map->qdma.hred); 3300 } 3301 3302 return 0; 3303 } 3304 3305 static void mtk_dma_free(struct mtk_eth *eth) 3306 { 3307 const struct mtk_soc_data *soc = eth->soc; 3308 int i, j, txqs = 1; 3309 3310 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3311 txqs = MTK_QDMA_NUM_QUEUES; 3312 3313 for (i = 0; i < MTK_MAX_DEVS; i++) { 3314 if (!eth->netdev[i]) 3315 continue; 3316 3317 for (j = 0; j < txqs; j++) 3318 netdev_tx_reset_subqueue(eth->netdev[i], j); 3319 } 3320 3321 if (eth->scratch_ring) { 3322 mtk_dma_ring_free(eth, soc->tx.fq_dma_size * soc->tx.desc_size, 3323 eth->scratch_ring, eth->phy_scratch_ring, 3324 true); 3325 eth->scratch_ring = NULL; 3326 eth->phy_scratch_ring = 0; 3327 } 3328 3329 mtk_tx_clean(eth); 3330 mtk_rx_clean(eth, ð->rx_ring[0], true); 3331 mtk_rx_clean(eth, ð->rx_ring_qdma, false); 3332 3333 if (eth->hwlro) { 3334 mtk_hwlro_rx_uninit(eth); 3335 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 3336 mtk_rx_clean(eth, ð->rx_ring[i], false); 3337 } 3338 3339 for (i = 0; i < DIV_ROUND_UP(soc->tx.fq_dma_size, MTK_FQ_DMA_LENGTH); i++) { 3340 kfree(eth->scratch_head[i]); 3341 eth->scratch_head[i] = NULL; 3342 } 3343 } 3344 3345 static bool mtk_hw_reset_check(struct mtk_eth *eth) 3346 { 3347 u32 val = mtk_r32(eth, MTK_INT_STATUS2); 3348 3349 return (val & MTK_FE_INT_FQ_EMPTY) || (val & MTK_FE_INT_RFIFO_UF) || 3350 (val & MTK_FE_INT_RFIFO_OV) || (val & MTK_FE_INT_TSO_FAIL) || 3351 (val & MTK_FE_INT_TSO_ALIGN) || (val & MTK_FE_INT_TSO_ILLEGAL); 3352 } 3353 3354 static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue) 3355 { 3356 struct mtk_mac *mac = netdev_priv(dev); 3357 struct mtk_eth *eth = mac->hw; 3358 3359 if (test_bit(MTK_RESETTING, ð->state)) 3360 return; 3361 3362 if (!mtk_hw_reset_check(eth)) 3363 return; 3364 3365 eth->netdev[mac->id]->stats.tx_errors++; 3366 netif_err(eth, tx_err, dev, "transmit timed out\n"); 3367 3368 schedule_work(ð->pending_work); 3369 } 3370 3371 static int mtk_get_irqs(struct platform_device *pdev, struct mtk_eth *eth) 3372 { 3373 int i; 3374 3375 /* future SoCs beginning with MT7988 should use named IRQs in dts */ 3376 eth->irq[MTK_FE_IRQ_TX] = platform_get_irq_byname_optional(pdev, "fe1"); 3377 eth->irq[MTK_FE_IRQ_RX] = platform_get_irq_byname_optional(pdev, "fe2"); 3378 if (eth->irq[MTK_FE_IRQ_TX] >= 0 && eth->irq[MTK_FE_IRQ_RX] >= 0) 3379 return 0; 3380 3381 /* only use legacy mode if platform_get_irq_byname_optional returned -ENXIO */ 3382 if (eth->irq[MTK_FE_IRQ_TX] != -ENXIO) 3383 return dev_err_probe(&pdev->dev, eth->irq[MTK_FE_IRQ_TX], 3384 "Error requesting FE TX IRQ\n"); 3385 3386 if (eth->irq[MTK_FE_IRQ_RX] != -ENXIO) 3387 return dev_err_probe(&pdev->dev, eth->irq[MTK_FE_IRQ_RX], 3388 "Error requesting FE RX IRQ\n"); 3389 3390 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) 3391 dev_warn(&pdev->dev, "legacy DT: missing interrupt-names."); 3392 3393 /* legacy way: 3394 * On MTK_SHARED_INT SoCs (MT7621 + MT7628) the first IRQ is taken 3395 * from devicetree and used for both RX and TX - it is shared. 3396 * On SoCs with non-shared IRQs the first entry is not used, 3397 * the second is for TX, and the third is for RX. 3398 */ 3399 for (i = 0; i < MTK_FE_IRQ_NUM; i++) { 3400 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { 3401 if (i == MTK_FE_IRQ_SHARED) 3402 eth->irq[MTK_FE_IRQ_SHARED] = platform_get_irq(pdev, i); 3403 else 3404 eth->irq[i] = eth->irq[MTK_FE_IRQ_SHARED]; 3405 } else { 3406 eth->irq[i] = platform_get_irq(pdev, i + 1); 3407 } 3408 3409 if (eth->irq[i] < 0) { 3410 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 3411 return -ENXIO; 3412 } 3413 } 3414 3415 return 0; 3416 } 3417 3418 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 3419 { 3420 struct mtk_eth *eth = _eth; 3421 3422 eth->rx_events++; 3423 if (likely(napi_schedule_prep(ð->rx_napi))) { 3424 mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask); 3425 __napi_schedule(ð->rx_napi); 3426 } 3427 3428 return IRQ_HANDLED; 3429 } 3430 3431 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 3432 { 3433 struct mtk_eth *eth = _eth; 3434 3435 eth->tx_events++; 3436 if (likely(napi_schedule_prep(ð->tx_napi))) { 3437 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3438 __napi_schedule(ð->tx_napi); 3439 } 3440 3441 return IRQ_HANDLED; 3442 } 3443 3444 static irqreturn_t mtk_handle_irq(int irq, void *_eth) 3445 { 3446 struct mtk_eth *eth = _eth; 3447 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3448 3449 if (mtk_r32(eth, reg_map->pdma.irq_mask) & 3450 eth->soc->rx.irq_done_mask) { 3451 if (mtk_r32(eth, reg_map->pdma.irq_status) & 3452 eth->soc->rx.irq_done_mask) 3453 mtk_handle_irq_rx(irq, _eth); 3454 } 3455 if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) { 3456 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) 3457 mtk_handle_irq_tx(irq, _eth); 3458 } 3459 3460 return IRQ_HANDLED; 3461 } 3462 3463 #ifdef CONFIG_NET_POLL_CONTROLLER 3464 static void mtk_poll_controller(struct net_device *dev) 3465 { 3466 struct mtk_mac *mac = netdev_priv(dev); 3467 struct mtk_eth *eth = mac->hw; 3468 3469 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3470 mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask); 3471 mtk_handle_irq_rx(eth->irq[MTK_FE_IRQ_RX], eth); 3472 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 3473 mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask); 3474 } 3475 #endif 3476 3477 static int mtk_start_dma(struct mtk_eth *eth) 3478 { 3479 u32 val, rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; 3480 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3481 int err; 3482 3483 err = mtk_dma_init(eth); 3484 if (err) { 3485 mtk_dma_free(eth); 3486 return err; 3487 } 3488 3489 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3490 val = mtk_r32(eth, reg_map->qdma.glo_cfg); 3491 val |= MTK_TX_DMA_EN | MTK_RX_DMA_EN | 3492 MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO | 3493 MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE; 3494 3495 if (mtk_is_netsys_v2_or_greater(eth)) 3496 val |= MTK_MUTLI_CNT | MTK_RESV_BUF | 3497 MTK_WCOMP_EN | MTK_DMAD_WR_WDONE | 3498 MTK_CHK_DDONE_EN; 3499 else 3500 val |= MTK_RX_BT_32DWORDS; 3501 mtk_w32(eth, val, reg_map->qdma.glo_cfg); 3502 3503 mtk_w32(eth, 3504 MTK_RX_DMA_EN | rx_2b_offset | 3505 MTK_RX_BT_32DWORDS | MTK_MULTI_EN, 3506 reg_map->pdma.glo_cfg); 3507 } else { 3508 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN | 3509 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS, 3510 reg_map->pdma.glo_cfg); 3511 } 3512 3513 return 0; 3514 } 3515 3516 static void mtk_gdm_config(struct mtk_eth *eth, u32 id, u32 config) 3517 { 3518 u32 val; 3519 3520 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3521 return; 3522 3523 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(id)); 3524 3525 /* default setup the forward port to send frame to PDMA */ 3526 val &= ~0xffff; 3527 3528 /* Enable RX checksum */ 3529 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 3530 3531 val |= config; 3532 3533 if (eth->netdev[id] && netdev_uses_dsa(eth->netdev[id])) 3534 val |= MTK_GDMA_SPECIAL_TAG; 3535 3536 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(id)); 3537 } 3538 3539 3540 static bool mtk_uses_dsa(struct net_device *dev) 3541 { 3542 #if IS_ENABLED(CONFIG_NET_DSA) 3543 return netdev_uses_dsa(dev) && 3544 dev->dsa_ptr->tag_ops->proto == DSA_TAG_PROTO_MTK; 3545 #else 3546 return false; 3547 #endif 3548 } 3549 3550 static int mtk_device_event(struct notifier_block *n, unsigned long event, void *ptr) 3551 { 3552 struct mtk_mac *mac = container_of(n, struct mtk_mac, device_notifier); 3553 struct mtk_eth *eth = mac->hw; 3554 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 3555 struct ethtool_link_ksettings s; 3556 struct net_device *ldev; 3557 struct list_head *iter; 3558 struct dsa_port *dp; 3559 3560 if (event != NETDEV_CHANGE) 3561 return NOTIFY_DONE; 3562 3563 netdev_for_each_lower_dev(dev, ldev, iter) { 3564 if (netdev_priv(ldev) == mac) 3565 goto found; 3566 } 3567 3568 return NOTIFY_DONE; 3569 3570 found: 3571 if (!dsa_user_dev_check(dev)) 3572 return NOTIFY_DONE; 3573 3574 if (__ethtool_get_link_ksettings(dev, &s)) 3575 return NOTIFY_DONE; 3576 3577 if (s.base.speed == 0 || s.base.speed == ((__u32)-1)) 3578 return NOTIFY_DONE; 3579 3580 dp = dsa_port_from_netdev(dev); 3581 if (dp->index >= MTK_QDMA_NUM_QUEUES) 3582 return NOTIFY_DONE; 3583 3584 if (mac->speed > 0 && mac->speed <= s.base.speed) 3585 s.base.speed = 0; 3586 3587 mtk_set_queue_speed(eth, dp->index + 3, s.base.speed); 3588 3589 return NOTIFY_DONE; 3590 } 3591 3592 static int mtk_max_gmac_mtu(struct mtk_eth *eth) 3593 { 3594 int i, max_mtu = ETH_DATA_LEN; 3595 3596 for (i = 0; i < ARRAY_SIZE(eth->netdev); i++) 3597 if (eth->netdev[i] && eth->netdev[i]->mtu > max_mtu) 3598 max_mtu = eth->netdev[i]->mtu; 3599 3600 return max_mtu; 3601 } 3602 3603 static int mtk_open(struct net_device *dev) 3604 { 3605 struct mtk_mac *mac = netdev_priv(dev); 3606 struct mtk_eth *eth = mac->hw; 3607 struct mtk_mac *target_mac; 3608 int i, err, ppe_num, mtu; 3609 3610 ppe_num = eth->soc->ppe_num; 3611 3612 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0); 3613 if (err) { 3614 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__, 3615 err); 3616 return err; 3617 } 3618 3619 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 3620 if (!refcount_read(ð->dma_refcnt)) { 3621 const struct mtk_soc_data *soc = eth->soc; 3622 u32 gdm_config; 3623 int i; 3624 3625 err = mtk_start_dma(eth); 3626 if (err) { 3627 phylink_disconnect_phy(mac->phylink); 3628 return err; 3629 } 3630 3631 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 3632 mtk_ppe_start(eth->ppe[i]); 3633 3634 for (i = 0; i < MTK_MAX_DEVS; i++) { 3635 if (!eth->netdev[i]) 3636 continue; 3637 3638 target_mac = netdev_priv(eth->netdev[i]); 3639 if (!soc->offload_version) { 3640 target_mac->ppe_idx = 0; 3641 gdm_config = MTK_GDMA_TO_PDMA; 3642 } else if (ppe_num >= 3 && target_mac->id == 2) { 3643 target_mac->ppe_idx = 2; 3644 gdm_config = soc->reg_map->gdma_to_ppe[2]; 3645 } else if (ppe_num >= 2 && target_mac->id == 1) { 3646 target_mac->ppe_idx = 1; 3647 gdm_config = soc->reg_map->gdma_to_ppe[1]; 3648 } else { 3649 target_mac->ppe_idx = 0; 3650 gdm_config = soc->reg_map->gdma_to_ppe[0]; 3651 } 3652 mtk_gdm_config(eth, target_mac->id, gdm_config); 3653 } 3654 3655 mtu = mtk_max_gmac_mtu(eth); 3656 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 3657 mtk_ppe_update_mtu(eth->ppe[i], mtu); 3658 3659 napi_enable(ð->tx_napi); 3660 napi_enable(ð->rx_napi); 3661 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 3662 mtk_rx_irq_enable(eth, soc->rx.irq_done_mask); 3663 refcount_set(ð->dma_refcnt, 1); 3664 } else { 3665 refcount_inc(ð->dma_refcnt); 3666 } 3667 3668 phylink_start(mac->phylink); 3669 netif_tx_start_all_queues(dev); 3670 3671 if (mtk_is_netsys_v2_or_greater(eth)) 3672 return 0; 3673 3674 if (mtk_uses_dsa(dev) && !eth->prog) { 3675 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { 3676 struct metadata_dst *md_dst = eth->dsa_meta[i]; 3677 3678 if (md_dst) 3679 continue; 3680 3681 md_dst = metadata_dst_alloc(0, METADATA_HW_PORT_MUX, 3682 GFP_KERNEL); 3683 if (!md_dst) 3684 return -ENOMEM; 3685 3686 md_dst->u.port_info.port_id = i; 3687 eth->dsa_meta[i] = md_dst; 3688 } 3689 } else { 3690 /* Hardware DSA untagging and VLAN RX offloading need to be 3691 * disabled if at least one MAC does not use DSA. 3692 */ 3693 u32 val = mtk_r32(eth, MTK_CDMP_IG_CTRL); 3694 3695 val &= ~MTK_CDMP_STAG_EN; 3696 mtk_w32(eth, val, MTK_CDMP_IG_CTRL); 3697 3698 mtk_w32(eth, 0, MTK_CDMP_EG_CTRL); 3699 } 3700 3701 return 0; 3702 } 3703 3704 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 3705 { 3706 u32 val; 3707 int i; 3708 3709 /* stop the dma engine */ 3710 spin_lock_bh(ð->page_lock); 3711 val = mtk_r32(eth, glo_cfg); 3712 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 3713 glo_cfg); 3714 spin_unlock_bh(ð->page_lock); 3715 3716 /* wait for dma stop */ 3717 for (i = 0; i < 10; i++) { 3718 val = mtk_r32(eth, glo_cfg); 3719 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 3720 msleep(20); 3721 continue; 3722 } 3723 break; 3724 } 3725 } 3726 3727 static int mtk_stop(struct net_device *dev) 3728 { 3729 struct mtk_mac *mac = netdev_priv(dev); 3730 struct mtk_eth *eth = mac->hw; 3731 int i; 3732 3733 phylink_stop(mac->phylink); 3734 3735 netif_tx_disable(dev); 3736 3737 phylink_disconnect_phy(mac->phylink); 3738 3739 /* only shutdown DMA if this is the last user */ 3740 if (!refcount_dec_and_test(ð->dma_refcnt)) 3741 return 0; 3742 3743 for (i = 0; i < MTK_MAX_DEVS; i++) 3744 mtk_gdm_config(eth, i, MTK_GDMA_DROP_ALL); 3745 3746 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3747 mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask); 3748 napi_disable(ð->tx_napi); 3749 napi_disable(ð->rx_napi); 3750 3751 cancel_work_sync(ð->rx_dim.work); 3752 cancel_work_sync(ð->tx_dim.work); 3753 3754 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3755 mtk_stop_dma(eth, eth->soc->reg_map->qdma.glo_cfg); 3756 mtk_stop_dma(eth, eth->soc->reg_map->pdma.glo_cfg); 3757 3758 mtk_dma_free(eth); 3759 3760 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 3761 mtk_ppe_stop(eth->ppe[i]); 3762 3763 return 0; 3764 } 3765 3766 static int mtk_xdp_setup(struct net_device *dev, struct bpf_prog *prog, 3767 struct netlink_ext_ack *extack) 3768 { 3769 struct mtk_mac *mac = netdev_priv(dev); 3770 struct mtk_eth *eth = mac->hw; 3771 struct bpf_prog *old_prog; 3772 bool need_update; 3773 3774 if (eth->hwlro) { 3775 NL_SET_ERR_MSG_MOD(extack, "XDP not supported with HWLRO"); 3776 return -EOPNOTSUPP; 3777 } 3778 3779 if (dev->mtu > MTK_PP_MAX_BUF_SIZE) { 3780 NL_SET_ERR_MSG_MOD(extack, "MTU too large for XDP"); 3781 return -EOPNOTSUPP; 3782 } 3783 3784 need_update = !!eth->prog != !!prog; 3785 if (netif_running(dev) && need_update) 3786 mtk_stop(dev); 3787 3788 old_prog = rcu_replace_pointer(eth->prog, prog, lockdep_rtnl_is_held()); 3789 3790 if (netif_running(dev) && need_update) { 3791 int err; 3792 3793 err = mtk_open(dev); 3794 if (err) { 3795 rcu_assign_pointer(eth->prog, old_prog); 3796 3797 return err; 3798 } 3799 } 3800 3801 if (old_prog) 3802 bpf_prog_put(old_prog); 3803 3804 return 0; 3805 } 3806 3807 static int mtk_xdp(struct net_device *dev, struct netdev_bpf *xdp) 3808 { 3809 switch (xdp->command) { 3810 case XDP_SETUP_PROG: 3811 return mtk_xdp_setup(dev, xdp->prog, xdp->extack); 3812 default: 3813 return -EINVAL; 3814 } 3815 } 3816 3817 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 3818 { 3819 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 3820 reset_bits, 3821 reset_bits); 3822 3823 usleep_range(1000, 1100); 3824 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 3825 reset_bits, 3826 ~reset_bits); 3827 mdelay(10); 3828 } 3829 3830 static void mtk_clk_disable(struct mtk_eth *eth) 3831 { 3832 int clk; 3833 3834 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) 3835 clk_disable_unprepare(eth->clks[clk]); 3836 } 3837 3838 static int mtk_clk_enable(struct mtk_eth *eth) 3839 { 3840 int clk, ret; 3841 3842 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { 3843 ret = clk_prepare_enable(eth->clks[clk]); 3844 if (ret) 3845 goto err_disable_clks; 3846 } 3847 3848 return 0; 3849 3850 err_disable_clks: 3851 while (--clk >= 0) 3852 clk_disable_unprepare(eth->clks[clk]); 3853 3854 return ret; 3855 } 3856 3857 static void mtk_dim_rx(struct work_struct *work) 3858 { 3859 struct dim *dim = container_of(work, struct dim, work); 3860 struct mtk_eth *eth = container_of(dim, struct mtk_eth, rx_dim); 3861 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3862 struct dim_cq_moder cur_profile; 3863 u32 val, cur; 3864 3865 cur_profile = net_dim_get_rx_moderation(eth->rx_dim.mode, 3866 dim->profile_ix); 3867 spin_lock_bh(ð->dim_lock); 3868 3869 val = mtk_r32(eth, reg_map->pdma.delay_irq); 3870 val &= MTK_PDMA_DELAY_TX_MASK; 3871 val |= MTK_PDMA_DELAY_RX_EN; 3872 3873 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 3874 val |= cur << MTK_PDMA_DELAY_RX_PTIME_SHIFT; 3875 3876 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 3877 val |= cur << MTK_PDMA_DELAY_RX_PINT_SHIFT; 3878 3879 mtk_w32(eth, val, reg_map->pdma.delay_irq); 3880 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3881 mtk_w32(eth, val, reg_map->qdma.delay_irq); 3882 3883 spin_unlock_bh(ð->dim_lock); 3884 3885 dim->state = DIM_START_MEASURE; 3886 } 3887 3888 static void mtk_dim_tx(struct work_struct *work) 3889 { 3890 struct dim *dim = container_of(work, struct dim, work); 3891 struct mtk_eth *eth = container_of(dim, struct mtk_eth, tx_dim); 3892 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3893 struct dim_cq_moder cur_profile; 3894 u32 val, cur; 3895 3896 cur_profile = net_dim_get_tx_moderation(eth->tx_dim.mode, 3897 dim->profile_ix); 3898 spin_lock_bh(ð->dim_lock); 3899 3900 val = mtk_r32(eth, reg_map->pdma.delay_irq); 3901 val &= MTK_PDMA_DELAY_RX_MASK; 3902 val |= MTK_PDMA_DELAY_TX_EN; 3903 3904 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 3905 val |= cur << MTK_PDMA_DELAY_TX_PTIME_SHIFT; 3906 3907 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 3908 val |= cur << MTK_PDMA_DELAY_TX_PINT_SHIFT; 3909 3910 mtk_w32(eth, val, reg_map->pdma.delay_irq); 3911 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3912 mtk_w32(eth, val, reg_map->qdma.delay_irq); 3913 3914 spin_unlock_bh(ð->dim_lock); 3915 3916 dim->state = DIM_START_MEASURE; 3917 } 3918 3919 static void mtk_set_mcr_max_rx(struct mtk_mac *mac, u32 val) 3920 { 3921 struct mtk_eth *eth = mac->hw; 3922 u32 mcr_cur, mcr_new; 3923 3924 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3925 return; 3926 3927 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 3928 mcr_new = mcr_cur & ~MAC_MCR_MAX_RX_MASK; 3929 3930 if (val <= 1518) 3931 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1518); 3932 else if (val <= 1536) 3933 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1536); 3934 else if (val <= 1552) 3935 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1552); 3936 else 3937 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_2048); 3938 3939 if (mcr_new != mcr_cur) 3940 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 3941 } 3942 3943 static void mtk_hw_reset(struct mtk_eth *eth) 3944 { 3945 u32 val; 3946 3947 if (mtk_is_netsys_v2_or_greater(eth)) 3948 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); 3949 3950 if (mtk_is_netsys_v3_or_greater(eth)) { 3951 val = RSTCTRL_PPE0_V3; 3952 3953 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3954 val |= RSTCTRL_PPE1_V3; 3955 3956 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) 3957 val |= RSTCTRL_PPE2; 3958 3959 val |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2; 3960 } else if (mtk_is_netsys_v2_or_greater(eth)) { 3961 val = RSTCTRL_PPE0_V2; 3962 3963 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3964 val |= RSTCTRL_PPE1; 3965 } else { 3966 val = RSTCTRL_PPE0; 3967 } 3968 3969 ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val); 3970 3971 if (mtk_is_netsys_v3_or_greater(eth)) 3972 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 3973 0x6f8ff); 3974 else if (mtk_is_netsys_v2_or_greater(eth)) 3975 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 3976 0x3ffffff); 3977 } 3978 3979 static u32 mtk_hw_reset_read(struct mtk_eth *eth) 3980 { 3981 u32 val; 3982 3983 regmap_read(eth->ethsys, ETHSYS_RSTCTRL, &val); 3984 return val; 3985 } 3986 3987 static void mtk_hw_warm_reset(struct mtk_eth *eth) 3988 { 3989 u32 rst_mask, val; 3990 3991 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, RSTCTRL_FE, 3992 RSTCTRL_FE); 3993 if (readx_poll_timeout_atomic(mtk_hw_reset_read, eth, val, 3994 val & RSTCTRL_FE, 1, 1000)) { 3995 dev_err(eth->dev, "warm reset failed\n"); 3996 mtk_hw_reset(eth); 3997 return; 3998 } 3999 4000 if (mtk_is_netsys_v3_or_greater(eth)) { 4001 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V3; 4002 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 4003 rst_mask |= RSTCTRL_PPE1_V3; 4004 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) 4005 rst_mask |= RSTCTRL_PPE2; 4006 4007 rst_mask |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2; 4008 } else if (mtk_is_netsys_v2_or_greater(eth)) { 4009 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2; 4010 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 4011 rst_mask |= RSTCTRL_PPE1; 4012 } else { 4013 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0; 4014 } 4015 4016 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, rst_mask); 4017 4018 udelay(1); 4019 val = mtk_hw_reset_read(eth); 4020 if (!(val & rst_mask)) 4021 dev_err(eth->dev, "warm reset stage0 failed %08x (%08x)\n", 4022 val, rst_mask); 4023 4024 rst_mask |= RSTCTRL_FE; 4025 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, ~rst_mask); 4026 4027 udelay(1); 4028 val = mtk_hw_reset_read(eth); 4029 if (val & rst_mask) 4030 dev_err(eth->dev, "warm reset stage1 failed %08x (%08x)\n", 4031 val, rst_mask); 4032 } 4033 4034 static bool mtk_hw_check_dma_hang(struct mtk_eth *eth) 4035 { 4036 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 4037 bool gmac1_tx, gmac2_tx, gdm1_tx, gdm2_tx; 4038 bool oq_hang, cdm1_busy, adma_busy; 4039 bool wtx_busy, cdm_full, oq_free; 4040 u32 wdidx, val, gdm1_fc, gdm2_fc; 4041 bool qfsm_hang, qfwd_hang; 4042 bool ret = false; 4043 4044 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 4045 return false; 4046 4047 /* WDMA sanity checks */ 4048 wdidx = mtk_r32(eth, reg_map->wdma_base[0] + 0xc); 4049 4050 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x204); 4051 wtx_busy = FIELD_GET(MTK_TX_DMA_BUSY, val); 4052 4053 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x230); 4054 cdm_full = !FIELD_GET(MTK_CDM_TXFIFO_RDY, val); 4055 4056 oq_free = (!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(24, 16)) && 4057 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x4) & GENMASK(8, 0)) && 4058 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x10) & GENMASK(24, 16))); 4059 4060 if (wdidx == eth->reset.wdidx && wtx_busy && cdm_full && oq_free) { 4061 if (++eth->reset.wdma_hang_count > 2) { 4062 eth->reset.wdma_hang_count = 0; 4063 ret = true; 4064 } 4065 goto out; 4066 } 4067 4068 /* QDMA sanity checks */ 4069 qfsm_hang = !!mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x234); 4070 qfwd_hang = !mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x308); 4071 4072 gdm1_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM1_FSM)) > 0; 4073 gdm2_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM2_FSM)) > 0; 4074 gmac1_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(0))) != 1; 4075 gmac2_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(1))) != 1; 4076 gdm1_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x24); 4077 gdm2_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x64); 4078 4079 if (qfsm_hang && qfwd_hang && 4080 ((gdm1_tx && gmac1_tx && gdm1_fc < 1) || 4081 (gdm2_tx && gmac2_tx && gdm2_fc < 1))) { 4082 if (++eth->reset.qdma_hang_count > 2) { 4083 eth->reset.qdma_hang_count = 0; 4084 ret = true; 4085 } 4086 goto out; 4087 } 4088 4089 /* ADMA sanity checks */ 4090 oq_hang = !!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(8, 0)); 4091 cdm1_busy = !!(mtk_r32(eth, MTK_FE_CDM1_FSM) & GENMASK(31, 16)); 4092 adma_busy = !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & GENMASK(4, 0)) && 4093 !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & BIT(6)); 4094 4095 if (oq_hang && cdm1_busy && adma_busy) { 4096 if (++eth->reset.adma_hang_count > 2) { 4097 eth->reset.adma_hang_count = 0; 4098 ret = true; 4099 } 4100 goto out; 4101 } 4102 4103 eth->reset.wdma_hang_count = 0; 4104 eth->reset.qdma_hang_count = 0; 4105 eth->reset.adma_hang_count = 0; 4106 out: 4107 eth->reset.wdidx = wdidx; 4108 4109 return ret; 4110 } 4111 4112 static void mtk_hw_reset_monitor_work(struct work_struct *work) 4113 { 4114 struct delayed_work *del_work = to_delayed_work(work); 4115 struct mtk_eth *eth = container_of(del_work, struct mtk_eth, 4116 reset.monitor_work); 4117 4118 if (test_bit(MTK_RESETTING, ð->state)) 4119 goto out; 4120 4121 /* DMA stuck checks */ 4122 if (mtk_hw_check_dma_hang(eth)) 4123 schedule_work(ð->pending_work); 4124 4125 out: 4126 schedule_delayed_work(ð->reset.monitor_work, 4127 MTK_DMA_MONITOR_TIMEOUT); 4128 } 4129 4130 static int mtk_hw_init(struct mtk_eth *eth, bool reset) 4131 { 4132 u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA | 4133 ETHSYS_DMA_AG_MAP_PPE; 4134 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 4135 int i, val, ret; 4136 4137 if (!reset && test_and_set_bit(MTK_HW_INIT, ð->state)) 4138 return 0; 4139 4140 if (!reset) { 4141 pm_runtime_enable(eth->dev); 4142 pm_runtime_get_sync(eth->dev); 4143 4144 ret = mtk_clk_enable(eth); 4145 if (ret) 4146 goto err_disable_pm; 4147 } 4148 4149 if (eth->ethsys) 4150 regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask, 4151 of_dma_is_coherent(eth->dma_dev->of_node) * dma_mask); 4152 4153 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 4154 ret = device_reset(eth->dev); 4155 if (ret) { 4156 dev_err(eth->dev, "MAC reset failed!\n"); 4157 goto err_disable_pm; 4158 } 4159 4160 /* set interrupt delays based on current Net DIM sample */ 4161 mtk_dim_rx(ð->rx_dim.work); 4162 mtk_dim_tx(ð->tx_dim.work); 4163 4164 /* disable delay and normal interrupt */ 4165 mtk_tx_irq_disable(eth, ~0); 4166 mtk_rx_irq_disable(eth, ~0); 4167 4168 return 0; 4169 } 4170 4171 msleep(100); 4172 4173 if (reset) 4174 mtk_hw_warm_reset(eth); 4175 else 4176 mtk_hw_reset(eth); 4177 4178 /* No MT7628/88 support yet */ 4179 if (reset && !MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 4180 mtk_mdio_config(eth); 4181 4182 if (mtk_is_netsys_v3_or_greater(eth)) { 4183 /* Set FE to PDMAv2 if necessary */ 4184 val = mtk_r32(eth, MTK_FE_GLO_MISC); 4185 mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC); 4186 } 4187 4188 if (eth->pctl) { 4189 /* Set GE2 driving and slew rate */ 4190 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 4191 4192 /* set GE2 TDSEL */ 4193 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 4194 4195 /* set GE2 TUNE */ 4196 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 4197 } 4198 4199 /* Set linkdown as the default for each GMAC. Its own MCR would be set 4200 * up with the more appropriate value when mtk_mac_config call is being 4201 * invoked. 4202 */ 4203 for (i = 0; i < MTK_MAX_DEVS; i++) { 4204 struct net_device *dev = eth->netdev[i]; 4205 4206 if (!dev) 4207 continue; 4208 4209 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); 4210 mtk_set_mcr_max_rx(netdev_priv(dev), 4211 dev->mtu + MTK_RX_ETH_HLEN); 4212 } 4213 4214 /* Indicates CDM to parse the MTK special tag from CPU 4215 * which also is working out for untag packets. 4216 */ 4217 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 4218 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); 4219 if (mtk_is_netsys_v1(eth)) { 4220 val = mtk_r32(eth, MTK_CDMP_IG_CTRL); 4221 mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL); 4222 4223 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 4224 } 4225 4226 /* set interrupt delays based on current Net DIM sample */ 4227 mtk_dim_rx(ð->rx_dim.work); 4228 mtk_dim_tx(ð->tx_dim.work); 4229 4230 /* disable delay and normal interrupt */ 4231 mtk_tx_irq_disable(eth, ~0); 4232 mtk_rx_irq_disable(eth, ~0); 4233 4234 /* FE int grouping */ 4235 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp); 4236 mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->pdma.int_grp + 4); 4237 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp); 4238 mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->qdma.int_grp + 4); 4239 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 4240 4241 if (mtk_is_netsys_v3_or_greater(eth)) { 4242 /* PSE dummy page mechanism */ 4243 mtk_w32(eth, PSE_DUMMY_WORK_GDM(1) | PSE_DUMMY_WORK_GDM(2) | 4244 PSE_DUMMY_WORK_GDM(3) | DUMMY_PAGE_THR, PSE_DUMY_REQ); 4245 4246 /* PSE free buffer drop threshold */ 4247 mtk_w32(eth, 0x00600009, PSE_IQ_REV(8)); 4248 4249 /* PSE should not drop port8, port9 and port13 packets from 4250 * WDMA Tx 4251 */ 4252 mtk_w32(eth, 0x00002300, PSE_DROP_CFG); 4253 4254 /* PSE should drop packets to port8, port9 and port13 on WDMA Rx 4255 * ring full 4256 */ 4257 mtk_w32(eth, 0x00002300, PSE_PPE_DROP(0)); 4258 mtk_w32(eth, 0x00002300, PSE_PPE_DROP(1)); 4259 mtk_w32(eth, 0x00002300, PSE_PPE_DROP(2)); 4260 4261 /* GDM and CDM Threshold */ 4262 mtk_w32(eth, 0x08000707, MTK_CDMW0_THRES); 4263 mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES); 4264 4265 /* Disable GDM1 RX CRC stripping */ 4266 mtk_m32(eth, MTK_GDMA_STRP_CRC, 0, MTK_GDMA_FWD_CFG(0)); 4267 4268 /* PSE GDM3 MIB counter has incorrect hw default values, 4269 * so the driver ought to read clear the values beforehand 4270 * in case ethtool retrieve wrong mib values. 4271 */ 4272 for (i = 0; i < 0x80; i += 0x4) 4273 mtk_r32(eth, reg_map->gdm1_cnt + 0x100 + i); 4274 } else if (!mtk_is_netsys_v1(eth)) { 4275 /* PSE should not drop port8 and port9 packets from WDMA Tx */ 4276 mtk_w32(eth, 0x00000300, PSE_DROP_CFG); 4277 4278 /* PSE should drop packets to port 8/9 on WDMA Rx ring full */ 4279 mtk_w32(eth, 0x00000300, PSE_PPE_DROP(0)); 4280 4281 /* PSE Free Queue Flow Control */ 4282 mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2); 4283 4284 /* PSE config input queue threshold */ 4285 mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1)); 4286 mtk_w32(eth, 0x01ff001a, PSE_IQ_REV(2)); 4287 mtk_w32(eth, 0x000e01ff, PSE_IQ_REV(3)); 4288 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(4)); 4289 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(5)); 4290 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(6)); 4291 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(7)); 4292 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(8)); 4293 4294 /* PSE config output queue threshold */ 4295 mtk_w32(eth, 0x000f000a, PSE_OQ_TH(1)); 4296 mtk_w32(eth, 0x001a000f, PSE_OQ_TH(2)); 4297 mtk_w32(eth, 0x000f001a, PSE_OQ_TH(3)); 4298 mtk_w32(eth, 0x01ff000f, PSE_OQ_TH(4)); 4299 mtk_w32(eth, 0x000f000f, PSE_OQ_TH(5)); 4300 mtk_w32(eth, 0x0006000f, PSE_OQ_TH(6)); 4301 mtk_w32(eth, 0x00060006, PSE_OQ_TH(7)); 4302 mtk_w32(eth, 0x00060006, PSE_OQ_TH(8)); 4303 4304 /* GDM and CDM Threshold */ 4305 mtk_w32(eth, 0x00000004, MTK_GDM2_THRES); 4306 mtk_w32(eth, 0x00000004, MTK_CDMW0_THRES); 4307 mtk_w32(eth, 0x00000004, MTK_CDMW1_THRES); 4308 mtk_w32(eth, 0x00000004, MTK_CDME0_THRES); 4309 mtk_w32(eth, 0x00000004, MTK_CDME1_THRES); 4310 mtk_w32(eth, 0x00000004, MTK_CDMM_THRES); 4311 } 4312 4313 return 0; 4314 4315 err_disable_pm: 4316 if (!reset) { 4317 pm_runtime_put_sync(eth->dev); 4318 pm_runtime_disable(eth->dev); 4319 } 4320 4321 return ret; 4322 } 4323 4324 static int mtk_hw_deinit(struct mtk_eth *eth) 4325 { 4326 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) 4327 return 0; 4328 4329 mtk_clk_disable(eth); 4330 4331 pm_runtime_put_sync(eth->dev); 4332 pm_runtime_disable(eth->dev); 4333 4334 return 0; 4335 } 4336 4337 static void mtk_uninit(struct net_device *dev) 4338 { 4339 struct mtk_mac *mac = netdev_priv(dev); 4340 struct mtk_eth *eth = mac->hw; 4341 4342 phylink_disconnect_phy(mac->phylink); 4343 mtk_tx_irq_disable(eth, ~0); 4344 mtk_rx_irq_disable(eth, ~0); 4345 } 4346 4347 static int mtk_change_mtu(struct net_device *dev, int new_mtu) 4348 { 4349 int length = new_mtu + MTK_RX_ETH_HLEN; 4350 struct mtk_mac *mac = netdev_priv(dev); 4351 struct mtk_eth *eth = mac->hw; 4352 int max_mtu, i; 4353 4354 if (rcu_access_pointer(eth->prog) && 4355 length > MTK_PP_MAX_BUF_SIZE) { 4356 netdev_err(dev, "Invalid MTU for XDP mode\n"); 4357 return -EINVAL; 4358 } 4359 4360 mtk_set_mcr_max_rx(mac, length); 4361 WRITE_ONCE(dev->mtu, new_mtu); 4362 4363 max_mtu = mtk_max_gmac_mtu(eth); 4364 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 4365 mtk_ppe_update_mtu(eth->ppe[i], max_mtu); 4366 4367 return 0; 4368 } 4369 4370 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 4371 { 4372 struct mtk_mac *mac = netdev_priv(dev); 4373 4374 switch (cmd) { 4375 case SIOCGMIIPHY: 4376 case SIOCGMIIREG: 4377 case SIOCSMIIREG: 4378 return phylink_mii_ioctl(mac->phylink, ifr, cmd); 4379 default: 4380 break; 4381 } 4382 4383 return -EOPNOTSUPP; 4384 } 4385 4386 static void mtk_prepare_for_reset(struct mtk_eth *eth) 4387 { 4388 u32 val; 4389 int i; 4390 4391 /* set FE PPE ports link down */ 4392 for (i = MTK_GMAC1_ID; 4393 i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID); 4394 i += 2) { 4395 val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) | MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT); 4396 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 4397 val |= MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT); 4398 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) 4399 val |= MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT); 4400 mtk_w32(eth, val, MTK_FE_GLO_CFG(i)); 4401 } 4402 4403 /* adjust PPE configurations to prepare for reset */ 4404 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 4405 mtk_ppe_prepare_reset(eth->ppe[i]); 4406 4407 /* disable NETSYS interrupts */ 4408 mtk_w32(eth, 0, MTK_FE_INT_ENABLE); 4409 4410 /* force link down GMAC */ 4411 for (i = 0; i < 2; i++) { 4412 val = mtk_r32(eth, MTK_MAC_MCR(i)) & ~MAC_MCR_FORCE_LINK; 4413 mtk_w32(eth, val, MTK_MAC_MCR(i)); 4414 } 4415 } 4416 4417 static void mtk_pending_work(struct work_struct *work) 4418 { 4419 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 4420 unsigned long restart = 0; 4421 u32 val; 4422 int i; 4423 4424 rtnl_lock(); 4425 set_bit(MTK_RESETTING, ð->state); 4426 4427 mtk_prepare_for_reset(eth); 4428 mtk_wed_fe_reset(); 4429 /* Run again reset preliminary configuration in order to avoid any 4430 * possible race during FE reset since it can run releasing RTNL lock. 4431 */ 4432 mtk_prepare_for_reset(eth); 4433 4434 /* stop all devices to make sure that dma is properly shut down */ 4435 for (i = 0; i < MTK_MAX_DEVS; i++) { 4436 if (!eth->netdev[i] || !netif_running(eth->netdev[i])) 4437 continue; 4438 4439 mtk_stop(eth->netdev[i]); 4440 __set_bit(i, &restart); 4441 } 4442 4443 usleep_range(15000, 16000); 4444 4445 if (eth->dev->pins) 4446 pinctrl_select_state(eth->dev->pins->p, 4447 eth->dev->pins->default_state); 4448 mtk_hw_init(eth, true); 4449 4450 /* restart DMA and enable IRQs */ 4451 for (i = 0; i < MTK_MAX_DEVS; i++) { 4452 if (!eth->netdev[i] || !test_bit(i, &restart)) 4453 continue; 4454 4455 if (mtk_open(eth->netdev[i])) { 4456 netif_alert(eth, ifup, eth->netdev[i], 4457 "Driver up/down cycle failed\n"); 4458 dev_close(eth->netdev[i]); 4459 } 4460 } 4461 4462 /* set FE PPE ports link up */ 4463 for (i = MTK_GMAC1_ID; 4464 i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID); 4465 i += 2) { 4466 val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) & ~MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT); 4467 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 4468 val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT); 4469 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) 4470 val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT); 4471 4472 mtk_w32(eth, val, MTK_FE_GLO_CFG(i)); 4473 } 4474 4475 clear_bit(MTK_RESETTING, ð->state); 4476 4477 mtk_wed_fe_reset_complete(); 4478 4479 rtnl_unlock(); 4480 } 4481 4482 static int mtk_free_dev(struct mtk_eth *eth) 4483 { 4484 int i; 4485 4486 for (i = 0; i < MTK_MAX_DEVS; i++) { 4487 if (!eth->netdev[i]) 4488 continue; 4489 free_netdev(eth->netdev[i]); 4490 } 4491 4492 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { 4493 if (!eth->dsa_meta[i]) 4494 break; 4495 dst_release(ð->dsa_meta[i]->dst); 4496 } 4497 4498 return 0; 4499 } 4500 4501 static int mtk_unreg_dev(struct mtk_eth *eth) 4502 { 4503 int i; 4504 4505 for (i = 0; i < MTK_MAX_DEVS; i++) { 4506 struct mtk_mac *mac; 4507 if (!eth->netdev[i]) 4508 continue; 4509 mac = netdev_priv(eth->netdev[i]); 4510 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 4511 unregister_netdevice_notifier(&mac->device_notifier); 4512 unregister_netdev(eth->netdev[i]); 4513 } 4514 4515 return 0; 4516 } 4517 4518 static void mtk_sgmii_destroy(struct mtk_eth *eth) 4519 { 4520 int i; 4521 4522 for (i = 0; i < MTK_MAX_DEVS; i++) 4523 mtk_pcs_lynxi_destroy(eth->sgmii_pcs[i]); 4524 } 4525 4526 static int mtk_cleanup(struct mtk_eth *eth) 4527 { 4528 mtk_sgmii_destroy(eth); 4529 mtk_unreg_dev(eth); 4530 mtk_free_dev(eth); 4531 cancel_work_sync(ð->pending_work); 4532 cancel_delayed_work_sync(ð->reset.monitor_work); 4533 4534 return 0; 4535 } 4536 4537 static int mtk_get_link_ksettings(struct net_device *ndev, 4538 struct ethtool_link_ksettings *cmd) 4539 { 4540 struct mtk_mac *mac = netdev_priv(ndev); 4541 4542 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4543 return -EBUSY; 4544 4545 return phylink_ethtool_ksettings_get(mac->phylink, cmd); 4546 } 4547 4548 static int mtk_set_link_ksettings(struct net_device *ndev, 4549 const struct ethtool_link_ksettings *cmd) 4550 { 4551 struct mtk_mac *mac = netdev_priv(ndev); 4552 4553 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4554 return -EBUSY; 4555 4556 return phylink_ethtool_ksettings_set(mac->phylink, cmd); 4557 } 4558 4559 static void mtk_get_drvinfo(struct net_device *dev, 4560 struct ethtool_drvinfo *info) 4561 { 4562 struct mtk_mac *mac = netdev_priv(dev); 4563 4564 strscpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 4565 strscpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 4566 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 4567 } 4568 4569 static u32 mtk_get_msglevel(struct net_device *dev) 4570 { 4571 struct mtk_mac *mac = netdev_priv(dev); 4572 4573 return mac->hw->msg_enable; 4574 } 4575 4576 static void mtk_set_msglevel(struct net_device *dev, u32 value) 4577 { 4578 struct mtk_mac *mac = netdev_priv(dev); 4579 4580 mac->hw->msg_enable = value; 4581 } 4582 4583 static int mtk_nway_reset(struct net_device *dev) 4584 { 4585 struct mtk_mac *mac = netdev_priv(dev); 4586 4587 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4588 return -EBUSY; 4589 4590 if (!mac->phylink) 4591 return -ENOTSUPP; 4592 4593 return phylink_ethtool_nway_reset(mac->phylink); 4594 } 4595 4596 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 4597 { 4598 int i; 4599 4600 switch (stringset) { 4601 case ETH_SS_STATS: { 4602 struct mtk_mac *mac = netdev_priv(dev); 4603 4604 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 4605 ethtool_puts(&data, mtk_ethtool_stats[i].str); 4606 if (mtk_page_pool_enabled(mac->hw)) 4607 page_pool_ethtool_stats_get_strings(data); 4608 break; 4609 } 4610 default: 4611 break; 4612 } 4613 } 4614 4615 static int mtk_get_sset_count(struct net_device *dev, int sset) 4616 { 4617 switch (sset) { 4618 case ETH_SS_STATS: { 4619 int count = ARRAY_SIZE(mtk_ethtool_stats); 4620 struct mtk_mac *mac = netdev_priv(dev); 4621 4622 if (mtk_page_pool_enabled(mac->hw)) 4623 count += page_pool_ethtool_stats_get_count(); 4624 return count; 4625 } 4626 default: 4627 return -EOPNOTSUPP; 4628 } 4629 } 4630 4631 static void mtk_ethtool_pp_stats(struct mtk_eth *eth, u64 *data) 4632 { 4633 struct page_pool_stats stats = {}; 4634 int i; 4635 4636 for (i = 0; i < ARRAY_SIZE(eth->rx_ring); i++) { 4637 struct mtk_rx_ring *ring = ð->rx_ring[i]; 4638 4639 if (!ring->page_pool) 4640 continue; 4641 4642 page_pool_get_stats(ring->page_pool, &stats); 4643 } 4644 page_pool_ethtool_stats_get(data, &stats); 4645 } 4646 4647 static void mtk_get_ethtool_stats(struct net_device *dev, 4648 struct ethtool_stats *stats, u64 *data) 4649 { 4650 struct mtk_mac *mac = netdev_priv(dev); 4651 struct mtk_hw_stats *hwstats = mac->hw_stats; 4652 u64 *data_src, *data_dst; 4653 unsigned int start; 4654 int i; 4655 4656 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4657 return; 4658 4659 if (netif_running(dev) && netif_device_present(dev)) { 4660 if (spin_trylock_bh(&hwstats->stats_lock)) { 4661 mtk_stats_update_mac(mac); 4662 spin_unlock_bh(&hwstats->stats_lock); 4663 } 4664 } 4665 4666 data_src = (u64 *)hwstats; 4667 4668 do { 4669 data_dst = data; 4670 start = u64_stats_fetch_begin(&hwstats->syncp); 4671 4672 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 4673 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 4674 if (mtk_page_pool_enabled(mac->hw)) 4675 mtk_ethtool_pp_stats(mac->hw, data_dst); 4676 } while (u64_stats_fetch_retry(&hwstats->syncp, start)); 4677 } 4678 4679 static u32 mtk_get_rx_ring_count(struct net_device *dev) 4680 { 4681 if (dev->hw_features & NETIF_F_LRO) 4682 return MTK_MAX_RX_RING_NUM; 4683 4684 return 0; 4685 } 4686 4687 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 4688 u32 *rule_locs) 4689 { 4690 int ret = -EOPNOTSUPP; 4691 4692 switch (cmd->cmd) { 4693 case ETHTOOL_GRXCLSRLCNT: 4694 if (dev->hw_features & NETIF_F_LRO) { 4695 struct mtk_mac *mac = netdev_priv(dev); 4696 4697 cmd->rule_cnt = mac->hwlro_ip_cnt; 4698 ret = 0; 4699 } 4700 break; 4701 case ETHTOOL_GRXCLSRULE: 4702 if (dev->hw_features & NETIF_F_LRO) 4703 ret = mtk_hwlro_get_fdir_entry(dev, cmd); 4704 break; 4705 case ETHTOOL_GRXCLSRLALL: 4706 if (dev->hw_features & NETIF_F_LRO) 4707 ret = mtk_hwlro_get_fdir_all(dev, cmd, 4708 rule_locs); 4709 break; 4710 default: 4711 break; 4712 } 4713 4714 return ret; 4715 } 4716 4717 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 4718 { 4719 int ret = -EOPNOTSUPP; 4720 4721 switch (cmd->cmd) { 4722 case ETHTOOL_SRXCLSRLINS: 4723 if (dev->hw_features & NETIF_F_LRO) 4724 ret = mtk_hwlro_add_ipaddr(dev, cmd); 4725 break; 4726 case ETHTOOL_SRXCLSRLDEL: 4727 if (dev->hw_features & NETIF_F_LRO) 4728 ret = mtk_hwlro_del_ipaddr(dev, cmd); 4729 break; 4730 default: 4731 break; 4732 } 4733 4734 return ret; 4735 } 4736 4737 static void mtk_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *pause) 4738 { 4739 struct mtk_mac *mac = netdev_priv(dev); 4740 4741 phylink_ethtool_get_pauseparam(mac->phylink, pause); 4742 } 4743 4744 static int mtk_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *pause) 4745 { 4746 struct mtk_mac *mac = netdev_priv(dev); 4747 4748 return phylink_ethtool_set_pauseparam(mac->phylink, pause); 4749 } 4750 4751 static int mtk_get_eee(struct net_device *dev, struct ethtool_keee *eee) 4752 { 4753 struct mtk_mac *mac = netdev_priv(dev); 4754 4755 return phylink_ethtool_get_eee(mac->phylink, eee); 4756 } 4757 4758 static int mtk_set_eee(struct net_device *dev, struct ethtool_keee *eee) 4759 { 4760 struct mtk_mac *mac = netdev_priv(dev); 4761 4762 return phylink_ethtool_set_eee(mac->phylink, eee); 4763 } 4764 4765 static u16 mtk_select_queue(struct net_device *dev, struct sk_buff *skb, 4766 struct net_device *sb_dev) 4767 { 4768 struct mtk_mac *mac = netdev_priv(dev); 4769 unsigned int queue = 0; 4770 4771 if (netdev_uses_dsa(dev)) 4772 queue = skb_get_queue_mapping(skb) + 3; 4773 else 4774 queue = mac->id; 4775 4776 if (queue >= dev->num_tx_queues) 4777 queue = 0; 4778 4779 return queue; 4780 } 4781 4782 static const struct ethtool_ops mtk_ethtool_ops = { 4783 .get_link_ksettings = mtk_get_link_ksettings, 4784 .set_link_ksettings = mtk_set_link_ksettings, 4785 .get_drvinfo = mtk_get_drvinfo, 4786 .get_msglevel = mtk_get_msglevel, 4787 .set_msglevel = mtk_set_msglevel, 4788 .nway_reset = mtk_nway_reset, 4789 .get_link = ethtool_op_get_link, 4790 .get_strings = mtk_get_strings, 4791 .get_sset_count = mtk_get_sset_count, 4792 .get_ethtool_stats = mtk_get_ethtool_stats, 4793 .get_pauseparam = mtk_get_pauseparam, 4794 .set_pauseparam = mtk_set_pauseparam, 4795 .get_rxnfc = mtk_get_rxnfc, 4796 .set_rxnfc = mtk_set_rxnfc, 4797 .get_rx_ring_count = mtk_get_rx_ring_count, 4798 .get_eee = mtk_get_eee, 4799 .set_eee = mtk_set_eee, 4800 }; 4801 4802 static const struct net_device_ops mtk_netdev_ops = { 4803 .ndo_uninit = mtk_uninit, 4804 .ndo_open = mtk_open, 4805 .ndo_stop = mtk_stop, 4806 .ndo_start_xmit = mtk_start_xmit, 4807 .ndo_set_mac_address = mtk_set_mac_address, 4808 .ndo_validate_addr = eth_validate_addr, 4809 .ndo_eth_ioctl = mtk_do_ioctl, 4810 .ndo_change_mtu = mtk_change_mtu, 4811 .ndo_tx_timeout = mtk_tx_timeout, 4812 .ndo_get_stats64 = mtk_get_stats64, 4813 .ndo_fix_features = mtk_fix_features, 4814 .ndo_set_features = mtk_set_features, 4815 #ifdef CONFIG_NET_POLL_CONTROLLER 4816 .ndo_poll_controller = mtk_poll_controller, 4817 #endif 4818 .ndo_setup_tc = mtk_eth_setup_tc, 4819 .ndo_bpf = mtk_xdp, 4820 .ndo_xdp_xmit = mtk_xdp_xmit, 4821 .ndo_select_queue = mtk_select_queue, 4822 }; 4823 4824 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 4825 { 4826 const struct phylink_mac_ops *mac_ops = &mtk_phylink_ops; 4827 const __be32 *_id = of_get_property(np, "reg", NULL); 4828 phy_interface_t phy_mode; 4829 struct phylink *phylink; 4830 struct mtk_mac *mac; 4831 int id, err, i; 4832 int txqs = 1; 4833 u32 val; 4834 4835 if (!_id) { 4836 dev_err(eth->dev, "missing mac id\n"); 4837 return -EINVAL; 4838 } 4839 4840 id = be32_to_cpup(_id); 4841 if (id >= MTK_MAX_DEVS) { 4842 dev_err(eth->dev, "%d is not a valid mac id\n", id); 4843 return -EINVAL; 4844 } 4845 4846 if (eth->netdev[id]) { 4847 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 4848 return -EINVAL; 4849 } 4850 4851 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 4852 txqs = MTK_QDMA_NUM_QUEUES; 4853 4854 eth->netdev[id] = alloc_etherdev_mqs(sizeof(*mac), txqs, 1); 4855 if (!eth->netdev[id]) { 4856 dev_err(eth->dev, "alloc_etherdev failed\n"); 4857 return -ENOMEM; 4858 } 4859 mac = netdev_priv(eth->netdev[id]); 4860 eth->mac[id] = mac; 4861 mac->id = id; 4862 mac->hw = eth; 4863 mac->of_node = np; 4864 4865 err = of_get_ethdev_address(mac->of_node, eth->netdev[id]); 4866 if (err == -EPROBE_DEFER) 4867 return err; 4868 4869 if (err) { 4870 /* If the mac address is invalid, use random mac address */ 4871 eth_hw_addr_random(eth->netdev[id]); 4872 dev_err(eth->dev, "generated random MAC address %pM\n", 4873 eth->netdev[id]->dev_addr); 4874 } 4875 4876 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); 4877 mac->hwlro_ip_cnt = 0; 4878 4879 mac->hw_stats = devm_kzalloc(eth->dev, 4880 sizeof(*mac->hw_stats), 4881 GFP_KERNEL); 4882 if (!mac->hw_stats) { 4883 dev_err(eth->dev, "failed to allocate counter memory\n"); 4884 err = -ENOMEM; 4885 goto free_netdev; 4886 } 4887 spin_lock_init(&mac->hw_stats->stats_lock); 4888 u64_stats_init(&mac->hw_stats->syncp); 4889 4890 if (mtk_is_netsys_v3_or_greater(eth)) 4891 mac->hw_stats->reg_offset = id * 0x80; 4892 else 4893 mac->hw_stats->reg_offset = id * 0x40; 4894 4895 /* phylink create */ 4896 err = of_get_phy_mode(np, &phy_mode); 4897 if (err) { 4898 dev_err(eth->dev, "incorrect phy-mode\n"); 4899 goto free_netdev; 4900 } 4901 4902 /* mac config is not set */ 4903 mac->interface = PHY_INTERFACE_MODE_NA; 4904 mac->speed = SPEED_UNKNOWN; 4905 4906 mac->phylink_config.dev = ð->netdev[id]->dev; 4907 mac->phylink_config.type = PHYLINK_NETDEV; 4908 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 4909 MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD; 4910 /* LPI above 1 Gbps is not supported */ 4911 mac->phylink_config.lpi_capabilities = MAC_100FD | MAC_1000FD; 4912 mac->phylink_config.lpi_timer_default = 1000; 4913 4914 /* MT7623 gmac0 is now missing its speed-specific PLL configuration 4915 * in its .mac_config method (since state->speed is not valid there. 4916 * Disable support for MII, GMII and RGMII. 4917 */ 4918 if (!mac->hw->soc->disable_pll_modes || mac->id != 0) { 4919 __set_bit(PHY_INTERFACE_MODE_MII, 4920 mac->phylink_config.supported_interfaces); 4921 __set_bit(PHY_INTERFACE_MODE_GMII, 4922 mac->phylink_config.supported_interfaces); 4923 4924 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) 4925 phy_interface_set_rgmii(mac->phylink_config.supported_interfaces); 4926 } 4927 4928 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id) 4929 __set_bit(PHY_INTERFACE_MODE_TRGMII, 4930 mac->phylink_config.supported_interfaces); 4931 4932 /* TRGMII is not permitted on MT7621 if using DDR2 */ 4933 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) && 4934 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII_MT7621_CLK)) { 4935 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val); 4936 if (val & SYSCFG_DRAM_TYPE_DDR2) 4937 __clear_bit(PHY_INTERFACE_MODE_TRGMII, 4938 mac->phylink_config.supported_interfaces); 4939 } 4940 4941 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { 4942 __set_bit(PHY_INTERFACE_MODE_SGMII, 4943 mac->phylink_config.supported_interfaces); 4944 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 4945 mac->phylink_config.supported_interfaces); 4946 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 4947 mac->phylink_config.supported_interfaces); 4948 } 4949 4950 if (mtk_is_netsys_v3_or_greater(mac->hw) && 4951 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_ESW) && 4952 id == MTK_GMAC1_ID) { 4953 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | 4954 MAC_SYM_PAUSE | 4955 MAC_10000FD; 4956 phy_interface_zero(mac->phylink_config.supported_interfaces); 4957 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 4958 mac->phylink_config.supported_interfaces); 4959 } 4960 4961 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 4962 mac_ops = &rt5350_phylink_ops; 4963 4964 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_2P5GPHY) && 4965 id == MTK_GMAC2_ID) 4966 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 4967 mac->phylink_config.supported_interfaces); 4968 4969 /* LPI wake-up timing is only verified on MTK_GMAC_EEE SoCs */ 4970 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GMAC_EEE)) { 4971 phy_interface_copy(mac->phylink_config.lpi_interfaces, 4972 mac->phylink_config.supported_interfaces); 4973 __clear_bit(PHY_INTERFACE_MODE_2500BASEX, 4974 mac->phylink_config.lpi_interfaces); 4975 for (i = 0; i < PHY_INTERFACE_MODE_MAX; i++) 4976 if (mtk_interface_mode_is_xgmii(eth, i)) 4977 __clear_bit(i, 4978 mac->phylink_config.lpi_interfaces); 4979 } 4980 4981 phylink = phylink_create(&mac->phylink_config, 4982 of_fwnode_handle(mac->of_node), 4983 phy_mode, mac_ops); 4984 if (IS_ERR(phylink)) { 4985 err = PTR_ERR(phylink); 4986 goto free_netdev; 4987 } 4988 4989 mac->phylink = phylink; 4990 4991 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 4992 eth->netdev[id]->watchdog_timeo = 5 * HZ; 4993 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 4994 eth->netdev[id]->base_addr = (unsigned long)eth->base; 4995 4996 eth->netdev[id]->hw_features = eth->soc->hw_features; 4997 if (eth->hwlro) 4998 eth->netdev[id]->hw_features |= NETIF_F_LRO; 4999 5000 eth->netdev[id]->vlan_features = eth->soc->hw_features & 5001 ~NETIF_F_HW_VLAN_CTAG_TX; 5002 eth->netdev[id]->features |= eth->soc->hw_features; 5003 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 5004 5005 eth->netdev[id]->irq = eth->irq[MTK_FE_IRQ_SHARED]; 5006 eth->netdev[id]->dev.of_node = np; 5007 5008 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 5009 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 5010 else 5011 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 5012 5013 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 5014 mac->device_notifier.notifier_call = mtk_device_event; 5015 register_netdevice_notifier(&mac->device_notifier); 5016 } 5017 5018 if (mtk_page_pool_enabled(eth)) 5019 eth->netdev[id]->xdp_features = NETDEV_XDP_ACT_BASIC | 5020 NETDEV_XDP_ACT_REDIRECT | 5021 NETDEV_XDP_ACT_NDO_XMIT | 5022 NETDEV_XDP_ACT_NDO_XMIT_SG; 5023 5024 return 0; 5025 5026 free_netdev: 5027 free_netdev(eth->netdev[id]); 5028 return err; 5029 } 5030 5031 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev) 5032 { 5033 struct net_device *dev, *tmp; 5034 LIST_HEAD(dev_list); 5035 int i; 5036 5037 rtnl_lock(); 5038 5039 for (i = 0; i < MTK_MAX_DEVS; i++) { 5040 dev = eth->netdev[i]; 5041 5042 if (!dev || !(dev->flags & IFF_UP)) 5043 continue; 5044 5045 list_add_tail(&dev->close_list, &dev_list); 5046 netdev_lock_ops(dev); 5047 } 5048 5049 netif_close_many(&dev_list, false); 5050 5051 list_for_each_entry(dev, &dev_list, close_list) 5052 netdev_unlock_ops(dev); 5053 5054 eth->dma_dev = dma_dev; 5055 5056 list_for_each_entry_safe(dev, tmp, &dev_list, close_list) { 5057 list_del_init(&dev->close_list); 5058 dev_open(dev, NULL); 5059 } 5060 5061 rtnl_unlock(); 5062 } 5063 5064 static int mtk_sgmii_init(struct mtk_eth *eth) 5065 { 5066 struct device_node *np; 5067 struct regmap *regmap; 5068 int i; 5069 5070 for (i = 0; i < MTK_MAX_DEVS; i++) { 5071 np = of_parse_phandle(eth->dev->of_node, "mediatek,sgmiisys", i); 5072 if (!np) 5073 break; 5074 5075 regmap = syscon_node_to_regmap(np); 5076 if (IS_ERR(regmap)) { 5077 of_node_put(np); 5078 return PTR_ERR(regmap); 5079 } 5080 5081 eth->sgmii_pcs[i] = mtk_pcs_lynxi_create(eth->dev, 5082 of_fwnode_handle(np), 5083 regmap, 5084 eth->soc->ana_rgc3); 5085 of_node_put(np); 5086 } 5087 5088 return 0; 5089 } 5090 5091 static int mtk_setup_legacy_sram(struct mtk_eth *eth, struct resource *res) 5092 { 5093 dev_warn(eth->dev, "legacy DT: using hard-coded SRAM offset.\n"); 5094 5095 if (res->start + MTK_ETH_SRAM_OFFSET + MTK_ETH_NETSYS_V2_SRAM_SIZE - 1 > 5096 res->end) 5097 return -EINVAL; 5098 5099 eth->sram_pool = devm_gen_pool_create(eth->dev, 5100 const_ilog2(MTK_ETH_SRAM_GRANULARITY), 5101 NUMA_NO_NODE, dev_name(eth->dev)); 5102 5103 if (IS_ERR(eth->sram_pool)) 5104 return PTR_ERR(eth->sram_pool); 5105 5106 return gen_pool_add_virt(eth->sram_pool, 5107 (unsigned long)eth->base + MTK_ETH_SRAM_OFFSET, 5108 res->start + MTK_ETH_SRAM_OFFSET, 5109 MTK_ETH_NETSYS_V2_SRAM_SIZE, NUMA_NO_NODE); 5110 } 5111 5112 static int mtk_probe(struct platform_device *pdev) 5113 { 5114 struct resource *res = NULL; 5115 struct device_node *mac_np; 5116 struct mtk_eth *eth; 5117 int err, i; 5118 5119 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 5120 if (!eth) 5121 return -ENOMEM; 5122 5123 eth->soc = of_device_get_match_data(&pdev->dev); 5124 5125 eth->dev = &pdev->dev; 5126 eth->dma_dev = &pdev->dev; 5127 eth->base = devm_platform_ioremap_resource(pdev, 0); 5128 if (IS_ERR(eth->base)) 5129 return PTR_ERR(eth->base); 5130 5131 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 5132 eth->ip_align = NET_IP_ALIGN; 5133 5134 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) { 5135 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(36)); 5136 if (!err) 5137 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 5138 5139 if (err) { 5140 dev_err(&pdev->dev, "Wrong DMA config\n"); 5141 return -EINVAL; 5142 } 5143 } 5144 5145 spin_lock_init(ð->page_lock); 5146 spin_lock_init(ð->tx_irq_lock); 5147 spin_lock_init(ð->rx_irq_lock); 5148 spin_lock_init(ð->dim_lock); 5149 5150 eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 5151 INIT_WORK(ð->rx_dim.work, mtk_dim_rx); 5152 INIT_DELAYED_WORK(ð->reset.monitor_work, mtk_hw_reset_monitor_work); 5153 5154 eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 5155 INIT_WORK(ð->tx_dim.work, mtk_dim_tx); 5156 5157 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 5158 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 5159 "mediatek,ethsys"); 5160 if (IS_ERR(eth->ethsys)) { 5161 dev_err(&pdev->dev, "no ethsys regmap found\n"); 5162 return PTR_ERR(eth->ethsys); 5163 } 5164 } 5165 5166 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) { 5167 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 5168 "mediatek,infracfg"); 5169 if (IS_ERR(eth->infra)) { 5170 dev_err(&pdev->dev, "no infracfg regmap found\n"); 5171 return PTR_ERR(eth->infra); 5172 } 5173 } 5174 5175 if (of_dma_is_coherent(pdev->dev.of_node)) { 5176 struct regmap *cci; 5177 5178 cci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 5179 "cci-control-port"); 5180 /* enable CPU/bus coherency */ 5181 if (!IS_ERR(cci)) 5182 regmap_write(cci, 0, 3); 5183 } 5184 5185 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 5186 err = mtk_sgmii_init(eth); 5187 5188 if (err) 5189 return err; 5190 } 5191 5192 if (eth->soc->required_pctl) { 5193 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 5194 "mediatek,pctl"); 5195 if (IS_ERR(eth->pctl)) { 5196 dev_err(&pdev->dev, "no pctl regmap found\n"); 5197 err = PTR_ERR(eth->pctl); 5198 goto err_destroy_sgmii; 5199 } 5200 } 5201 5202 if (mtk_is_netsys_v2_or_greater(eth)) { 5203 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 5204 if (!res) { 5205 err = -EINVAL; 5206 goto err_destroy_sgmii; 5207 } 5208 5209 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) { 5210 eth->sram_pool = of_gen_pool_get(pdev->dev.of_node, 5211 "sram", 0); 5212 if (!eth->sram_pool) { 5213 if (!mtk_is_netsys_v3_or_greater(eth)) { 5214 err = mtk_setup_legacy_sram(eth, res); 5215 if (err) 5216 goto err_destroy_sgmii; 5217 } else { 5218 dev_err(&pdev->dev, 5219 "Could not get SRAM pool\n"); 5220 err = -EINVAL; 5221 goto err_destroy_sgmii; 5222 } 5223 } 5224 } 5225 } 5226 5227 if (eth->soc->offload_version) { 5228 for (i = 0;; i++) { 5229 struct device_node *np; 5230 phys_addr_t wdma_phy; 5231 u32 wdma_base; 5232 5233 if (i >= ARRAY_SIZE(eth->soc->reg_map->wdma_base)) 5234 break; 5235 5236 np = of_parse_phandle(pdev->dev.of_node, 5237 "mediatek,wed", i); 5238 if (!np) 5239 break; 5240 5241 wdma_base = eth->soc->reg_map->wdma_base[i]; 5242 wdma_phy = res ? res->start + wdma_base : 0; 5243 mtk_wed_add_hw(np, eth, eth->base + wdma_base, 5244 wdma_phy, i); 5245 } 5246 } 5247 5248 err = mtk_get_irqs(pdev, eth); 5249 if (err) 5250 goto err_wed_exit; 5251 5252 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { 5253 eth->clks[i] = devm_clk_get(eth->dev, 5254 mtk_clks_source_name[i]); 5255 if (IS_ERR(eth->clks[i])) { 5256 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) { 5257 err = -EPROBE_DEFER; 5258 goto err_wed_exit; 5259 } 5260 if (eth->soc->required_clks & BIT(i)) { 5261 dev_err(&pdev->dev, "clock %s not found\n", 5262 mtk_clks_source_name[i]); 5263 err = -EINVAL; 5264 goto err_wed_exit; 5265 } 5266 eth->clks[i] = NULL; 5267 } 5268 } 5269 5270 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 5271 INIT_WORK(ð->pending_work, mtk_pending_work); 5272 5273 err = mtk_hw_init(eth, false); 5274 if (err) 5275 goto err_wed_exit; 5276 5277 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); 5278 5279 for_each_child_of_node(pdev->dev.of_node, mac_np) { 5280 if (!of_device_is_compatible(mac_np, 5281 "mediatek,eth-mac")) 5282 continue; 5283 5284 if (!of_device_is_available(mac_np)) 5285 continue; 5286 5287 err = mtk_add_mac(eth, mac_np); 5288 if (err) { 5289 of_node_put(mac_np); 5290 goto err_deinit_hw; 5291 } 5292 } 5293 5294 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { 5295 err = devm_request_irq(eth->dev, eth->irq[MTK_FE_IRQ_SHARED], 5296 mtk_handle_irq, 0, 5297 dev_name(eth->dev), eth); 5298 } else { 5299 err = devm_request_irq(eth->dev, eth->irq[MTK_FE_IRQ_TX], 5300 mtk_handle_irq_tx, 0, 5301 dev_name(eth->dev), eth); 5302 if (err) 5303 goto err_free_dev; 5304 5305 err = devm_request_irq(eth->dev, eth->irq[MTK_FE_IRQ_RX], 5306 mtk_handle_irq_rx, 0, 5307 dev_name(eth->dev), eth); 5308 } 5309 if (err) 5310 goto err_free_dev; 5311 5312 /* No MT7628/88 support yet */ 5313 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 5314 err = mtk_mdio_init(eth); 5315 if (err) 5316 goto err_free_dev; 5317 } 5318 5319 if (eth->soc->offload_version) { 5320 u8 ppe_num = eth->soc->ppe_num; 5321 5322 ppe_num = min_t(u8, ARRAY_SIZE(eth->ppe), ppe_num); 5323 for (i = 0; i < ppe_num; i++) { 5324 u32 ppe_addr = eth->soc->reg_map->ppe_base; 5325 5326 ppe_addr += (i == 2 ? 0xc00 : i * 0x400); 5327 eth->ppe[i] = mtk_ppe_init(eth, eth->base + ppe_addr, i); 5328 5329 if (!eth->ppe[i]) { 5330 err = -ENOMEM; 5331 goto err_deinit_ppe; 5332 } 5333 err = mtk_eth_offload_init(eth, i); 5334 5335 if (err) 5336 goto err_deinit_ppe; 5337 } 5338 } 5339 5340 for (i = 0; i < MTK_MAX_DEVS; i++) { 5341 if (!eth->netdev[i]) 5342 continue; 5343 5344 err = register_netdev(eth->netdev[i]); 5345 if (err) { 5346 dev_err(eth->dev, "error bringing up device\n"); 5347 goto err_deinit_ppe; 5348 } else 5349 netif_info(eth, probe, eth->netdev[i], 5350 "mediatek frame engine at 0x%08lx, irq %d\n", 5351 eth->netdev[i]->base_addr, eth->irq[MTK_FE_IRQ_SHARED]); 5352 } 5353 5354 /* we run 2 devices on the same DMA ring so we need a dummy device 5355 * for NAPI to work 5356 */ 5357 eth->dummy_dev = alloc_netdev_dummy(0); 5358 if (!eth->dummy_dev) { 5359 err = -ENOMEM; 5360 dev_err(eth->dev, "failed to allocated dummy device\n"); 5361 goto err_unreg_netdev; 5362 } 5363 netif_napi_add(eth->dummy_dev, ð->tx_napi, mtk_napi_tx); 5364 netif_napi_add(eth->dummy_dev, ð->rx_napi, mtk_napi_rx); 5365 5366 platform_set_drvdata(pdev, eth); 5367 schedule_delayed_work(ð->reset.monitor_work, 5368 MTK_DMA_MONITOR_TIMEOUT); 5369 5370 return 0; 5371 5372 err_unreg_netdev: 5373 mtk_unreg_dev(eth); 5374 err_deinit_ppe: 5375 mtk_ppe_deinit(eth); 5376 mtk_mdio_cleanup(eth); 5377 err_free_dev: 5378 mtk_free_dev(eth); 5379 err_deinit_hw: 5380 mtk_hw_deinit(eth); 5381 err_wed_exit: 5382 mtk_wed_exit(); 5383 err_destroy_sgmii: 5384 mtk_sgmii_destroy(eth); 5385 5386 return err; 5387 } 5388 5389 static void mtk_remove(struct platform_device *pdev) 5390 { 5391 struct mtk_eth *eth = platform_get_drvdata(pdev); 5392 struct mtk_mac *mac; 5393 int i; 5394 5395 /* stop all devices to make sure that dma is properly shut down */ 5396 for (i = 0; i < MTK_MAX_DEVS; i++) { 5397 if (!eth->netdev[i]) 5398 continue; 5399 mtk_stop(eth->netdev[i]); 5400 mac = netdev_priv(eth->netdev[i]); 5401 phylink_disconnect_phy(mac->phylink); 5402 } 5403 5404 mtk_wed_exit(); 5405 mtk_hw_deinit(eth); 5406 5407 netif_napi_del(ð->tx_napi); 5408 netif_napi_del(ð->rx_napi); 5409 mtk_cleanup(eth); 5410 free_netdev(eth->dummy_dev); 5411 mtk_mdio_cleanup(eth); 5412 } 5413 5414 static const struct mtk_soc_data mt2701_data = { 5415 .reg_map = &mtk_reg_map, 5416 .caps = MT7623_CAPS | MTK_HWLRO, 5417 .hw_features = MTK_HW_FEATURES, 5418 .required_clks = MT7623_CLKS_BITMAP, 5419 .required_pctl = true, 5420 .version = 1, 5421 .tx = { 5422 .desc_size = sizeof(struct mtk_tx_dma), 5423 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5424 .dma_len_offset = 16, 5425 .dma_size = MTK_DMA_SIZE(2K), 5426 .fq_dma_size = MTK_DMA_SIZE(2K), 5427 }, 5428 .rx = { 5429 .desc_size = sizeof(struct mtk_rx_dma), 5430 .irq_done_mask = MTK_RX_DONE_INT, 5431 .dma_l4_valid = RX_DMA_L4_VALID, 5432 .dma_size = MTK_DMA_SIZE(2K), 5433 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5434 .dma_len_offset = 16, 5435 }, 5436 }; 5437 5438 static const struct mtk_soc_data mt7621_data = { 5439 .reg_map = &mtk_reg_map, 5440 .caps = MT7621_CAPS, 5441 .hw_features = MTK_HW_FEATURES, 5442 .required_clks = MT7621_CLKS_BITMAP, 5443 .required_pctl = false, 5444 .version = 1, 5445 .offload_version = 1, 5446 .ppe_num = 1, 5447 .hash_offset = 2, 5448 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, 5449 .tx = { 5450 .desc_size = sizeof(struct mtk_tx_dma), 5451 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5452 .dma_len_offset = 16, 5453 .dma_size = MTK_DMA_SIZE(2K), 5454 .fq_dma_size = MTK_DMA_SIZE(2K), 5455 }, 5456 .rx = { 5457 .desc_size = sizeof(struct mtk_rx_dma), 5458 .irq_done_mask = MTK_RX_DONE_INT, 5459 .dma_l4_valid = RX_DMA_L4_VALID, 5460 .dma_size = MTK_DMA_SIZE(2K), 5461 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5462 .dma_len_offset = 16, 5463 }, 5464 }; 5465 5466 static const struct mtk_soc_data mt7622_data = { 5467 .reg_map = &mtk_reg_map, 5468 .ana_rgc3 = 0x2028, 5469 .caps = MT7622_CAPS | MTK_HWLRO, 5470 .hw_features = MTK_HW_FEATURES, 5471 .required_clks = MT7622_CLKS_BITMAP, 5472 .required_pctl = false, 5473 .version = 1, 5474 .offload_version = 2, 5475 .ppe_num = 1, 5476 .hash_offset = 2, 5477 .has_accounting = true, 5478 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, 5479 .tx = { 5480 .desc_size = sizeof(struct mtk_tx_dma), 5481 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5482 .dma_len_offset = 16, 5483 .dma_size = MTK_DMA_SIZE(2K), 5484 .fq_dma_size = MTK_DMA_SIZE(2K), 5485 }, 5486 .rx = { 5487 .desc_size = sizeof(struct mtk_rx_dma), 5488 .irq_done_mask = MTK_RX_DONE_INT, 5489 .dma_l4_valid = RX_DMA_L4_VALID, 5490 .dma_size = MTK_DMA_SIZE(2K), 5491 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5492 .dma_len_offset = 16, 5493 }, 5494 }; 5495 5496 static const struct mtk_soc_data mt7623_data = { 5497 .reg_map = &mtk_reg_map, 5498 .caps = MT7623_CAPS | MTK_HWLRO, 5499 .hw_features = MTK_HW_FEATURES, 5500 .required_clks = MT7623_CLKS_BITMAP, 5501 .required_pctl = true, 5502 .version = 1, 5503 .offload_version = 1, 5504 .ppe_num = 1, 5505 .hash_offset = 2, 5506 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, 5507 .disable_pll_modes = true, 5508 .tx = { 5509 .desc_size = sizeof(struct mtk_tx_dma), 5510 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5511 .dma_len_offset = 16, 5512 .dma_size = MTK_DMA_SIZE(2K), 5513 .fq_dma_size = MTK_DMA_SIZE(2K), 5514 }, 5515 .rx = { 5516 .desc_size = sizeof(struct mtk_rx_dma), 5517 .irq_done_mask = MTK_RX_DONE_INT, 5518 .dma_l4_valid = RX_DMA_L4_VALID, 5519 .dma_size = MTK_DMA_SIZE(2K), 5520 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5521 .dma_len_offset = 16, 5522 }, 5523 }; 5524 5525 static const struct mtk_soc_data mt7629_data = { 5526 .reg_map = &mtk_reg_map, 5527 .ana_rgc3 = 0x128, 5528 .caps = MT7629_CAPS | MTK_HWLRO, 5529 .hw_features = MTK_HW_FEATURES, 5530 .required_clks = MT7629_CLKS_BITMAP, 5531 .required_pctl = false, 5532 .has_accounting = true, 5533 .version = 1, 5534 .tx = { 5535 .desc_size = sizeof(struct mtk_tx_dma), 5536 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5537 .dma_len_offset = 16, 5538 .dma_size = MTK_DMA_SIZE(2K), 5539 .fq_dma_size = MTK_DMA_SIZE(2K), 5540 }, 5541 .rx = { 5542 .desc_size = sizeof(struct mtk_rx_dma), 5543 .irq_done_mask = MTK_RX_DONE_INT, 5544 .dma_l4_valid = RX_DMA_L4_VALID, 5545 .dma_size = MTK_DMA_SIZE(2K), 5546 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5547 .dma_len_offset = 16, 5548 }, 5549 }; 5550 5551 static const struct mtk_soc_data mt7981_data = { 5552 .reg_map = &mt7986_reg_map, 5553 .ana_rgc3 = 0x128, 5554 .caps = MT7981_CAPS, 5555 .hw_features = MTK_HW_FEATURES, 5556 .required_clks = MT7981_CLKS_BITMAP, 5557 .required_pctl = false, 5558 .version = 2, 5559 .offload_version = 2, 5560 .ppe_num = 2, 5561 .hash_offset = 4, 5562 .has_accounting = true, 5563 .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, 5564 .tx = { 5565 .desc_size = sizeof(struct mtk_tx_dma_v2), 5566 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 5567 .dma_len_offset = 8, 5568 .dma_size = MTK_DMA_SIZE(2K), 5569 .fq_dma_size = MTK_DMA_SIZE(2K), 5570 }, 5571 .rx = { 5572 .desc_size = sizeof(struct mtk_rx_dma), 5573 .irq_done_mask = MTK_RX_DONE_INT, 5574 .dma_l4_valid = RX_DMA_L4_VALID_V2, 5575 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5576 .dma_len_offset = 16, 5577 .dma_size = MTK_DMA_SIZE(2K), 5578 }, 5579 }; 5580 5581 static const struct mtk_soc_data mt7986_data = { 5582 .reg_map = &mt7986_reg_map, 5583 .ana_rgc3 = 0x128, 5584 .caps = MT7986_CAPS, 5585 .hw_features = MTK_HW_FEATURES, 5586 .required_clks = MT7986_CLKS_BITMAP, 5587 .required_pctl = false, 5588 .version = 2, 5589 .offload_version = 2, 5590 .ppe_num = 2, 5591 .hash_offset = 4, 5592 .has_accounting = true, 5593 .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, 5594 .tx = { 5595 .desc_size = sizeof(struct mtk_tx_dma_v2), 5596 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 5597 .dma_len_offset = 8, 5598 .dma_size = MTK_DMA_SIZE(2K), 5599 .fq_dma_size = MTK_DMA_SIZE(2K), 5600 }, 5601 .rx = { 5602 .desc_size = sizeof(struct mtk_rx_dma), 5603 .irq_done_mask = MTK_RX_DONE_INT, 5604 .dma_l4_valid = RX_DMA_L4_VALID_V2, 5605 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5606 .dma_len_offset = 16, 5607 .dma_size = MTK_DMA_SIZE(2K), 5608 }, 5609 }; 5610 5611 static const struct mtk_soc_data mt7988_data = { 5612 .reg_map = &mt7988_reg_map, 5613 .ana_rgc3 = 0x128, 5614 .caps = MT7988_CAPS, 5615 .hw_features = MTK_HW_FEATURES, 5616 .required_clks = MT7988_CLKS_BITMAP, 5617 .required_pctl = false, 5618 .version = 3, 5619 .offload_version = 2, 5620 .ppe_num = 3, 5621 .hash_offset = 4, 5622 .has_accounting = true, 5623 .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE, 5624 .tx = { 5625 .desc_size = sizeof(struct mtk_tx_dma_v2), 5626 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 5627 .dma_len_offset = 8, 5628 .dma_size = MTK_DMA_SIZE(2K), 5629 .fq_dma_size = MTK_DMA_SIZE(4K), 5630 }, 5631 .rx = { 5632 .desc_size = sizeof(struct mtk_rx_dma_v2), 5633 .irq_done_mask = MTK_RX_DONE_INT_V2, 5634 .dma_l4_valid = RX_DMA_L4_VALID_V2, 5635 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 5636 .dma_len_offset = 8, 5637 .dma_size = MTK_DMA_SIZE(2K), 5638 }, 5639 }; 5640 5641 static const struct mtk_soc_data rt5350_data = { 5642 .reg_map = &mt7628_reg_map, 5643 .caps = MT7628_CAPS, 5644 .hw_features = MTK_HW_FEATURES_MT7628, 5645 .required_clks = MT7628_CLKS_BITMAP, 5646 .required_pctl = false, 5647 .version = 1, 5648 .tx = { 5649 .desc_size = sizeof(struct mtk_tx_dma), 5650 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5651 .dma_len_offset = 16, 5652 .dma_size = MTK_DMA_SIZE(2K), 5653 }, 5654 .rx = { 5655 .desc_size = sizeof(struct mtk_rx_dma), 5656 .irq_done_mask = MTK_RX_DONE_INT, 5657 .dma_l4_valid = RX_DMA_L4_VALID_PDMA, 5658 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5659 .dma_len_offset = 16, 5660 .dma_size = MTK_DMA_SIZE(2K), 5661 }, 5662 }; 5663 5664 const struct of_device_id of_mtk_match[] = { 5665 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data }, 5666 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data }, 5667 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data }, 5668 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data }, 5669 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data }, 5670 { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data }, 5671 { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data }, 5672 { .compatible = "mediatek,mt7988-eth", .data = &mt7988_data }, 5673 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data }, 5674 {}, 5675 }; 5676 MODULE_DEVICE_TABLE(of, of_mtk_match); 5677 5678 static struct platform_driver mtk_driver = { 5679 .probe = mtk_probe, 5680 .remove = mtk_remove, 5681 .driver = { 5682 .name = "mtk_soc_eth", 5683 .of_match_table = of_mtk_match, 5684 }, 5685 }; 5686 5687 module_platform_driver(mtk_driver); 5688 5689 MODULE_LICENSE("GPL"); 5690 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 5691 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 5692 MODULE_IMPORT_NS("NETDEV_INTERNAL"); 5693