1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2020 MediaTek Inc.
3 *
4 */
5
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/pci.h>
9 #include <linux/of.h>
10
11 #include "mt7921.h"
12 #include "../mt76_connac2_mac.h"
13 #include "../dma.h"
14 #include "mcu.h"
15
16 static const struct pci_device_id mt7921_pci_device_table[] = {
17 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7961),
18 .driver_data = (kernel_ulong_t)MT7921_FIRMWARE_WM },
19 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7922),
20 .driver_data = (kernel_ulong_t)MT7922_FIRMWARE_WM },
21 { PCI_DEVICE(PCI_VENDOR_ID_ITTIM, 0x7922),
22 .driver_data = (kernel_ulong_t)MT7922_FIRMWARE_WM },
23 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0608),
24 .driver_data = (kernel_ulong_t)MT7921_FIRMWARE_WM },
25 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0616),
26 .driver_data = (kernel_ulong_t)MT7922_FIRMWARE_WM },
27 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7920),
28 .driver_data = (kernel_ulong_t)MT7920_FIRMWARE_WM },
29 { },
30 };
31
32 static bool mt7921_disable_aspm;
33 module_param_named(disable_aspm, mt7921_disable_aspm, bool, 0644);
34 MODULE_PARM_DESC(disable_aspm, "disable PCI ASPM support");
35
mt7921e_init_reset(struct mt792x_dev * dev)36 static int mt7921e_init_reset(struct mt792x_dev *dev)
37 {
38 return mt792x_wpdma_reset(dev, true);
39 }
40
mt7921e_unregister_device(struct mt792x_dev * dev)41 static void mt7921e_unregister_device(struct mt792x_dev *dev)
42 {
43 int i;
44 struct mt76_connac_pm *pm = &dev->pm;
45
46 cancel_work_sync(&dev->init_work);
47 mt76_unregister_device(&dev->mt76);
48 mt76_for_each_q_rx(&dev->mt76, i)
49 napi_disable(&dev->mt76.napi[i]);
50 cancel_delayed_work_sync(&pm->ps_work);
51 cancel_work_sync(&pm->wake_work);
52 cancel_work_sync(&dev->reset_work);
53
54 mt76_connac2_tx_token_put(&dev->mt76);
55 __mt792x_mcu_drv_pmctrl(dev);
56 mt792x_dma_cleanup(dev);
57 mt792x_wfsys_reset(dev);
58 skb_queue_purge(&dev->mt76.mcu.res_q);
59
60 tasklet_disable(&dev->mt76.irq_tasklet);
61 }
62
__mt7921_reg_addr(struct mt792x_dev * dev,u32 addr)63 static u32 __mt7921_reg_addr(struct mt792x_dev *dev, u32 addr)
64 {
65 static const struct mt76_connac_reg_map fixed_map[] = {
66 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
67 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
68 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
69 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
70 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
71 { 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
72 { 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
73 { 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
74 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
75 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */
76 { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
77 { 0x54000000, 0x02000, 0x01000 }, /* WFDMA PCIE0 MCU DMA0 */
78 { 0x55000000, 0x03000, 0x01000 }, /* WFDMA PCIE0 MCU DMA1 */
79 { 0x58000000, 0x06000, 0x01000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
80 { 0x59000000, 0x07000, 0x01000 }, /* WFDMA PCIE1 MCU DMA1 */
81 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
82 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */
83 { 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */
84 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
85 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
86 { 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */
87 { 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */
88 { 0x820cc000, 0x0e000, 0x01000 }, /* WF_UMAC_TOP (PP) */
89 { 0x820cd000, 0x0f000, 0x01000 }, /* WF_MDP_TOP */
90 { 0x74030000, 0x10000, 0x10000 }, /* PCIE_MAC_IREG */
91 { 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */
92 { 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */
93 { 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
94 { 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
95 { 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
96 { 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
97 { 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
98 { 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
99 { 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
100 { 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
101 { 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
102 { 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
103 { 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
104 { 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
105 { 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
106 { 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
107 { 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
108 { 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
109 { 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
110 };
111 int i;
112
113 if (addr < 0x100000)
114 return addr;
115
116 for (i = 0; i < ARRAY_SIZE(fixed_map); i++) {
117 u32 ofs;
118
119 if (addr < fixed_map[i].phys)
120 continue;
121
122 ofs = addr - fixed_map[i].phys;
123 if (ofs > fixed_map[i].size)
124 continue;
125
126 return fixed_map[i].maps + ofs;
127 }
128
129 if ((addr >= 0x18000000 && addr < 0x18c00000) ||
130 (addr >= 0x70000000 && addr < 0x78000000) ||
131 (addr >= 0x7c000000 && addr < 0x7c400000))
132 return mt7921_reg_map_l1(dev, addr);
133
134 dev_err(dev->mt76.dev, "Access currently unsupported address %08x\n",
135 addr);
136
137 return 0;
138 }
139
mt7921_rr(struct mt76_dev * mdev,u32 offset)140 static u32 mt7921_rr(struct mt76_dev *mdev, u32 offset)
141 {
142 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
143 u32 addr = __mt7921_reg_addr(dev, offset);
144
145 return dev->bus_ops->rr(mdev, addr);
146 }
147
mt7921_wr(struct mt76_dev * mdev,u32 offset,u32 val)148 static void mt7921_wr(struct mt76_dev *mdev, u32 offset, u32 val)
149 {
150 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
151 u32 addr = __mt7921_reg_addr(dev, offset);
152
153 dev->bus_ops->wr(mdev, addr, val);
154 }
155
mt7921_rmw(struct mt76_dev * mdev,u32 offset,u32 mask,u32 val)156 static u32 mt7921_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
157 {
158 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
159 u32 addr = __mt7921_reg_addr(dev, offset);
160
161 return dev->bus_ops->rmw(mdev, addr, mask, val);
162 }
163
mt7921_dma_init(struct mt792x_dev * dev)164 static int mt7921_dma_init(struct mt792x_dev *dev)
165 {
166 int ret;
167
168 mt76_dma_attach(&dev->mt76);
169
170 ret = mt792x_dma_disable(dev, true);
171 if (ret)
172 return ret;
173
174 /* init tx queue */
175 ret = mt76_connac_init_tx_queues(dev->phy.mt76, MT7921_TXQ_BAND0,
176 MT7921_TX_RING_SIZE,
177 MT_TX_RING_BASE, NULL, 0);
178 if (ret)
179 return ret;
180
181 mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, 0x4);
182
183 /* command to WM */
184 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7921_TXQ_MCU_WM,
185 MT7921_TX_MCU_RING_SIZE, MT_TX_RING_BASE);
186 if (ret)
187 return ret;
188
189 /* firmware download */
190 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, MT7921_TXQ_FWDL,
191 MT7921_TX_FWDL_RING_SIZE, MT_TX_RING_BASE);
192 if (ret)
193 return ret;
194
195 /* event from WM before firmware download */
196 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU],
197 MT7921_RXQ_MCU_WM,
198 MT7921_RX_MCU_RING_SIZE,
199 MT_RX_BUF_SIZE, MT_RX_EVENT_RING_BASE);
200 if (ret)
201 return ret;
202
203 /* Change mcu queue after firmware download */
204 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA],
205 MT7921_RXQ_MCU_WM,
206 MT7921_RX_MCU_WA_RING_SIZE,
207 MT_RX_BUF_SIZE, MT_WFDMA0(0x540));
208 if (ret)
209 return ret;
210
211 /* rx data */
212 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN],
213 MT7921_RXQ_BAND0, MT7921_RX_RING_SIZE,
214 MT_RX_BUF_SIZE, MT_RX_DATA_RING_BASE);
215 if (ret)
216 return ret;
217
218 ret = mt76_init_queues(dev, mt792x_poll_rx);
219 if (ret < 0)
220 return ret;
221
222 netif_napi_add_tx(dev->mt76.tx_napi_dev, &dev->mt76.tx_napi,
223 mt792x_poll_tx);
224 napi_enable(&dev->mt76.tx_napi);
225
226 return mt792x_dma_enable(dev);
227 }
228
mt7921_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)229 static int mt7921_pci_probe(struct pci_dev *pdev,
230 const struct pci_device_id *id)
231 {
232 static const struct mt76_driver_ops drv_ops = {
233 /* txwi_size = txd size + txp size */
234 .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_hw_txp),
235 .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ |
236 MT_DRV_AMSDU_OFFLOAD,
237 .survey_flags = SURVEY_INFO_TIME_TX |
238 SURVEY_INFO_TIME_RX |
239 SURVEY_INFO_TIME_BSS_RX,
240 .token_size = MT7921_TOKEN_SIZE,
241 .tx_prepare_skb = mt7921e_tx_prepare_skb,
242 .tx_complete_skb = mt76_connac_tx_complete_skb,
243 .rx_check = mt7921_rx_check,
244 .rx_skb = mt7921_queue_rx_skb,
245 .rx_poll_complete = mt792x_rx_poll_complete,
246 .sta_add = mt7921_mac_sta_add,
247 .sta_event = mt7921_mac_sta_event,
248 .sta_remove = mt7921_mac_sta_remove,
249 .update_survey = mt792x_update_channel,
250 .set_channel = mt7921_set_channel,
251 };
252 static const struct mt792x_hif_ops mt7921_pcie_ops = {
253 .init_reset = mt7921e_init_reset,
254 .reset = mt7921e_mac_reset,
255 .mcu_init = mt7921e_mcu_init,
256 .drv_own = mt792xe_mcu_drv_pmctrl,
257 .fw_own = mt792xe_mcu_fw_pmctrl,
258 };
259 static const struct mt792x_irq_map irq_map = {
260 .host_irq_enable = MT_WFDMA0_HOST_INT_ENA,
261 .tx = {
262 .all_complete_mask = MT_INT_TX_DONE_ALL,
263 .mcu_complete_mask = MT_INT_TX_DONE_MCU,
264 },
265 .rx = {
266 .data_complete_mask = MT_INT_RX_DONE_DATA,
267 .wm_complete_mask = MT_INT_RX_DONE_WM,
268 .wm2_complete_mask = MT_INT_RX_DONE_WM2,
269 },
270 };
271 struct ieee80211_ops *ops;
272 struct mt76_bus_ops *bus_ops;
273 struct mt792x_dev *dev;
274 struct mt76_dev *mdev;
275 u16 cmd, chipid;
276 u8 features;
277 int ret;
278
279 ret = pcim_enable_device(pdev);
280 if (ret)
281 return ret;
282
283 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
284 if (ret)
285 return ret;
286
287 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
288 if (!(cmd & PCI_COMMAND_MEMORY)) {
289 cmd |= PCI_COMMAND_MEMORY;
290 pci_write_config_word(pdev, PCI_COMMAND, cmd);
291 }
292 pci_set_master(pdev);
293
294 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
295 if (ret < 0)
296 return ret;
297
298 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
299 if (ret)
300 goto err_free_pci_vec;
301
302 if (mt7921_disable_aspm)
303 mt76_pci_disable_aspm(pdev);
304
305 ops = mt792x_get_mac80211_ops(&pdev->dev, &mt7921_ops,
306 (void *)id->driver_data, &features);
307 if (!ops) {
308 ret = -ENOMEM;
309 goto err_free_pci_vec;
310 }
311
312 mdev = mt76_alloc_device(&pdev->dev, sizeof(*dev), ops, &drv_ops);
313 if (!mdev) {
314 ret = -ENOMEM;
315 goto err_free_pci_vec;
316 }
317
318 pci_set_drvdata(pdev, mdev);
319
320 dev = container_of(mdev, struct mt792x_dev, mt76);
321 dev->fw_features = features;
322 dev->hif_ops = &mt7921_pcie_ops;
323 dev->irq_map = &irq_map;
324 mt76_mmio_init(&dev->mt76, pcim_iomap_table(pdev)[0]);
325 tasklet_init(&mdev->irq_tasklet, mt792x_irq_tasklet, (unsigned long)dev);
326
327 dev->phy.dev = dev;
328 dev->phy.mt76 = &dev->mt76.phy;
329 dev->mt76.phy.priv = &dev->phy;
330 dev->bus_ops = dev->mt76.bus;
331 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
332 GFP_KERNEL);
333 if (!bus_ops) {
334 ret = -ENOMEM;
335 goto err_free_dev;
336 }
337
338 bus_ops->rr = mt7921_rr;
339 bus_ops->wr = mt7921_wr;
340 bus_ops->rmw = mt7921_rmw;
341 dev->mt76.bus = bus_ops;
342
343 if (!mt7921_disable_aspm && mt76_pci_aspm_supported(pdev))
344 dev->aspm_supported = true;
345
346 ret = mt792xe_mcu_fw_pmctrl(dev);
347 if (ret)
348 goto err_free_dev;
349
350 ret = __mt792xe_mcu_drv_pmctrl(dev);
351 if (ret)
352 goto err_free_dev;
353
354 chipid = mt7921_l1_rr(dev, MT_HW_CHIPID);
355 if (chipid == 0x7961 && (mt7921_l1_rr(dev, MT_HW_BOUND) & BIT(7)))
356 chipid = 0x7920;
357 mdev->rev = (chipid << 16) |
358 (mt7921_l1_rr(dev, MT_HW_REV) & 0xff);
359 dev_info(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
360
361 ret = mt792x_wfsys_reset(dev);
362 if (ret)
363 goto err_free_dev;
364
365 mt76_wr(dev, irq_map.host_irq_enable, 0);
366
367 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
368
369 ret = devm_request_irq(mdev->dev, pdev->irq, mt792x_irq_handler,
370 IRQF_SHARED, KBUILD_MODNAME, dev);
371 if (ret)
372 goto err_free_dev;
373
374 ret = mt7921_dma_init(dev);
375 if (ret)
376 goto err_free_irq;
377
378 ret = mt7921_register_device(dev);
379 if (ret)
380 goto err_free_irq;
381
382 if (of_property_read_bool(dev->mt76.dev->of_node, "wakeup-source"))
383 device_init_wakeup(dev->mt76.dev, true);
384
385 return 0;
386
387 err_free_irq:
388 devm_free_irq(&pdev->dev, pdev->irq, dev);
389 err_free_dev:
390 mt76_free_device(&dev->mt76);
391 err_free_pci_vec:
392 pci_free_irq_vectors(pdev);
393
394 return ret;
395 }
396
mt7921_pci_remove(struct pci_dev * pdev)397 static void mt7921_pci_remove(struct pci_dev *pdev)
398 {
399 struct mt76_dev *mdev = pci_get_drvdata(pdev);
400 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
401
402 if (of_property_read_bool(dev->mt76.dev->of_node, "wakeup-source"))
403 device_init_wakeup(dev->mt76.dev, false);
404
405 mt7921e_unregister_device(dev);
406 set_bit(MT76_REMOVED, &mdev->phy.state);
407 devm_free_irq(&pdev->dev, pdev->irq, dev);
408 mt76_free_device(&dev->mt76);
409 pci_free_irq_vectors(pdev);
410 }
411
mt7921_pci_suspend(struct device * device)412 static int mt7921_pci_suspend(struct device *device)
413 {
414 struct pci_dev *pdev = to_pci_dev(device);
415 struct mt76_dev *mdev = pci_get_drvdata(pdev);
416 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
417 struct mt76_connac_pm *pm = &dev->pm;
418 int i, err;
419
420 pm->suspended = true;
421 flush_work(&dev->reset_work);
422 cancel_delayed_work_sync(&pm->ps_work);
423 cancel_work_sync(&pm->wake_work);
424
425 mt7921_roc_abort_sync(dev);
426
427 err = mt792x_mcu_drv_pmctrl(dev);
428 if (err < 0)
429 goto restore_suspend;
430
431 wait_event_timeout(dev->wait,
432 !dev->regd_in_progress, 5 * HZ);
433
434 err = mt7921_mcu_radio_led_ctrl(dev, EXT_CMD_RADIO_OFF_LED);
435 if (err < 0)
436 goto restore_suspend;
437
438 err = mt76_connac_mcu_set_hif_suspend(mdev, true);
439 if (err)
440 goto restore_suspend;
441
442 /* always enable deep sleep during suspend to reduce
443 * power consumption
444 */
445 mt76_connac_mcu_set_deep_sleep(&dev->mt76, true);
446
447 napi_disable(&mdev->tx_napi);
448 mt76_worker_disable(&mdev->tx_worker);
449
450 mt76_for_each_q_rx(mdev, i) {
451 napi_disable(&mdev->napi[i]);
452 }
453
454 /* wait until dma is idle */
455 mt76_poll(dev, MT_WFDMA0_GLO_CFG,
456 MT_WFDMA0_GLO_CFG_TX_DMA_BUSY |
457 MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 1000);
458
459 /* put dma disabled */
460 mt76_clear(dev, MT_WFDMA0_GLO_CFG,
461 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
462
463 /* disable interrupt */
464 mt76_wr(dev, dev->irq_map->host_irq_enable, 0);
465 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0);
466 synchronize_irq(pdev->irq);
467 tasklet_kill(&mdev->irq_tasklet);
468
469 err = mt792x_mcu_fw_pmctrl(dev);
470 if (err)
471 goto restore_napi;
472
473 return 0;
474
475 restore_napi:
476 mt76_for_each_q_rx(mdev, i) {
477 napi_enable(&mdev->napi[i]);
478 }
479 napi_enable(&mdev->tx_napi);
480
481 if (!pm->ds_enable)
482 mt76_connac_mcu_set_deep_sleep(&dev->mt76, false);
483
484 mt76_connac_mcu_set_hif_suspend(mdev, false);
485
486 restore_suspend:
487 pm->suspended = false;
488
489 if (err < 0)
490 mt792x_reset(&dev->mt76);
491
492 return err;
493 }
494
mt7921_pci_resume(struct device * device)495 static int mt7921_pci_resume(struct device *device)
496 {
497 struct pci_dev *pdev = to_pci_dev(device);
498 struct mt76_dev *mdev = pci_get_drvdata(pdev);
499 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
500 struct mt76_connac_pm *pm = &dev->pm;
501 int i, err;
502
503 err = mt792x_mcu_drv_pmctrl(dev);
504 if (err < 0)
505 goto failed;
506
507 mt792x_wpdma_reinit_cond(dev);
508
509 /* enable interrupt */
510 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
511 mt76_connac_irq_enable(&dev->mt76,
512 dev->irq_map->tx.all_complete_mask |
513 MT_INT_RX_DONE_ALL | MT_INT_MCU_CMD);
514 mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE);
515
516 /* put dma enabled */
517 mt76_set(dev, MT_WFDMA0_GLO_CFG,
518 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
519
520 mt76_worker_enable(&mdev->tx_worker);
521
522 local_bh_disable();
523 mt76_for_each_q_rx(mdev, i) {
524 napi_enable(&mdev->napi[i]);
525 napi_schedule(&mdev->napi[i]);
526 }
527 napi_enable(&mdev->tx_napi);
528 napi_schedule(&mdev->tx_napi);
529 local_bh_enable();
530
531 /* restore previous ds setting */
532 if (!pm->ds_enable)
533 mt76_connac_mcu_set_deep_sleep(&dev->mt76, false);
534
535 err = mt76_connac_mcu_set_hif_suspend(mdev, false);
536 if (err < 0)
537 goto failed;
538
539 mt7921_regd_update(dev);
540 err = mt7921_mcu_radio_led_ctrl(dev, EXT_CMD_RADIO_ON_LED);
541 failed:
542 pm->suspended = false;
543
544 if (err < 0)
545 mt792x_reset(&dev->mt76);
546
547 return err;
548 }
549
mt7921_pci_shutdown(struct pci_dev * pdev)550 static void mt7921_pci_shutdown(struct pci_dev *pdev)
551 {
552 mt7921_pci_remove(pdev);
553 }
554
555 static DEFINE_SIMPLE_DEV_PM_OPS(mt7921_pm_ops, mt7921_pci_suspend, mt7921_pci_resume);
556
557 static struct pci_driver mt7921_pci_driver = {
558 .name = KBUILD_MODNAME,
559 .id_table = mt7921_pci_device_table,
560 .probe = mt7921_pci_probe,
561 .remove = mt7921_pci_remove,
562 .shutdown = mt7921_pci_shutdown,
563 .driver.pm = pm_sleep_ptr(&mt7921_pm_ops),
564 };
565
566 module_pci_driver(mt7921_pci_driver);
567
568 MODULE_DEVICE_TABLE(pci, mt7921_pci_device_table);
569 MODULE_FIRMWARE(MT7920_FIRMWARE_WM);
570 MODULE_FIRMWARE(MT7920_ROM_PATCH);
571 MODULE_FIRMWARE(MT7921_FIRMWARE_WM);
572 MODULE_FIRMWARE(MT7921_ROM_PATCH);
573 MODULE_FIRMWARE(MT7922_FIRMWARE_WM);
574 MODULE_FIRMWARE(MT7922_ROM_PATCH);
575 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
576 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
577 MODULE_DESCRIPTION("MediaTek MT7921E (PCIe) wireless driver");
578 MODULE_LICENSE("Dual BSD/GPL");
579