xref: /linux/drivers/net/wireless/mediatek/mt76/mt7921/pci.c (revision c2933b2befe25309f4c5cfbea0ca80909735fd76)
1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2020 MediaTek Inc.
3  *
4  */
5 
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/pci.h>
9 #include <linux/of.h>
10 
11 #include "mt7921.h"
12 #include "../mt76_connac2_mac.h"
13 #include "../dma.h"
14 #include "mcu.h"
15 
16 static const struct pci_device_id mt7921_pci_device_table[] = {
17 	{ PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7961),
18 		.driver_data = (kernel_ulong_t)MT7921_FIRMWARE_WM },
19 	{ PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7922),
20 		.driver_data = (kernel_ulong_t)MT7922_FIRMWARE_WM },
21 	{ PCI_DEVICE(PCI_VENDOR_ID_ITTIM, 0x7922),
22 		.driver_data = (kernel_ulong_t)MT7922_FIRMWARE_WM },
23 	{ PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0608),
24 		.driver_data = (kernel_ulong_t)MT7921_FIRMWARE_WM },
25 	{ PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0616),
26 		.driver_data = (kernel_ulong_t)MT7922_FIRMWARE_WM },
27 	{ PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7920),
28 		.driver_data = (kernel_ulong_t)MT7920_FIRMWARE_WM },
29 	{ },
30 };
31 
32 static bool mt7921_disable_aspm;
33 module_param_named(disable_aspm, mt7921_disable_aspm, bool, 0644);
34 MODULE_PARM_DESC(disable_aspm, "disable PCI ASPM support");
35 
mt7921e_init_reset(struct mt792x_dev * dev)36 static int mt7921e_init_reset(struct mt792x_dev *dev)
37 {
38 	return mt792x_wpdma_reset(dev, true);
39 }
40 
mt7921e_unregister_device(struct mt792x_dev * dev)41 static void mt7921e_unregister_device(struct mt792x_dev *dev)
42 {
43 	int i;
44 	struct mt76_connac_pm *pm = &dev->pm;
45 	struct ieee80211_hw *hw = mt76_hw(dev);
46 
47 	if (dev->phy.chip_cap & MT792x_CHIP_CAP_WF_RF_PIN_CTRL_EVT_EN)
48 		wiphy_rfkill_stop_polling(hw->wiphy);
49 
50 	cancel_work_sync(&dev->init_work);
51 	mt76_unregister_device(&dev->mt76);
52 	mt76_for_each_q_rx(&dev->mt76, i)
53 		napi_disable(&dev->mt76.napi[i]);
54 	cancel_delayed_work_sync(&pm->ps_work);
55 	cancel_work_sync(&pm->wake_work);
56 	cancel_work_sync(&dev->reset_work);
57 
58 	mt76_connac2_tx_token_put(&dev->mt76);
59 	__mt792x_mcu_drv_pmctrl(dev);
60 	mt792x_dma_cleanup(dev);
61 	mt792x_wfsys_reset(dev);
62 	skb_queue_purge(&dev->mt76.mcu.res_q);
63 
64 	tasklet_disable(&dev->mt76.irq_tasklet);
65 }
66 
__mt7921_reg_addr(struct mt792x_dev * dev,u32 addr)67 static u32 __mt7921_reg_addr(struct mt792x_dev *dev, u32 addr)
68 {
69 	static const struct mt76_connac_reg_map fixed_map[] = {
70 		{ 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
71 		{ 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
72 		{ 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
73 		{ 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
74 		{ 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
75 		{ 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
76 		{ 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
77 		{ 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
78 		{ 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
79 		{ 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */
80 		{ 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
81 		{ 0x54000000, 0x02000, 0x01000 }, /* WFDMA PCIE0 MCU DMA0 */
82 		{ 0x55000000, 0x03000, 0x01000 }, /* WFDMA PCIE0 MCU DMA1 */
83 		{ 0x58000000, 0x06000, 0x01000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
84 		{ 0x59000000, 0x07000, 0x01000 }, /* WFDMA PCIE1 MCU DMA1 */
85 		{ 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
86 		{ 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */
87 		{ 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */
88 		{ 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
89 		{ 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
90 		{ 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */
91 		{ 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */
92 		{ 0x820cc000, 0x0e000, 0x01000 }, /* WF_UMAC_TOP (PP) */
93 		{ 0x820cd000, 0x0f000, 0x01000 }, /* WF_MDP_TOP */
94 		{ 0x74030000, 0x10000, 0x10000 }, /* PCIE_MAC_IREG */
95 		{ 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */
96 		{ 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */
97 		{ 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
98 		{ 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
99 		{ 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
100 		{ 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
101 		{ 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
102 		{ 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
103 		{ 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
104 		{ 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
105 		{ 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
106 		{ 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
107 		{ 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
108 		{ 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
109 		{ 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
110 		{ 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
111 		{ 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
112 		{ 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
113 		{ 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
114 	};
115 	int i;
116 
117 	if (addr < 0x100000)
118 		return addr;
119 
120 	for (i = 0; i < ARRAY_SIZE(fixed_map); i++) {
121 		u32 ofs;
122 
123 		if (addr < fixed_map[i].phys)
124 			continue;
125 
126 		ofs = addr - fixed_map[i].phys;
127 		if (ofs > fixed_map[i].size)
128 			continue;
129 
130 		return fixed_map[i].maps + ofs;
131 	}
132 
133 	if ((addr >= 0x18000000 && addr < 0x18c00000) ||
134 	    (addr >= 0x70000000 && addr < 0x78000000) ||
135 	    (addr >= 0x7c000000 && addr < 0x7c400000))
136 		return mt7921_reg_map_l1(dev, addr);
137 
138 	dev_err(dev->mt76.dev, "Access currently unsupported address %08x\n",
139 		addr);
140 
141 	return 0;
142 }
143 
mt7921_rr(struct mt76_dev * mdev,u32 offset)144 static u32 mt7921_rr(struct mt76_dev *mdev, u32 offset)
145 {
146 	struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
147 	u32 addr = __mt7921_reg_addr(dev, offset);
148 
149 	return dev->bus_ops->rr(mdev, addr);
150 }
151 
mt7921_wr(struct mt76_dev * mdev,u32 offset,u32 val)152 static void mt7921_wr(struct mt76_dev *mdev, u32 offset, u32 val)
153 {
154 	struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
155 	u32 addr = __mt7921_reg_addr(dev, offset);
156 
157 	dev->bus_ops->wr(mdev, addr, val);
158 }
159 
mt7921_rmw(struct mt76_dev * mdev,u32 offset,u32 mask,u32 val)160 static u32 mt7921_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
161 {
162 	struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
163 	u32 addr = __mt7921_reg_addr(dev, offset);
164 
165 	return dev->bus_ops->rmw(mdev, addr, mask, val);
166 }
167 
mt7921_dma_init(struct mt792x_dev * dev)168 static int mt7921_dma_init(struct mt792x_dev *dev)
169 {
170 	int ret;
171 
172 	mt76_dma_attach(&dev->mt76);
173 
174 	ret = mt792x_dma_disable(dev, true);
175 	if (ret)
176 		return ret;
177 
178 	/* init tx queue */
179 	ret = mt76_connac_init_tx_queues(dev->phy.mt76, MT7921_TXQ_BAND0,
180 					 MT7921_TX_RING_SIZE,
181 					 MT_TX_RING_BASE, NULL, 0);
182 	if (ret)
183 		return ret;
184 
185 	mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, 0x4);
186 
187 	/* command to WM */
188 	ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7921_TXQ_MCU_WM,
189 				  MT7921_TX_MCU_RING_SIZE, MT_TX_RING_BASE);
190 	if (ret)
191 		return ret;
192 
193 	/* firmware download */
194 	ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, MT7921_TXQ_FWDL,
195 				  MT7921_TX_FWDL_RING_SIZE, MT_TX_RING_BASE);
196 	if (ret)
197 		return ret;
198 
199 	/* event from WM before firmware download */
200 	ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU],
201 			       MT7921_RXQ_MCU_WM,
202 			       MT7921_RX_MCU_RING_SIZE,
203 			       MT_RX_BUF_SIZE, MT_RX_EVENT_RING_BASE);
204 	if (ret)
205 		return ret;
206 
207 	/* Change mcu queue after firmware download */
208 	ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA],
209 			       MT7921_RXQ_MCU_WM,
210 			       MT7921_RX_MCU_WA_RING_SIZE,
211 			       MT_RX_BUF_SIZE, MT_WFDMA0(0x540));
212 	if (ret)
213 		return ret;
214 
215 	/* rx data */
216 	ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN],
217 			       MT7921_RXQ_BAND0, MT7921_RX_RING_SIZE,
218 			       MT_RX_BUF_SIZE, MT_RX_DATA_RING_BASE);
219 	if (ret)
220 		return ret;
221 
222 	ret = mt76_init_queues(dev, mt792x_poll_rx);
223 	if (ret < 0)
224 		return ret;
225 
226 	netif_napi_add_tx(dev->mt76.tx_napi_dev, &dev->mt76.tx_napi,
227 			  mt792x_poll_tx);
228 	napi_enable(&dev->mt76.tx_napi);
229 
230 	return mt792x_dma_enable(dev);
231 }
232 
mt7921_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)233 static int mt7921_pci_probe(struct pci_dev *pdev,
234 			    const struct pci_device_id *id)
235 {
236 	static const struct mt76_driver_ops drv_ops = {
237 		/* txwi_size = txd size + txp size */
238 		.txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_hw_txp),
239 		.drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ |
240 			     MT_DRV_AMSDU_OFFLOAD,
241 		.survey_flags = SURVEY_INFO_TIME_TX |
242 				SURVEY_INFO_TIME_RX |
243 				SURVEY_INFO_TIME_BSS_RX,
244 		.token_size = MT7921_TOKEN_SIZE,
245 		.tx_prepare_skb = mt7921e_tx_prepare_skb,
246 		.tx_complete_skb = mt76_connac_tx_complete_skb,
247 		.rx_check = mt7921_rx_check,
248 		.rx_skb = mt7921_queue_rx_skb,
249 		.rx_poll_complete = mt792x_rx_poll_complete,
250 		.sta_add = mt7921_mac_sta_add,
251 		.sta_event = mt7921_mac_sta_event,
252 		.sta_remove = mt7921_mac_sta_remove,
253 		.update_survey = mt792x_update_channel,
254 		.set_channel = mt7921_set_channel,
255 	};
256 	static const struct mt792x_hif_ops mt7921_pcie_ops = {
257 		.init_reset = mt7921e_init_reset,
258 		.reset = mt7921e_mac_reset,
259 		.mcu_init = mt7921e_mcu_init,
260 		.drv_own = mt792xe_mcu_drv_pmctrl,
261 		.fw_own = mt792xe_mcu_fw_pmctrl,
262 	};
263 	static const struct mt792x_irq_map irq_map = {
264 		.host_irq_enable = MT_WFDMA0_HOST_INT_ENA,
265 		.tx = {
266 			.all_complete_mask = MT_INT_TX_DONE_ALL,
267 			.mcu_complete_mask = MT_INT_TX_DONE_MCU,
268 		},
269 		.rx = {
270 			.data_complete_mask = MT_INT_RX_DONE_DATA,
271 			.wm_complete_mask = MT_INT_RX_DONE_WM,
272 			.wm2_complete_mask = MT_INT_RX_DONE_WM2,
273 		},
274 	};
275 	struct ieee80211_ops *ops;
276 	struct mt76_bus_ops *bus_ops;
277 	struct mt792x_dev *dev;
278 	struct mt76_dev *mdev;
279 	u16 cmd, chipid;
280 	u8 features;
281 	int ret;
282 
283 	ret = pcim_enable_device(pdev);
284 	if (ret)
285 		return ret;
286 
287 	ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
288 	if (ret)
289 		return ret;
290 
291 	pci_read_config_word(pdev, PCI_COMMAND, &cmd);
292 	if (!(cmd & PCI_COMMAND_MEMORY)) {
293 		cmd |= PCI_COMMAND_MEMORY;
294 		pci_write_config_word(pdev, PCI_COMMAND, cmd);
295 	}
296 	pci_set_master(pdev);
297 
298 	ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
299 	if (ret < 0)
300 		return ret;
301 
302 	ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
303 	if (ret)
304 		goto err_free_pci_vec;
305 
306 	if (mt7921_disable_aspm)
307 		mt76_pci_disable_aspm(pdev);
308 
309 	ops = mt792x_get_mac80211_ops(&pdev->dev, &mt7921_ops,
310 				      (void *)id->driver_data, &features);
311 	if (!ops) {
312 		ret = -ENOMEM;
313 		goto err_free_pci_vec;
314 	}
315 
316 	mdev = mt76_alloc_device(&pdev->dev, sizeof(*dev), ops, &drv_ops);
317 	if (!mdev) {
318 		ret = -ENOMEM;
319 		goto err_free_pci_vec;
320 	}
321 
322 	pci_set_drvdata(pdev, mdev);
323 
324 	dev = container_of(mdev, struct mt792x_dev, mt76);
325 	dev->fw_features = features;
326 	dev->hif_ops = &mt7921_pcie_ops;
327 	dev->irq_map = &irq_map;
328 	mt76_mmio_init(&dev->mt76, pcim_iomap_table(pdev)[0]);
329 	tasklet_init(&mdev->irq_tasklet, mt792x_irq_tasklet, (unsigned long)dev);
330 
331 	dev->phy.dev = dev;
332 	dev->phy.mt76 = &dev->mt76.phy;
333 	dev->mt76.phy.priv = &dev->phy;
334 	dev->bus_ops = dev->mt76.bus;
335 	bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
336 			       GFP_KERNEL);
337 	if (!bus_ops) {
338 		ret = -ENOMEM;
339 		goto err_free_dev;
340 	}
341 
342 	bus_ops->rr = mt7921_rr;
343 	bus_ops->wr = mt7921_wr;
344 	bus_ops->rmw = mt7921_rmw;
345 	dev->mt76.bus = bus_ops;
346 
347 	if (!mt7921_disable_aspm && mt76_pci_aspm_supported(pdev))
348 		dev->aspm_supported = true;
349 
350 	ret = mt792xe_mcu_fw_pmctrl(dev);
351 	if (ret)
352 		goto err_free_dev;
353 
354 	ret = __mt792xe_mcu_drv_pmctrl(dev);
355 	if (ret)
356 		goto err_free_dev;
357 
358 	chipid = mt7921_l1_rr(dev, MT_HW_CHIPID);
359 	if (chipid == 0x7961 && (mt7921_l1_rr(dev, MT_HW_BOUND) & BIT(7)))
360 		chipid = 0x7920;
361 	mdev->rev = (chipid << 16) |
362 		    (mt7921_l1_rr(dev, MT_HW_REV) & 0xff);
363 	dev_info(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
364 
365 	ret = mt792x_wfsys_reset(dev);
366 	if (ret)
367 		goto err_free_dev;
368 
369 	mt76_wr(dev, irq_map.host_irq_enable, 0);
370 
371 	mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
372 
373 	ret = devm_request_irq(mdev->dev, pdev->irq, mt792x_irq_handler,
374 			       IRQF_SHARED, KBUILD_MODNAME, dev);
375 	if (ret)
376 		goto err_free_dev;
377 
378 	ret = mt7921_dma_init(dev);
379 	if (ret)
380 		goto err_free_irq;
381 
382 	ret = mt7921_register_device(dev);
383 	if (ret)
384 		goto err_free_irq;
385 
386 	if (of_property_read_bool(dev->mt76.dev->of_node, "wakeup-source"))
387 		device_init_wakeup(dev->mt76.dev, true);
388 
389 	return 0;
390 
391 err_free_irq:
392 	devm_free_irq(&pdev->dev, pdev->irq, dev);
393 err_free_dev:
394 	mt76_free_device(&dev->mt76);
395 err_free_pci_vec:
396 	pci_free_irq_vectors(pdev);
397 
398 	return ret;
399 }
400 
mt7921_pci_remove(struct pci_dev * pdev)401 static void mt7921_pci_remove(struct pci_dev *pdev)
402 {
403 	struct mt76_dev *mdev = pci_get_drvdata(pdev);
404 	struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
405 
406 	if (of_property_read_bool(dev->mt76.dev->of_node, "wakeup-source"))
407 		device_init_wakeup(dev->mt76.dev, false);
408 
409 	mt7921e_unregister_device(dev);
410 	set_bit(MT76_REMOVED, &mdev->phy.state);
411 	devm_free_irq(&pdev->dev, pdev->irq, dev);
412 	mt76_free_device(&dev->mt76);
413 	pci_free_irq_vectors(pdev);
414 }
415 
mt7921_pci_suspend(struct device * device)416 static int mt7921_pci_suspend(struct device *device)
417 {
418 	struct pci_dev *pdev = to_pci_dev(device);
419 	struct mt76_dev *mdev = pci_get_drvdata(pdev);
420 	struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
421 	struct mt76_connac_pm *pm = &dev->pm;
422 	int i, err;
423 
424 	pm->suspended = true;
425 	flush_work(&dev->reset_work);
426 	cancel_delayed_work_sync(&pm->ps_work);
427 	cancel_work_sync(&pm->wake_work);
428 
429 	mt7921_roc_abort_sync(dev);
430 
431 	err = mt792x_mcu_drv_pmctrl(dev);
432 	if (err < 0)
433 		goto restore_suspend;
434 
435 	wait_event_timeout(dev->wait,
436 			   !dev->regd_in_progress, 5 * HZ);
437 
438 	err = mt7921_mcu_radio_led_ctrl(dev, EXT_CMD_RADIO_OFF_LED);
439 	if (err < 0)
440 		goto restore_suspend;
441 
442 	err = mt76_connac_mcu_set_hif_suspend(mdev, true, true);
443 	if (err)
444 		goto restore_suspend;
445 
446 	/* always enable deep sleep during suspend to reduce
447 	 * power consumption
448 	 */
449 	mt76_connac_mcu_set_deep_sleep(&dev->mt76, true);
450 
451 	napi_disable(&mdev->tx_napi);
452 	mt76_worker_disable(&mdev->tx_worker);
453 
454 	mt76_for_each_q_rx(mdev, i) {
455 		napi_disable(&mdev->napi[i]);
456 	}
457 
458 	/* wait until dma is idle  */
459 	mt76_poll(dev, MT_WFDMA0_GLO_CFG,
460 		  MT_WFDMA0_GLO_CFG_TX_DMA_BUSY |
461 		  MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 1000);
462 
463 	/* put dma disabled */
464 	mt76_clear(dev, MT_WFDMA0_GLO_CFG,
465 		   MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
466 
467 	/* disable interrupt */
468 	mt76_wr(dev, dev->irq_map->host_irq_enable, 0);
469 	mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0);
470 	synchronize_irq(pdev->irq);
471 	tasklet_kill(&mdev->irq_tasklet);
472 
473 	err = mt792x_mcu_fw_pmctrl(dev);
474 	if (err)
475 		goto restore_napi;
476 
477 	return 0;
478 
479 restore_napi:
480 	mt76_for_each_q_rx(mdev, i) {
481 		napi_enable(&mdev->napi[i]);
482 	}
483 	napi_enable(&mdev->tx_napi);
484 
485 	if (!pm->ds_enable)
486 		mt76_connac_mcu_set_deep_sleep(&dev->mt76, false);
487 
488 	mt76_connac_mcu_set_hif_suspend(mdev, false, true);
489 
490 restore_suspend:
491 	pm->suspended = false;
492 
493 	if (err < 0)
494 		mt792x_reset(&dev->mt76);
495 
496 	return err;
497 }
498 
mt7921_pci_resume(struct device * device)499 static int mt7921_pci_resume(struct device *device)
500 {
501 	struct pci_dev *pdev = to_pci_dev(device);
502 	struct mt76_dev *mdev = pci_get_drvdata(pdev);
503 	struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
504 	struct mt76_connac_pm *pm = &dev->pm;
505 	int i, err;
506 
507 	err = mt792x_mcu_drv_pmctrl(dev);
508 	if (err < 0)
509 		goto failed;
510 
511 	mt792x_wpdma_reinit_cond(dev);
512 
513 	/* enable interrupt */
514 	mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
515 	mt76_connac_irq_enable(&dev->mt76,
516 			       dev->irq_map->tx.all_complete_mask |
517 			       MT_INT_RX_DONE_ALL | MT_INT_MCU_CMD);
518 	mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE);
519 
520 	/* put dma enabled */
521 	mt76_set(dev, MT_WFDMA0_GLO_CFG,
522 		 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
523 
524 	mt76_worker_enable(&mdev->tx_worker);
525 
526 	mt76_for_each_q_rx(mdev, i) {
527 		napi_enable(&mdev->napi[i]);
528 	}
529 	napi_enable(&mdev->tx_napi);
530 
531 	local_bh_disable();
532 	mt76_for_each_q_rx(mdev, i) {
533 		napi_schedule(&mdev->napi[i]);
534 	}
535 	napi_schedule(&mdev->tx_napi);
536 	local_bh_enable();
537 
538 	/* restore previous ds setting */
539 	if (!pm->ds_enable)
540 		mt76_connac_mcu_set_deep_sleep(&dev->mt76, false);
541 
542 	err = mt76_connac_mcu_set_hif_suspend(mdev, false, true);
543 	if (err < 0)
544 		goto failed;
545 
546 	mt7921_regd_update(dev);
547 	err = mt7921_mcu_radio_led_ctrl(dev, EXT_CMD_RADIO_ON_LED);
548 failed:
549 	pm->suspended = false;
550 
551 	if (err < 0)
552 		mt792x_reset(&dev->mt76);
553 
554 	return err;
555 }
556 
mt7921_pci_shutdown(struct pci_dev * pdev)557 static void mt7921_pci_shutdown(struct pci_dev *pdev)
558 {
559 	mt7921_pci_remove(pdev);
560 }
561 
562 static DEFINE_SIMPLE_DEV_PM_OPS(mt7921_pm_ops, mt7921_pci_suspend, mt7921_pci_resume);
563 
564 static struct pci_driver mt7921_pci_driver = {
565 	.name		= KBUILD_MODNAME,
566 	.id_table	= mt7921_pci_device_table,
567 	.probe		= mt7921_pci_probe,
568 	.remove		= mt7921_pci_remove,
569 	.shutdown	= mt7921_pci_shutdown,
570 	.driver.pm	= pm_sleep_ptr(&mt7921_pm_ops),
571 };
572 
573 module_pci_driver(mt7921_pci_driver);
574 
575 MODULE_DEVICE_TABLE(pci, mt7921_pci_device_table);
576 MODULE_FIRMWARE(MT7920_FIRMWARE_WM);
577 MODULE_FIRMWARE(MT7920_ROM_PATCH);
578 MODULE_FIRMWARE(MT7921_FIRMWARE_WM);
579 MODULE_FIRMWARE(MT7921_ROM_PATCH);
580 MODULE_FIRMWARE(MT7922_FIRMWARE_WM);
581 MODULE_FIRMWARE(MT7922_ROM_PATCH);
582 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
583 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
584 MODULE_DESCRIPTION("MediaTek MT7921E (PCIe) wireless driver");
585 MODULE_LICENSE("Dual BSD/GPL");
586