1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /* Copyright (C) 2020 MediaTek Inc. */
3
4 #include <linux/etherdevice.h>
5 #include <linux/hwmon.h>
6 #include <linux/hwmon-sysfs.h>
7 #include <linux/of.h>
8 #include <linux/thermal.h>
9 #include "mt7915.h"
10 #include "mac.h"
11 #include "mcu.h"
12 #include "coredump.h"
13 #include "eeprom.h"
14
15 static const struct ieee80211_iface_limit if_limits[] = {
16 {
17 .max = 1,
18 .types = BIT(NL80211_IFTYPE_ADHOC)
19 }, {
20 .max = 16,
21 .types = BIT(NL80211_IFTYPE_AP)
22 #ifdef CONFIG_MAC80211_MESH
23 | BIT(NL80211_IFTYPE_MESH_POINT)
24 #endif
25 }, {
26 .max = MT7915_MAX_INTERFACES,
27 .types = BIT(NL80211_IFTYPE_STATION)
28 }
29 };
30
31 static const struct ieee80211_iface_combination if_comb[] = {
32 {
33 .limits = if_limits,
34 .n_limits = ARRAY_SIZE(if_limits),
35 .max_interfaces = MT7915_MAX_INTERFACES,
36 .num_different_channels = 1,
37 .beacon_int_infra_match = true,
38 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
39 BIT(NL80211_CHAN_WIDTH_20) |
40 BIT(NL80211_CHAN_WIDTH_40) |
41 BIT(NL80211_CHAN_WIDTH_80) |
42 BIT(NL80211_CHAN_WIDTH_160),
43 }
44 };
45
mt7915_thermal_temp_show(struct device * dev,struct device_attribute * attr,char * buf)46 static ssize_t mt7915_thermal_temp_show(struct device *dev,
47 struct device_attribute *attr,
48 char *buf)
49 {
50 struct mt7915_phy *phy = dev_get_drvdata(dev);
51 int i = to_sensor_dev_attr(attr)->index;
52 int temperature;
53
54 switch (i) {
55 case 0:
56 mutex_lock(&phy->dev->mt76.mutex);
57 temperature = mt7915_mcu_get_temperature(phy);
58 mutex_unlock(&phy->dev->mt76.mutex);
59 if (temperature < 0)
60 return temperature;
61 /* display in millidegree celcius */
62 return sprintf(buf, "%u\n", temperature * 1000);
63 case 1:
64 case 2:
65 return sprintf(buf, "%u\n",
66 phy->throttle_temp[i - 1] * 1000);
67 case 3:
68 return sprintf(buf, "%hhu\n", phy->throttle_state);
69 default:
70 return -EINVAL;
71 }
72 }
73
mt7915_thermal_temp_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)74 static ssize_t mt7915_thermal_temp_store(struct device *dev,
75 struct device_attribute *attr,
76 const char *buf, size_t count)
77 {
78 struct mt7915_phy *phy = dev_get_drvdata(dev);
79 int ret, i = to_sensor_dev_attr(attr)->index;
80 long val;
81
82 ret = kstrtol(buf, 10, &val);
83 if (ret < 0)
84 return ret;
85
86 mutex_lock(&phy->dev->mt76.mutex);
87 val = DIV_ROUND_CLOSEST(clamp_val(val, 60 * 1000, 130 * 1000), 1000);
88
89 if ((i - 1 == MT7915_CRIT_TEMP_IDX &&
90 val > phy->throttle_temp[MT7915_MAX_TEMP_IDX]) ||
91 (i - 1 == MT7915_MAX_TEMP_IDX &&
92 val < phy->throttle_temp[MT7915_CRIT_TEMP_IDX])) {
93 dev_err(phy->dev->mt76.dev,
94 "temp1_max shall be greater than temp1_crit.");
95 mutex_unlock(&phy->dev->mt76.mutex);
96 return -EINVAL;
97 }
98
99 phy->throttle_temp[i - 1] = val;
100 ret = mt7915_mcu_set_thermal_protect(phy);
101 mutex_unlock(&phy->dev->mt76.mutex);
102 if (ret)
103 return ret;
104
105 return count;
106 }
107
108 static SENSOR_DEVICE_ATTR_RO(temp1_input, mt7915_thermal_temp, 0);
109 static SENSOR_DEVICE_ATTR_RW(temp1_crit, mt7915_thermal_temp, 1);
110 static SENSOR_DEVICE_ATTR_RW(temp1_max, mt7915_thermal_temp, 2);
111 static SENSOR_DEVICE_ATTR_RO(throttle1, mt7915_thermal_temp, 3);
112
113 static struct attribute *mt7915_hwmon_attrs[] = {
114 &sensor_dev_attr_temp1_input.dev_attr.attr,
115 &sensor_dev_attr_temp1_crit.dev_attr.attr,
116 &sensor_dev_attr_temp1_max.dev_attr.attr,
117 &sensor_dev_attr_throttle1.dev_attr.attr,
118 NULL,
119 };
120 ATTRIBUTE_GROUPS(mt7915_hwmon);
121
122 static int
mt7915_thermal_get_max_throttle_state(struct thermal_cooling_device * cdev,unsigned long * state)123 mt7915_thermal_get_max_throttle_state(struct thermal_cooling_device *cdev,
124 unsigned long *state)
125 {
126 *state = MT7915_CDEV_THROTTLE_MAX;
127
128 return 0;
129 }
130
131 static int
mt7915_thermal_get_cur_throttle_state(struct thermal_cooling_device * cdev,unsigned long * state)132 mt7915_thermal_get_cur_throttle_state(struct thermal_cooling_device *cdev,
133 unsigned long *state)
134 {
135 struct mt7915_phy *phy = cdev->devdata;
136
137 *state = phy->cdev_state;
138
139 return 0;
140 }
141
142 static int
mt7915_thermal_set_cur_throttle_state(struct thermal_cooling_device * cdev,unsigned long state)143 mt7915_thermal_set_cur_throttle_state(struct thermal_cooling_device *cdev,
144 unsigned long state)
145 {
146 struct mt7915_phy *phy = cdev->devdata;
147 u8 throttling = MT7915_THERMAL_THROTTLE_MAX - state;
148 int ret;
149
150 if (state > MT7915_CDEV_THROTTLE_MAX) {
151 dev_err(phy->dev->mt76.dev,
152 "please specify a valid throttling state\n");
153 return -EINVAL;
154 }
155
156 if (state == phy->cdev_state)
157 return 0;
158
159 /*
160 * cooling_device convention: 0 = no cooling, more = more cooling
161 * mcu convention: 1 = max cooling, more = less cooling
162 */
163 mutex_lock(&phy->dev->mt76.mutex);
164 ret = mt7915_mcu_set_thermal_throttling(phy, throttling);
165 mutex_unlock(&phy->dev->mt76.mutex);
166 if (ret)
167 return ret;
168
169 phy->cdev_state = state;
170
171 return 0;
172 }
173
174 static const struct thermal_cooling_device_ops mt7915_thermal_ops = {
175 .get_max_state = mt7915_thermal_get_max_throttle_state,
176 .get_cur_state = mt7915_thermal_get_cur_throttle_state,
177 .set_cur_state = mt7915_thermal_set_cur_throttle_state,
178 };
179
mt7915_thermal_get_temp(struct thermal_zone_device * tz,int * temp)180 static int mt7915_thermal_get_temp(struct thermal_zone_device *tz, int *temp)
181 {
182 struct mt7915_phy *phy = thermal_zone_device_priv(tz);
183 int val;
184
185 mutex_lock(&phy->dev->mt76.mutex);
186 val = mt7915_mcu_get_temperature(phy);
187 mutex_unlock(&phy->dev->mt76.mutex);
188 if (val < 0)
189 return val;
190
191 *temp = val * 1000;
192 return 0;
193 }
194
195 static const struct thermal_zone_device_ops mt7915_tz_ops = {
196 .get_temp = mt7915_thermal_get_temp,
197 };
198
mt7915_unregister_thermal(struct mt7915_phy * phy)199 static void mt7915_unregister_thermal(struct mt7915_phy *phy)
200 {
201 struct wiphy *wiphy = phy->mt76->hw->wiphy;
202
203 if (!phy->cdev)
204 return;
205
206 sysfs_remove_link(&wiphy->dev.kobj, "cooling_device");
207 thermal_cooling_device_unregister(phy->cdev);
208 }
209
mt7915_thermal_init(struct mt7915_phy * phy)210 static int mt7915_thermal_init(struct mt7915_phy *phy)
211 {
212 struct wiphy *wiphy = phy->mt76->hw->wiphy;
213 struct thermal_cooling_device *cdev;
214 struct device *hwmon;
215 const char *name;
216
217 name = devm_kasprintf(&wiphy->dev, GFP_KERNEL, "mt7915_%s",
218 wiphy_name(wiphy));
219 if (!name)
220 return -ENOMEM;
221
222 cdev = thermal_cooling_device_register(name, phy, &mt7915_thermal_ops);
223 if (!IS_ERR(cdev)) {
224 if (sysfs_create_link(&wiphy->dev.kobj, &cdev->device.kobj,
225 "cooling_device") < 0)
226 thermal_cooling_device_unregister(cdev);
227 else
228 phy->cdev = cdev;
229 }
230
231 /* initialize critical/maximum high temperature */
232 phy->throttle_temp[MT7915_CRIT_TEMP_IDX] = MT7915_CRIT_TEMP;
233 phy->throttle_temp[MT7915_MAX_TEMP_IDX] = MT7915_MAX_TEMP;
234
235 phy->tzone = devm_thermal_of_zone_register(phy->dev->mt76.dev,
236 phy->mt76->band_idx, phy,
237 &mt7915_tz_ops);
238 if (IS_ERR(phy->tzone)) {
239 if (PTR_ERR(phy->tzone) != -ENODEV)
240 dev_warn(phy->dev->mt76.dev,
241 "failed to register thermal zone: %ld\n",
242 PTR_ERR(phy->tzone));
243 phy->tzone = NULL;
244 }
245
246 if (!IS_REACHABLE(CONFIG_HWMON))
247 return 0;
248
249 hwmon = devm_hwmon_device_register_with_groups(&wiphy->dev, name, phy,
250 mt7915_hwmon_groups);
251 return PTR_ERR_OR_ZERO(hwmon);
252 }
253
mt7915_led_set_config(struct led_classdev * led_cdev,u8 delay_on,u8 delay_off)254 static void mt7915_led_set_config(struct led_classdev *led_cdev,
255 u8 delay_on, u8 delay_off)
256 {
257 struct mt7915_dev *dev;
258 struct mt76_phy *mphy;
259 u32 val;
260
261 mphy = container_of(led_cdev, struct mt76_phy, leds.cdev);
262 dev = container_of(mphy->dev, struct mt7915_dev, mt76);
263
264 /* set PWM mode */
265 val = FIELD_PREP(MT_LED_STATUS_DURATION, 0xffff) |
266 FIELD_PREP(MT_LED_STATUS_OFF, delay_off) |
267 FIELD_PREP(MT_LED_STATUS_ON, delay_on);
268 mt76_wr(dev, MT_LED_STATUS_0(mphy->band_idx), val);
269 mt76_wr(dev, MT_LED_STATUS_1(mphy->band_idx), val);
270
271 /* enable LED */
272 mt76_wr(dev, MT_LED_EN(mphy->band_idx), 1);
273
274 /* control LED */
275 val = MT_LED_CTRL_KICK;
276 if (dev->mphy.leds.al)
277 val |= MT_LED_CTRL_POLARITY;
278 if (mphy->band_idx)
279 val |= MT_LED_CTRL_BAND;
280
281 mt76_wr(dev, MT_LED_CTRL(mphy->band_idx), val);
282 mt76_clear(dev, MT_LED_CTRL(mphy->band_idx), MT_LED_CTRL_KICK);
283 }
284
mt7915_led_set_blink(struct led_classdev * led_cdev,unsigned long * delay_on,unsigned long * delay_off)285 static int mt7915_led_set_blink(struct led_classdev *led_cdev,
286 unsigned long *delay_on,
287 unsigned long *delay_off)
288 {
289 u16 delta_on = 0, delta_off = 0;
290
291 #define HW_TICK 10
292 #define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK)
293
294 if (*delay_on)
295 delta_on = TO_HW_TICK(*delay_on);
296 if (*delay_off)
297 delta_off = TO_HW_TICK(*delay_off);
298
299 mt7915_led_set_config(led_cdev, delta_on, delta_off);
300
301 return 0;
302 }
303
mt7915_led_set_brightness(struct led_classdev * led_cdev,enum led_brightness brightness)304 static void mt7915_led_set_brightness(struct led_classdev *led_cdev,
305 enum led_brightness brightness)
306 {
307 if (!brightness)
308 mt7915_led_set_config(led_cdev, 0, 0xff);
309 else
310 mt7915_led_set_config(led_cdev, 0xff, 0);
311 }
312
__mt7915_init_txpower(struct mt7915_phy * phy,struct ieee80211_supported_band * sband)313 static void __mt7915_init_txpower(struct mt7915_phy *phy,
314 struct ieee80211_supported_band *sband)
315 {
316 struct mt7915_dev *dev = phy->dev;
317 int i, n_chains = hweight16(phy->mt76->chainmask);
318 int path_delta = mt76_tx_power_path_delta(n_chains);
319 int pwr_delta = mt7915_eeprom_get_power_delta(dev, sband->band);
320 struct mt76_power_limits limits;
321
322 phy->sku_limit_en = true;
323 phy->sku_path_en = true;
324 for (i = 0; i < sband->n_channels; i++) {
325 struct ieee80211_channel *chan = &sband->channels[i];
326 u32 target_power = 0;
327 int j;
328
329 for (j = 0; j < n_chains; j++) {
330 u32 val;
331
332 val = mt7915_eeprom_get_target_power(dev, chan, j);
333 target_power = max(target_power, val);
334 }
335
336 target_power += pwr_delta;
337 target_power = mt76_get_rate_power_limits(phy->mt76, chan,
338 &limits,
339 target_power);
340
341 /* MT7915N can not enable Backoff table without setting value in dts */
342 if (!limits.path.ofdm[0])
343 phy->sku_path_en = false;
344
345 target_power += path_delta;
346 target_power = DIV_ROUND_UP(target_power, 2);
347 chan->max_power = min_t(int, chan->max_reg_power,
348 target_power);
349 chan->orig_mpwr = target_power;
350 }
351 }
352
mt7915_init_txpower(struct mt7915_phy * phy)353 void mt7915_init_txpower(struct mt7915_phy *phy)
354 {
355 if (!phy)
356 return;
357
358 if (phy->mt76->cap.has_2ghz)
359 __mt7915_init_txpower(phy, &phy->mt76->sband_2g.sband);
360 if (phy->mt76->cap.has_5ghz)
361 __mt7915_init_txpower(phy, &phy->mt76->sband_5g.sband);
362 if (phy->mt76->cap.has_6ghz)
363 __mt7915_init_txpower(phy, &phy->mt76->sband_6g.sband);
364 }
365
366 static void
mt7915_regd_notifier(struct wiphy * wiphy,struct regulatory_request * request)367 mt7915_regd_notifier(struct wiphy *wiphy,
368 struct regulatory_request *request)
369 {
370 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
371 struct mt7915_dev *dev = mt7915_hw_dev(hw);
372 struct mt76_phy *mphy = hw->priv;
373 struct mt7915_phy *phy = mphy->priv;
374
375 memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2));
376 dev->mt76.region = request->dfs_region;
377
378 if (dev->mt76.region == NL80211_DFS_UNSET)
379 mt7915_mcu_rdd_background_enable(phy, NULL);
380
381 mt7915_init_txpower(phy);
382
383 mphy->dfs_state = MT_DFS_STATE_UNKNOWN;
384 mt7915_dfs_init_radar_detector(phy);
385 }
386
387 static void
mt7915_init_wiphy(struct mt7915_phy * phy)388 mt7915_init_wiphy(struct mt7915_phy *phy)
389 {
390 struct mt76_phy *mphy = phy->mt76;
391 struct ieee80211_hw *hw = mphy->hw;
392 struct mt76_dev *mdev = &phy->dev->mt76;
393 struct wiphy *wiphy = hw->wiphy;
394 struct mt7915_dev *dev = phy->dev;
395
396 hw->queues = 4;
397 hw->max_rx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE;
398 hw->max_tx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE;
399 hw->netdev_features = NETIF_F_RXCSUM;
400
401 if (mtk_wed_device_active(&mdev->mmio.wed))
402 hw->netdev_features |= NETIF_F_HW_TC;
403
404 hw->radiotap_timestamp.units_pos =
405 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US;
406
407 phy->slottime = 9;
408
409 hw->sta_data_size = sizeof(struct mt7915_sta);
410 hw->vif_data_size = sizeof(struct mt7915_vif);
411
412 wiphy->iface_combinations = if_comb;
413 wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
414 wiphy->reg_notifier = mt7915_regd_notifier;
415 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
416 wiphy->mbssid_max_interfaces = 16;
417
418 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR);
419 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS);
420 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY);
421 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT);
422 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT);
423 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE);
424 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP);
425 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY);
426 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT);
427 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
428
429 if (!is_mt7915(&dev->mt76))
430 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_STA_TX_PWR);
431
432 if (mt7915_eeprom_has_background_radar(phy->dev) &&
433 (!mdev->dev->of_node ||
434 !of_property_read_bool(mdev->dev->of_node,
435 "mediatek,disable-radar-background")))
436 wiphy_ext_feature_set(wiphy,
437 NL80211_EXT_FEATURE_RADAR_BACKGROUND);
438
439 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
440 ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD);
441 ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD);
442 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID);
443 ieee80211_hw_set(hw, WANT_MONITOR_VIF);
444 ieee80211_hw_set(hw, SUPPORTS_TX_FRAG);
445
446 hw->max_tx_fragments = 4;
447
448 if (phy->mt76->cap.has_2ghz) {
449 phy->mt76->sband_2g.sband.ht_cap.cap |=
450 IEEE80211_HT_CAP_LDPC_CODING |
451 IEEE80211_HT_CAP_MAX_AMSDU;
452 if (is_mt7915(&dev->mt76))
453 phy->mt76->sband_2g.sband.ht_cap.ampdu_density =
454 IEEE80211_HT_MPDU_DENSITY_4;
455 else
456 phy->mt76->sband_2g.sband.ht_cap.ampdu_density =
457 IEEE80211_HT_MPDU_DENSITY_2;
458 }
459
460 if (phy->mt76->cap.has_5ghz) {
461 struct ieee80211_sta_vht_cap *vht_cap;
462
463 vht_cap = &phy->mt76->sband_5g.sband.vht_cap;
464 phy->mt76->sband_5g.sband.ht_cap.cap |=
465 IEEE80211_HT_CAP_LDPC_CODING |
466 IEEE80211_HT_CAP_MAX_AMSDU;
467
468 if (is_mt7915(&dev->mt76)) {
469 phy->mt76->sband_5g.sband.ht_cap.ampdu_density =
470 IEEE80211_HT_MPDU_DENSITY_4;
471
472 vht_cap->cap |=
473 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991 |
474 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK;
475
476 if (!dev->dbdc_support)
477 vht_cap->cap |=
478 IEEE80211_VHT_CAP_SHORT_GI_160 |
479 FIELD_PREP(IEEE80211_VHT_CAP_EXT_NSS_BW_MASK, 1);
480 } else {
481 phy->mt76->sband_5g.sband.ht_cap.ampdu_density =
482 IEEE80211_HT_MPDU_DENSITY_2;
483
484 vht_cap->cap |=
485 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
486 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK;
487
488 /* mt7916 dbdc with 2g 2x2 bw40 and 5g 2x2 bw160c */
489 vht_cap->cap |=
490 IEEE80211_VHT_CAP_SHORT_GI_160 |
491 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ;
492 }
493
494 if (!is_mt7915(&dev->mt76) || !dev->dbdc_support)
495 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW);
496 }
497
498 mt76_set_stream_caps(phy->mt76, true);
499 mt7915_set_stream_vht_txbf_caps(phy);
500 mt7915_set_stream_he_caps(phy);
501 mt7915_init_txpower(phy);
502
503 wiphy->available_antennas_rx = phy->mt76->antenna_mask;
504 wiphy->available_antennas_tx = phy->mt76->antenna_mask;
505
506 /* init led callbacks */
507 if (IS_ENABLED(CONFIG_MT76_LEDS)) {
508 mphy->leds.cdev.brightness_set = mt7915_led_set_brightness;
509 mphy->leds.cdev.blink_set = mt7915_led_set_blink;
510 }
511 }
512
513 static void
mt7915_mac_init_band(struct mt7915_dev * dev,u8 band)514 mt7915_mac_init_band(struct mt7915_dev *dev, u8 band)
515 {
516 u32 mask, set;
517
518 mt76_rmw_field(dev, MT_TMAC_CTCR0(band),
519 MT_TMAC_CTCR0_INS_DDLMT_REFTIME, 0x3f);
520 mt76_set(dev, MT_TMAC_CTCR0(band),
521 MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN |
522 MT_TMAC_CTCR0_INS_DDLMT_EN);
523
524 mask = MT_MDP_RCFR0_MCU_RX_MGMT |
525 MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR |
526 MT_MDP_RCFR0_MCU_RX_CTL_BAR;
527 set = FIELD_PREP(MT_MDP_RCFR0_MCU_RX_MGMT, MT_MDP_TO_HIF) |
528 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR, MT_MDP_TO_HIF) |
529 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_BAR, MT_MDP_TO_HIF);
530 mt76_rmw(dev, MT_MDP_BNRCFR0(band), mask, set);
531
532 mask = MT_MDP_RCFR1_MCU_RX_BYPASS |
533 MT_MDP_RCFR1_RX_DROPPED_UCAST |
534 MT_MDP_RCFR1_RX_DROPPED_MCAST;
535 set = FIELD_PREP(MT_MDP_RCFR1_MCU_RX_BYPASS, MT_MDP_TO_HIF) |
536 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_UCAST, MT_MDP_TO_HIF) |
537 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_MCAST, MT_MDP_TO_HIF);
538 mt76_rmw(dev, MT_MDP_BNRCFR1(band), mask, set);
539
540 mt76_rmw_field(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_MAX_RX_LEN, 0x680);
541
542 /* mt7915: disable rx rate report by default due to hw issues */
543 mt76_clear(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_RXD_G5_EN);
544
545 /* clear estimated value of EIFS for Rx duration & OBSS time */
546 mt76_wr(dev, MT_WF_RMAC_RSVD0(band), MT_WF_RMAC_RSVD0_EIFS_CLR);
547
548 /* clear backoff time for Rx duration */
549 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME1(band),
550 MT_WF_RMAC_MIB_NONQOSD_BACKOFF);
551 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME3(band),
552 MT_WF_RMAC_MIB_QOS01_BACKOFF);
553 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME4(band),
554 MT_WF_RMAC_MIB_QOS23_BACKOFF);
555
556 /* clear backoff time for Tx duration */
557 mt76_clear(dev, MT_WTBLOFF_TOP_ACR(band),
558 MT_WTBLOFF_TOP_ADM_BACKOFFTIME);
559
560 /* exclude estimated backoff time for Tx duration on MT7915 */
561 if (is_mt7915(&dev->mt76))
562 mt76_set(dev, MT_AGG_ATCR0(band),
563 MT_AGG_ATCR_MAC_BFF_TIME_EN);
564
565 /* clear backoff time and set software compensation for OBSS time */
566 mask = MT_WF_RMAC_MIB_OBSS_BACKOFF | MT_WF_RMAC_MIB_ED_OFFSET;
567 set = FIELD_PREP(MT_WF_RMAC_MIB_OBSS_BACKOFF, 0) |
568 FIELD_PREP(MT_WF_RMAC_MIB_ED_OFFSET, 4);
569 mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set);
570
571 /* filter out non-resp frames and get instanstaeous signal reporting */
572 mask = MT_WTBLOFF_TOP_RSCR_RCPI_MODE | MT_WTBLOFF_TOP_RSCR_RCPI_PARAM;
573 set = FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_MODE, 0) |
574 FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_PARAM, 0x3);
575 mt76_rmw(dev, MT_WTBLOFF_TOP_RSCR(band), mask, set);
576
577 /* MT_TXD5_TX_STATUS_HOST (MPDU format) has higher priority than
578 * MT_AGG_ACR_PPDU_TXS2H (PPDU format) even though ACR bit is set.
579 */
580 if (mtk_wed_device_active(&dev->mt76.mmio.wed))
581 mt76_set(dev, MT_AGG_ACR4(band), MT_AGG_ACR_PPDU_TXS2H);
582 }
583
584 static void
mt7915_init_led_mux(struct mt7915_dev * dev)585 mt7915_init_led_mux(struct mt7915_dev *dev)
586 {
587 if (!IS_ENABLED(CONFIG_MT76_LEDS))
588 return;
589
590 if (dev->dbdc_support) {
591 switch (mt76_chip(&dev->mt76)) {
592 case 0x7915:
593 mt76_rmw_field(dev, MT_LED_GPIO_MUX2,
594 GENMASK(11, 8), 4);
595 mt76_rmw_field(dev, MT_LED_GPIO_MUX3,
596 GENMASK(11, 8), 4);
597 break;
598 case 0x7986:
599 mt76_rmw_field(dev, MT_LED_GPIO_MUX0,
600 GENMASK(7, 4), 1);
601 mt76_rmw_field(dev, MT_LED_GPIO_MUX0,
602 GENMASK(11, 8), 1);
603 break;
604 case 0x7916:
605 mt76_rmw_field(dev, MT_LED_GPIO_MUX1,
606 GENMASK(27, 24), 3);
607 mt76_rmw_field(dev, MT_LED_GPIO_MUX1,
608 GENMASK(31, 28), 3);
609 break;
610 default:
611 break;
612 }
613 } else if (dev->mphy.leds.pin) {
614 switch (mt76_chip(&dev->mt76)) {
615 case 0x7915:
616 mt76_rmw_field(dev, MT_LED_GPIO_MUX3,
617 GENMASK(11, 8), 4);
618 break;
619 case 0x7986:
620 mt76_rmw_field(dev, MT_LED_GPIO_MUX0,
621 GENMASK(11, 8), 1);
622 break;
623 case 0x7916:
624 mt76_rmw_field(dev, MT_LED_GPIO_MUX1,
625 GENMASK(31, 28), 3);
626 break;
627 default:
628 break;
629 }
630 } else {
631 switch (mt76_chip(&dev->mt76)) {
632 case 0x7915:
633 mt76_rmw_field(dev, MT_LED_GPIO_MUX2,
634 GENMASK(11, 8), 4);
635 break;
636 case 0x7986:
637 mt76_rmw_field(dev, MT_LED_GPIO_MUX0,
638 GENMASK(7, 4), 1);
639 break;
640 case 0x7916:
641 mt76_rmw_field(dev, MT_LED_GPIO_MUX1,
642 GENMASK(27, 24), 3);
643 break;
644 default:
645 break;
646 }
647 }
648 }
649
mt7915_mac_init(struct mt7915_dev * dev)650 void mt7915_mac_init(struct mt7915_dev *dev)
651 {
652 int i;
653 u32 rx_len = is_mt7915(&dev->mt76) ? 0x400 : 0x680;
654
655 /* config pse qid6 wfdma port selection */
656 if (!is_mt7915(&dev->mt76) && dev->hif2)
657 mt76_rmw(dev, MT_WF_PP_TOP_RXQ_WFDMA_CF_5, 0,
658 MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK);
659
660 mt76_rmw_field(dev, MT_MDP_DCR1, MT_MDP_DCR1_MAX_RX_LEN, rx_len);
661
662 if (!is_mt7915(&dev->mt76))
663 mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT);
664 else
665 mt76_clear(dev, MT_PLE_HOST_RPT0, MT_PLE_HOST_RPT0_TX_LATENCY);
666
667 /* enable hardware de-agg */
668 mt76_set(dev, MT_MDP_DCR0, MT_MDP_DCR0_DAMSDU_EN);
669
670 for (i = 0; i < mt7915_wtbl_size(dev); i++)
671 mt7915_mac_wtbl_update(dev, i,
672 MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
673 for (i = 0; i < 2; i++)
674 mt7915_mac_init_band(dev, i);
675
676 mt7915_init_led_mux(dev);
677 }
678
mt7915_txbf_init(struct mt7915_dev * dev)679 int mt7915_txbf_init(struct mt7915_dev *dev)
680 {
681 int ret;
682
683 if (dev->dbdc_support) {
684 ret = mt7915_mcu_set_txbf(dev, MT_BF_MODULE_UPDATE);
685 if (ret)
686 return ret;
687 }
688
689 /* trigger sounding packets */
690 ret = mt7915_mcu_set_txbf(dev, MT_BF_SOUNDING_ON);
691 if (ret)
692 return ret;
693
694 /* enable eBF */
695 return mt7915_mcu_set_txbf(dev, MT_BF_TYPE_UPDATE);
696 }
697
698 static struct mt7915_phy *
mt7915_alloc_ext_phy(struct mt7915_dev * dev)699 mt7915_alloc_ext_phy(struct mt7915_dev *dev)
700 {
701 struct mt7915_phy *phy;
702 struct mt76_phy *mphy;
703
704 if (!dev->dbdc_support)
705 return NULL;
706
707 mphy = mt76_alloc_phy(&dev->mt76, sizeof(*phy), &mt7915_ops, MT_BAND1);
708 if (!mphy)
709 return ERR_PTR(-ENOMEM);
710
711 phy = mphy->priv;
712 phy->dev = dev;
713 phy->mt76 = mphy;
714
715 /* Bind main phy to band0 and ext_phy to band1 for dbdc case */
716 phy->mt76->band_idx = 1;
717
718 return phy;
719 }
720
721 static int
mt7915_register_ext_phy(struct mt7915_dev * dev,struct mt7915_phy * phy)722 mt7915_register_ext_phy(struct mt7915_dev *dev, struct mt7915_phy *phy)
723 {
724 struct mt76_phy *mphy = phy->mt76;
725 int ret;
726
727 INIT_DELAYED_WORK(&mphy->mac_work, mt7915_mac_work);
728
729 mt7915_eeprom_parse_hw_cap(dev, phy);
730
731 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR2,
732 ETH_ALEN);
733 /* Make the secondary PHY MAC address local without overlapping with
734 * the usual MAC address allocation scheme on multiple virtual interfaces
735 */
736 if (!is_valid_ether_addr(mphy->macaddr)) {
737 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR,
738 ETH_ALEN);
739 mphy->macaddr[0] |= 2;
740 mphy->macaddr[0] ^= BIT(7);
741 }
742 ret = mt76_eeprom_override(mphy);
743 if (ret)
744 return ret;
745
746 /* init wiphy according to mphy and phy */
747 mt7915_init_wiphy(phy);
748
749 ret = mt76_register_phy(mphy, true, mt76_rates,
750 ARRAY_SIZE(mt76_rates));
751 if (ret)
752 return ret;
753
754 ret = mt7915_thermal_init(phy);
755 if (ret)
756 goto unreg;
757
758 mt7915_init_debugfs(phy);
759
760 return 0;
761
762 unreg:
763 mt76_unregister_phy(mphy);
764 return ret;
765 }
766
mt7915_init_work(struct work_struct * work)767 static void mt7915_init_work(struct work_struct *work)
768 {
769 struct mt7915_dev *dev = container_of(work, struct mt7915_dev,
770 init_work);
771
772 mt7915_mcu_set_eeprom(dev);
773 mt7915_mac_init(dev);
774 mt7915_txbf_init(dev);
775 }
776
mt7915_wfsys_reset(struct mt7915_dev * dev)777 void mt7915_wfsys_reset(struct mt7915_dev *dev)
778 {
779 #define MT_MCU_DUMMY_RANDOM GENMASK(15, 0)
780 #define MT_MCU_DUMMY_DEFAULT GENMASK(31, 16)
781
782 if (is_mt7915(&dev->mt76)) {
783 u32 val = MT_TOP_PWR_KEY | MT_TOP_PWR_SW_PWR_ON | MT_TOP_PWR_PWR_ON;
784
785 mt76_wr(dev, MT_MCU_WFDMA0_DUMMY_CR, MT_MCU_DUMMY_RANDOM);
786
787 /* change to software control */
788 val |= MT_TOP_PWR_SW_RST;
789 mt76_wr(dev, MT_TOP_PWR_CTRL, val);
790
791 /* reset wfsys */
792 val &= ~MT_TOP_PWR_SW_RST;
793 mt76_wr(dev, MT_TOP_PWR_CTRL, val);
794
795 /* release wfsys then mcu re-executes romcode */
796 val |= MT_TOP_PWR_SW_RST;
797 mt76_wr(dev, MT_TOP_PWR_CTRL, val);
798
799 /* switch to hw control */
800 val &= ~MT_TOP_PWR_SW_RST;
801 val |= MT_TOP_PWR_HW_CTRL;
802 mt76_wr(dev, MT_TOP_PWR_CTRL, val);
803
804 /* check whether mcu resets to default */
805 if (!mt76_poll_msec(dev, MT_MCU_WFDMA0_DUMMY_CR,
806 MT_MCU_DUMMY_DEFAULT, MT_MCU_DUMMY_DEFAULT,
807 1000)) {
808 dev_err(dev->mt76.dev, "wifi subsystem reset failure\n");
809 return;
810 }
811
812 /* wfsys reset won't clear host registers */
813 mt76_clear(dev, MT_TOP_MISC, MT_TOP_MISC_FW_STATE);
814
815 msleep(100);
816 } else if (is_mt798x(&dev->mt76)) {
817 mt7986_wmac_disable(dev);
818 msleep(20);
819
820 mt7986_wmac_enable(dev);
821 msleep(20);
822 } else {
823 mt76_set(dev, MT_WF_SUBSYS_RST, 0x1);
824 msleep(20);
825
826 mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1);
827 msleep(20);
828 }
829 }
830
mt7915_band_config(struct mt7915_dev * dev)831 static bool mt7915_band_config(struct mt7915_dev *dev)
832 {
833 bool ret = true;
834
835 dev->phy.mt76->band_idx = 0;
836
837 if (is_mt798x(&dev->mt76)) {
838 u32 sku = mt7915_check_adie(dev, true);
839
840 /*
841 * for mt7986, dbdc support is determined by the number
842 * of adie chips and the main phy is bound to band1 when
843 * dbdc is disabled.
844 */
845 if (sku == MT7975_ONE_ADIE || sku == MT7976_ONE_ADIE) {
846 dev->phy.mt76->band_idx = 1;
847 ret = false;
848 }
849 } else {
850 ret = is_mt7915(&dev->mt76) ?
851 !!(mt76_rr(dev, MT_HW_BOUND) & BIT(5)) : true;
852 }
853
854 return ret;
855 }
856
857 static int
mt7915_init_hardware(struct mt7915_dev * dev,struct mt7915_phy * phy2)858 mt7915_init_hardware(struct mt7915_dev *dev, struct mt7915_phy *phy2)
859 {
860 int ret, idx;
861
862 mt76_wr(dev, MT_INT_MASK_CSR, 0);
863 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0);
864
865 INIT_WORK(&dev->init_work, mt7915_init_work);
866
867 ret = mt7915_dma_init(dev, phy2);
868 if (ret)
869 return ret;
870
871 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state);
872
873 ret = mt7915_mcu_init(dev);
874 if (ret)
875 return ret;
876
877 ret = mt7915_eeprom_init(dev);
878 if (ret < 0)
879 return ret;
880
881 if (dev->cal) {
882 ret = mt7915_mcu_apply_group_cal(dev);
883 if (ret)
884 return ret;
885 }
886
887 /* Beacon and mgmt frames should occupy wcid 0 */
888 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7915_WTBL_STA);
889 if (idx)
890 return -ENOSPC;
891
892 dev->mt76.global_wcid.idx = idx;
893 dev->mt76.global_wcid.hw_key_idx = -1;
894 dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET;
895 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid);
896
897 return 0;
898 }
899
mt7915_set_stream_vht_txbf_caps(struct mt7915_phy * phy)900 void mt7915_set_stream_vht_txbf_caps(struct mt7915_phy *phy)
901 {
902 int sts;
903 u32 *cap;
904
905 if (!phy->mt76->cap.has_5ghz)
906 return;
907
908 sts = hweight8(phy->mt76->chainmask);
909 cap = &phy->mt76->sband_5g.sband.vht_cap.cap;
910
911 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
912 IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE |
913 FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK,
914 sts - 1);
915
916 *cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK |
917 IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE |
918 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE);
919
920 if (sts < 2)
921 return;
922
923 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE |
924 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE |
925 FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK,
926 sts - 1);
927 }
928
929 static void
mt7915_set_stream_he_txbf_caps(struct mt7915_phy * phy,struct ieee80211_sta_he_cap * he_cap,int vif)930 mt7915_set_stream_he_txbf_caps(struct mt7915_phy *phy,
931 struct ieee80211_sta_he_cap *he_cap, int vif)
932 {
933 struct mt7915_dev *dev = phy->dev;
934 struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem;
935 int sts = hweight8(phy->mt76->chainmask);
936 u8 c, sts_160 = sts;
937
938 /* Can do 1/2 of STS in 160Mhz mode for mt7915 */
939 if (is_mt7915(&dev->mt76)) {
940 if (!dev->dbdc_support)
941 sts_160 /= 2;
942 else
943 sts_160 = 0;
944 }
945
946 #ifdef CONFIG_MAC80211_MESH
947 if (vif == NL80211_IFTYPE_MESH_POINT)
948 return;
949 #endif
950
951 elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER;
952 elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER;
953
954 c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK;
955 if (sts_160)
956 c |= IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK;
957 elem->phy_cap_info[5] &= ~c;
958
959 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
960 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB;
961 elem->phy_cap_info[6] &= ~c;
962
963 elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK;
964
965 c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US;
966 if (!is_mt7915(&dev->mt76))
967 c |= IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO;
968 elem->phy_cap_info[2] |= c;
969
970 c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
971 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4;
972 if (sts_160)
973 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4;
974 elem->phy_cap_info[4] |= c;
975
976 /* do not support NG16 due to spec D4.0 changes subcarrier idx */
977 c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU |
978 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU;
979
980 if (vif == NL80211_IFTYPE_STATION)
981 c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO;
982
983 elem->phy_cap_info[6] |= c;
984
985 if (sts < 2)
986 return;
987
988 /* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */
989 elem->phy_cap_info[7] |= min_t(int, sts - 1, 2) << 3;
990
991 if (vif != NL80211_IFTYPE_AP && vif != NL80211_IFTYPE_STATION)
992 return;
993
994 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER;
995
996 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK,
997 sts - 1);
998 if (sts_160)
999 c |= FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK,
1000 sts_160 - 1);
1001 elem->phy_cap_info[5] |= c;
1002
1003 if (vif != NL80211_IFTYPE_AP)
1004 return;
1005
1006 elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER;
1007
1008 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
1009 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB;
1010 elem->phy_cap_info[6] |= c;
1011
1012 if (!is_mt7915(&dev->mt76)) {
1013 c = IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ |
1014 IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ;
1015 elem->phy_cap_info[7] |= c;
1016 }
1017 }
1018
1019 static int
mt7915_init_he_caps(struct mt7915_phy * phy,enum nl80211_band band,struct ieee80211_sband_iftype_data * data)1020 mt7915_init_he_caps(struct mt7915_phy *phy, enum nl80211_band band,
1021 struct ieee80211_sband_iftype_data *data)
1022 {
1023 struct mt7915_dev *dev = phy->dev;
1024 int i, idx = 0, nss = hweight8(phy->mt76->antenna_mask);
1025 u16 mcs_map = 0;
1026 u16 mcs_map_160 = 0;
1027 u8 nss_160;
1028
1029 if (!is_mt7915(&dev->mt76))
1030 nss_160 = nss;
1031 else if (!dev->dbdc_support)
1032 /* Can do 1/2 of NSS streams in 160Mhz mode for mt7915 */
1033 nss_160 = nss / 2;
1034 else
1035 /* Can't do 160MHz with mt7915 dbdc */
1036 nss_160 = 0;
1037
1038 for (i = 0; i < 8; i++) {
1039 if (i < nss)
1040 mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2));
1041 else
1042 mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2));
1043
1044 if (i < nss_160)
1045 mcs_map_160 |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2));
1046 else
1047 mcs_map_160 |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2));
1048 }
1049
1050 for (i = 0; i < NUM_NL80211_IFTYPES; i++) {
1051 struct ieee80211_sta_he_cap *he_cap = &data[idx].he_cap;
1052 struct ieee80211_he_cap_elem *he_cap_elem =
1053 &he_cap->he_cap_elem;
1054 struct ieee80211_he_mcs_nss_supp *he_mcs =
1055 &he_cap->he_mcs_nss_supp;
1056
1057 switch (i) {
1058 case NL80211_IFTYPE_STATION:
1059 case NL80211_IFTYPE_AP:
1060 #ifdef CONFIG_MAC80211_MESH
1061 case NL80211_IFTYPE_MESH_POINT:
1062 #endif
1063 break;
1064 default:
1065 continue;
1066 }
1067
1068 data[idx].types_mask = BIT(i);
1069 he_cap->has_he = true;
1070
1071 he_cap_elem->mac_cap_info[0] =
1072 IEEE80211_HE_MAC_CAP0_HTC_HE;
1073 he_cap_elem->mac_cap_info[3] =
1074 IEEE80211_HE_MAC_CAP3_OMI_CONTROL |
1075 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3;
1076 he_cap_elem->mac_cap_info[4] =
1077 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU;
1078
1079 if (band == NL80211_BAND_2GHZ)
1080 he_cap_elem->phy_cap_info[0] =
1081 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G;
1082 else if (nss_160)
1083 he_cap_elem->phy_cap_info[0] =
1084 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G |
1085 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G;
1086 else
1087 he_cap_elem->phy_cap_info[0] =
1088 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G;
1089
1090 he_cap_elem->phy_cap_info[1] =
1091 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD;
1092 he_cap_elem->phy_cap_info[2] =
1093 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ |
1094 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ;
1095
1096 switch (i) {
1097 case NL80211_IFTYPE_AP:
1098 he_cap_elem->mac_cap_info[0] |=
1099 IEEE80211_HE_MAC_CAP0_TWT_RES;
1100 he_cap_elem->mac_cap_info[2] |=
1101 IEEE80211_HE_MAC_CAP2_BSR;
1102 he_cap_elem->mac_cap_info[4] |=
1103 IEEE80211_HE_MAC_CAP4_BQR;
1104 he_cap_elem->mac_cap_info[5] |=
1105 IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX;
1106 he_cap_elem->phy_cap_info[3] |=
1107 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK |
1108 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK;
1109 he_cap_elem->phy_cap_info[6] |=
1110 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE |
1111 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT;
1112 he_cap_elem->phy_cap_info[9] |=
1113 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU |
1114 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU;
1115 break;
1116 case NL80211_IFTYPE_STATION:
1117 he_cap_elem->mac_cap_info[1] |=
1118 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US;
1119
1120 if (band == NL80211_BAND_2GHZ)
1121 he_cap_elem->phy_cap_info[0] |=
1122 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G;
1123 else
1124 he_cap_elem->phy_cap_info[0] |=
1125 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G;
1126
1127 he_cap_elem->phy_cap_info[1] |=
1128 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
1129 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US;
1130 he_cap_elem->phy_cap_info[3] |=
1131 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK |
1132 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK;
1133 he_cap_elem->phy_cap_info[6] |=
1134 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB |
1135 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE |
1136 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT;
1137 he_cap_elem->phy_cap_info[7] |=
1138 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP |
1139 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI;
1140 he_cap_elem->phy_cap_info[8] |=
1141 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G |
1142 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484;
1143 if (nss_160)
1144 he_cap_elem->phy_cap_info[8] |=
1145 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
1146 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU;
1147 he_cap_elem->phy_cap_info[9] |=
1148 IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM |
1149 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK |
1150 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU |
1151 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU |
1152 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
1153 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB;
1154 break;
1155 }
1156
1157 memset(he_mcs, 0, sizeof(*he_mcs));
1158 he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map);
1159 he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map);
1160 he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map_160);
1161 he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map_160);
1162
1163 mt7915_set_stream_he_txbf_caps(phy, he_cap, i);
1164
1165 memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres));
1166 if (he_cap_elem->phy_cap_info[6] &
1167 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) {
1168 mt76_connac_gen_ppe_thresh(he_cap->ppe_thres, nss, band);
1169 } else {
1170 he_cap_elem->phy_cap_info[9] |=
1171 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US,
1172 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK);
1173 }
1174
1175 if (band == NL80211_BAND_6GHZ) {
1176 u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS |
1177 IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS;
1178
1179 cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_2,
1180 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) |
1181 u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K,
1182 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) |
1183 u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454,
1184 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN);
1185
1186 data[idx].he_6ghz_capa.capa = cpu_to_le16(cap);
1187 }
1188
1189 idx++;
1190 }
1191
1192 return idx;
1193 }
1194
mt7915_set_stream_he_caps(struct mt7915_phy * phy)1195 void mt7915_set_stream_he_caps(struct mt7915_phy *phy)
1196 {
1197 struct ieee80211_sband_iftype_data *data;
1198 struct ieee80211_supported_band *band;
1199 int n;
1200
1201 if (phy->mt76->cap.has_2ghz) {
1202 data = phy->iftype[NL80211_BAND_2GHZ];
1203 n = mt7915_init_he_caps(phy, NL80211_BAND_2GHZ, data);
1204
1205 band = &phy->mt76->sband_2g.sband;
1206 _ieee80211_set_sband_iftype_data(band, data, n);
1207 }
1208
1209 if (phy->mt76->cap.has_5ghz) {
1210 data = phy->iftype[NL80211_BAND_5GHZ];
1211 n = mt7915_init_he_caps(phy, NL80211_BAND_5GHZ, data);
1212
1213 band = &phy->mt76->sband_5g.sband;
1214 _ieee80211_set_sband_iftype_data(band, data, n);
1215 }
1216
1217 if (phy->mt76->cap.has_6ghz) {
1218 data = phy->iftype[NL80211_BAND_6GHZ];
1219 n = mt7915_init_he_caps(phy, NL80211_BAND_6GHZ, data);
1220
1221 band = &phy->mt76->sband_6g.sband;
1222 _ieee80211_set_sband_iftype_data(band, data, n);
1223 }
1224 }
1225
mt7915_unregister_ext_phy(struct mt7915_dev * dev)1226 static void mt7915_unregister_ext_phy(struct mt7915_dev *dev)
1227 {
1228 struct mt7915_phy *phy = mt7915_ext_phy(dev);
1229 struct mt76_phy *mphy = dev->mt76.phys[MT_BAND1];
1230
1231 if (!phy)
1232 return;
1233
1234 mt7915_unregister_thermal(phy);
1235 mt76_unregister_phy(mphy);
1236 ieee80211_free_hw(mphy->hw);
1237 }
1238
mt7915_stop_hardware(struct mt7915_dev * dev)1239 static void mt7915_stop_hardware(struct mt7915_dev *dev)
1240 {
1241 mt7915_mcu_exit(dev);
1242 mt76_connac2_tx_token_put(&dev->mt76);
1243 mt7915_dma_cleanup(dev);
1244 tasklet_disable(&dev->mt76.irq_tasklet);
1245
1246 if (is_mt798x(&dev->mt76))
1247 mt7986_wmac_disable(dev);
1248 }
1249
mt7915_register_device(struct mt7915_dev * dev)1250 int mt7915_register_device(struct mt7915_dev *dev)
1251 {
1252 struct mt7915_phy *phy2;
1253 int ret;
1254
1255 dev->phy.dev = dev;
1256 dev->phy.mt76 = &dev->mt76.phy;
1257 dev->mt76.phy.priv = &dev->phy;
1258 INIT_WORK(&dev->rc_work, mt7915_mac_sta_rc_work);
1259 INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7915_mac_work);
1260 INIT_LIST_HEAD(&dev->sta_rc_list);
1261 INIT_LIST_HEAD(&dev->twt_list);
1262
1263 init_waitqueue_head(&dev->reset_wait);
1264 INIT_WORK(&dev->reset_work, mt7915_mac_reset_work);
1265 INIT_WORK(&dev->dump_work, mt7915_mac_dump_work);
1266 mutex_init(&dev->dump_mutex);
1267
1268 dev->dbdc_support = mt7915_band_config(dev);
1269
1270 phy2 = mt7915_alloc_ext_phy(dev);
1271 if (IS_ERR(phy2))
1272 return PTR_ERR(phy2);
1273
1274 ret = mt7915_init_hardware(dev, phy2);
1275 if (ret)
1276 goto free_phy2;
1277
1278 mt7915_init_wiphy(&dev->phy);
1279
1280 #ifdef CONFIG_NL80211_TESTMODE
1281 dev->mt76.test_ops = &mt7915_testmode_ops;
1282 #endif
1283
1284 ret = mt76_register_device(&dev->mt76, true, mt76_rates,
1285 ARRAY_SIZE(mt76_rates));
1286 if (ret)
1287 goto stop_hw;
1288
1289 ret = mt7915_thermal_init(&dev->phy);
1290 if (ret)
1291 goto unreg_dev;
1292
1293 if (phy2) {
1294 ret = mt7915_register_ext_phy(dev, phy2);
1295 if (ret)
1296 goto unreg_thermal;
1297 }
1298
1299 ieee80211_queue_work(mt76_hw(dev), &dev->init_work);
1300
1301 dev->recovery.hw_init_done = true;
1302
1303 ret = mt7915_init_debugfs(&dev->phy);
1304 if (ret)
1305 goto unreg_ext_phy;
1306
1307 ret = mt7915_coredump_register(dev);
1308 if (ret)
1309 goto unreg_ext_phy;
1310
1311 return 0;
1312
1313 unreg_ext_phy:
1314 if (phy2) {
1315 mt7915_unregister_ext_phy(dev);
1316 phy2 = NULL;
1317 }
1318 unreg_thermal:
1319 mt7915_unregister_thermal(&dev->phy);
1320 unreg_dev:
1321 mt76_unregister_device(&dev->mt76);
1322 stop_hw:
1323 mt7915_stop_hardware(dev);
1324 free_phy2:
1325 if (phy2)
1326 ieee80211_free_hw(phy2->mt76->hw);
1327 return ret;
1328 }
1329
mt7915_unregister_device(struct mt7915_dev * dev)1330 void mt7915_unregister_device(struct mt7915_dev *dev)
1331 {
1332 cancel_work_sync(&dev->dump_work);
1333 cancel_work_sync(&dev->reset_work);
1334 cancel_work_sync(&dev->rc_work);
1335 mt7915_unregister_ext_phy(dev);
1336 mt7915_coredump_unregister(dev);
1337 mt7915_unregister_thermal(&dev->phy);
1338 mt76_unregister_device(&dev->mt76);
1339 mt7915_stop_hardware(dev);
1340
1341 mt76_free_device(&dev->mt76);
1342 }
1343