1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/etherdevice.h> 5 #include <linux/hwmon.h> 6 #include <linux/hwmon-sysfs.h> 7 #include <linux/of.h> 8 #include <linux/thermal.h> 9 #include "mt7915.h" 10 #include "mac.h" 11 #include "mcu.h" 12 #include "coredump.h" 13 #include "eeprom.h" 14 15 static const struct ieee80211_iface_limit if_limits[] = { 16 { 17 .max = 1, 18 .types = BIT(NL80211_IFTYPE_ADHOC) 19 }, { 20 .max = 16, 21 .types = BIT(NL80211_IFTYPE_AP) 22 #ifdef CONFIG_MAC80211_MESH 23 | BIT(NL80211_IFTYPE_MESH_POINT) 24 #endif 25 }, { 26 .max = MT7915_MAX_INTERFACES, 27 .types = BIT(NL80211_IFTYPE_STATION) 28 } 29 }; 30 31 static const struct ieee80211_iface_combination if_comb[] = { 32 { 33 .limits = if_limits, 34 .n_limits = ARRAY_SIZE(if_limits), 35 .max_interfaces = MT7915_MAX_INTERFACES, 36 .num_different_channels = 1, 37 .beacon_int_infra_match = true, 38 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 39 BIT(NL80211_CHAN_WIDTH_20) | 40 BIT(NL80211_CHAN_WIDTH_40) | 41 BIT(NL80211_CHAN_WIDTH_80) | 42 BIT(NL80211_CHAN_WIDTH_160), 43 } 44 }; 45 46 static ssize_t mt7915_thermal_temp_show(struct device *dev, 47 struct device_attribute *attr, 48 char *buf) 49 { 50 struct mt7915_phy *phy = dev_get_drvdata(dev); 51 int i = to_sensor_dev_attr(attr)->index; 52 int temperature; 53 54 switch (i) { 55 case 0: 56 mutex_lock(&phy->dev->mt76.mutex); 57 temperature = mt7915_mcu_get_temperature(phy); 58 mutex_unlock(&phy->dev->mt76.mutex); 59 if (temperature < 0) 60 return temperature; 61 /* display in millidegree celcius */ 62 return sprintf(buf, "%u\n", temperature * 1000); 63 case 1: 64 case 2: 65 return sprintf(buf, "%u\n", 66 phy->throttle_temp[i - 1] * 1000); 67 case 3: 68 return sprintf(buf, "%hhu\n", phy->throttle_state); 69 default: 70 return -EINVAL; 71 } 72 } 73 74 static ssize_t mt7915_thermal_temp_store(struct device *dev, 75 struct device_attribute *attr, 76 const char *buf, size_t count) 77 { 78 struct mt7915_phy *phy = dev_get_drvdata(dev); 79 int ret, i = to_sensor_dev_attr(attr)->index; 80 long val; 81 82 ret = kstrtol(buf, 10, &val); 83 if (ret < 0) 84 return ret; 85 86 mutex_lock(&phy->dev->mt76.mutex); 87 val = DIV_ROUND_CLOSEST(clamp_val(val, 60 * 1000, 130 * 1000), 1000); 88 89 if ((i - 1 == MT7915_CRIT_TEMP_IDX && 90 val > phy->throttle_temp[MT7915_MAX_TEMP_IDX]) || 91 (i - 1 == MT7915_MAX_TEMP_IDX && 92 val < phy->throttle_temp[MT7915_CRIT_TEMP_IDX])) { 93 dev_err(phy->dev->mt76.dev, 94 "temp1_max shall be greater than temp1_crit."); 95 mutex_unlock(&phy->dev->mt76.mutex); 96 return -EINVAL; 97 } 98 99 phy->throttle_temp[i - 1] = val; 100 ret = mt7915_mcu_set_thermal_protect(phy); 101 mutex_unlock(&phy->dev->mt76.mutex); 102 if (ret) 103 return ret; 104 105 return count; 106 } 107 108 static SENSOR_DEVICE_ATTR_RO(temp1_input, mt7915_thermal_temp, 0); 109 static SENSOR_DEVICE_ATTR_RW(temp1_crit, mt7915_thermal_temp, 1); 110 static SENSOR_DEVICE_ATTR_RW(temp1_max, mt7915_thermal_temp, 2); 111 static SENSOR_DEVICE_ATTR_RO(throttle1, mt7915_thermal_temp, 3); 112 113 static struct attribute *mt7915_hwmon_attrs[] = { 114 &sensor_dev_attr_temp1_input.dev_attr.attr, 115 &sensor_dev_attr_temp1_crit.dev_attr.attr, 116 &sensor_dev_attr_temp1_max.dev_attr.attr, 117 &sensor_dev_attr_throttle1.dev_attr.attr, 118 NULL, 119 }; 120 ATTRIBUTE_GROUPS(mt7915_hwmon); 121 122 static int 123 mt7915_thermal_get_max_throttle_state(struct thermal_cooling_device *cdev, 124 unsigned long *state) 125 { 126 *state = MT7915_CDEV_THROTTLE_MAX; 127 128 return 0; 129 } 130 131 static int 132 mt7915_thermal_get_cur_throttle_state(struct thermal_cooling_device *cdev, 133 unsigned long *state) 134 { 135 struct mt7915_phy *phy = cdev->devdata; 136 137 *state = phy->cdev_state; 138 139 return 0; 140 } 141 142 static int 143 mt7915_thermal_set_cur_throttle_state(struct thermal_cooling_device *cdev, 144 unsigned long state) 145 { 146 struct mt7915_phy *phy = cdev->devdata; 147 u8 throttling = MT7915_THERMAL_THROTTLE_MAX - state; 148 int ret; 149 150 if (state > MT7915_CDEV_THROTTLE_MAX) { 151 dev_err(phy->dev->mt76.dev, 152 "please specify a valid throttling state\n"); 153 return -EINVAL; 154 } 155 156 if (state == phy->cdev_state) 157 return 0; 158 159 /* 160 * cooling_device convention: 0 = no cooling, more = more cooling 161 * mcu convention: 1 = max cooling, more = less cooling 162 */ 163 mutex_lock(&phy->dev->mt76.mutex); 164 ret = mt7915_mcu_set_thermal_throttling(phy, throttling); 165 mutex_unlock(&phy->dev->mt76.mutex); 166 if (ret) 167 return ret; 168 169 phy->cdev_state = state; 170 171 return 0; 172 } 173 174 static const struct thermal_cooling_device_ops mt7915_thermal_ops = { 175 .get_max_state = mt7915_thermal_get_max_throttle_state, 176 .get_cur_state = mt7915_thermal_get_cur_throttle_state, 177 .set_cur_state = mt7915_thermal_set_cur_throttle_state, 178 }; 179 180 static int mt7915_thermal_get_temp(struct thermal_zone_device *tz, int *temp) 181 { 182 struct mt7915_phy *phy = thermal_zone_device_priv(tz); 183 int val; 184 185 mutex_lock(&phy->dev->mt76.mutex); 186 val = mt7915_mcu_get_temperature(phy); 187 mutex_unlock(&phy->dev->mt76.mutex); 188 if (val < 0) 189 return val; 190 191 *temp = val * 1000; 192 return 0; 193 } 194 195 static const struct thermal_zone_device_ops mt7915_tz_ops = { 196 .get_temp = mt7915_thermal_get_temp, 197 }; 198 199 static void mt7915_unregister_thermal(struct mt7915_phy *phy) 200 { 201 struct wiphy *wiphy = phy->mt76->hw->wiphy; 202 203 if (phy->tzone) { 204 devm_thermal_of_zone_unregister(phy->dev->mt76.dev, phy->tzone); 205 phy->tzone = NULL; 206 } 207 208 if (!phy->cdev) 209 return; 210 211 sysfs_remove_link(&wiphy->dev.kobj, "cooling_device"); 212 thermal_cooling_device_unregister(phy->cdev); 213 phy->cdev = NULL; 214 } 215 216 static int mt7915_thermal_init(struct mt7915_phy *phy) 217 { 218 struct wiphy *wiphy = phy->mt76->hw->wiphy; 219 struct thermal_cooling_device *cdev; 220 struct device *hwmon; 221 const char *name; 222 223 name = devm_kasprintf(&wiphy->dev, GFP_KERNEL, "mt7915_%s", 224 wiphy_name(wiphy)); 225 if (!name) 226 return -ENOMEM; 227 228 cdev = thermal_cooling_device_register(name, phy, &mt7915_thermal_ops); 229 if (!IS_ERR(cdev)) { 230 if (sysfs_create_link(&wiphy->dev.kobj, &cdev->device.kobj, 231 "cooling_device") < 0) 232 thermal_cooling_device_unregister(cdev); 233 else 234 phy->cdev = cdev; 235 } 236 237 /* initialize critical/maximum high temperature */ 238 phy->throttle_temp[MT7915_CRIT_TEMP_IDX] = MT7915_CRIT_TEMP; 239 phy->throttle_temp[MT7915_MAX_TEMP_IDX] = MT7915_MAX_TEMP; 240 241 phy->tzone = devm_thermal_of_zone_register(phy->dev->mt76.dev, 242 phy->mt76->band_idx, phy, 243 &mt7915_tz_ops); 244 if (IS_ERR(phy->tzone)) { 245 if (PTR_ERR(phy->tzone) != -ENODEV) 246 dev_warn(phy->dev->mt76.dev, 247 "failed to register thermal zone %d: %ld\n", 248 phy->mt76->band_idx, PTR_ERR(phy->tzone)); 249 phy->tzone = NULL; 250 } 251 252 if (!IS_REACHABLE(CONFIG_HWMON)) 253 return 0; 254 255 hwmon = devm_hwmon_device_register_with_groups(&wiphy->dev, name, phy, 256 mt7915_hwmon_groups); 257 if (IS_ERR(hwmon)) { 258 mt7915_unregister_thermal(phy); 259 return PTR_ERR(hwmon); 260 } 261 262 return 0; 263 } 264 265 static void mt7915_led_set_config(struct led_classdev *led_cdev, 266 u8 delay_on, u8 delay_off) 267 { 268 struct mt7915_dev *dev; 269 struct mt76_phy *mphy; 270 u32 val; 271 272 mphy = container_of(led_cdev, struct mt76_phy, leds.cdev); 273 dev = container_of(mphy->dev, struct mt7915_dev, mt76); 274 275 /* set PWM mode */ 276 val = FIELD_PREP(MT_LED_STATUS_DURATION, 0xffff) | 277 FIELD_PREP(MT_LED_STATUS_OFF, delay_off) | 278 FIELD_PREP(MT_LED_STATUS_ON, delay_on); 279 mt76_wr(dev, MT_LED_STATUS_0(mphy->band_idx), val); 280 mt76_wr(dev, MT_LED_STATUS_1(mphy->band_idx), val); 281 282 /* enable LED */ 283 mt76_wr(dev, MT_LED_EN(mphy->band_idx), 1); 284 285 /* control LED */ 286 val = MT_LED_CTRL_KICK; 287 if (dev->mphy.leds.al) 288 val |= MT_LED_CTRL_POLARITY; 289 if (mphy->band_idx) 290 val |= MT_LED_CTRL_BAND; 291 292 mt76_wr(dev, MT_LED_CTRL(mphy->band_idx), val); 293 mt76_clear(dev, MT_LED_CTRL(mphy->band_idx), MT_LED_CTRL_KICK); 294 } 295 296 static int mt7915_led_set_blink(struct led_classdev *led_cdev, 297 unsigned long *delay_on, 298 unsigned long *delay_off) 299 { 300 u16 delta_on = 0, delta_off = 0; 301 302 #define HW_TICK 10 303 #define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK) 304 305 if (*delay_on) 306 delta_on = TO_HW_TICK(*delay_on); 307 if (*delay_off) 308 delta_off = TO_HW_TICK(*delay_off); 309 310 mt7915_led_set_config(led_cdev, delta_on, delta_off); 311 312 return 0; 313 } 314 315 static void mt7915_led_set_brightness(struct led_classdev *led_cdev, 316 enum led_brightness brightness) 317 { 318 if (!brightness) 319 mt7915_led_set_config(led_cdev, 0, 0xff); 320 else 321 mt7915_led_set_config(led_cdev, 0xff, 0); 322 } 323 324 static void __mt7915_init_txpower(struct mt7915_phy *phy, 325 struct ieee80211_supported_band *sband) 326 { 327 struct mt7915_dev *dev = phy->dev; 328 int i, n_chains = hweight16(phy->mt76->chainmask); 329 int path_delta = mt76_tx_power_path_delta(n_chains); 330 int pwr_delta = mt7915_eeprom_get_power_delta(dev, sband->band); 331 struct mt76_power_limits limits; 332 333 phy->sku_limit_en = true; 334 phy->sku_path_en = true; 335 for (i = 0; i < sband->n_channels; i++) { 336 struct ieee80211_channel *chan = &sband->channels[i]; 337 u32 target_power = 0; 338 int j; 339 340 for (j = 0; j < n_chains; j++) { 341 u32 val; 342 343 val = mt7915_eeprom_get_target_power(dev, chan, j); 344 target_power = max(target_power, val); 345 } 346 347 target_power += pwr_delta; 348 target_power = mt76_get_rate_power_limits(phy->mt76, chan, 349 &limits, 350 target_power); 351 352 /* MT7915N can not enable Backoff table without setting value in dts */ 353 if (!limits.path.ofdm[0]) 354 phy->sku_path_en = false; 355 356 target_power += path_delta; 357 target_power = DIV_ROUND_UP(target_power, 2); 358 chan->max_power = min_t(int, chan->max_reg_power, 359 target_power); 360 chan->orig_mpwr = target_power; 361 } 362 } 363 364 void mt7915_init_txpower(struct mt7915_phy *phy) 365 { 366 if (!phy) 367 return; 368 369 if (phy->mt76->cap.has_2ghz) 370 __mt7915_init_txpower(phy, &phy->mt76->sband_2g.sband); 371 if (phy->mt76->cap.has_5ghz) 372 __mt7915_init_txpower(phy, &phy->mt76->sband_5g.sband); 373 if (phy->mt76->cap.has_6ghz) 374 __mt7915_init_txpower(phy, &phy->mt76->sband_6g.sband); 375 } 376 377 static void 378 mt7915_regd_notifier(struct wiphy *wiphy, 379 struct regulatory_request *request) 380 { 381 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 382 struct mt7915_dev *dev = mt7915_hw_dev(hw); 383 struct mt76_phy *mphy = hw->priv; 384 struct mt7915_phy *phy = mphy->priv; 385 386 memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2)); 387 dev->mt76.region = request->dfs_region; 388 389 if (dev->mt76.region == NL80211_DFS_UNSET) 390 mt7915_mcu_rdd_background_enable(phy, NULL); 391 392 mt7915_init_txpower(phy); 393 394 mphy->dfs_state = MT_DFS_STATE_UNKNOWN; 395 mt7915_dfs_init_radar_detector(phy); 396 } 397 398 static void 399 mt7915_init_wiphy(struct mt7915_phy *phy) 400 { 401 struct mt76_phy *mphy = phy->mt76; 402 struct ieee80211_hw *hw = mphy->hw; 403 struct mt76_dev *mdev = &phy->dev->mt76; 404 struct wiphy *wiphy = hw->wiphy; 405 struct mt7915_dev *dev = phy->dev; 406 407 hw->queues = 4; 408 hw->max_rx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE; 409 hw->max_tx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE; 410 hw->netdev_features = NETIF_F_RXCSUM; 411 412 if (mtk_wed_device_active(&mdev->mmio.wed)) 413 hw->netdev_features |= NETIF_F_HW_TC; 414 415 hw->radiotap_timestamp.units_pos = 416 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US; 417 418 phy->slottime = 9; 419 420 hw->sta_data_size = sizeof(struct mt7915_sta); 421 hw->vif_data_size = sizeof(struct mt7915_vif); 422 423 wiphy->iface_combinations = if_comb; 424 wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); 425 wiphy->reg_notifier = mt7915_regd_notifier; 426 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 427 wiphy->mbssid_max_interfaces = 16; 428 429 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR); 430 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS); 431 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY); 432 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT); 433 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT); 434 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE); 435 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP); 436 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY); 437 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT); 438 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 439 440 if (!is_mt7915(&dev->mt76)) 441 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_STA_TX_PWR); 442 443 if (mt7915_eeprom_has_background_radar(phy->dev) && 444 (!mdev->dev->of_node || 445 !of_property_read_bool(mdev->dev->of_node, 446 "mediatek,disable-radar-background"))) 447 wiphy_ext_feature_set(wiphy, 448 NL80211_EXT_FEATURE_RADAR_BACKGROUND); 449 450 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 451 ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD); 452 ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD); 453 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 454 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 455 ieee80211_hw_set(hw, SUPPORTS_TX_FRAG); 456 457 hw->max_tx_fragments = 4; 458 459 if (phy->mt76->cap.has_2ghz) { 460 phy->mt76->sband_2g.sband.ht_cap.cap |= 461 IEEE80211_HT_CAP_LDPC_CODING | 462 IEEE80211_HT_CAP_MAX_AMSDU; 463 if (is_mt7915(&dev->mt76)) 464 phy->mt76->sband_2g.sband.ht_cap.ampdu_density = 465 IEEE80211_HT_MPDU_DENSITY_4; 466 else 467 phy->mt76->sband_2g.sband.ht_cap.ampdu_density = 468 IEEE80211_HT_MPDU_DENSITY_2; 469 } 470 471 if (phy->mt76->cap.has_5ghz) { 472 struct ieee80211_sta_vht_cap *vht_cap; 473 474 vht_cap = &phy->mt76->sband_5g.sband.vht_cap; 475 phy->mt76->sband_5g.sband.ht_cap.cap |= 476 IEEE80211_HT_CAP_LDPC_CODING | 477 IEEE80211_HT_CAP_MAX_AMSDU; 478 479 if (is_mt7915(&dev->mt76)) { 480 phy->mt76->sband_5g.sband.ht_cap.ampdu_density = 481 IEEE80211_HT_MPDU_DENSITY_4; 482 483 vht_cap->cap |= 484 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991 | 485 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK; 486 487 if (!dev->dbdc_support) 488 vht_cap->cap |= 489 IEEE80211_VHT_CAP_SHORT_GI_160 | 490 FIELD_PREP(IEEE80211_VHT_CAP_EXT_NSS_BW_MASK, 1); 491 } else { 492 phy->mt76->sband_5g.sband.ht_cap.ampdu_density = 493 IEEE80211_HT_MPDU_DENSITY_2; 494 495 vht_cap->cap |= 496 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 497 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK; 498 499 /* mt7916 dbdc with 2g 2x2 bw40 and 5g 2x2 bw160c */ 500 vht_cap->cap |= 501 IEEE80211_VHT_CAP_SHORT_GI_160 | 502 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ; 503 } 504 505 if (!is_mt7915(&dev->mt76) || !dev->dbdc_support) 506 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 507 } 508 509 mt76_set_stream_caps(phy->mt76, true); 510 mt7915_set_stream_vht_txbf_caps(phy); 511 mt7915_set_stream_he_caps(phy); 512 mt7915_init_txpower(phy); 513 514 wiphy->available_antennas_rx = phy->mt76->antenna_mask; 515 wiphy->available_antennas_tx = phy->mt76->antenna_mask; 516 517 /* init led callbacks */ 518 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 519 mphy->leds.cdev.brightness_set = mt7915_led_set_brightness; 520 mphy->leds.cdev.blink_set = mt7915_led_set_blink; 521 } 522 } 523 524 static void 525 mt7915_mac_init_band(struct mt7915_dev *dev, u8 band) 526 { 527 u32 mask, set; 528 529 mt76_rmw_field(dev, MT_TMAC_CTCR0(band), 530 MT_TMAC_CTCR0_INS_DDLMT_REFTIME, 0x3f); 531 mt76_set(dev, MT_TMAC_CTCR0(band), 532 MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN | 533 MT_TMAC_CTCR0_INS_DDLMT_EN); 534 535 mask = MT_MDP_RCFR0_MCU_RX_MGMT | 536 MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR | 537 MT_MDP_RCFR0_MCU_RX_CTL_BAR; 538 set = FIELD_PREP(MT_MDP_RCFR0_MCU_RX_MGMT, MT_MDP_TO_HIF) | 539 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR, MT_MDP_TO_HIF) | 540 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_BAR, MT_MDP_TO_HIF); 541 mt76_rmw(dev, MT_MDP_BNRCFR0(band), mask, set); 542 543 mask = MT_MDP_RCFR1_MCU_RX_BYPASS | 544 MT_MDP_RCFR1_RX_DROPPED_UCAST | 545 MT_MDP_RCFR1_RX_DROPPED_MCAST; 546 set = FIELD_PREP(MT_MDP_RCFR1_MCU_RX_BYPASS, MT_MDP_TO_HIF) | 547 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_UCAST, MT_MDP_TO_HIF) | 548 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_MCAST, MT_MDP_TO_HIF); 549 mt76_rmw(dev, MT_MDP_BNRCFR1(band), mask, set); 550 551 mt76_rmw_field(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_MAX_RX_LEN, 0x680); 552 553 /* mt7915: disable rx rate report by default due to hw issues */ 554 mt76_clear(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_RXD_G5_EN); 555 556 /* clear estimated value of EIFS for Rx duration & OBSS time */ 557 mt76_wr(dev, MT_WF_RMAC_RSVD0(band), MT_WF_RMAC_RSVD0_EIFS_CLR); 558 559 /* clear backoff time for Rx duration */ 560 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME1(band), 561 MT_WF_RMAC_MIB_NONQOSD_BACKOFF); 562 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME3(band), 563 MT_WF_RMAC_MIB_QOS01_BACKOFF); 564 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME4(band), 565 MT_WF_RMAC_MIB_QOS23_BACKOFF); 566 567 /* clear backoff time for Tx duration */ 568 mt76_clear(dev, MT_WTBLOFF_TOP_ACR(band), 569 MT_WTBLOFF_TOP_ADM_BACKOFFTIME); 570 571 /* exclude estimated backoff time for Tx duration on MT7915 */ 572 if (is_mt7915(&dev->mt76)) 573 mt76_set(dev, MT_AGG_ATCR0(band), 574 MT_AGG_ATCR_MAC_BFF_TIME_EN); 575 576 /* clear backoff time and set software compensation for OBSS time */ 577 mask = MT_WF_RMAC_MIB_OBSS_BACKOFF | MT_WF_RMAC_MIB_ED_OFFSET; 578 set = FIELD_PREP(MT_WF_RMAC_MIB_OBSS_BACKOFF, 0) | 579 FIELD_PREP(MT_WF_RMAC_MIB_ED_OFFSET, 4); 580 mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set); 581 582 /* filter out non-resp frames and get instanstaeous signal reporting */ 583 mask = MT_WTBLOFF_TOP_RSCR_RCPI_MODE | MT_WTBLOFF_TOP_RSCR_RCPI_PARAM; 584 set = FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_MODE, 0) | 585 FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_PARAM, 0x3); 586 mt76_rmw(dev, MT_WTBLOFF_TOP_RSCR(band), mask, set); 587 588 /* MT_TXD5_TX_STATUS_HOST (MPDU format) has higher priority than 589 * MT_AGG_ACR_PPDU_TXS2H (PPDU format) even though ACR bit is set. 590 */ 591 if (mtk_wed_device_active(&dev->mt76.mmio.wed)) 592 mt76_set(dev, MT_AGG_ACR4(band), MT_AGG_ACR_PPDU_TXS2H); 593 } 594 595 static void 596 mt7915_init_led_mux(struct mt7915_dev *dev) 597 { 598 if (!IS_ENABLED(CONFIG_MT76_LEDS)) 599 return; 600 601 if (dev->dbdc_support) { 602 switch (mt76_chip(&dev->mt76)) { 603 case 0x7915: 604 mt76_rmw_field(dev, MT_LED_GPIO_MUX2, 605 GENMASK(11, 8), 4); 606 mt76_rmw_field(dev, MT_LED_GPIO_MUX3, 607 GENMASK(11, 8), 4); 608 break; 609 case 0x7986: 610 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 611 GENMASK(7, 4), 1); 612 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 613 GENMASK(11, 8), 1); 614 break; 615 case 0x7916: 616 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 617 GENMASK(27, 24), 3); 618 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 619 GENMASK(31, 28), 3); 620 break; 621 default: 622 break; 623 } 624 } else if (dev->mphy.leds.pin) { 625 switch (mt76_chip(&dev->mt76)) { 626 case 0x7915: 627 mt76_rmw_field(dev, MT_LED_GPIO_MUX3, 628 GENMASK(11, 8), 4); 629 break; 630 case 0x7986: 631 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 632 GENMASK(11, 8), 1); 633 break; 634 case 0x7916: 635 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 636 GENMASK(31, 28), 3); 637 break; 638 default: 639 break; 640 } 641 } else { 642 switch (mt76_chip(&dev->mt76)) { 643 case 0x7915: 644 mt76_rmw_field(dev, MT_LED_GPIO_MUX2, 645 GENMASK(11, 8), 4); 646 break; 647 case 0x7986: 648 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 649 GENMASK(7, 4), 1); 650 break; 651 case 0x7916: 652 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 653 GENMASK(27, 24), 3); 654 break; 655 default: 656 break; 657 } 658 } 659 } 660 661 void mt7915_mac_init(struct mt7915_dev *dev) 662 { 663 int i; 664 u32 rx_len = is_mt7915(&dev->mt76) ? 0x400 : 0x680; 665 666 /* config pse qid6 wfdma port selection */ 667 if (!is_mt7915(&dev->mt76) && dev->hif2) 668 mt76_rmw(dev, MT_WF_PP_TOP_RXQ_WFDMA_CF_5, 0, 669 MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK); 670 671 mt76_rmw_field(dev, MT_MDP_DCR1, MT_MDP_DCR1_MAX_RX_LEN, rx_len); 672 673 if (!is_mt7915(&dev->mt76)) 674 mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT); 675 else 676 mt76_clear(dev, MT_PLE_HOST_RPT0, MT_PLE_HOST_RPT0_TX_LATENCY); 677 678 /* enable hardware de-agg */ 679 mt76_set(dev, MT_MDP_DCR0, MT_MDP_DCR0_DAMSDU_EN); 680 681 for (i = 0; i < mt7915_wtbl_size(dev); i++) 682 mt7915_mac_wtbl_update(dev, i, 683 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 684 for (i = 0; i < 2; i++) 685 mt7915_mac_init_band(dev, i); 686 687 mt7915_init_led_mux(dev); 688 } 689 690 int mt7915_txbf_init(struct mt7915_dev *dev) 691 { 692 int ret; 693 694 if (dev->dbdc_support) { 695 ret = mt7915_mcu_set_txbf(dev, MT_BF_MODULE_UPDATE); 696 if (ret) 697 return ret; 698 } 699 700 /* trigger sounding packets */ 701 ret = mt7915_mcu_set_txbf(dev, MT_BF_SOUNDING_ON); 702 if (ret) 703 return ret; 704 705 /* enable eBF */ 706 return mt7915_mcu_set_txbf(dev, MT_BF_TYPE_UPDATE); 707 } 708 709 static struct mt7915_phy * 710 mt7915_alloc_ext_phy(struct mt7915_dev *dev) 711 { 712 struct mt7915_phy *phy; 713 struct mt76_phy *mphy; 714 715 if (!dev->dbdc_support) 716 return NULL; 717 718 mphy = mt76_alloc_phy(&dev->mt76, sizeof(*phy), &mt7915_ops, MT_BAND1); 719 if (!mphy) 720 return ERR_PTR(-ENOMEM); 721 722 phy = mphy->priv; 723 phy->dev = dev; 724 phy->mt76 = mphy; 725 726 /* Bind main phy to band0 and ext_phy to band1 for dbdc case */ 727 phy->mt76->band_idx = 1; 728 729 return phy; 730 } 731 732 static int 733 mt7915_register_ext_phy(struct mt7915_dev *dev, struct mt7915_phy *phy) 734 { 735 struct mt76_phy *mphy = phy->mt76; 736 int ret; 737 738 INIT_DELAYED_WORK(&mphy->mac_work, mt7915_mac_work); 739 740 mt7915_eeprom_parse_hw_cap(dev, phy); 741 742 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR2, 743 ETH_ALEN); 744 /* Make the secondary PHY MAC address local without overlapping with 745 * the usual MAC address allocation scheme on multiple virtual interfaces 746 */ 747 if (!is_valid_ether_addr(mphy->macaddr)) { 748 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR, 749 ETH_ALEN); 750 mphy->macaddr[0] |= 2; 751 mphy->macaddr[0] ^= BIT(7); 752 } 753 ret = mt76_eeprom_override(mphy); 754 if (ret) 755 return ret; 756 757 /* init wiphy according to mphy and phy */ 758 mt7915_init_wiphy(phy); 759 760 ret = mt76_register_phy(mphy, true, mt76_rates, 761 ARRAY_SIZE(mt76_rates)); 762 if (ret) 763 return ret; 764 765 ret = mt7915_thermal_init(phy); 766 if (ret) 767 goto unreg; 768 769 mt7915_init_debugfs(phy); 770 771 return 0; 772 773 unreg: 774 mt76_unregister_phy(mphy); 775 return ret; 776 } 777 778 static void mt7915_init_work(struct work_struct *work) 779 { 780 struct mt7915_dev *dev = container_of(work, struct mt7915_dev, 781 init_work); 782 783 mt7915_mcu_set_eeprom(dev); 784 mt7915_mac_init(dev); 785 mt7915_txbf_init(dev); 786 } 787 788 void mt7915_wfsys_reset(struct mt7915_dev *dev) 789 { 790 #define MT_MCU_DUMMY_RANDOM GENMASK(15, 0) 791 #define MT_MCU_DUMMY_DEFAULT GENMASK(31, 16) 792 793 if (is_mt7915(&dev->mt76)) { 794 u32 val = MT_TOP_PWR_KEY | MT_TOP_PWR_SW_PWR_ON | MT_TOP_PWR_PWR_ON; 795 796 mt76_wr(dev, MT_MCU_WFDMA0_DUMMY_CR, MT_MCU_DUMMY_RANDOM); 797 798 /* change to software control */ 799 val |= MT_TOP_PWR_SW_RST; 800 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 801 802 /* reset wfsys */ 803 val &= ~MT_TOP_PWR_SW_RST; 804 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 805 806 /* release wfsys then mcu re-executes romcode */ 807 val |= MT_TOP_PWR_SW_RST; 808 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 809 810 /* switch to hw control */ 811 val &= ~MT_TOP_PWR_SW_RST; 812 val |= MT_TOP_PWR_HW_CTRL; 813 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 814 815 /* check whether mcu resets to default */ 816 if (!mt76_poll_msec(dev, MT_MCU_WFDMA0_DUMMY_CR, 817 MT_MCU_DUMMY_DEFAULT, MT_MCU_DUMMY_DEFAULT, 818 1000)) { 819 dev_err(dev->mt76.dev, "wifi subsystem reset failure\n"); 820 return; 821 } 822 823 /* wfsys reset won't clear host registers */ 824 mt76_clear(dev, MT_TOP_MISC, MT_TOP_MISC_FW_STATE); 825 826 msleep(100); 827 } else if (is_mt798x(&dev->mt76)) { 828 mt7986_wmac_disable(dev); 829 msleep(20); 830 831 mt7986_wmac_enable(dev); 832 msleep(20); 833 } else { 834 mt76_set(dev, MT_WF_SUBSYS_RST, 0x1); 835 msleep(20); 836 837 mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1); 838 msleep(20); 839 } 840 } 841 842 static bool mt7915_band_config(struct mt7915_dev *dev) 843 { 844 bool ret = true; 845 846 dev->phy.mt76->band_idx = 0; 847 848 if (is_mt798x(&dev->mt76)) { 849 u32 sku = mt7915_check_adie(dev, true); 850 851 /* 852 * for mt7986, dbdc support is determined by the number 853 * of adie chips and the main phy is bound to band1 when 854 * dbdc is disabled. 855 */ 856 if (sku == MT7975_ONE_ADIE || sku == MT7976_ONE_ADIE) { 857 dev->phy.mt76->band_idx = 1; 858 ret = false; 859 } 860 } else { 861 ret = is_mt7915(&dev->mt76) ? 862 !!(mt76_rr(dev, MT_HW_BOUND) & BIT(5)) : true; 863 } 864 865 return ret; 866 } 867 868 static int 869 mt7915_init_hardware(struct mt7915_dev *dev, struct mt7915_phy *phy2) 870 { 871 int ret, idx; 872 873 mt76_wr(dev, MT_INT_MASK_CSR, 0); 874 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 875 876 INIT_WORK(&dev->init_work, mt7915_init_work); 877 878 ret = mt7915_dma_init(dev, phy2); 879 if (ret) 880 return ret; 881 882 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state); 883 884 ret = mt7915_mcu_init(dev); 885 if (ret) 886 return ret; 887 888 ret = mt7915_eeprom_init(dev); 889 if (ret < 0) 890 return ret; 891 892 if (dev->cal) { 893 ret = mt7915_mcu_apply_group_cal(dev); 894 if (ret) 895 return ret; 896 } 897 898 /* Beacon and mgmt frames should occupy wcid 0 */ 899 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7915_WTBL_STA); 900 if (idx) 901 return -ENOSPC; 902 903 dev->mt76.global_wcid.idx = idx; 904 dev->mt76.global_wcid.hw_key_idx = -1; 905 dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET; 906 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid); 907 908 return 0; 909 } 910 911 void mt7915_set_stream_vht_txbf_caps(struct mt7915_phy *phy) 912 { 913 int sts; 914 u32 *cap; 915 916 if (!phy->mt76->cap.has_5ghz) 917 return; 918 919 sts = hweight8(phy->mt76->chainmask); 920 cap = &phy->mt76->sband_5g.sband.vht_cap.cap; 921 922 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 923 IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 924 FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 925 sts - 1); 926 927 *cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK | 928 IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 929 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE); 930 931 if (sts < 2) 932 return; 933 934 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 935 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE | 936 FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 937 sts - 1); 938 } 939 940 static void 941 mt7915_set_stream_he_txbf_caps(struct mt7915_phy *phy, 942 struct ieee80211_sta_he_cap *he_cap, int vif) 943 { 944 struct mt7915_dev *dev = phy->dev; 945 struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem; 946 int sts = hweight8(phy->mt76->chainmask); 947 u8 c, sts_160 = sts; 948 949 /* Can do 1/2 of STS in 160Mhz mode for mt7915 */ 950 if (is_mt7915(&dev->mt76)) { 951 if (!dev->dbdc_support) 952 sts_160 /= 2; 953 else 954 sts_160 = 0; 955 } 956 957 #ifdef CONFIG_MAC80211_MESH 958 if (vif == NL80211_IFTYPE_MESH_POINT) 959 return; 960 #endif 961 962 elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 963 elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 964 965 c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK; 966 if (sts_160) 967 c |= IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK; 968 elem->phy_cap_info[5] &= ~c; 969 970 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 971 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 972 elem->phy_cap_info[6] &= ~c; 973 974 elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK; 975 976 c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US; 977 if (!is_mt7915(&dev->mt76)) 978 c |= IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO; 979 elem->phy_cap_info[2] |= c; 980 981 c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 982 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; 983 if (sts_160) 984 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 985 elem->phy_cap_info[4] |= c; 986 987 /* do not support NG16 due to spec D4.0 changes subcarrier idx */ 988 c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 989 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU; 990 991 if (vif == NL80211_IFTYPE_STATION) 992 c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO; 993 994 elem->phy_cap_info[6] |= c; 995 996 if (sts < 2) 997 return; 998 999 /* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */ 1000 elem->phy_cap_info[7] |= min_t(int, sts - 1, 2) << 3; 1001 1002 if (vif != NL80211_IFTYPE_AP && vif != NL80211_IFTYPE_STATION) 1003 return; 1004 1005 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 1006 1007 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 1008 sts - 1); 1009 if (sts_160) 1010 c |= FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK, 1011 sts_160 - 1); 1012 elem->phy_cap_info[5] |= c; 1013 1014 if (vif != NL80211_IFTYPE_AP) 1015 return; 1016 1017 elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 1018 1019 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 1020 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 1021 elem->phy_cap_info[6] |= c; 1022 1023 if (!is_mt7915(&dev->mt76)) { 1024 c = IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ | 1025 IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ; 1026 elem->phy_cap_info[7] |= c; 1027 } 1028 } 1029 1030 static int 1031 mt7915_init_he_caps(struct mt7915_phy *phy, enum nl80211_band band, 1032 struct ieee80211_sband_iftype_data *data) 1033 { 1034 struct mt7915_dev *dev = phy->dev; 1035 int i, idx = 0, nss = hweight8(phy->mt76->antenna_mask); 1036 u16 mcs_map = 0; 1037 u16 mcs_map_160 = 0; 1038 u8 nss_160; 1039 1040 if (!is_mt7915(&dev->mt76)) 1041 nss_160 = nss; 1042 else if (!dev->dbdc_support) 1043 /* Can do 1/2 of NSS streams in 160Mhz mode for mt7915 */ 1044 nss_160 = nss / 2; 1045 else 1046 /* Can't do 160MHz with mt7915 dbdc */ 1047 nss_160 = 0; 1048 1049 for (i = 0; i < 8; i++) { 1050 if (i < nss) 1051 mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 1052 else 1053 mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 1054 1055 if (i < nss_160) 1056 mcs_map_160 |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 1057 else 1058 mcs_map_160 |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 1059 } 1060 1061 for (i = 0; i < NUM_NL80211_IFTYPES; i++) { 1062 struct ieee80211_sta_he_cap *he_cap = &data[idx].he_cap; 1063 struct ieee80211_he_cap_elem *he_cap_elem = 1064 &he_cap->he_cap_elem; 1065 struct ieee80211_he_mcs_nss_supp *he_mcs = 1066 &he_cap->he_mcs_nss_supp; 1067 1068 switch (i) { 1069 case NL80211_IFTYPE_STATION: 1070 case NL80211_IFTYPE_AP: 1071 #ifdef CONFIG_MAC80211_MESH 1072 case NL80211_IFTYPE_MESH_POINT: 1073 #endif 1074 break; 1075 default: 1076 continue; 1077 } 1078 1079 data[idx].types_mask = BIT(i); 1080 he_cap->has_he = true; 1081 1082 he_cap_elem->mac_cap_info[0] = 1083 IEEE80211_HE_MAC_CAP0_HTC_HE; 1084 he_cap_elem->mac_cap_info[3] = 1085 IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 1086 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3; 1087 he_cap_elem->mac_cap_info[4] = 1088 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 1089 1090 if (band == NL80211_BAND_2GHZ) 1091 he_cap_elem->phy_cap_info[0] = 1092 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 1093 else if (nss_160) 1094 he_cap_elem->phy_cap_info[0] = 1095 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 1096 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 1097 else 1098 he_cap_elem->phy_cap_info[0] = 1099 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; 1100 1101 he_cap_elem->phy_cap_info[1] = 1102 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD; 1103 he_cap_elem->phy_cap_info[2] = 1104 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 1105 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ; 1106 1107 switch (i) { 1108 case NL80211_IFTYPE_AP: 1109 he_cap_elem->mac_cap_info[0] |= 1110 IEEE80211_HE_MAC_CAP0_TWT_RES; 1111 he_cap_elem->mac_cap_info[2] |= 1112 IEEE80211_HE_MAC_CAP2_BSR; 1113 he_cap_elem->mac_cap_info[4] |= 1114 IEEE80211_HE_MAC_CAP4_BQR; 1115 he_cap_elem->mac_cap_info[5] |= 1116 IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX; 1117 he_cap_elem->phy_cap_info[3] |= 1118 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1119 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1120 he_cap_elem->phy_cap_info[6] |= 1121 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1122 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1123 he_cap_elem->phy_cap_info[9] |= 1124 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1125 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU; 1126 break; 1127 case NL80211_IFTYPE_STATION: 1128 he_cap_elem->mac_cap_info[1] |= 1129 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 1130 1131 if (band == NL80211_BAND_2GHZ) 1132 he_cap_elem->phy_cap_info[0] |= 1133 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G; 1134 else 1135 he_cap_elem->phy_cap_info[0] |= 1136 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G; 1137 1138 he_cap_elem->phy_cap_info[1] |= 1139 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 1140 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 1141 he_cap_elem->phy_cap_info[3] |= 1142 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1143 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1144 he_cap_elem->phy_cap_info[6] |= 1145 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB | 1146 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1147 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1148 he_cap_elem->phy_cap_info[7] |= 1149 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 1150 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI; 1151 he_cap_elem->phy_cap_info[8] |= 1152 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 1153 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484; 1154 if (nss_160) 1155 he_cap_elem->phy_cap_info[8] |= 1156 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 1157 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; 1158 he_cap_elem->phy_cap_info[9] |= 1159 IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 1160 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK | 1161 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1162 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 1163 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 1164 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB; 1165 break; 1166 } 1167 1168 memset(he_mcs, 0, sizeof(*he_mcs)); 1169 he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map); 1170 he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map); 1171 he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map_160); 1172 he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map_160); 1173 1174 mt7915_set_stream_he_txbf_caps(phy, he_cap, i); 1175 1176 memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres)); 1177 if (he_cap_elem->phy_cap_info[6] & 1178 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) { 1179 mt76_connac_gen_ppe_thresh(he_cap->ppe_thres, nss, band); 1180 } else { 1181 he_cap_elem->phy_cap_info[9] |= 1182 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 1183 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 1184 } 1185 1186 if (band == NL80211_BAND_6GHZ) { 1187 u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS | 1188 IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS; 1189 1190 cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_2, 1191 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 1192 u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 1193 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 1194 u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 1195 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 1196 1197 data[idx].he_6ghz_capa.capa = cpu_to_le16(cap); 1198 } 1199 1200 idx++; 1201 } 1202 1203 return idx; 1204 } 1205 1206 void mt7915_set_stream_he_caps(struct mt7915_phy *phy) 1207 { 1208 struct ieee80211_sband_iftype_data *data; 1209 struct ieee80211_supported_band *band; 1210 int n; 1211 1212 if (phy->mt76->cap.has_2ghz) { 1213 data = phy->iftype[NL80211_BAND_2GHZ]; 1214 n = mt7915_init_he_caps(phy, NL80211_BAND_2GHZ, data); 1215 1216 band = &phy->mt76->sband_2g.sband; 1217 _ieee80211_set_sband_iftype_data(band, data, n); 1218 } 1219 1220 if (phy->mt76->cap.has_5ghz) { 1221 data = phy->iftype[NL80211_BAND_5GHZ]; 1222 n = mt7915_init_he_caps(phy, NL80211_BAND_5GHZ, data); 1223 1224 band = &phy->mt76->sband_5g.sband; 1225 _ieee80211_set_sband_iftype_data(band, data, n); 1226 } 1227 1228 if (phy->mt76->cap.has_6ghz) { 1229 data = phy->iftype[NL80211_BAND_6GHZ]; 1230 n = mt7915_init_he_caps(phy, NL80211_BAND_6GHZ, data); 1231 1232 band = &phy->mt76->sband_6g.sband; 1233 _ieee80211_set_sband_iftype_data(band, data, n); 1234 } 1235 } 1236 1237 static void mt7915_unregister_ext_phy(struct mt7915_dev *dev) 1238 { 1239 struct mt7915_phy *phy = mt7915_ext_phy(dev); 1240 struct mt76_phy *mphy = dev->mt76.phys[MT_BAND1]; 1241 1242 if (!phy) 1243 return; 1244 1245 mt7915_unregister_thermal(phy); 1246 mt76_unregister_phy(mphy); 1247 ieee80211_free_hw(mphy->hw); 1248 } 1249 1250 static void mt7915_stop_hardware(struct mt7915_dev *dev) 1251 { 1252 int i; 1253 1254 mt76_for_each_q_rx(&dev->mt76, i) { 1255 if (!mt76_queue_is_wed_rro(&dev->mt76.q_rx[i])) 1256 napi_disable(&dev->mt76.napi[i]); 1257 } 1258 mt7915_mcu_exit(dev); 1259 mt76_connac2_tx_token_put(&dev->mt76); 1260 mt7915_dma_cleanup(dev); 1261 tasklet_disable(&dev->mt76.irq_tasklet); 1262 1263 if (is_mt798x(&dev->mt76)) 1264 mt7986_wmac_disable(dev); 1265 } 1266 1267 int mt7915_register_device(struct mt7915_dev *dev) 1268 { 1269 struct mt7915_phy *phy2; 1270 int ret; 1271 1272 dev->phy.dev = dev; 1273 dev->phy.mt76 = &dev->mt76.phy; 1274 dev->mt76.phy.priv = &dev->phy; 1275 INIT_WORK(&dev->rc_work, mt7915_mac_sta_rc_work); 1276 INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7915_mac_work); 1277 INIT_LIST_HEAD(&dev->sta_rc_list); 1278 INIT_LIST_HEAD(&dev->twt_list); 1279 1280 init_waitqueue_head(&dev->reset_wait); 1281 INIT_WORK(&dev->reset_work, mt7915_mac_reset_work); 1282 INIT_WORK(&dev->dump_work, mt7915_mac_dump_work); 1283 mutex_init(&dev->dump_mutex); 1284 1285 dev->dbdc_support = mt7915_band_config(dev); 1286 1287 phy2 = mt7915_alloc_ext_phy(dev); 1288 if (IS_ERR(phy2)) 1289 return PTR_ERR(phy2); 1290 1291 ret = mt7915_init_hardware(dev, phy2); 1292 if (ret) 1293 goto free_phy2; 1294 1295 mt7915_init_wiphy(&dev->phy); 1296 1297 #ifdef CONFIG_NL80211_TESTMODE 1298 dev->mt76.test_ops = &mt7915_testmode_ops; 1299 #endif 1300 1301 ret = mt76_register_device(&dev->mt76, true, mt76_rates, 1302 ARRAY_SIZE(mt76_rates)); 1303 if (ret) 1304 goto stop_hw; 1305 1306 ret = mt7915_thermal_init(&dev->phy); 1307 if (ret) 1308 goto unreg_dev; 1309 1310 if (phy2) { 1311 ret = mt7915_register_ext_phy(dev, phy2); 1312 if (ret) 1313 goto unreg_thermal; 1314 } 1315 1316 ieee80211_queue_work(mt76_hw(dev), &dev->init_work); 1317 1318 dev->recovery.hw_init_done = true; 1319 1320 ret = mt7915_init_debugfs(&dev->phy); 1321 if (ret) 1322 goto unreg_ext_phy; 1323 1324 ret = mt7915_coredump_register(dev); 1325 if (ret) 1326 goto unreg_ext_phy; 1327 1328 return 0; 1329 1330 unreg_ext_phy: 1331 if (phy2) { 1332 mt7915_unregister_ext_phy(dev); 1333 phy2 = NULL; 1334 } 1335 unreg_thermal: 1336 mt7915_unregister_thermal(&dev->phy); 1337 unreg_dev: 1338 mt76_unregister_device(&dev->mt76); 1339 stop_hw: 1340 mt7915_stop_hardware(dev); 1341 free_phy2: 1342 if (phy2) 1343 ieee80211_free_hw(phy2->mt76->hw); 1344 return ret; 1345 } 1346 1347 void mt7915_unregister_device(struct mt7915_dev *dev) 1348 { 1349 cancel_work_sync(&dev->dump_work); 1350 cancel_work_sync(&dev->reset_work); 1351 cancel_work_sync(&dev->rc_work); 1352 mt7915_unregister_ext_phy(dev); 1353 mt7915_coredump_unregister(dev); 1354 mt7915_unregister_thermal(&dev->phy); 1355 mt76_unregister_device(&dev->mt76); 1356 mt7915_stop_hardware(dev); 1357 1358 mt76_free_device(&dev->mt76); 1359 } 1360