1 // SPDX-License-Identifier: ISC
2 /*
3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
4 */
5
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/pci.h>
9
10 #include "mt76x0.h"
11 #include "mcu.h"
12
mt76x0e_start(struct ieee80211_hw * hw)13 static int mt76x0e_start(struct ieee80211_hw *hw)
14 {
15 struct mt76x02_dev *dev = hw->priv;
16
17 mt76x02_mac_start(dev);
18 mt76x0_phy_calibrate(dev, true);
19 ieee80211_queue_delayed_work(dev->mt76.hw, &dev->mphy.mac_work,
20 MT_MAC_WORK_INTERVAL);
21 ieee80211_queue_delayed_work(dev->mt76.hw, &dev->cal_work,
22 MT_CALIBRATE_INTERVAL);
23 set_bit(MT76_STATE_RUNNING, &dev->mphy.state);
24
25 return 0;
26 }
27
mt76x0e_stop_hw(struct mt76x02_dev * dev)28 static void mt76x0e_stop_hw(struct mt76x02_dev *dev)
29 {
30 cancel_delayed_work_sync(&dev->cal_work);
31 cancel_delayed_work_sync(&dev->mphy.mac_work);
32 clear_bit(MT76_RESTART, &dev->mphy.state);
33
34 if (!mt76_poll(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_BUSY,
35 0, 1000))
36 dev_warn(dev->mt76.dev, "TX DMA did not stop\n");
37 mt76_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_EN);
38
39 mt76x0_mac_stop(dev);
40
41 if (!mt76_poll(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_RX_DMA_BUSY,
42 0, 1000))
43 dev_warn(dev->mt76.dev, "TX DMA did not stop\n");
44 mt76_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_RX_DMA_EN);
45 }
46
mt76x0e_stop(struct ieee80211_hw * hw,bool suspend)47 static void mt76x0e_stop(struct ieee80211_hw *hw, bool suspend)
48 {
49 struct mt76x02_dev *dev = hw->priv;
50
51 clear_bit(MT76_STATE_RUNNING, &dev->mphy.state);
52 mt76x0e_stop_hw(dev);
53 }
54
55 static void
mt76x0e_flush(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u32 queues,bool drop)56 mt76x0e_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
57 u32 queues, bool drop)
58 {
59 }
60
61 static const struct ieee80211_ops mt76x0e_ops = {
62 .add_chanctx = ieee80211_emulate_add_chanctx,
63 .remove_chanctx = ieee80211_emulate_remove_chanctx,
64 .change_chanctx = ieee80211_emulate_change_chanctx,
65 .switch_vif_chanctx = ieee80211_emulate_switch_vif_chanctx,
66 .tx = mt76x02_tx,
67 .start = mt76x0e_start,
68 .stop = mt76x0e_stop,
69 .add_interface = mt76x02_add_interface,
70 .remove_interface = mt76x02_remove_interface,
71 .config = mt76x0_config,
72 .configure_filter = mt76x02_configure_filter,
73 .bss_info_changed = mt76x02_bss_info_changed,
74 .sta_state = mt76_sta_state,
75 .sta_pre_rcu_remove = mt76_sta_pre_rcu_remove,
76 .set_key = mt76x02_set_key,
77 .conf_tx = mt76x02_conf_tx,
78 .sw_scan_start = mt76_sw_scan,
79 .sw_scan_complete = mt76x02_sw_scan_complete,
80 .ampdu_action = mt76x02_ampdu_action,
81 .sta_rate_tbl_update = mt76x02_sta_rate_tbl_update,
82 .wake_tx_queue = mt76_wake_tx_queue,
83 .get_survey = mt76_get_survey,
84 .get_txpower = mt76_get_txpower,
85 .flush = mt76x0e_flush,
86 .set_tim = mt76_set_tim,
87 .release_buffered_frames = mt76_release_buffered_frames,
88 .set_coverage_class = mt76x02_set_coverage_class,
89 .set_rts_threshold = mt76x02_set_rts_threshold,
90 .get_antenna = mt76_get_antenna,
91 .reconfig_complete = mt76x02_reconfig_complete,
92 .set_sar_specs = mt76x0_set_sar_specs,
93 };
94
mt76x0e_init_hardware(struct mt76x02_dev * dev,bool resume)95 static int mt76x0e_init_hardware(struct mt76x02_dev *dev, bool resume)
96 {
97 int err;
98
99 mt76x0_chip_onoff(dev, true, false);
100 if (!mt76x02_wait_for_mac(&dev->mt76))
101 return -ETIMEDOUT;
102
103 mt76x02_dma_disable(dev);
104 err = mt76x0e_mcu_init(dev);
105 if (err < 0)
106 return err;
107
108 if (!resume) {
109 err = mt76x02_dma_init(dev);
110 if (err < 0)
111 return err;
112 }
113
114 err = mt76x0_init_hardware(dev);
115 if (err < 0)
116 return err;
117
118 mt76x02e_init_beacon_config(dev);
119
120 if (mt76_chip(&dev->mt76) == 0x7610) {
121 u16 val;
122
123 mt76_clear(dev, MT_COEXCFG0, BIT(0));
124
125 val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_0);
126 if (!(val & MT_EE_NIC_CONF_0_PA_IO_CURRENT))
127 mt76_set(dev, MT_XO_CTRL7, 0xc03);
128 }
129
130 mt76_clear(dev, 0x110, BIT(9));
131 mt76_set(dev, MT_MAX_LEN_CFG, BIT(13));
132
133 return 0;
134 }
135
mt76x0e_register_device(struct mt76x02_dev * dev)136 static int mt76x0e_register_device(struct mt76x02_dev *dev)
137 {
138 int err;
139
140 err = mt76x0e_init_hardware(dev, false);
141 if (err < 0)
142 return err;
143
144 err = mt76x0_register_device(dev);
145 if (err < 0)
146 return err;
147
148 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state);
149
150 return 0;
151 }
152
153 static int
mt76x0e_probe(struct pci_dev * pdev,const struct pci_device_id * id)154 mt76x0e_probe(struct pci_dev *pdev, const struct pci_device_id *id)
155 {
156 static const struct mt76_driver_ops drv_ops = {
157 .txwi_size = sizeof(struct mt76x02_txwi),
158 .drv_flags = MT_DRV_TX_ALIGNED4_SKBS |
159 MT_DRV_SW_RX_AIRTIME |
160 MT_DRV_IGNORE_TXS_FAILED,
161 .survey_flags = SURVEY_INFO_TIME_TX,
162 .update_survey = mt76x02_update_channel,
163 .set_channel = mt76x0_set_channel,
164 .tx_prepare_skb = mt76x02_tx_prepare_skb,
165 .tx_complete_skb = mt76x02_tx_complete_skb,
166 .rx_skb = mt76x02_queue_rx_skb,
167 .rx_poll_complete = mt76x02_rx_poll_complete,
168 .sta_ps = mt76x02_sta_ps,
169 .sta_add = mt76x02_sta_add,
170 .sta_remove = mt76x02_sta_remove,
171 };
172 struct mt76x02_dev *dev;
173 struct mt76_dev *mdev;
174 int ret;
175
176 ret = pcim_enable_device(pdev);
177 if (ret)
178 return ret;
179
180 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
181 if (ret)
182 return ret;
183
184 pci_set_master(pdev);
185
186 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
187 if (ret)
188 return ret;
189
190 mt76_pci_disable_aspm(pdev);
191
192 mdev = mt76_alloc_device(&pdev->dev, sizeof(*dev), &mt76x0e_ops,
193 &drv_ops);
194 if (!mdev)
195 return -ENOMEM;
196
197 dev = container_of(mdev, struct mt76x02_dev, mt76);
198 mutex_init(&dev->phy_mutex);
199
200 mt76_mmio_init(mdev, pcim_iomap_table(pdev)[0]);
201
202 mdev->rev = mt76_rr(dev, MT_ASIC_VERSION);
203 dev_info(mdev->dev, "ASIC revision: %08x\n", mdev->rev);
204
205 mt76_wr(dev, MT_INT_MASK_CSR, 0);
206
207 ret = devm_request_irq(mdev->dev, pdev->irq, mt76x02_irq_handler,
208 IRQF_SHARED, KBUILD_MODNAME, dev);
209 if (ret)
210 goto error;
211
212 ret = mt76x0e_register_device(dev);
213 if (ret < 0)
214 goto error;
215
216 return 0;
217
218 error:
219 mt76_free_device(&dev->mt76);
220
221 return ret;
222 }
223
mt76x0e_cleanup(struct mt76x02_dev * dev)224 static void mt76x0e_cleanup(struct mt76x02_dev *dev)
225 {
226 clear_bit(MT76_STATE_INITIALIZED, &dev->mphy.state);
227 tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
228 mt76x0_chip_onoff(dev, false, false);
229 mt76x0e_stop_hw(dev);
230 mt76_dma_cleanup(&dev->mt76);
231 mt76x02_mcu_cleanup(dev);
232 }
233
234 static void
mt76x0e_remove(struct pci_dev * pdev)235 mt76x0e_remove(struct pci_dev *pdev)
236 {
237 struct mt76_dev *mdev = pci_get_drvdata(pdev);
238 struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76);
239
240 mt76_unregister_device(mdev);
241 mt76x0e_cleanup(dev);
242 mt76_free_device(mdev);
243 }
244
245 #ifdef CONFIG_PM
mt76x0e_suspend(struct pci_dev * pdev,pm_message_t state)246 static int mt76x0e_suspend(struct pci_dev *pdev, pm_message_t state)
247 {
248 struct mt76_dev *mdev = pci_get_drvdata(pdev);
249 struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76);
250 int i;
251
252 mt76_worker_disable(&mdev->tx_worker);
253 for (i = 0; i < ARRAY_SIZE(mdev->phy.q_tx); i++)
254 mt76_queue_tx_cleanup(dev, mdev->phy.q_tx[i], true);
255 for (i = 0; i < ARRAY_SIZE(mdev->q_mcu); i++)
256 mt76_queue_tx_cleanup(dev, mdev->q_mcu[i], true);
257 napi_disable(&mdev->tx_napi);
258
259 mt76_for_each_q_rx(mdev, i)
260 napi_disable(&mdev->napi[i]);
261
262 mt76x02_dma_disable(dev);
263 mt76x02_mcu_cleanup(dev);
264 mt76x0_chip_onoff(dev, false, false);
265
266 pci_enable_wake(pdev, pci_choose_state(pdev, state), true);
267 pci_save_state(pdev);
268
269 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
270 }
271
mt76x0e_resume(struct pci_dev * pdev)272 static int mt76x0e_resume(struct pci_dev *pdev)
273 {
274 struct mt76_dev *mdev = pci_get_drvdata(pdev);
275 struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76);
276 int err, i;
277
278 err = pci_set_power_state(pdev, PCI_D0);
279 if (err)
280 return err;
281
282 pci_restore_state(pdev);
283
284 mt76_worker_enable(&mdev->tx_worker);
285
286 mt76_for_each_q_rx(mdev, i) {
287 mt76_queue_rx_reset(dev, i);
288 napi_enable(&mdev->napi[i]);
289 }
290 napi_enable(&mdev->tx_napi);
291
292 local_bh_disable();
293 mt76_for_each_q_rx(mdev, i) {
294 napi_schedule(&mdev->napi[i]);
295 }
296 napi_schedule(&mdev->tx_napi);
297 local_bh_enable();
298
299 return mt76x0e_init_hardware(dev, true);
300 }
301 #endif /* CONFIG_PM */
302
303 static const struct pci_device_id mt76x0e_device_table[] = {
304 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7610) },
305 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7630) },
306 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7650) },
307 { },
308 };
309
310 MODULE_DEVICE_TABLE(pci, mt76x0e_device_table);
311 MODULE_FIRMWARE(MT7610E_FIRMWARE);
312 MODULE_FIRMWARE(MT7650E_FIRMWARE);
313 MODULE_DESCRIPTION("MediaTek MT76x0E (PCIe) wireless driver");
314 MODULE_LICENSE("Dual BSD/GPL");
315
316 static struct pci_driver mt76x0e_driver = {
317 .name = KBUILD_MODNAME,
318 .id_table = mt76x0e_device_table,
319 .probe = mt76x0e_probe,
320 .remove = mt76x0e_remove,
321 #ifdef CONFIG_PM
322 .suspend = mt76x0e_suspend,
323 .resume = mt76x0e_resume,
324 #endif /* CONFIG_PM */
325 };
326
327 module_pci_driver(mt76x0e_driver);
328