1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 *
4 * Copyright (C) 2015 Nikolay Martynov <mar.kolya@gmail.com>
5 * Copyright (C) 2015 John Crispin <john@phrozen.org>
6 */
7
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/slab.h>
11 #include <linux/sys_soc.h>
12 #include <linux/memblock.h>
13 #include <linux/pci.h>
14 #include <linux/bug.h>
15
16 #include <asm/bootinfo.h>
17 #include <asm/mipsregs.h>
18 #include <asm/smp-ops.h>
19 #include <asm/mips-cps.h>
20 #include <asm/mach-ralink/ralink_regs.h>
21 #include <asm/mach-ralink/mt7621.h>
22
23 #include "common.h"
24
25 #define MT7621_MEM_TEST_PATTERN 0xaa5555aa
26
27 static u32 detect_magic __initdata;
28 static struct ralink_soc_info *soc_info_ptr;
29
pcibios_root_bridge_prepare(struct pci_host_bridge * bridge)30 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
31 {
32 struct resource_entry *entry;
33 resource_size_t mask;
34
35 entry = resource_list_first_type(&bridge->windows, IORESOURCE_MEM);
36 if (!entry) {
37 pr_err("Cannot get memory resource\n");
38 return -EINVAL;
39 }
40
41 if (mips_cps_numiocu(0)) {
42 /*
43 * Hardware doesn't accept mask values with 1s after
44 * 0s (e.g. 0xffef), so warn if that's happen
45 */
46 mask = ~(entry->res->end - entry->res->start) & CM_GCR_REGn_MASK_ADDRMASK;
47 WARN_ON(mask && BIT(ffz(~mask)) - 1 != ~mask);
48
49 write_gcr_reg1_base(entry->res->start);
50 write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
51 pr_info("PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
52 (unsigned long long)read_gcr_reg1_base(),
53 (unsigned long long)read_gcr_reg1_mask());
54 }
55
56 return 0;
57 }
58
mips_cpc_default_phys_base(void)59 phys_addr_t mips_cpc_default_phys_base(void)
60 {
61 panic("Cannot detect cpc address");
62 }
63
mt7621_addr_wraparound_test(phys_addr_t size)64 static bool __init mt7621_addr_wraparound_test(phys_addr_t size)
65 {
66 void *dm = (void *)KSEG1ADDR(&detect_magic);
67
68 if (CPHYSADDR(dm + size) >= MT7621_LOWMEM_MAX_SIZE)
69 return true;
70 __raw_writel(MT7621_MEM_TEST_PATTERN, dm);
71 if (__raw_readl(dm) != __raw_readl(dm + size))
72 return false;
73 __raw_writel(~MT7621_MEM_TEST_PATTERN, dm);
74 return __raw_readl(dm) == __raw_readl(dm + size);
75 }
76
mt7621_memory_detect(void)77 static void __init mt7621_memory_detect(void)
78 {
79 phys_addr_t size;
80
81 for (size = 32 * SZ_1M; size <= 256 * SZ_1M; size <<= 1) {
82 if (mt7621_addr_wraparound_test(size)) {
83 memblock_add(MT7621_LOWMEM_BASE, size);
84 return;
85 }
86 }
87
88 memblock_add(MT7621_LOWMEM_BASE, MT7621_LOWMEM_MAX_SIZE);
89 memblock_add(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE);
90 }
91
mt7621_get_soc_name0(void)92 static unsigned int __init mt7621_get_soc_name0(void)
93 {
94 return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_NAME0);
95 }
96
mt7621_get_soc_name1(void)97 static unsigned int __init mt7621_get_soc_name1(void)
98 {
99 return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_NAME1);
100 }
101
mt7621_soc_valid(void)102 static bool __init mt7621_soc_valid(void)
103 {
104 if (mt7621_get_soc_name0() == MT7621_CHIP_NAME0 &&
105 mt7621_get_soc_name1() == MT7621_CHIP_NAME1)
106 return true;
107 else
108 return false;
109 }
110
mt7621_get_soc_id(void)111 static const char __init *mt7621_get_soc_id(void)
112 {
113 if (mt7621_soc_valid())
114 return "MT7621";
115 else
116 return "invalid";
117 }
118
mt7621_get_soc_rev(void)119 static unsigned int __init mt7621_get_soc_rev(void)
120 {
121 return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_REV);
122 }
123
mt7621_get_soc_ver(void)124 static unsigned int __init mt7621_get_soc_ver(void)
125 {
126 return (mt7621_get_soc_rev() >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK;
127 }
128
mt7621_get_soc_eco(void)129 static unsigned int __init mt7621_get_soc_eco(void)
130 {
131 return (mt7621_get_soc_rev() & CHIP_REV_ECO_MASK);
132 }
133
mt7621_get_soc_revision(void)134 static const char __init *mt7621_get_soc_revision(void)
135 {
136 if (mt7621_get_soc_rev() == 1 && mt7621_get_soc_eco() == 1)
137 return "E2";
138 else
139 return "E1";
140 }
141
mt7621_soc_dev_init(void)142 static int __init mt7621_soc_dev_init(void)
143 {
144 struct soc_device *soc_dev;
145 struct soc_device_attribute *soc_dev_attr;
146
147 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
148 if (!soc_dev_attr)
149 return -ENOMEM;
150
151 soc_dev_attr->soc_id = "mt7621";
152 soc_dev_attr->family = "Ralink";
153 soc_dev_attr->revision = mt7621_get_soc_revision();
154
155 soc_dev_attr->data = soc_info_ptr;
156
157 soc_dev = soc_device_register(soc_dev_attr);
158 if (IS_ERR(soc_dev)) {
159 kfree(soc_dev_attr);
160 return PTR_ERR(soc_dev);
161 }
162
163 return 0;
164 }
165 device_initcall(mt7621_soc_dev_init);
166
prom_soc_init(struct ralink_soc_info * soc_info)167 void __init prom_soc_init(struct ralink_soc_info *soc_info)
168 {
169 /* Early detection of CMP support */
170 mips_cm_probe();
171 mips_cpc_probe();
172
173 if (mips_cps_numiocu(0)) {
174 /*
175 * mips_cm_probe() wipes out bootloader
176 * config for CM regions and we have to configure them
177 * again. This SoC cannot talk to pamlbus devices
178 * without proper iocu region set up.
179 *
180 * FIXME: it would be better to do this with values
181 * from DT, but we need this very early because
182 * without this we cannot talk to pretty much anything
183 * including serial.
184 */
185 write_gcr_reg0_base(MT7621_PALMBUS_BASE);
186 write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE |
187 CM_GCR_REGn_MASK_CMTGT_IOCU0);
188 __sync();
189 }
190
191 if (mt7621_soc_valid())
192 soc_info->compatible = "mediatek,mt7621-soc";
193 else
194 panic("mt7621: unknown SoC, n0:%08x n1:%08x\n",
195 mt7621_get_soc_name0(),
196 mt7621_get_soc_name1());
197 ralink_soc = MT762X_SOC_MT7621AT;
198
199 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
200 "MediaTek %s ver:%u eco:%u",
201 mt7621_get_soc_id(),
202 mt7621_get_soc_ver(),
203 mt7621_get_soc_eco());
204
205 soc_info->mem_detect = mt7621_memory_detect;
206
207 soc_info_ptr = soc_info;
208
209 if (!register_cps_smp_ops())
210 return;
211 if (!register_vsmp_smp_ops())
212 return;
213 }
214