1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Copyright (c) 2021 MediaTek Inc. 4 5 #include <linux/platform_device.h> 6 #include <linux/mfd/mt6359/registers.h> 7 #include <linux/mfd/mt6359p/registers.h> 8 #include <linux/mfd/mt6397/core.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/regmap.h> 12 #include <linux/regulator/driver.h> 13 #include <linux/regulator/machine.h> 14 #include <linux/regulator/mt6359-regulator.h> 15 #include <linux/regulator/of_regulator.h> 16 17 #define MT6359_BUCK_MODE_AUTO 0 18 #define MT6359_BUCK_MODE_FORCE_PWM 1 19 #define MT6359_BUCK_MODE_NORMAL 0 20 #define MT6359_BUCK_MODE_LP 2 21 22 /* 23 * MT6359 regulators' information 24 * 25 * @desc: standard fields of regulator description. 26 * @status_reg: for query status of regulators. 27 * @qi: Mask for query enable signal status of regulators. 28 * @modeset_reg: for operating AUTO/PWM mode register. 29 * @modeset_mask: MASK for operating modeset register. 30 */ 31 struct mt6359_regulator_info { 32 struct regulator_desc desc; 33 u32 status_reg; 34 u32 qi; 35 u32 modeset_reg; 36 u32 modeset_mask; 37 u32 lp_mode_reg; 38 u32 lp_mode_mask; 39 }; 40 41 #define MT6359_BUCK(match, _name, supply, min, max, step, \ 42 _enable_reg, _status_reg, \ 43 _vsel_reg, _vsel_mask, \ 44 _lp_mode_reg, _lp_mode_shift, \ 45 _modeset_reg, _modeset_shift) \ 46 [MT6359_ID_##_name] = { \ 47 .desc = { \ 48 .name = #_name, \ 49 .supply_name = supply, \ 50 .of_match = of_match_ptr(match), \ 51 .regulators_node = of_match_ptr("regulators"), \ 52 .ops = &mt6359_volt_linear_ops, \ 53 .type = REGULATOR_VOLTAGE, \ 54 .id = MT6359_ID_##_name, \ 55 .owner = THIS_MODULE, \ 56 .uV_step = (step), \ 57 .n_voltages = ((max) - (min)) / (step) + 1, \ 58 .min_uV = (min), \ 59 .vsel_reg = _vsel_reg, \ 60 .vsel_mask = _vsel_mask, \ 61 .enable_reg = _enable_reg, \ 62 .enable_mask = BIT(0), \ 63 .of_map_mode = mt6359_map_mode, \ 64 }, \ 65 .status_reg = _status_reg, \ 66 .qi = BIT(0), \ 67 .lp_mode_reg = _lp_mode_reg, \ 68 .lp_mode_mask = BIT(_lp_mode_shift), \ 69 .modeset_reg = _modeset_reg, \ 70 .modeset_mask = BIT(_modeset_shift), \ 71 } 72 73 #define MT6359_LDO_LINEAR(match, _name, supply, min, max, step, \ 74 _enable_reg, _status_reg, _vsel_reg, _vsel_mask) \ 75 [MT6359_ID_##_name] = { \ 76 .desc = { \ 77 .name = #_name, \ 78 .supply_name = supply, \ 79 .of_match = of_match_ptr(match), \ 80 .regulators_node = of_match_ptr("regulators"), \ 81 .ops = &mt6359_volt_linear_ops, \ 82 .type = REGULATOR_VOLTAGE, \ 83 .id = MT6359_ID_##_name, \ 84 .owner = THIS_MODULE, \ 85 .uV_step = (step), \ 86 .n_voltages = ((max) - (min)) / (step) + 1, \ 87 .min_uV = (min), \ 88 .vsel_reg = _vsel_reg, \ 89 .vsel_mask = _vsel_mask, \ 90 .enable_reg = _enable_reg, \ 91 .enable_mask = BIT(0), \ 92 }, \ 93 .status_reg = _status_reg, \ 94 .qi = BIT(0), \ 95 } 96 97 #define MT6359_LDO(match, _name, supply, _volt_table, \ 98 _enable_reg, _enable_mask, _status_reg, \ 99 _vsel_reg, _vsel_mask, _en_delay) \ 100 [MT6359_ID_##_name] = { \ 101 .desc = { \ 102 .name = #_name, \ 103 .supply_name = supply, \ 104 .of_match = of_match_ptr(match), \ 105 .regulators_node = of_match_ptr("regulators"), \ 106 .ops = &mt6359_volt_table_ops, \ 107 .type = REGULATOR_VOLTAGE, \ 108 .id = MT6359_ID_##_name, \ 109 .owner = THIS_MODULE, \ 110 .n_voltages = ARRAY_SIZE(_volt_table), \ 111 .volt_table = _volt_table, \ 112 .vsel_reg = _vsel_reg, \ 113 .vsel_mask = _vsel_mask, \ 114 .enable_reg = _enable_reg, \ 115 .enable_mask = BIT(_enable_mask), \ 116 .enable_time = _en_delay, \ 117 }, \ 118 .status_reg = _status_reg, \ 119 .qi = BIT(0), \ 120 } 121 122 #define MT6359_REG_FIXED(match, _name, supply, \ 123 _enable_reg, _status_reg, \ 124 _fixed_volt) \ 125 [MT6359_ID_##_name] = { \ 126 .desc = { \ 127 .name = #_name, \ 128 .supply_name = supply, \ 129 .of_match = of_match_ptr(match), \ 130 .regulators_node = of_match_ptr("regulators"), \ 131 .ops = &mt6359_volt_fixed_ops, \ 132 .type = REGULATOR_VOLTAGE, \ 133 .id = MT6359_ID_##_name, \ 134 .owner = THIS_MODULE, \ 135 .n_voltages = 1, \ 136 .enable_reg = _enable_reg, \ 137 .enable_mask = BIT(0), \ 138 .fixed_uV = (_fixed_volt), \ 139 }, \ 140 .status_reg = _status_reg, \ 141 .qi = BIT(0), \ 142 } 143 144 #define MT6359P_LDO1(match, _name, supply, _ops, \ 145 _volt_table, _enable_reg, \ 146 _enable_mask, _status_reg, \ 147 _vsel_reg, _vsel_mask) \ 148 [MT6359_ID_##_name] = { \ 149 .desc = { \ 150 .name = #_name, \ 151 .supply_name = supply, \ 152 .of_match = of_match_ptr(match), \ 153 .regulators_node = of_match_ptr("regulators"), \ 154 .ops = &_ops, \ 155 .type = REGULATOR_VOLTAGE, \ 156 .id = MT6359_ID_##_name, \ 157 .owner = THIS_MODULE, \ 158 .n_voltages = ARRAY_SIZE(_volt_table), \ 159 .volt_table = _volt_table, \ 160 .vsel_reg = _vsel_reg, \ 161 .vsel_mask = _vsel_mask, \ 162 .enable_reg = _enable_reg, \ 163 .enable_mask = BIT(_enable_mask), \ 164 }, \ 165 .status_reg = _status_reg, \ 166 .qi = BIT(0), \ 167 } 168 169 #define MT6359_LDO_NOOP(match, _name, supply) \ 170 [MT6359_ID_##_name] = { \ 171 .desc = { \ 172 .name = #_name, \ 173 .supply_name = supply, \ 174 .of_match = of_match_ptr(match), \ 175 .regulators_node = of_match_ptr("regulators"), \ 176 .ops = &mt6359_noop_ops, \ 177 .type = REGULATOR_VOLTAGE, \ 178 .id = MT6359_ID_##_name, \ 179 .owner = THIS_MODULE, \ 180 }, \ 181 } 182 183 static const unsigned int vsim1_voltages[] = { 184 0, 0, 0, 1700000, 1800000, 0, 0, 0, 2700000, 0, 0, 3000000, 3100000, 185 }; 186 187 static const unsigned int vibr_voltages[] = { 188 1200000, 1300000, 1500000, 0, 1800000, 2000000, 0, 0, 2700000, 2800000, 189 0, 3000000, 0, 3300000, 190 }; 191 192 static const unsigned int vrf12_voltages[] = { 193 0, 0, 1100000, 1200000, 1300000, 194 }; 195 196 static const unsigned int volt18_voltages[] = { 197 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1700000, 1800000, 1900000, 198 }; 199 200 static const unsigned int vcn13_voltages[] = { 201 900000, 1000000, 0, 1200000, 1300000, 202 }; 203 204 static const unsigned int vcn33_voltages[] = { 205 0, 0, 0, 0, 0, 0, 0, 0, 0, 2800000, 0, 0, 0, 3300000, 3400000, 3500000, 206 }; 207 208 static const unsigned int vefuse_voltages[] = { 209 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1700000, 1800000, 1900000, 2000000, 210 }; 211 212 static const unsigned int vxo22_voltages[] = { 213 1800000, 0, 0, 0, 2200000, 214 }; 215 216 static const unsigned int vrfck_voltages[] = { 217 0, 0, 1500000, 0, 0, 0, 0, 1600000, 0, 0, 0, 0, 1700000, 218 }; 219 220 static const unsigned int vrfck_voltages_1[] = { 221 1240000, 1600000, 222 }; 223 224 static const unsigned int vio28_voltages[] = { 225 0, 0, 0, 0, 0, 0, 0, 0, 0, 2800000, 2900000, 3000000, 3100000, 3300000, 226 }; 227 228 static const unsigned int vemc_voltages[] = { 229 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2900000, 3000000, 0, 3300000, 230 }; 231 232 static const unsigned int vemc_voltages_1[] = { 233 0, 0, 0, 0, 0, 0, 0, 0, 2500000, 2800000, 2900000, 3000000, 3100000, 234 3300000, 235 }; 236 237 static const unsigned int va12_voltages[] = { 238 0, 0, 0, 0, 0, 0, 1200000, 1300000, 239 }; 240 241 static const unsigned int va09_voltages[] = { 242 0, 0, 800000, 900000, 0, 0, 1200000, 243 }; 244 245 static const unsigned int vrf18_voltages[] = { 246 0, 0, 0, 0, 0, 1700000, 1800000, 1810000, 247 }; 248 249 static const unsigned int vbbck_voltages[] = { 250 0, 0, 0, 0, 1100000, 0, 0, 0, 1150000, 0, 0, 0, 1200000, 251 }; 252 253 static const unsigned int vsim2_voltages[] = { 254 0, 0, 0, 1700000, 1800000, 0, 0, 0, 2700000, 0, 0, 3000000, 3100000, 255 }; 256 257 static inline unsigned int mt6359_map_mode(unsigned int mode) 258 { 259 switch (mode) { 260 case MT6359_BUCK_MODE_NORMAL: 261 return REGULATOR_MODE_NORMAL; 262 case MT6359_BUCK_MODE_FORCE_PWM: 263 return REGULATOR_MODE_FAST; 264 case MT6359_BUCK_MODE_LP: 265 return REGULATOR_MODE_IDLE; 266 default: 267 return REGULATOR_MODE_INVALID; 268 } 269 } 270 271 static int mt6359_get_status(struct regulator_dev *rdev) 272 { 273 int ret; 274 u32 regval; 275 const struct mt6359_regulator_info *info = rdev_get_drvdata(rdev); 276 277 ret = regmap_read(rdev->regmap, info->status_reg, ®val); 278 if (ret != 0) { 279 dev_err(&rdev->dev, "Failed to get enable reg: %d\n", ret); 280 return ret; 281 } 282 283 if (regval & info->qi) 284 return REGULATOR_STATUS_ON; 285 else 286 return REGULATOR_STATUS_OFF; 287 } 288 289 static unsigned int mt6359_regulator_get_mode(struct regulator_dev *rdev) 290 { 291 const struct mt6359_regulator_info *info = rdev_get_drvdata(rdev); 292 int ret, regval; 293 294 ret = regmap_read(rdev->regmap, info->modeset_reg, ®val); 295 if (ret != 0) { 296 dev_err(&rdev->dev, 297 "Failed to get mt6359 buck mode: %d\n", ret); 298 return ret; 299 } 300 301 regval &= info->modeset_mask; 302 regval >>= ffs(info->modeset_mask) - 1; 303 304 if (regval == MT6359_BUCK_MODE_FORCE_PWM) 305 return REGULATOR_MODE_FAST; 306 307 ret = regmap_read(rdev->regmap, info->lp_mode_reg, ®val); 308 if (ret != 0) { 309 dev_err(&rdev->dev, 310 "Failed to get mt6359 buck lp mode: %d\n", ret); 311 return ret; 312 } 313 314 if (regval & info->lp_mode_mask) 315 return REGULATOR_MODE_IDLE; 316 else 317 return REGULATOR_MODE_NORMAL; 318 } 319 320 static int mt6359_regulator_set_mode(struct regulator_dev *rdev, 321 unsigned int mode) 322 { 323 const struct mt6359_regulator_info *info = rdev_get_drvdata(rdev); 324 int ret = 0, val; 325 int curr_mode; 326 327 curr_mode = mt6359_regulator_get_mode(rdev); 328 switch (mode) { 329 case REGULATOR_MODE_FAST: 330 val = MT6359_BUCK_MODE_FORCE_PWM; 331 val <<= ffs(info->modeset_mask) - 1; 332 ret = regmap_update_bits(rdev->regmap, 333 info->modeset_reg, 334 info->modeset_mask, 335 val); 336 break; 337 case REGULATOR_MODE_NORMAL: 338 if (curr_mode == REGULATOR_MODE_FAST) { 339 val = MT6359_BUCK_MODE_AUTO; 340 val <<= ffs(info->modeset_mask) - 1; 341 ret = regmap_update_bits(rdev->regmap, 342 info->modeset_reg, 343 info->modeset_mask, 344 val); 345 } else if (curr_mode == REGULATOR_MODE_IDLE) { 346 val = MT6359_BUCK_MODE_NORMAL; 347 val <<= ffs(info->lp_mode_mask) - 1; 348 ret = regmap_update_bits(rdev->regmap, 349 info->lp_mode_reg, 350 info->lp_mode_mask, 351 val); 352 udelay(100); 353 } 354 break; 355 case REGULATOR_MODE_IDLE: 356 val = MT6359_BUCK_MODE_LP >> 1; 357 val <<= ffs(info->lp_mode_mask) - 1; 358 ret = regmap_update_bits(rdev->regmap, 359 info->lp_mode_reg, 360 info->lp_mode_mask, 361 val); 362 break; 363 default: 364 return -EINVAL; 365 } 366 367 if (ret != 0) { 368 dev_err(&rdev->dev, 369 "Failed to set mt6359 buck mode: %d\n", ret); 370 } 371 372 return ret; 373 } 374 375 static int mt6359p_vemc_set_voltage_sel(struct regulator_dev *rdev, 376 u32 sel) 377 { 378 const struct mt6359_regulator_info *info = rdev_get_drvdata(rdev); 379 int ret; 380 u32 val = 0; 381 382 sel <<= ffs(info->desc.vsel_mask) - 1; 383 ret = regmap_write(rdev->regmap, MT6359P_TMA_KEY_ADDR, TMA_KEY); 384 if (ret) 385 return ret; 386 387 ret = regmap_read(rdev->regmap, MT6359P_VM_MODE_ADDR, &val); 388 if (ret) 389 return ret; 390 391 switch (val) { 392 case 0: 393 /* If HW trapping is 0, use VEMC_VOSEL_0 */ 394 ret = regmap_update_bits(rdev->regmap, 395 info->desc.vsel_reg, 396 info->desc.vsel_mask, sel); 397 break; 398 case 1: 399 /* If HW trapping is 1, use VEMC_VOSEL_1 */ 400 ret = regmap_update_bits(rdev->regmap, 401 info->desc.vsel_reg + 0x2, 402 info->desc.vsel_mask, sel); 403 break; 404 default: 405 return -EINVAL; 406 } 407 408 if (ret) 409 return ret; 410 411 ret = regmap_write(rdev->regmap, MT6359P_TMA_KEY_ADDR, 0); 412 return ret; 413 } 414 415 static int mt6359p_vemc_get_voltage_sel(struct regulator_dev *rdev) 416 { 417 const struct mt6359_regulator_info *info = rdev_get_drvdata(rdev); 418 int ret; 419 u32 val = 0; 420 421 ret = regmap_read(rdev->regmap, MT6359P_VM_MODE_ADDR, &val); 422 if (ret) 423 return ret; 424 switch (val) { 425 case 0: 426 /* If HW trapping is 0, use VEMC_VOSEL_0 */ 427 ret = regmap_read(rdev->regmap, 428 info->desc.vsel_reg, &val); 429 break; 430 case 1: 431 /* If HW trapping is 1, use VEMC_VOSEL_1 */ 432 ret = regmap_read(rdev->regmap, 433 info->desc.vsel_reg + 0x2, &val); 434 break; 435 default: 436 return -EINVAL; 437 } 438 if (ret) 439 return ret; 440 441 val &= info->desc.vsel_mask; 442 val >>= ffs(info->desc.vsel_mask) - 1; 443 444 return val; 445 } 446 447 static const struct regulator_ops mt6359_volt_linear_ops = { 448 .list_voltage = regulator_list_voltage_linear, 449 .map_voltage = regulator_map_voltage_linear, 450 .set_voltage_sel = regulator_set_voltage_sel_regmap, 451 .get_voltage_sel = regulator_get_voltage_sel_regmap, 452 .set_voltage_time_sel = regulator_set_voltage_time_sel, 453 .enable = regulator_enable_regmap, 454 .disable = regulator_disable_regmap, 455 .is_enabled = regulator_is_enabled_regmap, 456 .get_status = mt6359_get_status, 457 .set_mode = mt6359_regulator_set_mode, 458 .get_mode = mt6359_regulator_get_mode, 459 }; 460 461 static const struct regulator_ops mt6359_volt_table_ops = { 462 .list_voltage = regulator_list_voltage_table, 463 .map_voltage = regulator_map_voltage_iterate, 464 .set_voltage_sel = regulator_set_voltage_sel_regmap, 465 .get_voltage_sel = regulator_get_voltage_sel_regmap, 466 .set_voltage_time_sel = regulator_set_voltage_time_sel, 467 .enable = regulator_enable_regmap, 468 .disable = regulator_disable_regmap, 469 .is_enabled = regulator_is_enabled_regmap, 470 .get_status = mt6359_get_status, 471 }; 472 473 static const struct regulator_ops mt6359_volt_fixed_ops = { 474 .enable = regulator_enable_regmap, 475 .disable = regulator_disable_regmap, 476 .is_enabled = regulator_is_enabled_regmap, 477 .get_status = mt6359_get_status, 478 }; 479 480 static const struct regulator_ops mt6359p_vemc_ops = { 481 .list_voltage = regulator_list_voltage_table, 482 .map_voltage = regulator_map_voltage_iterate, 483 .set_voltage_sel = mt6359p_vemc_set_voltage_sel, 484 .get_voltage_sel = mt6359p_vemc_get_voltage_sel, 485 .set_voltage_time_sel = regulator_set_voltage_time_sel, 486 .enable = regulator_enable_regmap, 487 .disable = regulator_disable_regmap, 488 .is_enabled = regulator_is_enabled_regmap, 489 .get_status = mt6359_get_status, 490 }; 491 492 /* Used for backward-compatible placeholder regulators */ 493 static const struct regulator_ops mt6359_noop_ops = {}; 494 495 /* The array is indexed by id(MT6359_ID_XXX) */ 496 static const struct mt6359_regulator_info mt6359_regulators[] = { 497 MT6359_BUCK("buck_vs1", VS1, "vsys-vs1", 800000, 2200000, 12500, 498 MT6359_RG_BUCK_VS1_EN_ADDR, 499 MT6359_DA_VS1_EN_ADDR, MT6359_RG_BUCK_VS1_VOSEL_ADDR, 500 MT6359_RG_BUCK_VS1_VOSEL_MASK << 501 MT6359_RG_BUCK_VS1_VOSEL_SHIFT, 502 MT6359_RG_BUCK_VS1_LP_ADDR, MT6359_RG_BUCK_VS1_LP_SHIFT, 503 MT6359_RG_VS1_FPWM_ADDR, MT6359_RG_VS1_FPWM_SHIFT), 504 MT6359_BUCK("buck_vgpu11", VGPU11, "vsys-vgpu11", 400000, 1193750, 6250, 505 MT6359_RG_BUCK_VGPU11_EN_ADDR, 506 MT6359_DA_VGPU11_EN_ADDR, MT6359_RG_BUCK_VGPU11_VOSEL_ADDR, 507 MT6359_RG_BUCK_VGPU11_VOSEL_MASK << 508 MT6359_RG_BUCK_VGPU11_VOSEL_SHIFT, 509 MT6359_RG_BUCK_VGPU11_LP_ADDR, 510 MT6359_RG_BUCK_VGPU11_LP_SHIFT, 511 MT6359_RG_VGPU11_FCCM_ADDR, MT6359_RG_VGPU11_FCCM_SHIFT), 512 MT6359_BUCK("buck_vmodem", VMODEM, "vsys-vmodem", 400000, 1100000, 6250, 513 MT6359_RG_BUCK_VMODEM_EN_ADDR, 514 MT6359_DA_VMODEM_EN_ADDR, MT6359_RG_BUCK_VMODEM_VOSEL_ADDR, 515 MT6359_RG_BUCK_VMODEM_VOSEL_MASK << 516 MT6359_RG_BUCK_VMODEM_VOSEL_SHIFT, 517 MT6359_RG_BUCK_VMODEM_LP_ADDR, 518 MT6359_RG_BUCK_VMODEM_LP_SHIFT, 519 MT6359_RG_VMODEM_FCCM_ADDR, MT6359_RG_VMODEM_FCCM_SHIFT), 520 MT6359_BUCK("buck_vpu", VPU, "vsys-vpu", 400000, 1193750, 6250, 521 MT6359_RG_BUCK_VPU_EN_ADDR, 522 MT6359_DA_VPU_EN_ADDR, MT6359_RG_BUCK_VPU_VOSEL_ADDR, 523 MT6359_RG_BUCK_VPU_VOSEL_MASK << 524 MT6359_RG_BUCK_VPU_VOSEL_SHIFT, 525 MT6359_RG_BUCK_VPU_LP_ADDR, MT6359_RG_BUCK_VPU_LP_SHIFT, 526 MT6359_RG_VPU_FCCM_ADDR, MT6359_RG_VPU_FCCM_SHIFT), 527 MT6359_BUCK("buck_vcore", VCORE, "vsys-vcore", 400000, 1193750, 6250, 528 MT6359_RG_BUCK_VCORE_EN_ADDR, 529 MT6359_DA_VCORE_EN_ADDR, MT6359_RG_BUCK_VCORE_VOSEL_ADDR, 530 MT6359_RG_BUCK_VCORE_VOSEL_MASK << 531 MT6359_RG_BUCK_VCORE_VOSEL_SHIFT, 532 MT6359_RG_BUCK_VCORE_LP_ADDR, MT6359_RG_BUCK_VCORE_LP_SHIFT, 533 MT6359_RG_VCORE_FCCM_ADDR, MT6359_RG_VCORE_FCCM_SHIFT), 534 MT6359_BUCK("buck_vs2", VS2, "vsys-vs2", 800000, 1600000, 12500, 535 MT6359_RG_BUCK_VS2_EN_ADDR, 536 MT6359_DA_VS2_EN_ADDR, MT6359_RG_BUCK_VS2_VOSEL_ADDR, 537 MT6359_RG_BUCK_VS2_VOSEL_MASK << 538 MT6359_RG_BUCK_VS2_VOSEL_SHIFT, 539 MT6359_RG_BUCK_VS2_LP_ADDR, MT6359_RG_BUCK_VS2_LP_SHIFT, 540 MT6359_RG_VS2_FPWM_ADDR, MT6359_RG_VS2_FPWM_SHIFT), 541 MT6359_BUCK("buck_vpa", VPA, "vsys-vpa", 500000, 3650000, 50000, 542 MT6359_RG_BUCK_VPA_EN_ADDR, 543 MT6359_DA_VPA_EN_ADDR, MT6359_RG_BUCK_VPA_VOSEL_ADDR, 544 MT6359_RG_BUCK_VPA_VOSEL_MASK << 545 MT6359_RG_BUCK_VPA_VOSEL_SHIFT, 546 MT6359_RG_BUCK_VPA_LP_ADDR, MT6359_RG_BUCK_VPA_LP_SHIFT, 547 MT6359_RG_VPA_MODESET_ADDR, MT6359_RG_VPA_MODESET_SHIFT), 548 MT6359_BUCK("buck_vproc2", VPROC2, "vsys-vproc2", 400000, 1193750, 6250, 549 MT6359_RG_BUCK_VPROC2_EN_ADDR, 550 MT6359_DA_VPROC2_EN_ADDR, MT6359_RG_BUCK_VPROC2_VOSEL_ADDR, 551 MT6359_RG_BUCK_VPROC2_VOSEL_MASK << 552 MT6359_RG_BUCK_VPROC2_VOSEL_SHIFT, 553 MT6359_RG_BUCK_VPROC2_LP_ADDR, 554 MT6359_RG_BUCK_VPROC2_LP_SHIFT, 555 MT6359_RG_VPROC2_FCCM_ADDR, MT6359_RG_VPROC2_FCCM_SHIFT), 556 MT6359_BUCK("buck_vproc1", VPROC1, "vsys-vproc1", 400000, 1193750, 6250, 557 MT6359_RG_BUCK_VPROC1_EN_ADDR, 558 MT6359_DA_VPROC1_EN_ADDR, MT6359_RG_BUCK_VPROC1_VOSEL_ADDR, 559 MT6359_RG_BUCK_VPROC1_VOSEL_MASK << 560 MT6359_RG_BUCK_VPROC1_VOSEL_SHIFT, 561 MT6359_RG_BUCK_VPROC1_LP_ADDR, 562 MT6359_RG_BUCK_VPROC1_LP_SHIFT, 563 MT6359_RG_VPROC1_FCCM_ADDR, MT6359_RG_VPROC1_FCCM_SHIFT), 564 MT6359_BUCK("buck_vcore_sshub", VCORE_SSHUB, "vsys-vcore", 400000, 1193750, 6250, 565 MT6359_RG_BUCK_VCORE_SSHUB_EN_ADDR, 566 MT6359_DA_VCORE_EN_ADDR, 567 MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_ADDR, 568 MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_MASK << 569 MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_SHIFT, 570 MT6359_RG_BUCK_VCORE_LP_ADDR, MT6359_RG_BUCK_VCORE_LP_SHIFT, 571 MT6359_RG_VCORE_FCCM_ADDR, MT6359_RG_VCORE_FCCM_SHIFT), 572 MT6359_REG_FIXED("ldo_vaud18", VAUD18, "vs1-ldo1", MT6359_RG_LDO_VAUD18_EN_ADDR, 573 MT6359_DA_VAUD18_B_EN_ADDR, 1800000), 574 MT6359_LDO("ldo_vsim1", VSIM1, "vsys-ldo2", vsim1_voltages, 575 MT6359_RG_LDO_VSIM1_EN_ADDR, MT6359_RG_LDO_VSIM1_EN_SHIFT, 576 MT6359_DA_VSIM1_B_EN_ADDR, MT6359_RG_VSIM1_VOSEL_ADDR, 577 MT6359_RG_VSIM1_VOSEL_MASK << MT6359_RG_VSIM1_VOSEL_SHIFT, 578 480), 579 MT6359_LDO("ldo_vibr", VIBR, "vsys-ldo1", vibr_voltages, 580 MT6359_RG_LDO_VIBR_EN_ADDR, MT6359_RG_LDO_VIBR_EN_SHIFT, 581 MT6359_DA_VIBR_B_EN_ADDR, MT6359_RG_VIBR_VOSEL_ADDR, 582 MT6359_RG_VIBR_VOSEL_MASK << MT6359_RG_VIBR_VOSEL_SHIFT, 583 240), 584 MT6359_LDO("ldo_vrf12", VRF12, "vs2-ldo2", vrf12_voltages, 585 MT6359_RG_LDO_VRF12_EN_ADDR, MT6359_RG_LDO_VRF12_EN_SHIFT, 586 MT6359_DA_VRF12_B_EN_ADDR, MT6359_RG_VRF12_VOSEL_ADDR, 587 MT6359_RG_VRF12_VOSEL_MASK << MT6359_RG_VRF12_VOSEL_SHIFT, 588 120), 589 MT6359_REG_FIXED("ldo_vusb", VUSB, "vsys-ldo2", MT6359_RG_LDO_VUSB_EN_0_ADDR, 590 MT6359_DA_VUSB_B_EN_ADDR, 3000000), 591 MT6359_LDO_LINEAR("ldo_vsram_proc2", VSRAM_PROC2, "vs2-ldo1", 500000, 1293750, 6250, 592 MT6359_RG_LDO_VSRAM_PROC2_EN_ADDR, 593 MT6359_DA_VSRAM_PROC2_B_EN_ADDR, 594 MT6359_RG_LDO_VSRAM_PROC2_VOSEL_ADDR, 595 MT6359_RG_LDO_VSRAM_PROC2_VOSEL_MASK << 596 MT6359_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT), 597 MT6359_LDO("ldo_vio18", VIO18, "vs1-ldo2", volt18_voltages, 598 MT6359_RG_LDO_VIO18_EN_ADDR, MT6359_RG_LDO_VIO18_EN_SHIFT, 599 MT6359_DA_VIO18_B_EN_ADDR, MT6359_RG_VIO18_VOSEL_ADDR, 600 MT6359_RG_VIO18_VOSEL_MASK << MT6359_RG_VIO18_VOSEL_SHIFT, 601 960), 602 MT6359_LDO("ldo_vcamio", VCAMIO, "vs1-ldo1", volt18_voltages, 603 MT6359_RG_LDO_VCAMIO_EN_ADDR, MT6359_RG_LDO_VCAMIO_EN_SHIFT, 604 MT6359_DA_VCAMIO_B_EN_ADDR, MT6359_RG_VCAMIO_VOSEL_ADDR, 605 MT6359_RG_VCAMIO_VOSEL_MASK << MT6359_RG_VCAMIO_VOSEL_SHIFT, 606 1290), 607 MT6359_REG_FIXED("ldo_vcn18", VCN18, "vs1-ldo2", MT6359_RG_LDO_VCN18_EN_ADDR, 608 MT6359_DA_VCN18_B_EN_ADDR, 1800000), 609 MT6359_REG_FIXED("ldo_vfe28", VFE28, "vsys-ldo1", MT6359_RG_LDO_VFE28_EN_ADDR, 610 MT6359_DA_VFE28_B_EN_ADDR, 2800000), 611 MT6359_LDO("ldo_vcn13", VCN13, "vs2-ldo2", vcn13_voltages, 612 MT6359_RG_LDO_VCN13_EN_ADDR, MT6359_RG_LDO_VCN13_EN_SHIFT, 613 MT6359_DA_VCN13_B_EN_ADDR, MT6359_RG_VCN13_VOSEL_ADDR, 614 MT6359_RG_VCN13_VOSEL_MASK << MT6359_RG_VCN13_VOSEL_SHIFT, 615 240), 616 MT6359_LDO("ldo_vcn33_1", VCN33_1, "vsys-ldo1", vcn33_voltages, 617 MT6359_RG_LDO_VCN33_1_EN_0_ADDR, 618 MT6359_RG_LDO_VCN33_1_EN_0_SHIFT, 619 MT6359_DA_VCN33_1_B_EN_ADDR, MT6359_RG_VCN33_1_VOSEL_ADDR, 620 MT6359_RG_VCN33_1_VOSEL_MASK << 621 MT6359_RG_VCN33_1_VOSEL_SHIFT, 240), 622 MT6359_REG_FIXED("ldo_vaux18", VAUX18, "vsys-ldo2", MT6359_RG_LDO_VAUX18_EN_ADDR, 623 MT6359_DA_VAUX18_B_EN_ADDR, 1800000), 624 MT6359_LDO_LINEAR("ldo_vsram_others", VSRAM_OTHERS, "vs2-ldo1", 500000, 1293750, 625 6250, 626 MT6359_RG_LDO_VSRAM_OTHERS_EN_ADDR, 627 MT6359_DA_VSRAM_OTHERS_B_EN_ADDR, 628 MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_ADDR, 629 MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_MASK << 630 MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT), 631 MT6359_LDO("ldo_vefuse", VEFUSE, "vs1-ldo2", vefuse_voltages, 632 MT6359_RG_LDO_VEFUSE_EN_ADDR, MT6359_RG_LDO_VEFUSE_EN_SHIFT, 633 MT6359_DA_VEFUSE_B_EN_ADDR, MT6359_RG_VEFUSE_VOSEL_ADDR, 634 MT6359_RG_VEFUSE_VOSEL_MASK << MT6359_RG_VEFUSE_VOSEL_SHIFT, 635 240), 636 MT6359_LDO("ldo_vxo22", VXO22, "vsys-ldo2", vxo22_voltages, 637 MT6359_RG_LDO_VXO22_EN_ADDR, MT6359_RG_LDO_VXO22_EN_SHIFT, 638 MT6359_DA_VXO22_B_EN_ADDR, MT6359_RG_VXO22_VOSEL_ADDR, 639 MT6359_RG_VXO22_VOSEL_MASK << MT6359_RG_VXO22_VOSEL_SHIFT, 640 120), 641 MT6359_LDO("ldo_vrfck", VRFCK, "vsys-ldo2", vrfck_voltages, 642 MT6359_RG_LDO_VRFCK_EN_ADDR, MT6359_RG_LDO_VRFCK_EN_SHIFT, 643 MT6359_DA_VRFCK_B_EN_ADDR, MT6359_RG_VRFCK_VOSEL_ADDR, 644 MT6359_RG_VRFCK_VOSEL_MASK << MT6359_RG_VRFCK_VOSEL_SHIFT, 645 480), 646 MT6359_REG_FIXED("ldo_vbif28", VBIF28, "vsys-ldo2", MT6359_RG_LDO_VBIF28_EN_ADDR, 647 MT6359_DA_VBIF28_B_EN_ADDR, 2800000), 648 MT6359_LDO("ldo_vio28", VIO28, "vsys-ldo2", vio28_voltages, 649 MT6359_RG_LDO_VIO28_EN_ADDR, MT6359_RG_LDO_VIO28_EN_SHIFT, 650 MT6359_DA_VIO28_B_EN_ADDR, MT6359_RG_VIO28_VOSEL_ADDR, 651 MT6359_RG_VIO28_VOSEL_MASK << MT6359_RG_VIO28_VOSEL_SHIFT, 652 240), 653 MT6359_LDO("ldo_vemc", VEMC, "vsys-ldo2", vemc_voltages, 654 MT6359_RG_LDO_VEMC_EN_ADDR, MT6359_RG_LDO_VEMC_EN_SHIFT, 655 MT6359_DA_VEMC_B_EN_ADDR, MT6359_RG_VEMC_VOSEL_ADDR, 656 MT6359_RG_VEMC_VOSEL_MASK << MT6359_RG_VEMC_VOSEL_SHIFT, 657 240), 658 MT6359_LDO("ldo_vcn33_2", VCN33_2, "vsys-ldo1", vcn33_voltages, 659 MT6359_RG_LDO_VCN33_2_EN_0_ADDR, 660 MT6359_RG_LDO_VCN33_2_EN_0_SHIFT, 661 MT6359_DA_VCN33_2_B_EN_ADDR, MT6359_RG_VCN33_2_VOSEL_ADDR, 662 MT6359_RG_VCN33_2_VOSEL_MASK << 663 MT6359_RG_VCN33_2_VOSEL_SHIFT, 240), 664 MT6359_LDO("ldo_va12", VA12, "vs2-ldo2", va12_voltages, 665 MT6359_RG_LDO_VA12_EN_ADDR, MT6359_RG_LDO_VA12_EN_SHIFT, 666 MT6359_DA_VA12_B_EN_ADDR, MT6359_RG_VA12_VOSEL_ADDR, 667 MT6359_RG_VA12_VOSEL_MASK << MT6359_RG_VA12_VOSEL_SHIFT, 668 240), 669 MT6359_LDO("ldo_va09", VA09, "vs2-ldo2", va09_voltages, 670 MT6359_RG_LDO_VA09_EN_ADDR, MT6359_RG_LDO_VA09_EN_SHIFT, 671 MT6359_DA_VA09_B_EN_ADDR, MT6359_RG_VA09_VOSEL_ADDR, 672 MT6359_RG_VA09_VOSEL_MASK << MT6359_RG_VA09_VOSEL_SHIFT, 673 240), 674 MT6359_LDO("ldo_vrf18", VRF18, "vs1-ldo2", vrf18_voltages, 675 MT6359_RG_LDO_VRF18_EN_ADDR, MT6359_RG_LDO_VRF18_EN_SHIFT, 676 MT6359_DA_VRF18_B_EN_ADDR, MT6359_RG_VRF18_VOSEL_ADDR, 677 MT6359_RG_VRF18_VOSEL_MASK << MT6359_RG_VRF18_VOSEL_SHIFT, 678 120), 679 MT6359_LDO_LINEAR("ldo_vsram_md", VSRAM_MD, "vs2-ldo1", 500000, 1100000, 6250, 680 MT6359_RG_LDO_VSRAM_MD_EN_ADDR, 681 MT6359_DA_VSRAM_MD_B_EN_ADDR, 682 MT6359_RG_LDO_VSRAM_MD_VOSEL_ADDR, 683 MT6359_RG_LDO_VSRAM_MD_VOSEL_MASK << 684 MT6359_RG_LDO_VSRAM_MD_VOSEL_SHIFT), 685 MT6359_LDO("ldo_vufs", VUFS, "vs1-ldo1", volt18_voltages, 686 MT6359_RG_LDO_VUFS_EN_ADDR, MT6359_RG_LDO_VUFS_EN_SHIFT, 687 MT6359_DA_VUFS_B_EN_ADDR, MT6359_RG_VUFS_VOSEL_ADDR, 688 MT6359_RG_VUFS_VOSEL_MASK << MT6359_RG_VUFS_VOSEL_SHIFT, 689 1920), 690 MT6359_LDO("ldo_vm18", VM18, "vs1-ldo1", volt18_voltages, 691 MT6359_RG_LDO_VM18_EN_ADDR, MT6359_RG_LDO_VM18_EN_SHIFT, 692 MT6359_DA_VM18_B_EN_ADDR, MT6359_RG_VM18_VOSEL_ADDR, 693 MT6359_RG_VM18_VOSEL_MASK << MT6359_RG_VM18_VOSEL_SHIFT, 694 1920), 695 /* vbbck is fed from vio18 internally. */ 696 MT6359_LDO("ldo_vbbck", VBBCK, "LDO_VIO18", vbbck_voltages, 697 MT6359_RG_LDO_VBBCK_EN_ADDR, MT6359_RG_LDO_VBBCK_EN_SHIFT, 698 MT6359_DA_VBBCK_B_EN_ADDR, MT6359_RG_VBBCK_VOSEL_ADDR, 699 MT6359_RG_VBBCK_VOSEL_MASK << MT6359_RG_VBBCK_VOSEL_SHIFT, 700 240), 701 MT6359_LDO_LINEAR("ldo_vsram_proc1", VSRAM_PROC1, "vs2-ldo1", 500000, 1293750, 6250, 702 MT6359_RG_LDO_VSRAM_PROC1_EN_ADDR, 703 MT6359_DA_VSRAM_PROC1_B_EN_ADDR, 704 MT6359_RG_LDO_VSRAM_PROC1_VOSEL_ADDR, 705 MT6359_RG_LDO_VSRAM_PROC1_VOSEL_MASK << 706 MT6359_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT), 707 MT6359_LDO("ldo_vsim2", VSIM2, "vsys-ldo2", vsim2_voltages, 708 MT6359_RG_LDO_VSIM2_EN_ADDR, MT6359_RG_LDO_VSIM2_EN_SHIFT, 709 MT6359_DA_VSIM2_B_EN_ADDR, MT6359_RG_VSIM2_VOSEL_ADDR, 710 MT6359_RG_VSIM2_VOSEL_MASK << MT6359_RG_VSIM2_VOSEL_SHIFT, 711 480), 712 MT6359_LDO_LINEAR("ldo_vsram_others_sshub", VSRAM_OTHERS_SSHUB, "vs2-ldo1", 713 500000, 1293750, 6250, 714 MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR, 715 MT6359_DA_VSRAM_OTHERS_B_EN_ADDR, 716 MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR, 717 MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK << 718 MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT), 719 /* Placeholders for DT backward compatibility */ 720 MT6359_LDO_NOOP("ldo_vcn33_1_bt", VCN33_1_BT, "LDO_VCN33_1"), 721 MT6359_LDO_NOOP("ldo_vcn33_1_wifi", VCN33_1_WIFI, "LDO_VCN33_1"), 722 MT6359_LDO_NOOP("ldo_vcn33_2_bt", VCN33_2_BT, "LDO_VCN33_2"), 723 MT6359_LDO_NOOP("ldo_vcn33_2_wifi", VCN33_2_WIFI, "LDO_VCN33_2"), 724 }; 725 726 static const struct mt6359_regulator_info mt6359p_regulators[] = { 727 MT6359_BUCK("buck_vs1", VS1, "vsys-vs1", 800000, 2200000, 12500, 728 MT6359_RG_BUCK_VS1_EN_ADDR, 729 MT6359_DA_VS1_EN_ADDR, MT6359_RG_BUCK_VS1_VOSEL_ADDR, 730 MT6359_RG_BUCK_VS1_VOSEL_MASK << 731 MT6359_RG_BUCK_VS1_VOSEL_SHIFT, 732 MT6359_RG_BUCK_VS1_LP_ADDR, MT6359_RG_BUCK_VS1_LP_SHIFT, 733 MT6359_RG_VS1_FPWM_ADDR, MT6359_RG_VS1_FPWM_SHIFT), 734 MT6359_BUCK("buck_vgpu11", VGPU11, "vsys-vgpu11", 400000, 1193750, 6250, 735 MT6359_RG_BUCK_VGPU11_EN_ADDR, 736 MT6359_DA_VGPU11_EN_ADDR, MT6359P_RG_BUCK_VGPU11_VOSEL_ADDR, 737 MT6359_RG_BUCK_VGPU11_VOSEL_MASK << 738 MT6359_RG_BUCK_VGPU11_VOSEL_SHIFT, 739 MT6359_RG_BUCK_VGPU11_LP_ADDR, 740 MT6359_RG_BUCK_VGPU11_LP_SHIFT, 741 MT6359_RG_VGPU11_FCCM_ADDR, MT6359_RG_VGPU11_FCCM_SHIFT), 742 MT6359_BUCK("buck_vmodem", VMODEM, "vsys-vmodem", 400000, 1100000, 6250, 743 MT6359_RG_BUCK_VMODEM_EN_ADDR, 744 MT6359_DA_VMODEM_EN_ADDR, MT6359_RG_BUCK_VMODEM_VOSEL_ADDR, 745 MT6359_RG_BUCK_VMODEM_VOSEL_MASK << 746 MT6359_RG_BUCK_VMODEM_VOSEL_SHIFT, 747 MT6359_RG_BUCK_VMODEM_LP_ADDR, 748 MT6359_RG_BUCK_VMODEM_LP_SHIFT, 749 MT6359_RG_VMODEM_FCCM_ADDR, MT6359_RG_VMODEM_FCCM_SHIFT), 750 MT6359_BUCK("buck_vpu", VPU, "vsys-vpu", 400000, 1193750, 6250, 751 MT6359_RG_BUCK_VPU_EN_ADDR, 752 MT6359_DA_VPU_EN_ADDR, MT6359_RG_BUCK_VPU_VOSEL_ADDR, 753 MT6359_RG_BUCK_VPU_VOSEL_MASK << 754 MT6359_RG_BUCK_VPU_VOSEL_SHIFT, 755 MT6359_RG_BUCK_VPU_LP_ADDR, MT6359_RG_BUCK_VPU_LP_SHIFT, 756 MT6359_RG_VPU_FCCM_ADDR, MT6359_RG_VPU_FCCM_SHIFT), 757 MT6359_BUCK("buck_vcore", VCORE, "vsys-vcore", 506250, 1300000, 6250, 758 MT6359_RG_BUCK_VCORE_EN_ADDR, 759 MT6359_DA_VCORE_EN_ADDR, MT6359P_RG_BUCK_VCORE_VOSEL_ADDR, 760 MT6359_RG_BUCK_VCORE_VOSEL_MASK << 761 MT6359_RG_BUCK_VCORE_VOSEL_SHIFT, 762 MT6359_RG_BUCK_VCORE_LP_ADDR, MT6359_RG_BUCK_VCORE_LP_SHIFT, 763 MT6359_RG_VCORE_FCCM_ADDR, MT6359_RG_VCORE_FCCM_SHIFT), 764 MT6359_BUCK("buck_vs2", VS2, "vsys-vs2", 800000, 1600000, 12500, 765 MT6359_RG_BUCK_VS2_EN_ADDR, 766 MT6359_DA_VS2_EN_ADDR, MT6359_RG_BUCK_VS2_VOSEL_ADDR, 767 MT6359_RG_BUCK_VS2_VOSEL_MASK << 768 MT6359_RG_BUCK_VS2_VOSEL_SHIFT, 769 MT6359_RG_BUCK_VS2_LP_ADDR, MT6359_RG_BUCK_VS2_LP_SHIFT, 770 MT6359_RG_VS2_FPWM_ADDR, MT6359_RG_VS2_FPWM_SHIFT), 771 MT6359_BUCK("buck_vpa", VPA, "vsys-vpa", 500000, 3650000, 50000, 772 MT6359_RG_BUCK_VPA_EN_ADDR, 773 MT6359_DA_VPA_EN_ADDR, MT6359_RG_BUCK_VPA_VOSEL_ADDR, 774 MT6359_RG_BUCK_VPA_VOSEL_MASK << 775 MT6359_RG_BUCK_VPA_VOSEL_SHIFT, 776 MT6359_RG_BUCK_VPA_LP_ADDR, MT6359_RG_BUCK_VPA_LP_SHIFT, 777 MT6359_RG_VPA_MODESET_ADDR, MT6359_RG_VPA_MODESET_SHIFT), 778 MT6359_BUCK("buck_vproc2", VPROC2, "vsys-vproc2", 400000, 1193750, 6250, 779 MT6359_RG_BUCK_VPROC2_EN_ADDR, 780 MT6359_DA_VPROC2_EN_ADDR, MT6359_RG_BUCK_VPROC2_VOSEL_ADDR, 781 MT6359_RG_BUCK_VPROC2_VOSEL_MASK << 782 MT6359_RG_BUCK_VPROC2_VOSEL_SHIFT, 783 MT6359_RG_BUCK_VPROC2_LP_ADDR, 784 MT6359_RG_BUCK_VPROC2_LP_SHIFT, 785 MT6359_RG_VPROC2_FCCM_ADDR, MT6359_RG_VPROC2_FCCM_SHIFT), 786 MT6359_BUCK("buck_vproc1", VPROC1, "vsys-vproc1", 400000, 1193750, 6250, 787 MT6359_RG_BUCK_VPROC1_EN_ADDR, 788 MT6359_DA_VPROC1_EN_ADDR, MT6359_RG_BUCK_VPROC1_VOSEL_ADDR, 789 MT6359_RG_BUCK_VPROC1_VOSEL_MASK << 790 MT6359_RG_BUCK_VPROC1_VOSEL_SHIFT, 791 MT6359_RG_BUCK_VPROC1_LP_ADDR, 792 MT6359_RG_BUCK_VPROC1_LP_SHIFT, 793 MT6359_RG_VPROC1_FCCM_ADDR, MT6359_RG_VPROC1_FCCM_SHIFT), 794 MT6359_BUCK("buck_vgpu11_sshub", VGPU11_SSHUB, "vsys-vgpu11", 400000, 1193750, 6250, 795 MT6359P_RG_BUCK_VGPU11_SSHUB_EN_ADDR, 796 MT6359_DA_VGPU11_EN_ADDR, 797 MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_ADDR, 798 MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_MASK << 799 MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_SHIFT, 800 MT6359_RG_BUCK_VGPU11_LP_ADDR, 801 MT6359_RG_BUCK_VGPU11_LP_SHIFT, 802 MT6359_RG_VGPU11_FCCM_ADDR, MT6359_RG_VGPU11_FCCM_SHIFT), 803 MT6359_REG_FIXED("ldo_vaud18", VAUD18, "vs1-ldo1", MT6359P_RG_LDO_VAUD18_EN_ADDR, 804 MT6359P_DA_VAUD18_B_EN_ADDR, 1800000), 805 MT6359_LDO("ldo_vsim1", VSIM1, "vsys-ldo2", vsim1_voltages, 806 MT6359P_RG_LDO_VSIM1_EN_ADDR, MT6359P_RG_LDO_VSIM1_EN_SHIFT, 807 MT6359P_DA_VSIM1_B_EN_ADDR, MT6359P_RG_VSIM1_VOSEL_ADDR, 808 MT6359_RG_VSIM1_VOSEL_MASK << MT6359_RG_VSIM1_VOSEL_SHIFT, 809 480), 810 MT6359_LDO("ldo_vibr", VIBR, "vsys-ldo1", vibr_voltages, 811 MT6359P_RG_LDO_VIBR_EN_ADDR, MT6359P_RG_LDO_VIBR_EN_SHIFT, 812 MT6359P_DA_VIBR_B_EN_ADDR, MT6359P_RG_VIBR_VOSEL_ADDR, 813 MT6359_RG_VIBR_VOSEL_MASK << MT6359_RG_VIBR_VOSEL_SHIFT, 814 240), 815 MT6359_LDO("ldo_vrf12", VRF12, "vs2-ldo2", vrf12_voltages, 816 MT6359P_RG_LDO_VRF12_EN_ADDR, MT6359P_RG_LDO_VRF12_EN_SHIFT, 817 MT6359P_DA_VRF12_B_EN_ADDR, MT6359P_RG_VRF12_VOSEL_ADDR, 818 MT6359_RG_VRF12_VOSEL_MASK << MT6359_RG_VRF12_VOSEL_SHIFT, 819 480), 820 MT6359_REG_FIXED("ldo_vusb", VUSB, "vsys-ldo2", MT6359P_RG_LDO_VUSB_EN_0_ADDR, 821 MT6359P_DA_VUSB_B_EN_ADDR, 3000000), 822 MT6359_LDO_LINEAR("ldo_vsram_proc2", VSRAM_PROC2, "vs2-ldo1", 500000, 1293750, 6250, 823 MT6359P_RG_LDO_VSRAM_PROC2_EN_ADDR, 824 MT6359P_DA_VSRAM_PROC2_B_EN_ADDR, 825 MT6359P_RG_LDO_VSRAM_PROC2_VOSEL_ADDR, 826 MT6359_RG_LDO_VSRAM_PROC2_VOSEL_MASK << 827 MT6359_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT), 828 MT6359_LDO("ldo_vio18", VIO18, "vs1-ldo2", volt18_voltages, 829 MT6359P_RG_LDO_VIO18_EN_ADDR, MT6359P_RG_LDO_VIO18_EN_SHIFT, 830 MT6359P_DA_VIO18_B_EN_ADDR, MT6359P_RG_VIO18_VOSEL_ADDR, 831 MT6359_RG_VIO18_VOSEL_MASK << MT6359_RG_VIO18_VOSEL_SHIFT, 832 960), 833 MT6359_LDO("ldo_vcamio", VCAMIO, "vs1-ldo1", volt18_voltages, 834 MT6359P_RG_LDO_VCAMIO_EN_ADDR, 835 MT6359P_RG_LDO_VCAMIO_EN_SHIFT, 836 MT6359P_DA_VCAMIO_B_EN_ADDR, MT6359P_RG_VCAMIO_VOSEL_ADDR, 837 MT6359_RG_VCAMIO_VOSEL_MASK << MT6359_RG_VCAMIO_VOSEL_SHIFT, 838 1290), 839 MT6359_REG_FIXED("ldo_vcn18", VCN18, "vs1-ldo2", MT6359P_RG_LDO_VCN18_EN_ADDR, 840 MT6359P_DA_VCN18_B_EN_ADDR, 1800000), 841 MT6359_REG_FIXED("ldo_vfe28", VFE28, "vsys-ldo1", MT6359P_RG_LDO_VFE28_EN_ADDR, 842 MT6359P_DA_VFE28_B_EN_ADDR, 2800000), 843 MT6359_LDO("ldo_vcn13", VCN13, "vs2-ldo2", vcn13_voltages, 844 MT6359P_RG_LDO_VCN13_EN_ADDR, MT6359P_RG_LDO_VCN13_EN_SHIFT, 845 MT6359P_DA_VCN13_B_EN_ADDR, MT6359P_RG_VCN13_VOSEL_ADDR, 846 MT6359_RG_VCN13_VOSEL_MASK << MT6359_RG_VCN13_VOSEL_SHIFT, 847 240), 848 MT6359_LDO("ldo_vcn33_1", VCN33_1, "vsys-ldo1", vcn33_voltages, 849 MT6359P_RG_LDO_VCN33_1_EN_0_ADDR, 850 MT6359_RG_LDO_VCN33_1_EN_0_SHIFT, 851 MT6359P_DA_VCN33_1_B_EN_ADDR, MT6359P_RG_VCN33_1_VOSEL_ADDR, 852 MT6359_RG_VCN33_1_VOSEL_MASK << 853 MT6359_RG_VCN33_1_VOSEL_SHIFT, 240), 854 MT6359_REG_FIXED("ldo_vaux18", VAUX18, "vsys-ldo2", MT6359P_RG_LDO_VAUX18_EN_ADDR, 855 MT6359P_DA_VAUX18_B_EN_ADDR, 1800000), 856 MT6359_LDO_LINEAR("ldo_vsram_others", VSRAM_OTHERS, "vs2-ldo1", 500000, 1293750, 857 6250, 858 MT6359P_RG_LDO_VSRAM_OTHERS_EN_ADDR, 859 MT6359P_DA_VSRAM_OTHERS_B_EN_ADDR, 860 MT6359P_RG_LDO_VSRAM_OTHERS_VOSEL_ADDR, 861 MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_MASK << 862 MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT), 863 MT6359_LDO("ldo_vefuse", VEFUSE, "vs1-ldo2", vefuse_voltages, 864 MT6359P_RG_LDO_VEFUSE_EN_ADDR, 865 MT6359P_RG_LDO_VEFUSE_EN_SHIFT, 866 MT6359P_DA_VEFUSE_B_EN_ADDR, MT6359P_RG_VEFUSE_VOSEL_ADDR, 867 MT6359_RG_VEFUSE_VOSEL_MASK << MT6359_RG_VEFUSE_VOSEL_SHIFT, 868 240), 869 MT6359_LDO("ldo_vxo22", VXO22, "vsys-ldo2", vxo22_voltages, 870 MT6359P_RG_LDO_VXO22_EN_ADDR, MT6359P_RG_LDO_VXO22_EN_SHIFT, 871 MT6359P_DA_VXO22_B_EN_ADDR, MT6359P_RG_VXO22_VOSEL_ADDR, 872 MT6359_RG_VXO22_VOSEL_MASK << MT6359_RG_VXO22_VOSEL_SHIFT, 873 480), 874 MT6359_LDO("ldo_vrfck_1", VRFCK, "vsys-ldo2", vrfck_voltages_1, 875 MT6359P_RG_LDO_VRFCK_EN_ADDR, MT6359P_RG_LDO_VRFCK_EN_SHIFT, 876 MT6359P_DA_VRFCK_B_EN_ADDR, MT6359P_RG_VRFCK_VOSEL_ADDR, 877 MT6359_RG_VRFCK_VOSEL_MASK << MT6359_RG_VRFCK_VOSEL_SHIFT, 878 480), 879 MT6359_REG_FIXED("ldo_vbif28", VBIF28, "vsys-ldo2", MT6359P_RG_LDO_VBIF28_EN_ADDR, 880 MT6359P_DA_VBIF28_B_EN_ADDR, 2800000), 881 MT6359_LDO("ldo_vio28", VIO28, "vsys-ldo2", vio28_voltages, 882 MT6359P_RG_LDO_VIO28_EN_ADDR, MT6359P_RG_LDO_VIO28_EN_SHIFT, 883 MT6359P_DA_VIO28_B_EN_ADDR, MT6359P_RG_VIO28_VOSEL_ADDR, 884 MT6359_RG_VIO28_VOSEL_MASK << MT6359_RG_VIO28_VOSEL_SHIFT, 885 1920), 886 MT6359P_LDO1("ldo_vemc_1", VEMC, "vsys-ldo2", mt6359p_vemc_ops, vemc_voltages_1, 887 MT6359P_RG_LDO_VEMC_EN_ADDR, MT6359P_RG_LDO_VEMC_EN_SHIFT, 888 MT6359P_DA_VEMC_B_EN_ADDR, 889 MT6359P_RG_LDO_VEMC_VOSEL_0_ADDR, 890 MT6359P_RG_LDO_VEMC_VOSEL_0_MASK << 891 MT6359P_RG_LDO_VEMC_VOSEL_0_SHIFT), 892 MT6359_LDO("ldo_vcn33_2", VCN33_2, "vsys-ldo1", vcn33_voltages, 893 MT6359P_RG_LDO_VCN33_2_EN_0_ADDR, 894 MT6359P_RG_LDO_VCN33_2_EN_0_SHIFT, 895 MT6359P_DA_VCN33_2_B_EN_ADDR, MT6359P_RG_VCN33_2_VOSEL_ADDR, 896 MT6359_RG_VCN33_2_VOSEL_MASK << 897 MT6359_RG_VCN33_2_VOSEL_SHIFT, 240), 898 MT6359_LDO("ldo_va12", VA12, "vs2-ldo2", va12_voltages, 899 MT6359P_RG_LDO_VA12_EN_ADDR, MT6359P_RG_LDO_VA12_EN_SHIFT, 900 MT6359P_DA_VA12_B_EN_ADDR, MT6359P_RG_VA12_VOSEL_ADDR, 901 MT6359_RG_VA12_VOSEL_MASK << MT6359_RG_VA12_VOSEL_SHIFT, 902 960), 903 MT6359_LDO("ldo_va09", VA09, "vs2-ldo2", va09_voltages, 904 MT6359P_RG_LDO_VA09_EN_ADDR, MT6359P_RG_LDO_VA09_EN_SHIFT, 905 MT6359P_DA_VA09_B_EN_ADDR, MT6359P_RG_VA09_VOSEL_ADDR, 906 MT6359_RG_VA09_VOSEL_MASK << MT6359_RG_VA09_VOSEL_SHIFT, 907 960), 908 MT6359_LDO("ldo_vrf18", VRF18, "vs1-ldo2", vrf18_voltages, 909 MT6359P_RG_LDO_VRF18_EN_ADDR, MT6359P_RG_LDO_VRF18_EN_SHIFT, 910 MT6359P_DA_VRF18_B_EN_ADDR, MT6359P_RG_VRF18_VOSEL_ADDR, 911 MT6359_RG_VRF18_VOSEL_MASK << MT6359_RG_VRF18_VOSEL_SHIFT, 912 240), 913 MT6359_LDO_LINEAR("ldo_vsram_md", VSRAM_MD, "vs2-ldo1", 500000, 1293750, 6250, 914 MT6359P_RG_LDO_VSRAM_MD_EN_ADDR, 915 MT6359P_DA_VSRAM_MD_B_EN_ADDR, 916 MT6359P_RG_LDO_VSRAM_MD_VOSEL_ADDR, 917 MT6359_RG_LDO_VSRAM_MD_VOSEL_MASK << 918 MT6359_RG_LDO_VSRAM_MD_VOSEL_SHIFT), 919 MT6359_LDO("ldo_vufs", VUFS, "vs1-ldo1", volt18_voltages, 920 MT6359P_RG_LDO_VUFS_EN_ADDR, MT6359P_RG_LDO_VUFS_EN_SHIFT, 921 MT6359P_DA_VUFS_B_EN_ADDR, MT6359P_RG_VUFS_VOSEL_ADDR, 922 MT6359_RG_VUFS_VOSEL_MASK << MT6359_RG_VUFS_VOSEL_SHIFT, 923 1920), 924 MT6359_LDO("ldo_vm18", VM18, "vs1-ldo1", volt18_voltages, 925 MT6359P_RG_LDO_VM18_EN_ADDR, MT6359P_RG_LDO_VM18_EN_SHIFT, 926 MT6359P_DA_VM18_B_EN_ADDR, MT6359P_RG_VM18_VOSEL_ADDR, 927 MT6359_RG_VM18_VOSEL_MASK << MT6359_RG_VM18_VOSEL_SHIFT, 928 1920), 929 /* vbbck is fed from vio18 internally. */ 930 MT6359_LDO("ldo_vbbck", VBBCK, "LDO_VIO18", vbbck_voltages, 931 MT6359P_RG_LDO_VBBCK_EN_ADDR, MT6359P_RG_LDO_VBBCK_EN_SHIFT, 932 MT6359P_DA_VBBCK_B_EN_ADDR, MT6359P_RG_VBBCK_VOSEL_ADDR, 933 MT6359P_RG_VBBCK_VOSEL_MASK << MT6359P_RG_VBBCK_VOSEL_SHIFT, 934 480), 935 MT6359_LDO_LINEAR("ldo_vsram_proc1", VSRAM_PROC1, "vs2-ldo1", 500000, 1293750, 6250, 936 MT6359P_RG_LDO_VSRAM_PROC1_EN_ADDR, 937 MT6359P_DA_VSRAM_PROC1_B_EN_ADDR, 938 MT6359P_RG_LDO_VSRAM_PROC1_VOSEL_ADDR, 939 MT6359_RG_LDO_VSRAM_PROC1_VOSEL_MASK << 940 MT6359_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT), 941 MT6359_LDO("ldo_vsim2", VSIM2, "vsys-ldo2", vsim2_voltages, 942 MT6359P_RG_LDO_VSIM2_EN_ADDR, MT6359P_RG_LDO_VSIM2_EN_SHIFT, 943 MT6359P_DA_VSIM2_B_EN_ADDR, MT6359P_RG_VSIM2_VOSEL_ADDR, 944 MT6359_RG_VSIM2_VOSEL_MASK << MT6359_RG_VSIM2_VOSEL_SHIFT, 945 480), 946 MT6359_LDO_LINEAR("ldo_vsram_others_sshub", VSRAM_OTHERS_SSHUB, "vs2-ldo1", 947 500000, 1293750, 6250, 948 MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR, 949 MT6359P_DA_VSRAM_OTHERS_B_EN_ADDR, 950 MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR, 951 MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK << 952 MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT), 953 /* Placeholders for DT backward compatibility */ 954 MT6359_LDO_NOOP("ldo_vcn33_1_bt", VCN33_1_BT, "LDO_VCN33_1"), 955 MT6359_LDO_NOOP("ldo_vcn33_1_wifi", VCN33_1_WIFI, "LDO_VCN33_1"), 956 MT6359_LDO_NOOP("ldo_vcn33_2_bt", VCN33_2_BT, "LDO_VCN33_2"), 957 MT6359_LDO_NOOP("ldo_vcn33_2_wifi", VCN33_2_WIFI, "LDO_VCN33_2"), 958 }; 959 960 struct mt6359_vcn33_regs { 961 u32 wifi_en_reg; 962 u32 wifi_en_mask; 963 u32 bt_en_reg; 964 u32 bt_en_mask; 965 }; 966 967 static const struct mt6359_vcn33_regs vcn33_regs[][2] = { 968 { /* MT6359 */ 969 { 970 .wifi_en_reg = MT6359_RG_LDO_VCN33_1_EN_1_ADDR, 971 .wifi_en_mask = BIT(MT6359_RG_LDO_VCN33_1_EN_1_SHIFT), 972 .bt_en_reg = MT6359_RG_LDO_VCN33_1_EN_0_ADDR, 973 .bt_en_mask = BIT(MT6359_RG_LDO_VCN33_1_EN_0_SHIFT), 974 }, { 975 .wifi_en_reg = MT6359_RG_LDO_VCN33_2_EN_1_ADDR, 976 .wifi_en_mask = BIT(MT6359_RG_LDO_VCN33_2_EN_1_SHIFT), 977 .bt_en_reg = MT6359_RG_LDO_VCN33_2_EN_0_ADDR, 978 .bt_en_mask = BIT(MT6359_RG_LDO_VCN33_2_EN_0_SHIFT), 979 } 980 }, { /* MT6359P */ 981 { 982 .wifi_en_reg = MT6359P_RG_LDO_VCN33_1_EN_1_ADDR, 983 .wifi_en_mask = BIT(MT6359P_RG_LDO_VCN33_1_EN_1_SHIFT), 984 .bt_en_reg = MT6359P_RG_LDO_VCN33_1_EN_0_ADDR, 985 .bt_en_mask = BIT(MT6359_RG_LDO_VCN33_1_EN_0_SHIFT), 986 }, { 987 .wifi_en_reg = MT6359P_RG_LDO_VCN33_2_EN_1_ADDR, 988 .wifi_en_mask = BIT(MT6359_RG_LDO_VCN33_2_EN_1_SHIFT), 989 .bt_en_reg = MT6359P_RG_LDO_VCN33_2_EN_0_ADDR, 990 .bt_en_mask = BIT(MT6359P_RG_LDO_VCN33_2_EN_0_SHIFT), 991 } 992 } 993 }; 994 995 static int mt6359_sync_vcn33_setting(struct device *dev, unsigned int idx) 996 { 997 struct mt6397_chip *mt6397 = dev_get_drvdata(dev->parent); 998 unsigned int val; 999 int ret; 1000 1001 /* 1002 * VCN33_[12]_WIFI and VCN33_[12]_BT are two separate enable bits for 1003 * the same regulator. They share the same voltage setting and output 1004 * pin. Instead of having two potentially conflicting regulators, just 1005 * have one regulator. Sync the two enable bits and only use one in 1006 * the regulator device. 1007 */ 1008 for (unsigned int i = 0; i < ARRAY_SIZE(vcn33_regs[0]); i++) { 1009 u32 bt_en_mask = vcn33_regs[idx][i].bt_en_mask; 1010 u32 wifi_en_mask = vcn33_regs[idx][i].wifi_en_mask; 1011 1012 ret = regmap_read(mt6397->regmap, vcn33_regs[idx][i].wifi_en_reg, &val); 1013 if (ret) 1014 return dev_err_probe(dev, ret, "Failed to read VCN33_%u_WIFI setting\n", 1015 i + 1); 1016 1017 if (!(val & wifi_en_mask)) 1018 continue; 1019 1020 /* Sync VCN33_[12]_WIFI enable status to VCN33_[12]_BT */ 1021 ret = regmap_update_bits(mt6397->regmap, vcn33_regs[idx][i].bt_en_reg, 1022 bt_en_mask, bt_en_mask); 1023 if (ret) 1024 return dev_err_probe(dev, ret, 1025 "Failed to sync VCN33_%u_WIFI setting to VCN33_%u_BT\n", 1026 i + 1, i + 1); 1027 1028 /* Disable VCN33_[12]_WIFI */ 1029 ret = regmap_update_bits(mt6397->regmap, vcn33_regs[idx][i].wifi_en_reg, 1030 wifi_en_mask, 0); 1031 if (ret) 1032 return dev_err_probe(dev, ret, "Failed to disable VCN33_%u_WIFI\n", i + 1); 1033 } 1034 1035 return 0; 1036 } 1037 1038 static int mt6359_regulator_probe(struct platform_device *pdev) 1039 { 1040 struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent); 1041 struct regulator_config config = {}; 1042 struct regulator_dev *rdev; 1043 const struct mt6359_regulator_info *mt6359_info; 1044 const char *vio18_name, *vcn33_1_name, *vcn33_2_name; 1045 int i, hw_ver, ret; 1046 1047 ret = regmap_read(mt6397->regmap, MT6359P_HWCID, &hw_ver); 1048 if (ret) 1049 return ret; 1050 1051 if (hw_ver >= MT6359P_CHIP_VER) { 1052 mt6359_info = mt6359p_regulators; 1053 ret = mt6359_sync_vcn33_setting(&pdev->dev, 1); 1054 if (ret) 1055 return ret; 1056 } else { 1057 mt6359_info = mt6359_regulators; 1058 ret = mt6359_sync_vcn33_setting(&pdev->dev, 0); 1059 if (ret) 1060 return ret; 1061 } 1062 1063 vio18_name = mt6359_info[MT6359_ID_VIO18].desc.name; 1064 vcn33_1_name = mt6359_info[MT6359_ID_VCN33_1].desc.name; 1065 vcn33_2_name = mt6359_info[MT6359_ID_VCN33_2].desc.name; 1066 1067 config.dev = mt6397->dev; 1068 config.regmap = mt6397->regmap; 1069 for (i = 0; i < MT6359_MAX_REGULATOR; i++, mt6359_info++) { 1070 const struct regulator_desc *desc = &mt6359_info->desc; 1071 struct regulator_desc *_desc; 1072 1073 /* drop const here, but all uses in the driver are const */ 1074 config.driver_data = (void *)mt6359_info; 1075 1076 /* Use vio18's actual name as supply_name for vbbck */ 1077 if (i == MT6359_ID_VBBCK && strcmp(desc->supply_name, vio18_name) != 0) { 1078 _desc = devm_kzalloc(&pdev->dev, sizeof(*_desc), GFP_KERNEL); 1079 if (!_desc) 1080 return -ENOMEM; 1081 1082 memcpy(_desc, desc, sizeof(*_desc)); 1083 _desc->supply_name = vio18_name; 1084 desc = _desc; 1085 } 1086 1087 /* Use vcn33_1's actual name as supply_name for vcn33_1_(bt|wifi) */ 1088 if ((i == MT6359_ID_VCN33_1_BT || i == MT6359_ID_VCN33_1_WIFI) && 1089 strcmp(desc->supply_name, vcn33_1_name) != 0) { 1090 _desc = devm_kzalloc(&pdev->dev, sizeof(*_desc), GFP_KERNEL); 1091 if (!_desc) 1092 return -ENOMEM; 1093 1094 memcpy(_desc, desc, sizeof(*_desc)); 1095 _desc->supply_name = vcn33_1_name; 1096 desc = _desc; 1097 } 1098 1099 /* Use vcn33_2's actual name as supply_name for vcn33_2_(bt|wifi) */ 1100 if ((i == MT6359_ID_VCN33_2_BT || i == MT6359_ID_VCN33_2_WIFI) && 1101 strcmp(desc->supply_name, vcn33_2_name) != 0) { 1102 _desc = devm_kzalloc(&pdev->dev, sizeof(*_desc), GFP_KERNEL); 1103 if (!_desc) 1104 return -ENOMEM; 1105 1106 memcpy(_desc, desc, sizeof(*_desc)); 1107 _desc->supply_name = vcn33_2_name; 1108 desc = _desc; 1109 } 1110 1111 rdev = devm_regulator_register(&pdev->dev, desc, &config); 1112 if (IS_ERR(rdev)) { 1113 dev_err(&pdev->dev, "failed to register %s\n", mt6359_info->desc.name); 1114 return PTR_ERR(rdev); 1115 } 1116 1117 /* Save vio18 name for vbbck */ 1118 if (i == MT6359_ID_VIO18) 1119 vio18_name = rdev_get_name(rdev); 1120 1121 /* Save vcn33_1 name for vbbck */ 1122 if (i == MT6359_ID_VCN33_1) 1123 vcn33_1_name = rdev_get_name(rdev); 1124 1125 /* Save vcn33_2 name for vbbck */ 1126 if (i == MT6359_ID_VCN33_2) 1127 vcn33_2_name = rdev_get_name(rdev); 1128 } 1129 1130 return 0; 1131 } 1132 1133 static const struct platform_device_id mt6359_platform_ids[] = { 1134 { .name = "mt6359-regulator" }, 1135 { /* sentinel */ } 1136 }; 1137 MODULE_DEVICE_TABLE(platform, mt6359_platform_ids); 1138 1139 static struct platform_driver mt6359_regulator_driver = { 1140 .driver = { 1141 .name = "mt6359-regulator", 1142 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1143 }, 1144 .probe = mt6359_regulator_probe, 1145 .id_table = mt6359_platform_ids, 1146 }; 1147 1148 module_platform_driver(mt6359_regulator_driver); 1149 1150 MODULE_AUTHOR("Wen Su <wen.su@mediatek.com>"); 1151 MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6359 PMIC"); 1152 MODULE_LICENSE("GPL"); 1153