1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * MediaTek MT6359 PMIC AUXADC IIO driver 4 * 5 * Copyright (c) 2021 MediaTek Inc. 6 * Copyright (c) 2024 Collabora Ltd 7 * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/bits.h> 12 #include <linux/cleanup.h> 13 #include <linux/delay.h> 14 #include <linux/module.h> 15 #include <linux/mod_devicetable.h> 16 #include <linux/platform_device.h> 17 #include <linux/property.h> 18 #include <linux/regmap.h> 19 #include <linux/types.h> 20 21 #include <linux/iio/iio.h> 22 23 #include <linux/mfd/mt6397/core.h> 24 25 #include <dt-bindings/iio/adc/mediatek,mt6357-auxadc.h> 26 #include <dt-bindings/iio/adc/mediatek,mt6358-auxadc.h> 27 #include <dt-bindings/iio/adc/mediatek,mt6359-auxadc.h> 28 #include <dt-bindings/iio/adc/mediatek,mt6363-auxadc.h> 29 30 #define AUXADC_AVG_TIME_US 10 31 #define AUXADC_POLL_DELAY_US 100 32 #define AUXADC_TIMEOUT_US 32000 33 #define IMP_STOP_DELAY_US 150 34 #define IMP_POLL_DELAY_US 1000 35 36 /* For PMIC_RG_RESET_VAL and MT6358_IMP0_CLEAR, the bits specific purpose is unknown. */ 37 #define PMIC_RG_RESET_VAL (BIT(0) | BIT(3)) 38 #define PMIC_AUXADC_RDY_BIT BIT(15) 39 #define MT6357_IMP_ADC_NUM 30 40 #define MT6358_IMP_ADC_NUM 28 41 42 #define MT6358_DCM_CK_SW_EN GENMASK(1, 0) 43 #define MT6358_IMP0_CLEAR (BIT(14) | BIT(7)) 44 #define MT6358_IMP0_IRQ_RDY BIT(8) 45 #define MT6358_IMP1_AUTOREPEAT_EN BIT(15) 46 47 #define MT6359_IMP0_CONV_EN BIT(0) 48 #define MT6359_IMP1_IRQ_RDY BIT(15) 49 50 #define MT6363_EXT_CHAN_MASK GENMASK(2, 0) 51 #define MT6363_EXT_PURES_MASK GENMASK(4, 3) 52 #define MT6363_PULLUP_RES_100K 0 53 #define MT6363_PULLUP_RES_30K 1 54 #define MT6363_PULLUP_RES_OPEN 3 55 56 enum mtk_pmic_auxadc_regs { 57 PMIC_AUXADC_ADC0, 58 PMIC_AUXADC_DCM_CON, 59 PMIC_AUXADC_IMP0, 60 PMIC_AUXADC_IMP1, 61 PMIC_AUXADC_IMP3, 62 PMIC_AUXADC_RQST0, 63 PMIC_AUXADC_RQST1, 64 PMIC_AUXADC_RQST3, 65 PMIC_AUXADC_SDMADC_CON0, 66 PMIC_HK_TOP_WKEY, 67 PMIC_HK_TOP_RST_CON0, 68 PMIC_FGADC_R_CON0, 69 PMIC_AUXADC_REGS_MAX 70 }; 71 72 enum mtk_pmic_auxadc_channels { 73 PMIC_AUXADC_CHAN_BATADC, 74 PMIC_AUXADC_CHAN_ISENSE, 75 PMIC_AUXADC_CHAN_VCDT, 76 PMIC_AUXADC_CHAN_BAT_TEMP, 77 PMIC_AUXADC_CHAN_BATID, 78 PMIC_AUXADC_CHAN_CHIP_TEMP, 79 PMIC_AUXADC_CHAN_VCORE_TEMP, 80 PMIC_AUXADC_CHAN_VPROC_TEMP, 81 PMIC_AUXADC_CHAN_VGPU_TEMP, 82 PMIC_AUXADC_CHAN_ACCDET, 83 PMIC_AUXADC_CHAN_VDCXO, 84 PMIC_AUXADC_CHAN_TSX_TEMP, 85 PMIC_AUXADC_CHAN_HPOFS_CAL, 86 PMIC_AUXADC_CHAN_DCXO_TEMP, 87 PMIC_AUXADC_CHAN_VTREF, 88 PMIC_AUXADC_CHAN_VBIF, 89 PMIC_AUXADC_CHAN_VSYSSNS, 90 PMIC_AUXADC_CHAN_VIN1, 91 PMIC_AUXADC_CHAN_VIN2, 92 PMIC_AUXADC_CHAN_VIN3, 93 PMIC_AUXADC_CHAN_VIN4, 94 PMIC_AUXADC_CHAN_VIN5, 95 PMIC_AUXADC_CHAN_VIN6, 96 PMIC_AUXADC_CHAN_VIN7, 97 PMIC_AUXADC_CHAN_IBAT, 98 PMIC_AUXADC_CHAN_VBAT, 99 PMIC_AUXADC_CHAN_MAX 100 }; 101 102 /** 103 * struct mt6359_auxadc - Main driver structure 104 * @dev: Device pointer 105 * @regmap: Regmap from SoC PMIC Wrapper 106 * @chip_info: PMIC specific chip info 107 * @lock: Mutex to serialize AUXADC reading vs configuration 108 * @timed_out: Signals whether the last read timed out 109 */ 110 struct mt6359_auxadc { 111 struct device *dev; 112 struct regmap *regmap; 113 const struct mtk_pmic_auxadc_info *chip_info; 114 struct mutex lock; 115 bool timed_out; 116 }; 117 118 /** 119 * struct mtk_pmic_auxadc_chan - PMIC AUXADC channel data 120 * @req_idx: Request register number 121 * @req_mask: Bitmask to activate a channel 122 * @rdy_idx: Readiness register number 123 * @rdy_mask: Bitmask to determine channel readiness 124 * @ext_sel_idx: PMIC GPIO channel register number 125 * @ext_sel_ch: PMIC GPIO number 126 * @ext_sel_pu: PMIC GPIO channel pullup resistor selector 127 * @num_samples: Number of AUXADC samples for averaging 128 * @r_ratio: Resistance ratio fractional 129 */ 130 struct mtk_pmic_auxadc_chan { 131 u8 req_idx; 132 u16 req_mask; 133 u8 rdy_idx; 134 u16 rdy_mask; 135 s8 ext_sel_idx; 136 u8 ext_sel_ch; 137 u8 ext_sel_pu; 138 u16 num_samples; 139 struct u8_fract r_ratio; 140 }; 141 142 /** 143 * struct mtk_pmic_auxadc_info - PMIC specific chip info 144 * @model_name: PMIC model name 145 * @channels: IIO specification of ADC channels 146 * @num_channels: Number of ADC channels 147 * @desc: PMIC AUXADC channel data 148 * @regs: List of PMIC specific registers 149 * @sec_unlock_key: Security unlock key for HK_TOP writes 150 * @vref_mV: AUXADC Reference Voltage (VREF) in millivolts 151 * @imp_adc_num: ADC channel for battery impedance readings 152 * @is_spmi: Defines whether this PMIC communicates over SPMI 153 * @no_reset: If true, this PMIC does not support ADC reset 154 * @read_imp: Callback to read impedance channels 155 */ 156 struct mtk_pmic_auxadc_info { 157 const char *model_name; 158 const struct iio_chan_spec *channels; 159 u8 num_channels; 160 const struct mtk_pmic_auxadc_chan *desc; 161 const u16 *regs; 162 u16 sec_unlock_key; 163 u32 vref_mV; 164 u8 imp_adc_num; 165 bool is_spmi; 166 bool no_reset; 167 int (*read_imp)(struct mt6359_auxadc *adc_dev, 168 const struct iio_chan_spec *chan, int *vbat, int *ibat); 169 }; 170 171 #define MTK_PMIC_ADC_EXT_CHAN(_ch_idx, _req_idx, _req_bit, _rdy_idx, _rdy_bit, \ 172 _ext_sel_idx, _ext_sel_ch, _ext_sel_pu, \ 173 _samples, _rnum, _rdiv) \ 174 [PMIC_AUXADC_CHAN_##_ch_idx] = { \ 175 .req_idx = _req_idx, \ 176 .req_mask = BIT(_req_bit), \ 177 .rdy_idx = _rdy_idx, \ 178 .rdy_mask = BIT(_rdy_bit), \ 179 .ext_sel_idx = _ext_sel_idx, \ 180 .ext_sel_ch = _ext_sel_ch, \ 181 .ext_sel_pu = _ext_sel_pu, \ 182 .num_samples = _samples, \ 183 .r_ratio = { _rnum, _rdiv } \ 184 } 185 186 #define MTK_PMIC_ADC_CHAN(_ch_idx, _req_idx, _req_bit, _rdy_idx, _rdy_bit, \ 187 _samples, _rnum, _rdiv) \ 188 MTK_PMIC_ADC_EXT_CHAN(_ch_idx, _req_idx, _req_bit, _rdy_idx, _rdy_bit, \ 189 -1, 0, 0, _samples, _rnum, _rdiv) 190 191 #define MTK_PMIC_IIO_CHAN(_model, _name, _ch_idx, _adc_idx, _nbits, _ch_type) \ 192 { \ 193 .type = _ch_type, \ 194 .channel = _model##_AUXADC_##_ch_idx, \ 195 .address = _adc_idx, \ 196 .scan_index = PMIC_AUXADC_CHAN_##_ch_idx, \ 197 .datasheet_name = __stringify(_name), \ 198 .scan_type = { \ 199 .sign = 'u', \ 200 .realbits = _nbits, \ 201 .storagebits = 16, \ 202 .endianness = IIO_CPU \ 203 }, \ 204 .indexed = 1, \ 205 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE) \ 206 } 207 208 static const struct iio_chan_spec mt6357_auxadc_channels[] = { 209 MTK_PMIC_IIO_CHAN(MT6357, bat_adc, BATADC, 0, 15, IIO_RESISTANCE), 210 MTK_PMIC_IIO_CHAN(MT6357, isense, ISENSE, 1, 12, IIO_CURRENT), 211 MTK_PMIC_IIO_CHAN(MT6357, cdt_v, VCDT, 2, 12, IIO_TEMP), 212 MTK_PMIC_IIO_CHAN(MT6357, batt_temp, BAT_TEMP, 3, 12, IIO_TEMP), 213 MTK_PMIC_IIO_CHAN(MT6357, chip_temp, CHIP_TEMP, 4, 12, IIO_TEMP), 214 MTK_PMIC_IIO_CHAN(MT6357, acc_det, ACCDET, 5, 12, IIO_RESISTANCE), 215 MTK_PMIC_IIO_CHAN(MT6357, dcxo_v, VDCXO, 6, 12, IIO_VOLTAGE), 216 MTK_PMIC_IIO_CHAN(MT6357, tsx_temp, TSX_TEMP, 7, 15, IIO_TEMP), 217 MTK_PMIC_IIO_CHAN(MT6357, hp_ofs_cal, HPOFS_CAL, 9, 15, IIO_RESISTANCE), 218 MTK_PMIC_IIO_CHAN(MT6357, dcxo_temp, DCXO_TEMP, 36, 15, IIO_TEMP), 219 MTK_PMIC_IIO_CHAN(MT6357, vcore_temp, VCORE_TEMP, 40, 12, IIO_TEMP), 220 MTK_PMIC_IIO_CHAN(MT6357, vproc_temp, VPROC_TEMP, 41, 12, IIO_TEMP), 221 222 /* Battery impedance channels */ 223 MTK_PMIC_IIO_CHAN(MT6357, batt_v, VBAT, 0, 15, IIO_VOLTAGE), 224 }; 225 226 static const struct mtk_pmic_auxadc_chan mt6357_auxadc_ch_desc[] = { 227 MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 128, 3, 1), 228 MTK_PMIC_ADC_CHAN(ISENSE, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 128, 3, 1), 229 MTK_PMIC_ADC_CHAN(VCDT, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 8, 1, 1), 230 MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, PMIC_AUXADC_IMP0, 8, 8, 1, 1), 231 MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, PMIC_AUXADC_IMP0, 8, 8, 1, 1), 232 MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, PMIC_AUXADC_IMP0, 8, 8, 1, 1), 233 MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, PMIC_AUXADC_IMP0, 8, 128, 1, 1), 234 MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, PMIC_AUXADC_IMP0, 8, 256, 1, 1), 235 MTK_PMIC_ADC_CHAN(DCXO_TEMP, PMIC_AUXADC_RQST0, 10, PMIC_AUXADC_IMP0, 8, 16, 1, 1), 236 MTK_PMIC_ADC_CHAN(VBIF, PMIC_AUXADC_RQST0, 11, PMIC_AUXADC_IMP0, 8, 8, 1, 1), 237 MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST1, 5, PMIC_AUXADC_IMP0, 8, 8, 1, 1), 238 MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST1, 6, PMIC_AUXADC_IMP0, 8, 8, 1, 1), 239 240 /* Battery impedance channels */ 241 MTK_PMIC_ADC_CHAN(VBAT, 0, 0, PMIC_AUXADC_IMP0, 8, 128, 3, 1), 242 }; 243 244 static const u16 mt6357_auxadc_regs[] = { 245 [PMIC_HK_TOP_RST_CON0] = 0x0f90, 246 [PMIC_AUXADC_DCM_CON] = 0x122e, 247 [PMIC_AUXADC_ADC0] = 0x1088, 248 [PMIC_AUXADC_IMP0] = 0x119c, 249 [PMIC_AUXADC_IMP1] = 0x119e, 250 [PMIC_AUXADC_RQST0] = 0x110e, 251 [PMIC_AUXADC_RQST1] = 0x1114, 252 }; 253 254 static const struct iio_chan_spec mt6358_auxadc_channels[] = { 255 MTK_PMIC_IIO_CHAN(MT6358, bat_adc, BATADC, 0, 15, IIO_RESISTANCE), 256 MTK_PMIC_IIO_CHAN(MT6358, cdt_v, VCDT, 2, 12, IIO_TEMP), 257 MTK_PMIC_IIO_CHAN(MT6358, batt_temp, BAT_TEMP, 3, 12, IIO_TEMP), 258 MTK_PMIC_IIO_CHAN(MT6358, chip_temp, CHIP_TEMP, 4, 12, IIO_TEMP), 259 MTK_PMIC_IIO_CHAN(MT6358, acc_det, ACCDET, 5, 12, IIO_RESISTANCE), 260 MTK_PMIC_IIO_CHAN(MT6358, dcxo_v, VDCXO, 6, 12, IIO_VOLTAGE), 261 MTK_PMIC_IIO_CHAN(MT6358, tsx_temp, TSX_TEMP, 7, 15, IIO_TEMP), 262 MTK_PMIC_IIO_CHAN(MT6358, hp_ofs_cal, HPOFS_CAL, 9, 15, IIO_RESISTANCE), 263 MTK_PMIC_IIO_CHAN(MT6358, dcxo_temp, DCXO_TEMP, 10, 15, IIO_TEMP), 264 MTK_PMIC_IIO_CHAN(MT6358, bif_v, VBIF, 11, 12, IIO_VOLTAGE), 265 MTK_PMIC_IIO_CHAN(MT6358, vcore_temp, VCORE_TEMP, 38, 12, IIO_TEMP), 266 MTK_PMIC_IIO_CHAN(MT6358, vproc_temp, VPROC_TEMP, 39, 12, IIO_TEMP), 267 MTK_PMIC_IIO_CHAN(MT6358, vgpu_temp, VGPU_TEMP, 40, 12, IIO_TEMP), 268 269 /* Battery impedance channels */ 270 MTK_PMIC_IIO_CHAN(MT6358, batt_v, VBAT, 0, 15, IIO_VOLTAGE), 271 }; 272 273 static const struct mtk_pmic_auxadc_chan mt6358_auxadc_ch_desc[] = { 274 MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 128, 3, 1), 275 MTK_PMIC_ADC_CHAN(VCDT, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 8, 1, 1), 276 MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, PMIC_AUXADC_IMP0, 8, 8, 2, 1), 277 MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, PMIC_AUXADC_IMP0, 8, 8, 1, 1), 278 MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, PMIC_AUXADC_IMP0, 8, 8, 1, 1), 279 MTK_PMIC_ADC_CHAN(VDCXO, PMIC_AUXADC_RQST0, 6, PMIC_AUXADC_IMP0, 8, 8, 3, 2), 280 MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, PMIC_AUXADC_IMP0, 8, 128, 1, 1), 281 MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, PMIC_AUXADC_IMP0, 8, 256, 1, 1), 282 MTK_PMIC_ADC_CHAN(DCXO_TEMP, PMIC_AUXADC_RQST0, 10, PMIC_AUXADC_IMP0, 8, 16, 1, 1), 283 MTK_PMIC_ADC_CHAN(VBIF, PMIC_AUXADC_RQST0, 11, PMIC_AUXADC_IMP0, 8, 8, 2, 1), 284 MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST1, 8, PMIC_AUXADC_IMP0, 8, 8, 1, 1), 285 MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST1, 9, PMIC_AUXADC_IMP0, 8, 8, 1, 1), 286 MTK_PMIC_ADC_CHAN(VGPU_TEMP, PMIC_AUXADC_RQST1, 10, PMIC_AUXADC_IMP0, 8, 8, 1, 1), 287 288 /* Battery impedance channels */ 289 MTK_PMIC_ADC_CHAN(VBAT, 0, 0, PMIC_AUXADC_IMP0, 8, 128, 7, 2), 290 }; 291 292 static const u16 mt6358_auxadc_regs[] = { 293 [PMIC_HK_TOP_RST_CON0] = 0x0f90, 294 [PMIC_AUXADC_DCM_CON] = 0x1260, 295 [PMIC_AUXADC_ADC0] = 0x1088, 296 [PMIC_AUXADC_IMP0] = 0x1208, 297 [PMIC_AUXADC_IMP1] = 0x120a, 298 [PMIC_AUXADC_RQST0] = 0x1108, 299 [PMIC_AUXADC_RQST1] = 0x110a, 300 }; 301 302 static const struct iio_chan_spec mt6359_auxadc_channels[] = { 303 MTK_PMIC_IIO_CHAN(MT6359, bat_adc, BATADC, 0, 15, IIO_RESISTANCE), 304 MTK_PMIC_IIO_CHAN(MT6359, batt_temp, BAT_TEMP, 3, 12, IIO_TEMP), 305 MTK_PMIC_IIO_CHAN(MT6359, chip_temp, CHIP_TEMP, 4, 12, IIO_TEMP), 306 MTK_PMIC_IIO_CHAN(MT6359, acc_det, ACCDET, 5, 12, IIO_RESISTANCE), 307 MTK_PMIC_IIO_CHAN(MT6359, dcxo_v, VDCXO, 6, 12, IIO_VOLTAGE), 308 MTK_PMIC_IIO_CHAN(MT6359, tsx_temp, TSX_TEMP, 7, 15, IIO_TEMP), 309 MTK_PMIC_IIO_CHAN(MT6359, hp_ofs_cal, HPOFS_CAL, 9, 15, IIO_RESISTANCE), 310 MTK_PMIC_IIO_CHAN(MT6359, dcxo_temp, DCXO_TEMP, 10, 15, IIO_TEMP), 311 MTK_PMIC_IIO_CHAN(MT6359, bif_v, VBIF, 11, 12, IIO_VOLTAGE), 312 MTK_PMIC_IIO_CHAN(MT6359, vcore_temp, VCORE_TEMP, 30, 12, IIO_TEMP), 313 MTK_PMIC_IIO_CHAN(MT6359, vproc_temp, VPROC_TEMP, 31, 12, IIO_TEMP), 314 MTK_PMIC_IIO_CHAN(MT6359, vgpu_temp, VGPU_TEMP, 32, 12, IIO_TEMP), 315 316 /* Battery impedance channels */ 317 MTK_PMIC_IIO_CHAN(MT6359, batt_v, VBAT, 0, 15, IIO_VOLTAGE), 318 MTK_PMIC_IIO_CHAN(MT6359, batt_i, IBAT, 0, 15, IIO_CURRENT), 319 }; 320 321 static const struct mtk_pmic_auxadc_chan mt6359_auxadc_ch_desc[] = { 322 MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP1, 15, 128, 7, 2), 323 MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, PMIC_AUXADC_IMP1, 15, 8, 5, 2), 324 MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, PMIC_AUXADC_IMP1, 15, 8, 1, 1), 325 MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, PMIC_AUXADC_IMP1, 15, 8, 1, 1), 326 MTK_PMIC_ADC_CHAN(VDCXO, PMIC_AUXADC_RQST0, 6, PMIC_AUXADC_IMP1, 15, 8, 3, 2), 327 MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, PMIC_AUXADC_IMP1, 15, 128, 1, 1), 328 MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, PMIC_AUXADC_IMP1, 15, 256, 1, 1), 329 MTK_PMIC_ADC_CHAN(DCXO_TEMP, PMIC_AUXADC_RQST0, 10, PMIC_AUXADC_IMP1, 15, 16, 1, 1), 330 MTK_PMIC_ADC_CHAN(VBIF, PMIC_AUXADC_RQST0, 11, PMIC_AUXADC_IMP1, 15, 8, 5, 2), 331 MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST1, 8, PMIC_AUXADC_IMP1, 15, 8, 1, 1), 332 MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST1, 9, PMIC_AUXADC_IMP1, 15, 8, 1, 1), 333 MTK_PMIC_ADC_CHAN(VGPU_TEMP, PMIC_AUXADC_RQST1, 10, PMIC_AUXADC_IMP1, 15, 8, 1, 1), 334 335 /* Battery impedance channels */ 336 MTK_PMIC_ADC_CHAN(VBAT, 0, 0, PMIC_AUXADC_IMP1, 15, 128, 7, 2), 337 MTK_PMIC_ADC_CHAN(IBAT, 0, 0, PMIC_AUXADC_IMP1, 15, 128, 7, 2), 338 }; 339 340 static const u16 mt6359_auxadc_regs[] = { 341 [PMIC_FGADC_R_CON0] = 0x0d88, 342 [PMIC_HK_TOP_WKEY] = 0x0fb4, 343 [PMIC_HK_TOP_RST_CON0] = 0x0f90, 344 [PMIC_AUXADC_RQST0] = 0x1108, 345 [PMIC_AUXADC_RQST1] = 0x110a, 346 [PMIC_AUXADC_ADC0] = 0x1088, 347 [PMIC_AUXADC_IMP0] = 0x1208, 348 [PMIC_AUXADC_IMP1] = 0x120a, 349 [PMIC_AUXADC_IMP3] = 0x120e, 350 }; 351 352 static const struct iio_chan_spec mt6363_auxadc_channels[] = { 353 MTK_PMIC_IIO_CHAN(MT6363, bat_adc, BATADC, 0, 15, IIO_RESISTANCE), 354 MTK_PMIC_IIO_CHAN(MT6363, cdt_v, VCDT, 2, 12, IIO_TEMP), 355 MTK_PMIC_IIO_CHAN(MT6363, batt_temp, BAT_TEMP, 3, 12, IIO_TEMP), 356 MTK_PMIC_IIO_CHAN(MT6363, chip_temp, CHIP_TEMP, 4, 12, IIO_TEMP), 357 MTK_PMIC_IIO_CHAN(MT6363, sys_sns_v, VSYSSNS, 6, 15, IIO_VOLTAGE), 358 MTK_PMIC_IIO_CHAN(MT6363, tref_v, VTREF, 11, 12, IIO_VOLTAGE), 359 MTK_PMIC_IIO_CHAN(MT6363, vcore_temp, VCORE_TEMP, 38, 12, IIO_TEMP), 360 MTK_PMIC_IIO_CHAN(MT6363, vproc_temp, VPROC_TEMP, 39, 12, IIO_TEMP), 361 MTK_PMIC_IIO_CHAN(MT6363, vgpu_temp, VGPU_TEMP, 40, 12, IIO_TEMP), 362 363 /* For VIN, ADC12 holds the result depending on which GPIO was activated */ 364 MTK_PMIC_IIO_CHAN(MT6363, in1_v, VIN1, 45, 15, IIO_VOLTAGE), 365 MTK_PMIC_IIO_CHAN(MT6363, in2_v, VIN2, 45, 15, IIO_VOLTAGE), 366 MTK_PMIC_IIO_CHAN(MT6363, in3_v, VIN3, 45, 15, IIO_VOLTAGE), 367 MTK_PMIC_IIO_CHAN(MT6363, in4_v, VIN4, 45, 15, IIO_VOLTAGE), 368 MTK_PMIC_IIO_CHAN(MT6363, in5_v, VIN5, 45, 15, IIO_VOLTAGE), 369 MTK_PMIC_IIO_CHAN(MT6363, in6_v, VIN6, 45, 15, IIO_VOLTAGE), 370 MTK_PMIC_IIO_CHAN(MT6363, in7_v, VIN7, 45, 15, IIO_VOLTAGE), 371 }; 372 373 static const struct mtk_pmic_auxadc_chan mt6363_auxadc_ch_desc[] = { 374 MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_ADC0, 15, 64, 4, 1), 375 MTK_PMIC_ADC_CHAN(VCDT, PMIC_AUXADC_RQST0, 2, PMIC_AUXADC_ADC0, 15, 32, 1, 1), 376 MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, PMIC_AUXADC_ADC0, 15, 32, 3, 2), 377 MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, PMIC_AUXADC_ADC0, 15, 32, 1, 1), 378 MTK_PMIC_ADC_CHAN(VSYSSNS, PMIC_AUXADC_RQST1, 6, PMIC_AUXADC_ADC0, 15, 64, 3, 1), 379 MTK_PMIC_ADC_CHAN(VTREF, PMIC_AUXADC_RQST1, 3, PMIC_AUXADC_ADC0, 15, 32, 3, 2), 380 MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST3, 0, PMIC_AUXADC_ADC0, 15, 32, 1, 1), 381 MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST3, 1, PMIC_AUXADC_ADC0, 15, 32, 1, 1), 382 MTK_PMIC_ADC_CHAN(VGPU_TEMP, PMIC_AUXADC_RQST3, 2, PMIC_AUXADC_ADC0, 15, 32, 1, 1), 383 384 MTK_PMIC_ADC_EXT_CHAN(VIN1, 385 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, 386 PMIC_AUXADC_SDMADC_CON0, 1, MT6363_PULLUP_RES_100K, 32, 1, 1), 387 MTK_PMIC_ADC_EXT_CHAN(VIN2, 388 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, 389 PMIC_AUXADC_SDMADC_CON0, 2, MT6363_PULLUP_RES_100K, 32, 1, 1), 390 MTK_PMIC_ADC_EXT_CHAN(VIN3, 391 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, 392 PMIC_AUXADC_SDMADC_CON0, 3, MT6363_PULLUP_RES_100K, 32, 1, 1), 393 MTK_PMIC_ADC_EXT_CHAN(VIN4, 394 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, 395 PMIC_AUXADC_SDMADC_CON0, 4, MT6363_PULLUP_RES_100K, 32, 1, 1), 396 MTK_PMIC_ADC_EXT_CHAN(VIN5, 397 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, 398 PMIC_AUXADC_SDMADC_CON0, 5, MT6363_PULLUP_RES_100K, 32, 1, 1), 399 MTK_PMIC_ADC_EXT_CHAN(VIN6, 400 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, 401 PMIC_AUXADC_SDMADC_CON0, 6, MT6363_PULLUP_RES_100K, 32, 1, 1), 402 MTK_PMIC_ADC_EXT_CHAN(VIN7, 403 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, 404 PMIC_AUXADC_SDMADC_CON0, 7, MT6363_PULLUP_RES_100K, 32, 1, 1), 405 }; 406 407 static const u16 mt6363_auxadc_regs[] = { 408 [PMIC_AUXADC_RQST0] = 0x1108, 409 [PMIC_AUXADC_RQST1] = 0x1109, 410 [PMIC_AUXADC_RQST3] = 0x110c, 411 [PMIC_AUXADC_ADC0] = 0x1088, 412 [PMIC_AUXADC_IMP0] = 0x1208, 413 [PMIC_AUXADC_IMP1] = 0x1209, 414 }; 415 416 static const struct iio_chan_spec mt6373_auxadc_channels[] = { 417 MTK_PMIC_IIO_CHAN(MT6363, chip_temp, CHIP_TEMP, 4, 12, IIO_TEMP), 418 MTK_PMIC_IIO_CHAN(MT6363, vcore_temp, VCORE_TEMP, 38, 12, IIO_TEMP), 419 MTK_PMIC_IIO_CHAN(MT6363, vproc_temp, VPROC_TEMP, 39, 12, IIO_TEMP), 420 MTK_PMIC_IIO_CHAN(MT6363, vgpu_temp, VGPU_TEMP, 40, 12, IIO_TEMP), 421 422 /* For VIN, ADC12 holds the result depending on which GPIO was activated */ 423 MTK_PMIC_IIO_CHAN(MT6363, in1_v, VIN1, 45, 15, IIO_VOLTAGE), 424 MTK_PMIC_IIO_CHAN(MT6363, in2_v, VIN2, 45, 15, IIO_VOLTAGE), 425 MTK_PMIC_IIO_CHAN(MT6363, in3_v, VIN3, 45, 15, IIO_VOLTAGE), 426 MTK_PMIC_IIO_CHAN(MT6363, in4_v, VIN4, 45, 15, IIO_VOLTAGE), 427 MTK_PMIC_IIO_CHAN(MT6363, in5_v, VIN5, 45, 15, IIO_VOLTAGE), 428 }; 429 430 static const struct mtk_pmic_auxadc_chan mt6373_auxadc_ch_desc[] = { 431 MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, PMIC_AUXADC_ADC0, 15, 32, 1, 1), 432 MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST3, 0, PMIC_AUXADC_ADC0, 15, 32, 1, 1), 433 MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST3, 1, PMIC_AUXADC_ADC0, 15, 32, 1, 1), 434 MTK_PMIC_ADC_CHAN(VGPU_TEMP, PMIC_AUXADC_RQST3, 2, PMIC_AUXADC_ADC0, 15, 32, 1, 1), 435 436 MTK_PMIC_ADC_EXT_CHAN(VIN1, 437 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, 438 PMIC_AUXADC_SDMADC_CON0, 1, MT6363_PULLUP_RES_30K, 32, 1, 1), 439 MTK_PMIC_ADC_EXT_CHAN(VIN2, 440 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, 441 PMIC_AUXADC_SDMADC_CON0, 2, MT6363_PULLUP_RES_OPEN, 32, 1, 1), 442 MTK_PMIC_ADC_EXT_CHAN(VIN3, 443 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, 444 PMIC_AUXADC_SDMADC_CON0, 3, MT6363_PULLUP_RES_OPEN, 32, 1, 1), 445 MTK_PMIC_ADC_EXT_CHAN(VIN4, 446 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, 447 PMIC_AUXADC_SDMADC_CON0, 4, MT6363_PULLUP_RES_OPEN, 32, 1, 1), 448 MTK_PMIC_ADC_EXT_CHAN(VIN5, 449 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, 450 PMIC_AUXADC_SDMADC_CON0, 5, MT6363_PULLUP_RES_OPEN, 32, 1, 1), 451 }; 452 453 static void mt6358_stop_imp_conv(struct mt6359_auxadc *adc_dev) 454 { 455 const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info; 456 struct regmap *regmap = adc_dev->regmap; 457 458 regmap_set_bits(regmap, cinfo->regs[PMIC_AUXADC_IMP0], MT6358_IMP0_CLEAR); 459 regmap_clear_bits(regmap, cinfo->regs[PMIC_AUXADC_IMP0], MT6358_IMP0_CLEAR); 460 regmap_clear_bits(regmap, cinfo->regs[PMIC_AUXADC_IMP1], MT6358_IMP1_AUTOREPEAT_EN); 461 regmap_clear_bits(regmap, cinfo->regs[PMIC_AUXADC_DCM_CON], MT6358_DCM_CK_SW_EN); 462 } 463 464 static int mt6358_start_imp_conv(struct mt6359_auxadc *adc_dev, const struct iio_chan_spec *chan) 465 { 466 const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info; 467 const struct mtk_pmic_auxadc_chan *desc = &cinfo->desc[chan->scan_index]; 468 struct regmap *regmap = adc_dev->regmap; 469 u32 val; 470 int ret; 471 472 regmap_set_bits(regmap, cinfo->regs[PMIC_AUXADC_DCM_CON], MT6358_DCM_CK_SW_EN); 473 regmap_set_bits(regmap, cinfo->regs[PMIC_AUXADC_IMP1], MT6358_IMP1_AUTOREPEAT_EN); 474 475 ret = regmap_read_poll_timeout(regmap, cinfo->regs[desc->rdy_idx], 476 val, val & desc->rdy_mask, 477 IMP_POLL_DELAY_US, AUXADC_TIMEOUT_US); 478 if (ret) { 479 mt6358_stop_imp_conv(adc_dev); 480 return ret; 481 } 482 483 return 0; 484 } 485 486 static int mt6358_read_imp(struct mt6359_auxadc *adc_dev, 487 const struct iio_chan_spec *chan, int *vbat, int *ibat) 488 { 489 const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info; 490 struct regmap *regmap = adc_dev->regmap; 491 u16 reg_adc0 = cinfo->regs[PMIC_AUXADC_ADC0]; 492 u32 val_v; 493 int ret; 494 495 ret = mt6358_start_imp_conv(adc_dev, chan); 496 if (ret) 497 return ret; 498 499 /* Read the params before stopping */ 500 val_v = 0; 501 regmap_read(regmap, reg_adc0 + (cinfo->imp_adc_num << 1), &val_v); 502 503 mt6358_stop_imp_conv(adc_dev); 504 505 if (vbat) 506 *vbat = val_v; 507 if (ibat) 508 *ibat = 0; 509 510 return 0; 511 } 512 513 static int mt6359_read_imp(struct mt6359_auxadc *adc_dev, 514 const struct iio_chan_spec *chan, int *vbat, int *ibat) 515 { 516 const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info; 517 const struct mtk_pmic_auxadc_chan *desc = &cinfo->desc[chan->scan_index]; 518 struct regmap *regmap = adc_dev->regmap; 519 u32 val, val_v, val_i; 520 int ret; 521 522 /* Start conversion */ 523 regmap_write(regmap, cinfo->regs[PMIC_AUXADC_IMP0], MT6359_IMP0_CONV_EN); 524 ret = regmap_read_poll_timeout(regmap, cinfo->regs[desc->rdy_idx], 525 val, val & desc->rdy_mask, 526 IMP_POLL_DELAY_US, AUXADC_TIMEOUT_US); 527 528 /* Stop conversion regardless of the result */ 529 regmap_write(regmap, cinfo->regs[PMIC_AUXADC_IMP0], 0); 530 if (ret) 531 return ret; 532 533 /* If it succeeded, wait for the registers to be populated */ 534 fsleep(IMP_STOP_DELAY_US); 535 536 ret = regmap_read(regmap, cinfo->regs[PMIC_AUXADC_IMP3], &val_v); 537 if (ret) 538 return ret; 539 540 ret = regmap_read(regmap, cinfo->regs[PMIC_FGADC_R_CON0], &val_i); 541 if (ret) 542 return ret; 543 544 if (vbat) 545 *vbat = val_v; 546 if (ibat) 547 *ibat = val_i; 548 549 return 0; 550 } 551 552 static const struct mtk_pmic_auxadc_info mt6357_chip_info = { 553 .model_name = "MT6357", 554 .channels = mt6357_auxadc_channels, 555 .num_channels = ARRAY_SIZE(mt6357_auxadc_channels), 556 .desc = mt6357_auxadc_ch_desc, 557 .regs = mt6357_auxadc_regs, 558 .imp_adc_num = MT6357_IMP_ADC_NUM, 559 .read_imp = mt6358_read_imp, 560 .vref_mV = 1800, 561 }; 562 563 static const struct mtk_pmic_auxadc_info mt6358_chip_info = { 564 .model_name = "MT6358", 565 .channels = mt6358_auxadc_channels, 566 .num_channels = ARRAY_SIZE(mt6358_auxadc_channels), 567 .desc = mt6358_auxadc_ch_desc, 568 .regs = mt6358_auxadc_regs, 569 .imp_adc_num = MT6358_IMP_ADC_NUM, 570 .read_imp = mt6358_read_imp, 571 .vref_mV = 1800, 572 }; 573 574 static const struct mtk_pmic_auxadc_info mt6359_chip_info = { 575 .model_name = "MT6359", 576 .channels = mt6359_auxadc_channels, 577 .num_channels = ARRAY_SIZE(mt6359_auxadc_channels), 578 .desc = mt6359_auxadc_ch_desc, 579 .regs = mt6359_auxadc_regs, 580 .sec_unlock_key = 0x6359, 581 .read_imp = mt6359_read_imp, 582 .vref_mV = 1800, 583 }; 584 585 static const struct mtk_pmic_auxadc_info mt6363_chip_info = { 586 .model_name = "MT6363", 587 .channels = mt6363_auxadc_channels, 588 .num_channels = ARRAY_SIZE(mt6363_auxadc_channels), 589 .desc = mt6363_auxadc_ch_desc, 590 .regs = mt6363_auxadc_regs, 591 .is_spmi = true, 592 .no_reset = true, 593 .vref_mV = 1840, 594 }; 595 596 static const struct mtk_pmic_auxadc_info mt6373_chip_info = { 597 .model_name = "MT6373", 598 .channels = mt6373_auxadc_channels, 599 .num_channels = ARRAY_SIZE(mt6373_auxadc_channels), 600 .desc = mt6373_auxadc_ch_desc, 601 .regs = mt6363_auxadc_regs, 602 .is_spmi = true, 603 .no_reset = true, 604 .vref_mV = 1840, 605 }; 606 607 static void mt6359_auxadc_reset(struct mt6359_auxadc *adc_dev) 608 { 609 const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info; 610 struct regmap *regmap = adc_dev->regmap; 611 612 /* Some PMICs do not support reset */ 613 if (cinfo->no_reset) 614 return; 615 616 /* Unlock HK_TOP writes */ 617 if (cinfo->sec_unlock_key) 618 regmap_write(regmap, cinfo->regs[PMIC_HK_TOP_WKEY], cinfo->sec_unlock_key); 619 620 /* Assert ADC reset */ 621 regmap_set_bits(regmap, cinfo->regs[PMIC_HK_TOP_RST_CON0], PMIC_RG_RESET_VAL); 622 623 /* De-assert ADC reset. No wait required, as pwrap takes care of that for us. */ 624 regmap_clear_bits(regmap, cinfo->regs[PMIC_HK_TOP_RST_CON0], PMIC_RG_RESET_VAL); 625 626 /* Lock HK_TOP writes again */ 627 if (cinfo->sec_unlock_key) 628 regmap_write(regmap, cinfo->regs[PMIC_HK_TOP_WKEY], 0); 629 } 630 631 /** 632 * mt6359_auxadc_sample_adc_val() - Start ADC channel sampling and read value 633 * @adc_dev: Main driver structure 634 * @chan: IIO Channel spec for requested ADC 635 * @out: Preallocated variable to store the value read from HW 636 * 637 * This function starts the sampling for an ADC channel, waits until all 638 * of the samples are averaged and then reads the value from the HW. 639 * 640 * Note that the caller must stop the ADC sampling on its own, as this 641 * function *never* stops it. 642 * 643 * Return: 644 * Negative number for error; 645 * Upon success returns zero and writes the read value to *out. 646 */ 647 static int mt6359_auxadc_sample_adc_val(struct mt6359_auxadc *adc_dev, 648 const struct iio_chan_spec *chan, u32 *out) 649 { 650 const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info; 651 const struct mtk_pmic_auxadc_chan *desc = &cinfo->desc[chan->scan_index]; 652 struct regmap *regmap = adc_dev->regmap; 653 u32 reg, rdy_mask, val, lval; 654 int ret; 655 656 /* Request to start sampling for ADC channel */ 657 ret = regmap_write(regmap, cinfo->regs[desc->req_idx], desc->req_mask); 658 if (ret) 659 return ret; 660 661 /* Wait until all samples are averaged */ 662 fsleep(desc->num_samples * AUXADC_AVG_TIME_US); 663 664 reg = cinfo->regs[PMIC_AUXADC_ADC0] + (chan->address << 1); 665 rdy_mask = PMIC_AUXADC_RDY_BIT; 666 667 /* 668 * Even though for both PWRAP and SPMI cases the ADC HW signals that 669 * the data is ready by setting AUXADC_RDY_BIT, for SPMI the register 670 * read is only 8 bits long: for this case, the check has to be done 671 * on the ADC(x)_H register (high bits) and the rdy_mask needs to be 672 * shifted to the right by the same 8 bits. 673 */ 674 if (cinfo->is_spmi) { 675 rdy_mask >>= 8; 676 reg += 1; 677 } 678 679 ret = regmap_read_poll_timeout(regmap, reg, val, val & rdy_mask, 680 AUXADC_POLL_DELAY_US, AUXADC_TIMEOUT_US); 681 if (ret) { 682 dev_dbg(adc_dev->dev, "ADC read timeout for chan %lu\n", chan->address); 683 return ret; 684 } 685 686 if (cinfo->is_spmi) { 687 ret = regmap_read(regmap, reg - 1, &lval); 688 if (ret) 689 return ret; 690 691 val = (val << 8) | lval; 692 } 693 694 *out = val; 695 return 0; 696 } 697 698 static int mt6359_auxadc_read_adc(struct mt6359_auxadc *adc_dev, 699 const struct iio_chan_spec *chan, int *out) 700 { 701 const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info; 702 const struct mtk_pmic_auxadc_chan *desc = &cinfo->desc[chan->scan_index]; 703 struct regmap *regmap = adc_dev->regmap; 704 int ret, adc_stop_err; 705 u8 ext_sel; 706 u32 val; 707 708 if (desc->ext_sel_idx >= 0) { 709 ext_sel = FIELD_PREP(MT6363_EXT_PURES_MASK, desc->ext_sel_pu); 710 ext_sel |= FIELD_PREP(MT6363_EXT_CHAN_MASK, desc->ext_sel_ch); 711 712 ret = regmap_update_bits(regmap, cinfo->regs[desc->ext_sel_idx], 713 MT6363_EXT_PURES_MASK | MT6363_EXT_CHAN_MASK, 714 ext_sel); 715 if (ret) 716 return ret; 717 } 718 719 /* 720 * Get sampled value, then stop sampling unconditionally; the gathered 721 * value is good regardless of if the ADC could be stopped. 722 * 723 * Note that if the ADC cannot be stopped but sampling was ok, this 724 * function will not return any error, but will set the timed_out 725 * status: this is not critical, as the ADC may auto recover and auto 726 * stop after some time (depending on the PMIC model); if not, the next 727 * read attempt will return -ETIMEDOUT and, for models that support it, 728 * reset will be triggered. 729 */ 730 ret = mt6359_auxadc_sample_adc_val(adc_dev, chan, &val); 731 732 adc_stop_err = regmap_write(regmap, cinfo->regs[desc->req_idx], 0); 733 if (adc_stop_err) { 734 dev_warn(adc_dev->dev, "Could not stop the ADC: %d\n,", adc_stop_err); 735 adc_dev->timed_out = true; 736 } 737 738 /* If any sampling error occurred, the retrieved value is invalid */ 739 if (ret) 740 return ret; 741 742 /* ...and deactivate the ADC GPIO if previously done */ 743 if (desc->ext_sel_idx >= 0) { 744 ext_sel = FIELD_PREP(MT6363_EXT_PURES_MASK, MT6363_PULLUP_RES_OPEN); 745 746 ret = regmap_update_bits(regmap, cinfo->regs[desc->ext_sel_idx], 747 MT6363_EXT_PURES_MASK, ext_sel); 748 if (ret) 749 return ret; 750 } 751 752 /* Everything went fine, give back the ADC reading */ 753 *out = val & GENMASK(chan->scan_type.realbits - 1, 0); 754 return 0; 755 } 756 757 static int mt6359_auxadc_read_label(struct iio_dev *indio_dev, 758 const struct iio_chan_spec *chan, char *label) 759 { 760 return sysfs_emit(label, "%s\n", chan->datasheet_name); 761 } 762 763 static int mt6359_auxadc_read_raw(struct iio_dev *indio_dev, 764 const struct iio_chan_spec *chan, 765 int *val, int *val2, long mask) 766 { 767 struct mt6359_auxadc *adc_dev = iio_priv(indio_dev); 768 const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info; 769 const struct mtk_pmic_auxadc_chan *desc = &cinfo->desc[chan->scan_index]; 770 int ret; 771 772 if (mask == IIO_CHAN_INFO_SCALE) { 773 *val = desc->r_ratio.numerator * cinfo->vref_mV; 774 775 if (desc->r_ratio.denominator > 1) { 776 *val2 = desc->r_ratio.denominator; 777 return IIO_VAL_FRACTIONAL; 778 } 779 780 return IIO_VAL_INT; 781 } 782 783 scoped_guard(mutex, &adc_dev->lock) { 784 switch (chan->scan_index) { 785 case PMIC_AUXADC_CHAN_IBAT: 786 if (!adc_dev->chip_info->read_imp) 787 return -EOPNOTSUPP; 788 789 ret = adc_dev->chip_info->read_imp(adc_dev, chan, NULL, val); 790 break; 791 case PMIC_AUXADC_CHAN_VBAT: 792 if (!adc_dev->chip_info->read_imp) 793 return -EOPNOTSUPP; 794 795 ret = adc_dev->chip_info->read_imp(adc_dev, chan, val, NULL); 796 break; 797 default: 798 ret = mt6359_auxadc_read_adc(adc_dev, chan, val); 799 break; 800 } 801 } 802 803 if (ret) { 804 /* 805 * If we get more than one timeout, it's possible that the 806 * AUXADC is stuck: perform a full reset to recover it. 807 */ 808 if (ret == -ETIMEDOUT) { 809 if (adc_dev->timed_out) { 810 dev_warn(adc_dev->dev, "Resetting stuck ADC!\r\n"); 811 mt6359_auxadc_reset(adc_dev); 812 } 813 adc_dev->timed_out = true; 814 } 815 return ret; 816 } 817 adc_dev->timed_out = false; 818 819 return IIO_VAL_INT; 820 } 821 822 static const struct iio_info mt6359_auxadc_iio_info = { 823 .read_label = mt6359_auxadc_read_label, 824 .read_raw = mt6359_auxadc_read_raw, 825 }; 826 827 static int mt6359_auxadc_probe(struct platform_device *pdev) 828 { 829 const struct mtk_pmic_auxadc_info *chip_info; 830 struct device *dev = &pdev->dev; 831 struct device *mfd_dev = dev->parent; 832 struct mt6359_auxadc *adc_dev; 833 struct iio_dev *indio_dev; 834 struct device *regmap_dev; 835 struct regmap *regmap; 836 int ret; 837 838 chip_info = device_get_match_data(dev); 839 if (!chip_info) 840 return -EINVAL; 841 /* 842 * The regmap for this device has to be acquired differently for 843 * SoC PMIC Wrapper and SPMI PMIC cases: 844 * 845 * If this is under SPMI, the regmap comes from the direct parent of 846 * this driver: this_device->parent(mfd). 847 * ... or ... 848 * If this is under the SoC PMIC Wrapper, the regmap comes from the 849 * parent of the MT6397 MFD: this_device->parent(mfd)->parent(pwrap) 850 */ 851 if (chip_info->is_spmi) 852 regmap_dev = mfd_dev; 853 else 854 regmap_dev = mfd_dev->parent; 855 856 857 /* Regmap is from SoC PMIC Wrapper, parent of the mt6397 MFD */ 858 regmap = dev_get_regmap(regmap_dev, NULL); 859 if (!regmap) 860 return dev_err_probe(dev, -ENODEV, "Failed to get regmap\n"); 861 862 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc_dev)); 863 if (!indio_dev) 864 return -ENOMEM; 865 866 adc_dev = iio_priv(indio_dev); 867 adc_dev->regmap = regmap; 868 adc_dev->dev = dev; 869 adc_dev->chip_info = chip_info; 870 871 mutex_init(&adc_dev->lock); 872 873 mt6359_auxadc_reset(adc_dev); 874 875 indio_dev->name = adc_dev->chip_info->model_name; 876 indio_dev->info = &mt6359_auxadc_iio_info; 877 indio_dev->modes = INDIO_DIRECT_MODE; 878 indio_dev->channels = adc_dev->chip_info->channels; 879 indio_dev->num_channels = adc_dev->chip_info->num_channels; 880 881 ret = devm_iio_device_register(dev, indio_dev); 882 if (ret) 883 return dev_err_probe(dev, ret, "failed to register iio device\n"); 884 885 return 0; 886 } 887 888 static const struct of_device_id mt6359_auxadc_of_match[] = { 889 { .compatible = "mediatek,mt6357-auxadc", .data = &mt6357_chip_info }, 890 { .compatible = "mediatek,mt6358-auxadc", .data = &mt6358_chip_info }, 891 { .compatible = "mediatek,mt6359-auxadc", .data = &mt6359_chip_info }, 892 { .compatible = "mediatek,mt6363-auxadc", .data = &mt6363_chip_info }, 893 { .compatible = "mediatek,mt6373-auxadc", .data = &mt6373_chip_info }, 894 { } 895 }; 896 MODULE_DEVICE_TABLE(of, mt6359_auxadc_of_match); 897 898 static struct platform_driver mt6359_auxadc_driver = { 899 .driver = { 900 .name = "mt6359-auxadc", 901 .of_match_table = mt6359_auxadc_of_match, 902 }, 903 .probe = mt6359_auxadc_probe, 904 }; 905 module_platform_driver(mt6359_auxadc_driver); 906 907 MODULE_LICENSE("GPL"); 908 MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>"); 909 MODULE_DESCRIPTION("MediaTek MT6359 PMIC AUXADC Driver"); 910