1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #include <linux/dma-mapping.h> 9 #include <linux/fault-inject.h> 10 #include <linux/debugfs.h> 11 #include <linux/of_address.h> 12 #include <linux/uaccess.h> 13 14 #include <drm/drm_drv.h> 15 #include <drm/drm_file.h> 16 #include <drm/drm_ioctl.h> 17 #include <drm/drm_of.h> 18 19 #include "msm_drv.h" 20 #include "msm_debugfs.h" 21 #include "msm_gem.h" 22 #include "msm_gpu.h" 23 #include "msm_kms.h" 24 25 /* 26 * MSM driver version: 27 * - 1.0.0 - initial interface 28 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers 29 * - 1.2.0 - adds explicit fence support for submit ioctl 30 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW + 31 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for 32 * MSM_GEM_INFO ioctl. 33 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get 34 * GEM object's debug name 35 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl 36 * - 1.6.0 - Syncobj support 37 * - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count 38 * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx) 39 * - 1.9.0 - Add MSM_SUBMIT_FENCE_SN_IN 40 * - 1.10.0 - Add MSM_SUBMIT_BO_NO_IMPLICIT 41 * - 1.11.0 - Add wait boost (MSM_WAIT_FENCE_BOOST, MSM_PREP_BOOST) 42 * - 1.12.0 - Add MSM_INFO_SET_METADATA and MSM_INFO_GET_METADATA 43 * - 1.13.0 - Add VM_BIND 44 */ 45 #define MSM_VERSION_MAJOR 1 46 #define MSM_VERSION_MINOR 13 47 #define MSM_VERSION_PATCHLEVEL 0 48 49 bool dumpstate; 50 MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors"); 51 module_param(dumpstate, bool, 0600); 52 53 static bool modeset = true; 54 MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)"); 55 module_param(modeset, bool, 0600); 56 57 /* 58 * separate_gpu_kms (tristate): 59 * -1 (default): decide automatically based on hardware topology. Split devices 60 * if there is more than one GPU or more than one display master. 61 * 0: force single DRM device (bind display + GPU) 62 * 1: force separate DRM devices 63 */ 64 static int separate_gpu_kms = -1; 65 MODULE_PARM_DESC(separate_gpu_kms, 66 "Use separate DRM device for the GPU (-1=auto (default), 0=single DRM device, 1=separate DRM devices)"); 67 module_param(separate_gpu_kms, int, 0400); 68 69 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 70 static bool transparent_hugepage = true; 71 module_param(transparent_hugepage, bool, 0400); 72 MODULE_PARM_DESC(transparent_hugepage, "Use a dedicated tmpfs mount point with Transparent Hugepage enabled (true = default)"); 73 #else 74 #define transparent_hugepage false 75 #endif 76 77 DECLARE_FAULT_ATTR(fail_gem_alloc); 78 DECLARE_FAULT_ATTR(fail_gem_iova); 79 80 static void msm_gem_thp_init(struct drm_device *dev) 81 { 82 int err; 83 84 if (!transparent_hugepage) 85 return; 86 87 err = drm_gem_huge_mnt_create(dev, "within_size"); 88 if (drm_gem_get_huge_mnt(dev)) 89 drm_info(dev, "Using Transparent Hugepage\n"); 90 else if (err) 91 drm_warn(dev, "Can't use Transparent Hugepage (%d)\n", err); 92 } 93 94 static const struct of_device_id msm_gpu_match[]; 95 static inline bool msm_gpu_node_present(struct device_node *np) 96 { 97 return np && of_device_is_available(np) && adreno_has_gpu(np); 98 } 99 100 static int msm_count_gpus(void) 101 { 102 struct device_node *np; 103 int count = 0; 104 105 for_each_matching_node(np, msm_gpu_match) { 106 if (msm_gpu_node_present(np)) 107 count++; 108 } 109 110 return count; 111 } 112 113 static bool msm_separate_gpu_kms_auto(void) 114 { 115 int gpus = msm_count_gpus(); 116 int display_subsystems = msm_count_mdss() + msm_count_mdp4(); 117 118 if (gpus <= 0 || display_subsystems <= 0) 119 return false; 120 121 /* Single card if there is exactly one GPU and one display subsystem */ 122 return gpus > 1 || display_subsystems > 1; 123 } 124 125 bool msm_separate_gpu_kms_components(void) 126 { 127 if (msm_count_gpus() == 0) 128 return true; 129 130 switch (separate_gpu_kms) { 131 case 0: 132 return false; 133 case 1: 134 return true; 135 default: 136 return msm_separate_gpu_kms_auto(); 137 } 138 } 139 140 static int msm_drm_uninit(struct device *dev, const struct component_ops *gpu_ops) 141 { 142 struct platform_device *pdev = to_platform_device(dev); 143 struct msm_drm_private *priv = platform_get_drvdata(pdev); 144 struct drm_device *ddev = priv->dev; 145 146 /* 147 * Shutdown the hw if we're far enough along where things might be on. 148 * If we run this too early, we'll end up panicking in any variety of 149 * places. Since we don't register the drm device until late in 150 * msm_drm_init, drm_dev->registered is used as an indicator that the 151 * shutdown will be successful. 152 */ 153 if (ddev->registered) { 154 drm_dev_unregister(ddev); 155 if (priv->kms) 156 msm_drm_kms_unregister(dev); 157 } 158 159 msm_gem_shrinker_cleanup(ddev); 160 161 msm_rd_debugfs_cleanup(priv); 162 163 if (priv->kms) 164 msm_drm_kms_uninit(dev); 165 166 if (gpu_ops) 167 gpu_ops->unbind(dev, dev, NULL); 168 else 169 component_unbind_all(dev, ddev); 170 171 ddev->dev_private = NULL; 172 drm_dev_put(ddev); 173 174 return 0; 175 } 176 177 static int msm_drm_init(struct device *dev, const struct drm_driver *drv, 178 const struct component_ops *gpu_ops) 179 { 180 struct msm_drm_private *priv = dev_get_drvdata(dev); 181 struct drm_device *ddev; 182 int ret; 183 184 if (drm_firmware_drivers_only()) 185 return -ENODEV; 186 187 ddev = drm_dev_alloc(drv, dev); 188 if (IS_ERR(ddev)) { 189 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n"); 190 return PTR_ERR(ddev); 191 } 192 ddev->dev_private = priv; 193 priv->dev = ddev; 194 195 INIT_LIST_HEAD(&priv->objects); 196 mutex_init(&priv->obj_lock); 197 198 /* 199 * Initialize the LRUs: 200 */ 201 drm_gem_lru_init(&priv->lru.unbacked); 202 drm_gem_lru_init(&priv->lru.pinned); 203 drm_gem_lru_init(&priv->lru.willneed); 204 drm_gem_lru_init(&priv->lru.dontneed); 205 206 /* Initialize stall-on-fault */ 207 spin_lock_init(&priv->fault_stall_lock); 208 priv->stall_enabled = true; 209 210 /* Teach lockdep about lock ordering wrt. shrinker: */ 211 fs_reclaim_acquire(GFP_KERNEL); 212 might_lock(&ddev->gem_lru_mutex); 213 fs_reclaim_release(GFP_KERNEL); 214 215 if (priv->kms_init) { 216 ret = drmm_mode_config_init(ddev); 217 if (ret) 218 goto err_put_dev; 219 } 220 221 dma_set_max_seg_size(dev, UINT_MAX); 222 223 /* Bind all our sub-components: */ 224 if (gpu_ops) 225 ret = gpu_ops->bind(dev, dev, NULL); 226 else 227 ret = component_bind_all(dev, ddev); 228 if (ret) 229 goto err_put_dev; 230 231 ret = msm_gem_shrinker_init(ddev); 232 if (ret) 233 goto err_msm_uninit; 234 235 msm_gem_thp_init(ddev); 236 237 if (priv->kms_init) { 238 ret = msm_drm_kms_init(dev, drv); 239 if (ret) 240 goto err_msm_uninit; 241 } 242 243 ret = drm_dev_register(ddev, 0); 244 if (ret) 245 goto err_msm_uninit; 246 247 ret = msm_debugfs_late_init(ddev); 248 if (ret) 249 goto err_msm_uninit; 250 251 if (priv->kms_init) 252 msm_drm_kms_post_init(dev); 253 254 return 0; 255 256 err_msm_uninit: 257 msm_drm_uninit(dev, gpu_ops); 258 259 return ret; 260 261 err_put_dev: 262 drm_dev_put(ddev); 263 264 return ret; 265 } 266 267 /* 268 * DRM operations: 269 */ 270 271 static void load_gpu(struct drm_device *dev) 272 { 273 static DEFINE_MUTEX(init_lock); 274 struct msm_drm_private *priv = dev->dev_private; 275 276 mutex_lock(&init_lock); 277 278 if (!priv->gpu) 279 priv->gpu = adreno_load_gpu(dev); 280 281 mutex_unlock(&init_lock); 282 } 283 284 /** 285 * msm_context_vm - lazily create the context's VM 286 * 287 * @dev: the drm device 288 * @ctx: the context 289 * 290 * The VM is lazily created, so that userspace has a chance to opt-in to having 291 * a userspace managed VM before the VM is created. 292 * 293 * Note that this does not return a reference to the VM. Once the VM is created, 294 * it exists for the lifetime of the context. 295 */ 296 struct drm_gpuvm *msm_context_vm(struct drm_device *dev, struct msm_context *ctx) 297 { 298 struct msm_drm_private *priv = dev->dev_private; 299 struct drm_gpuvm *vm = smp_load_acquire(&ctx->vm); 300 301 /* Once ctx->vm is created it is valid for the lifetime of the context: */ 302 if (vm) 303 return vm; 304 305 guard(rwsem_write)(&ctx->ctxlock); 306 307 if (!ctx->vm) { 308 vm = msm_gpu_create_private_vm( 309 priv->gpu, current, !ctx->userspace_managed_vm); 310 if (!IS_ERR_OR_NULL(vm)) 311 smp_store_release(&ctx->vm, vm); 312 } 313 314 return ctx->vm; 315 } 316 317 static int context_init(struct drm_device *dev, struct drm_file *file) 318 { 319 static atomic_t ident = ATOMIC_INIT(0); 320 struct msm_context *ctx; 321 322 ctx = kzalloc_obj(*ctx); 323 if (!ctx) 324 return -ENOMEM; 325 326 INIT_LIST_HEAD(&ctx->submitqueues); 327 init_rwsem(&ctx->ctxlock); 328 329 kref_init(&ctx->ref); 330 msm_submitqueue_init(dev, ctx); 331 332 file->driver_priv = ctx; 333 334 ctx->seqno = atomic_inc_return(&ident); 335 336 return 0; 337 } 338 339 static int msm_open(struct drm_device *dev, struct drm_file *file) 340 { 341 /* For now, load gpu on open.. to avoid the requirement of having 342 * firmware in the initrd. 343 */ 344 load_gpu(dev); 345 346 return context_init(dev, file); 347 } 348 349 static void context_close(struct msm_context *ctx) 350 { 351 ctx->closed = true; 352 msm_submitqueue_close(ctx); 353 msm_context_put(ctx); 354 } 355 356 static void msm_postclose(struct drm_device *dev, struct drm_file *file) 357 { 358 struct msm_drm_private *priv = dev->dev_private; 359 struct msm_context *ctx = file->driver_priv; 360 361 /* 362 * It is not possible to set sysprof param to non-zero if gpu 363 * is not initialized: 364 */ 365 if (priv->gpu) 366 msm_context_set_sysprof(ctx, priv->gpu, 0); 367 368 context_close(ctx); 369 } 370 371 /* 372 * DRM ioctls: 373 */ 374 375 static int msm_ioctl_get_param(struct drm_device *dev, void *data, 376 struct drm_file *file) 377 { 378 struct msm_drm_private *priv = dev->dev_private; 379 struct drm_msm_param *args = data; 380 struct msm_gpu *gpu; 381 382 /* for now, we just have 3d pipe.. eventually this would need to 383 * be more clever to dispatch to appropriate gpu module: 384 */ 385 if ((args->pipe != MSM_PIPE_3D0) || (args->pad != 0)) 386 return -EINVAL; 387 388 gpu = priv->gpu; 389 390 if (!gpu) 391 return -ENXIO; 392 393 return gpu->funcs->get_param(gpu, file->driver_priv, 394 args->param, &args->value, &args->len); 395 } 396 397 static int msm_ioctl_set_param(struct drm_device *dev, void *data, 398 struct drm_file *file) 399 { 400 struct msm_drm_private *priv = dev->dev_private; 401 struct drm_msm_param *args = data; 402 struct msm_gpu *gpu; 403 404 if ((args->pipe != MSM_PIPE_3D0) || (args->pad != 0)) 405 return -EINVAL; 406 407 gpu = priv->gpu; 408 409 if (!gpu) 410 return -ENXIO; 411 412 return gpu->funcs->set_param(gpu, file->driver_priv, 413 args->param, args->value, args->len); 414 } 415 416 static int msm_ioctl_gem_new(struct drm_device *dev, void *data, 417 struct drm_file *file) 418 { 419 struct drm_msm_gem_new *args = data; 420 uint32_t flags = args->flags; 421 422 if (args->flags & ~MSM_BO_FLAGS) { 423 DRM_ERROR("invalid flags: %08x\n", args->flags); 424 return -EINVAL; 425 } 426 427 /* 428 * Uncached CPU mappings are deprecated, as of: 429 * 430 * 9ef364432db4 ("drm/msm: deprecate MSM_BO_UNCACHED (map as writecombine instead)") 431 * 432 * So promote them to WC. 433 */ 434 if (flags & MSM_BO_UNCACHED) { 435 flags &= ~MSM_BO_CACHED; 436 flags |= MSM_BO_WC; 437 } 438 439 if (should_fail(&fail_gem_alloc, args->size)) 440 return -ENOMEM; 441 442 return msm_gem_new_handle(dev, file, args->size, 443 args->flags, &args->handle, NULL); 444 } 445 446 static inline ktime_t to_ktime(struct drm_msm_timespec timeout) 447 { 448 return ktime_set(timeout.tv_sec, timeout.tv_nsec); 449 } 450 451 static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data, 452 struct drm_file *file) 453 { 454 struct drm_msm_gem_cpu_prep *args = data; 455 struct drm_gem_object *obj; 456 ktime_t timeout = to_ktime(args->timeout); 457 int ret; 458 459 if (args->op & ~MSM_PREP_FLAGS) { 460 DRM_ERROR("invalid op: %08x\n", args->op); 461 return -EINVAL; 462 } 463 464 obj = drm_gem_object_lookup(file, args->handle); 465 if (!obj) 466 return -ENOENT; 467 468 ret = msm_gem_cpu_prep(obj, args->op, &timeout); 469 470 drm_gem_object_put(obj); 471 472 return ret; 473 } 474 475 static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data, 476 struct drm_file *file) 477 { 478 struct drm_msm_gem_cpu_fini *args = data; 479 struct drm_gem_object *obj; 480 int ret; 481 482 obj = drm_gem_object_lookup(file, args->handle); 483 if (!obj) 484 return -ENOENT; 485 486 ret = msm_gem_cpu_fini(obj); 487 488 drm_gem_object_put(obj); 489 490 return ret; 491 } 492 493 static int msm_ioctl_gem_info_iova(struct drm_device *dev, 494 struct drm_file *file, struct drm_gem_object *obj, 495 uint64_t *iova) 496 { 497 struct msm_drm_private *priv = dev->dev_private; 498 struct msm_context *ctx = file->driver_priv; 499 struct drm_gpuvm *vm = msm_context_vm(dev, ctx); 500 501 if (!priv->gpu) 502 return -EINVAL; 503 504 if (!vm) 505 return UERR(ENOMEM, dev, "no VM"); 506 507 if (msm_context_is_vmbind(ctx)) 508 return UERR(EINVAL, dev, "VM_BIND is enabled"); 509 510 if (should_fail(&fail_gem_iova, obj->size)) 511 return -ENOMEM; 512 513 /* 514 * Don't pin the memory here - just get an address so that userspace can 515 * be productive 516 */ 517 return msm_gem_get_iova(obj, vm, iova); 518 } 519 520 static int msm_ioctl_gem_info_set_iova(struct drm_device *dev, 521 struct drm_file *file, struct drm_gem_object *obj, 522 uint64_t iova) 523 { 524 struct msm_drm_private *priv = dev->dev_private; 525 struct msm_context *ctx = file->driver_priv; 526 struct drm_gpuvm *vm = msm_context_vm(dev, ctx); 527 528 if (!priv->gpu) 529 return -EINVAL; 530 531 if (!vm) 532 return UERR(ENOMEM, dev, "no VM"); 533 534 if (msm_context_is_vmbind(ctx)) 535 return UERR(EINVAL, dev, "VM_BIND is enabled"); 536 537 /* Only supported if per-process address space is supported: */ 538 if (priv->gpu->vm == vm) 539 return UERR(EOPNOTSUPP, dev, "requires per-process pgtables"); 540 541 if (should_fail(&fail_gem_iova, obj->size)) 542 return -ENOMEM; 543 544 return msm_gem_set_iova(obj, vm, iova); 545 } 546 547 static int msm_ioctl_gem_info_set_metadata(struct drm_gem_object *obj, 548 __user void *metadata, 549 u32 metadata_size) 550 { 551 struct msm_gem_object *msm_obj = to_msm_bo(obj); 552 void *new_metadata; 553 void *buf; 554 int ret; 555 556 /* Impose a moderate upper bound on metadata size: */ 557 if (metadata_size > 128) { 558 return -EOVERFLOW; 559 } 560 561 /* Use a temporary buf to keep copy_from_user() outside of gem obj lock: */ 562 buf = memdup_user(metadata, metadata_size); 563 if (IS_ERR(buf)) 564 return PTR_ERR(buf); 565 566 ret = msm_gem_lock_interruptible(obj); 567 if (ret) 568 goto out; 569 570 new_metadata = 571 krealloc(msm_obj->metadata, metadata_size, GFP_KERNEL); 572 if (!new_metadata) { 573 ret = -ENOMEM; 574 goto out; 575 } 576 577 msm_obj->metadata = new_metadata; 578 msm_obj->metadata_size = metadata_size; 579 memcpy(msm_obj->metadata, buf, metadata_size); 580 581 msm_gem_unlock(obj); 582 583 out: 584 kfree(buf); 585 586 return ret; 587 } 588 589 static int msm_ioctl_gem_info_get_metadata(struct drm_gem_object *obj, 590 __user void *metadata, 591 u32 *metadata_size) 592 { 593 struct msm_gem_object *msm_obj = to_msm_bo(obj); 594 void *buf; 595 int ret, len; 596 597 if (!metadata) { 598 /* 599 * Querying the size is inherently racey, but 600 * EXT_external_objects expects the app to confirm 601 * via device and driver UUIDs that the exporter and 602 * importer versions match. All we can do from the 603 * kernel side is check the length under obj lock 604 * when userspace tries to retrieve the metadata 605 */ 606 *metadata_size = msm_obj->metadata_size; 607 return 0; 608 } 609 610 ret = msm_gem_lock_interruptible(obj); 611 if (ret) 612 return ret; 613 614 /* Avoid copy_to_user() under gem obj lock: */ 615 len = msm_obj->metadata_size; 616 buf = kmemdup(msm_obj->metadata, len, GFP_KERNEL); 617 618 if (!buf) { 619 msm_gem_unlock(obj); 620 return -ENOMEM; 621 } 622 623 msm_gem_unlock(obj); 624 625 if (*metadata_size < len) { 626 ret = -ETOOSMALL; 627 } else if (copy_to_user(metadata, buf, len)) { 628 ret = -EFAULT; 629 } else { 630 *metadata_size = len; 631 } 632 633 kfree(buf); 634 635 return ret; 636 } 637 638 static int msm_ioctl_gem_info(struct drm_device *dev, void *data, 639 struct drm_file *file) 640 { 641 struct drm_msm_gem_info *args = data; 642 struct drm_gem_object *obj; 643 struct msm_gem_object *msm_obj; 644 int i, ret = 0; 645 646 if (args->pad) 647 return -EINVAL; 648 649 switch (args->info) { 650 case MSM_INFO_GET_OFFSET: 651 case MSM_INFO_GET_IOVA: 652 case MSM_INFO_SET_IOVA: 653 case MSM_INFO_GET_FLAGS: 654 /* value returned as immediate, not pointer, so len==0: */ 655 if (args->len) 656 return -EINVAL; 657 break; 658 case MSM_INFO_SET_NAME: 659 case MSM_INFO_GET_NAME: 660 case MSM_INFO_SET_METADATA: 661 case MSM_INFO_GET_METADATA: 662 break; 663 default: 664 return -EINVAL; 665 } 666 667 obj = drm_gem_object_lookup(file, args->handle); 668 if (!obj) 669 return -ENOENT; 670 671 msm_obj = to_msm_bo(obj); 672 673 switch (args->info) { 674 case MSM_INFO_GET_OFFSET: 675 ret = drm_gem_create_mmap_offset(obj); 676 if (ret == 0) 677 args->value = drm_vma_node_offset_addr(&obj->vma_node); 678 break; 679 case MSM_INFO_GET_IOVA: 680 ret = msm_ioctl_gem_info_iova(dev, file, obj, &args->value); 681 break; 682 case MSM_INFO_SET_IOVA: 683 ret = msm_ioctl_gem_info_set_iova(dev, file, obj, args->value); 684 break; 685 case MSM_INFO_GET_FLAGS: 686 if (drm_gem_is_imported(obj)) { 687 ret = -EINVAL; 688 break; 689 } 690 /* Hide internal kernel-only flags: */ 691 args->value = to_msm_bo(obj)->flags & MSM_BO_FLAGS; 692 ret = 0; 693 break; 694 case MSM_INFO_SET_NAME: 695 /* length check should leave room for terminating null: */ 696 if (args->len >= sizeof(msm_obj->name)) { 697 ret = -EINVAL; 698 break; 699 } 700 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value), 701 args->len)) { 702 msm_obj->name[0] = '\0'; 703 ret = -EFAULT; 704 break; 705 } 706 msm_obj->name[args->len] = '\0'; 707 for (i = 0; i < args->len; i++) { 708 if (!isprint(msm_obj->name[i])) { 709 msm_obj->name[i] = '\0'; 710 break; 711 } 712 } 713 break; 714 case MSM_INFO_GET_NAME: 715 if (args->value && (args->len < strlen(msm_obj->name))) { 716 ret = -ETOOSMALL; 717 break; 718 } 719 args->len = strlen(msm_obj->name); 720 if (args->value) { 721 if (copy_to_user(u64_to_user_ptr(args->value), 722 msm_obj->name, args->len)) 723 ret = -EFAULT; 724 } 725 break; 726 case MSM_INFO_SET_METADATA: 727 ret = msm_ioctl_gem_info_set_metadata( 728 obj, u64_to_user_ptr(args->value), args->len); 729 break; 730 case MSM_INFO_GET_METADATA: 731 ret = msm_ioctl_gem_info_get_metadata( 732 obj, u64_to_user_ptr(args->value), &args->len); 733 break; 734 } 735 736 drm_gem_object_put(obj); 737 738 return ret; 739 } 740 741 static int wait_fence(struct msm_gpu_submitqueue *queue, uint32_t fence_id, 742 ktime_t timeout, uint32_t flags) 743 { 744 struct dma_fence *fence; 745 int ret; 746 747 if (fence_after(fence_id, queue->last_fence)) { 748 DRM_ERROR_RATELIMITED("waiting on invalid fence: %u (of %u)\n", 749 fence_id, queue->last_fence); 750 return -EINVAL; 751 } 752 753 /* 754 * Map submitqueue scoped "seqno" (which is actually an idr key) 755 * back to underlying dma-fence 756 * 757 * The fence is removed from the fence_idr when the submit is 758 * retired, so if the fence is not found it means there is nothing 759 * to wait for 760 */ 761 spin_lock(&queue->idr_lock); 762 fence = idr_find(&queue->fence_idr, fence_id); 763 if (fence) 764 fence = dma_fence_get_rcu(fence); 765 spin_unlock(&queue->idr_lock); 766 767 if (!fence) 768 return 0; 769 770 if (flags & MSM_WAIT_FENCE_BOOST) 771 dma_fence_set_deadline(fence, ktime_get()); 772 773 ret = dma_fence_wait_timeout(fence, true, timeout_to_jiffies(&timeout)); 774 if (ret == 0) { 775 ret = -ETIMEDOUT; 776 } else if (ret != -ERESTARTSYS) { 777 ret = 0; 778 } 779 780 dma_fence_put(fence); 781 782 return ret; 783 } 784 785 static int msm_ioctl_wait_fence(struct drm_device *dev, void *data, 786 struct drm_file *file) 787 { 788 struct msm_drm_private *priv = dev->dev_private; 789 struct drm_msm_wait_fence *args = data; 790 struct msm_gpu_submitqueue *queue; 791 int ret; 792 793 if (args->flags & ~MSM_WAIT_FENCE_FLAGS) { 794 DRM_ERROR("invalid flags: %08x\n", args->flags); 795 return -EINVAL; 796 } 797 798 if (!priv->gpu) 799 return 0; 800 801 queue = msm_submitqueue_get(file->driver_priv, args->queueid); 802 if (!queue) 803 return -ENOENT; 804 805 ret = wait_fence(queue, args->fence, to_ktime(args->timeout), args->flags); 806 807 msm_submitqueue_put(queue); 808 809 return ret; 810 } 811 812 static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data, 813 struct drm_file *file) 814 { 815 struct drm_msm_gem_madvise *args = data; 816 struct drm_gem_object *obj; 817 int ret; 818 819 switch (args->madv) { 820 case MSM_MADV_DONTNEED: 821 case MSM_MADV_WILLNEED: 822 break; 823 default: 824 return -EINVAL; 825 } 826 827 obj = drm_gem_object_lookup(file, args->handle); 828 if (!obj) { 829 return -ENOENT; 830 } 831 832 ret = msm_gem_madvise(obj, args->madv); 833 if (ret >= 0) { 834 args->retained = ret; 835 ret = 0; 836 } 837 838 drm_gem_object_put(obj); 839 840 return ret; 841 } 842 843 844 static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data, 845 struct drm_file *file) 846 { 847 struct drm_msm_submitqueue *args = data; 848 849 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS) 850 return -EINVAL; 851 852 return msm_submitqueue_create(dev, file->driver_priv, args->prio, 853 args->flags, &args->id); 854 } 855 856 static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data, 857 struct drm_file *file) 858 { 859 return msm_submitqueue_query(dev, file->driver_priv, data); 860 } 861 862 static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data, 863 struct drm_file *file) 864 { 865 u32 id = *(u32 *) data; 866 867 return msm_submitqueue_remove(file->driver_priv, id); 868 } 869 870 static const struct drm_ioctl_desc msm_ioctls[] = { 871 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_ALLOW), 872 DRM_IOCTL_DEF_DRV(MSM_SET_PARAM, msm_ioctl_set_param, DRM_RENDER_ALLOW), 873 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_RENDER_ALLOW), 874 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_RENDER_ALLOW), 875 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW), 876 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW), 877 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_RENDER_ALLOW), 878 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_RENDER_ALLOW), 879 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_ALLOW), 880 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_RENDER_ALLOW), 881 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW), 882 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW), 883 DRM_IOCTL_DEF_DRV(MSM_VM_BIND, msm_ioctl_vm_bind, DRM_RENDER_ALLOW), 884 DRM_IOCTL_DEF_DRV(MSM_PERFCNTR_CONFIG, msm_ioctl_perfcntr_config, DRM_RENDER_ALLOW), 885 }; 886 887 static void msm_show_fdinfo(struct drm_printer *p, struct drm_file *file) 888 { 889 struct drm_device *dev = file->minor->dev; 890 struct msm_drm_private *priv = dev->dev_private; 891 892 if (!priv->gpu) 893 return; 894 895 msm_gpu_show_fdinfo(priv->gpu, file->driver_priv, p); 896 897 drm_show_memory_stats(p, file); 898 } 899 900 static const struct file_operations fops = { 901 .owner = THIS_MODULE, 902 DRM_GEM_FOPS, 903 .show_fdinfo = drm_show_fdinfo, 904 }; 905 906 #define DRIVER_FEATURES_GPU ( \ 907 DRIVER_GEM | \ 908 DRIVER_RENDER | \ 909 DRIVER_SYNCOBJ | \ 910 DRIVER_SYNCOBJ_TIMELINE | \ 911 0 ) 912 913 #define DRIVER_FEATURES_KMS ( \ 914 DRIVER_GEM | \ 915 DRIVER_ATOMIC | \ 916 DRIVER_MODESET | \ 917 0 ) 918 919 static const struct drm_driver msm_driver = { 920 .driver_features = DRIVER_FEATURES_GPU | DRIVER_FEATURES_KMS, 921 .open = msm_open, 922 .postclose = msm_postclose, 923 .dumb_create = msm_gem_dumb_create, 924 .dumb_map_offset = drm_gem_dumb_map_offset, 925 .gem_prime_import = msm_gem_prime_import, 926 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table, 927 #ifdef CONFIG_DEBUG_FS 928 .debugfs_init = msm_debugfs_init, 929 #endif 930 MSM_FBDEV_DRIVER_OPS, 931 .show_fdinfo = msm_show_fdinfo, 932 .ioctls = msm_ioctls, 933 .num_ioctls = ARRAY_SIZE(msm_ioctls), 934 .fops = &fops, 935 .name = "msm", 936 .desc = "MSM Snapdragon DRM", 937 .major = MSM_VERSION_MAJOR, 938 .minor = MSM_VERSION_MINOR, 939 .patchlevel = MSM_VERSION_PATCHLEVEL, 940 }; 941 942 static const struct drm_driver msm_kms_driver = { 943 .driver_features = DRIVER_FEATURES_KMS, 944 .open = msm_open, 945 .postclose = msm_postclose, 946 .dumb_create = msm_gem_dumb_create, 947 .dumb_map_offset = drm_gem_dumb_map_offset, 948 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table, 949 #ifdef CONFIG_DEBUG_FS 950 .debugfs_init = msm_debugfs_init, 951 #endif 952 MSM_FBDEV_DRIVER_OPS, 953 .show_fdinfo = msm_show_fdinfo, 954 .fops = &fops, 955 .name = "msm-kms", 956 .desc = "MSM Snapdragon DRM", 957 .major = MSM_VERSION_MAJOR, 958 .minor = MSM_VERSION_MINOR, 959 .patchlevel = MSM_VERSION_PATCHLEVEL, 960 }; 961 962 static const struct drm_driver msm_gpu_driver = { 963 .driver_features = DRIVER_FEATURES_GPU, 964 .open = msm_open, 965 .postclose = msm_postclose, 966 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table, 967 #ifdef CONFIG_DEBUG_FS 968 .debugfs_init = msm_debugfs_init, 969 #endif 970 .show_fdinfo = msm_show_fdinfo, 971 .ioctls = msm_ioctls, 972 .num_ioctls = ARRAY_SIZE(msm_ioctls), 973 .fops = &fops, 974 .name = "msm", 975 .desc = "MSM Snapdragon DRM", 976 .major = MSM_VERSION_MAJOR, 977 .minor = MSM_VERSION_MINOR, 978 .patchlevel = MSM_VERSION_PATCHLEVEL, 979 }; 980 981 /* 982 * Componentized driver support: 983 */ 984 985 /* 986 * Identify what components need to be added by parsing what remote-endpoints 987 * our MDP output ports are connected to. In the case of LVDS on MDP4, there 988 * is no external component that we need to add since LVDS is within MDP4 989 * itself. 990 */ 991 static int add_mdp_components(struct device *master_dev, 992 struct component_match **matchptr) 993 { 994 struct device_node *np = master_dev->of_node; 995 struct device_node *ep_node; 996 997 for_each_endpoint_of_node(np, ep_node) { 998 struct device_node *intf; 999 struct of_endpoint ep; 1000 int ret; 1001 1002 ret = of_graph_parse_endpoint(ep_node, &ep); 1003 if (ret) { 1004 DRM_DEV_ERROR(master_dev, "unable to parse port endpoint\n"); 1005 of_node_put(ep_node); 1006 return ret; 1007 } 1008 1009 /* 1010 * The LCDC/LVDS port on MDP4 is a speacial case where the 1011 * remote-endpoint isn't a component that we need to add 1012 */ 1013 if (of_device_is_compatible(np, "qcom,mdp4") && 1014 ep.port == 0) 1015 continue; 1016 1017 /* 1018 * It's okay if some of the ports don't have a remote endpoint 1019 * specified. It just means that the port isn't connected to 1020 * any external interface. 1021 */ 1022 intf = of_graph_get_remote_port_parent(ep_node); 1023 if (!intf) 1024 continue; 1025 1026 if (of_device_is_available(intf)) 1027 drm_of_component_match_add(master_dev, matchptr, 1028 component_compare_of, intf); 1029 1030 of_node_put(intf); 1031 } 1032 1033 return 0; 1034 } 1035 1036 #if !IS_REACHABLE(CONFIG_DRM_MSM_MDP5) || !IS_REACHABLE(CONFIG_DRM_MSM_DPU) 1037 bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver) 1038 { 1039 /* If just a single driver is enabled, use it no matter what */ 1040 return true; 1041 } 1042 #else 1043 1044 static bool prefer_mdp5 = true; 1045 MODULE_PARM_DESC(prefer_mdp5, "Select whether MDP5 or DPU driver should be preferred"); 1046 module_param(prefer_mdp5, bool, 0444); 1047 1048 /* list all platforms that have been migrated from mdp5 to dpu driver */ 1049 static const char *const msm_mdp5_dpu_migrated[] = { 1050 /* there never was qcom,msm8998-mdp5 */ 1051 "qcom,sdm630-mdp5", 1052 "qcom,sdm660-mdp5", 1053 NULL 1054 }; 1055 1056 /* list all platforms supported by both mdp5 and dpu drivers */ 1057 static const char *const msm_mdp5_dpu_migration[] = { 1058 "qcom,msm8917-mdp5", 1059 "qcom,msm8937-mdp5", 1060 "qcom,msm8953-mdp5", 1061 "qcom,msm8996-mdp5", 1062 NULL, 1063 }; 1064 1065 bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver) 1066 { 1067 /* If it is not an MDP5 device, use DPU */ 1068 if (!of_device_is_compatible(dev->of_node, "qcom,mdp5")) 1069 return dpu_driver; 1070 1071 /* If it is no longer supported by MDP5, use DPU */ 1072 if (of_device_compatible_match(dev->of_node, msm_mdp5_dpu_migrated)) 1073 return dpu_driver; 1074 1075 /* If it is not in the migration list, use MDP5 */ 1076 if (!of_device_compatible_match(dev->of_node, msm_mdp5_dpu_migration)) 1077 return !dpu_driver; 1078 1079 return prefer_mdp5 ? !dpu_driver : dpu_driver; 1080 } 1081 #endif 1082 1083 /* 1084 * We don't know what's the best binding to link the gpu with the drm device. 1085 * Fow now, we just hunt for all the possible gpus that we support, and add them 1086 * as components. 1087 */ 1088 static const struct of_device_id msm_gpu_match[] = { 1089 { .compatible = "qcom,adreno" }, 1090 { .compatible = "qcom,adreno-3xx" }, 1091 { .compatible = "amd,imageon" }, 1092 { .compatible = "qcom,kgsl-3d0" }, 1093 { }, 1094 }; 1095 1096 static int add_gpu_components(struct device *dev, 1097 struct component_match **matchptr) 1098 { 1099 struct device_node *np; 1100 1101 np = of_find_matching_node(NULL, msm_gpu_match); 1102 if (!np) 1103 return 0; 1104 1105 if (msm_gpu_node_present(np)) 1106 drm_of_component_match_add(dev, matchptr, component_compare_of, np); 1107 1108 of_node_put(np); 1109 1110 return 0; 1111 } 1112 1113 static int msm_drm_bind(struct device *dev) 1114 { 1115 return msm_drm_init(dev, 1116 msm_separate_gpu_kms_components() ? 1117 &msm_kms_driver : 1118 &msm_driver, 1119 NULL); 1120 } 1121 1122 static void msm_drm_unbind(struct device *dev) 1123 { 1124 msm_drm_uninit(dev, NULL); 1125 } 1126 1127 const struct component_master_ops msm_drm_ops = { 1128 .bind = msm_drm_bind, 1129 .unbind = msm_drm_unbind, 1130 }; 1131 1132 int msm_drv_probe(struct device *master_dev, 1133 int (*kms_init)(struct drm_device *dev), 1134 struct msm_kms *kms) 1135 { 1136 struct msm_drm_private *priv; 1137 struct component_match *match = NULL; 1138 int ret; 1139 1140 priv = devm_kzalloc(master_dev, sizeof(*priv), GFP_KERNEL); 1141 if (!priv) 1142 return -ENOMEM; 1143 1144 priv->kms = kms; 1145 priv->kms_init = kms_init; 1146 dev_set_drvdata(master_dev, priv); 1147 1148 /* Add mdp components if we have KMS. */ 1149 if (kms_init) { 1150 ret = add_mdp_components(master_dev, &match); 1151 if (ret) 1152 return ret; 1153 } 1154 1155 if (!msm_separate_gpu_kms_components()) { 1156 ret = add_gpu_components(master_dev, &match); 1157 if (ret) 1158 return ret; 1159 } 1160 1161 /* on all devices that I am aware of, iommu's which can map 1162 * any address the cpu can see are used: 1163 */ 1164 ret = dma_set_mask_and_coherent(master_dev, ~0); 1165 if (ret) 1166 return ret; 1167 1168 ret = component_master_add_with_match(master_dev, &msm_drm_ops, match); 1169 if (ret) 1170 return ret; 1171 1172 return 0; 1173 } 1174 1175 int msm_gpu_probe(struct platform_device *pdev, 1176 const struct component_ops *ops) 1177 { 1178 struct msm_drm_private *priv; 1179 int ret; 1180 1181 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1182 if (!priv) 1183 return -ENOMEM; 1184 1185 platform_set_drvdata(pdev, priv); 1186 1187 /* on all devices that I am aware of, iommu's which can map 1188 * any address the cpu can see are used: 1189 */ 1190 ret = dma_set_mask_and_coherent(&pdev->dev, ~0); 1191 if (ret) 1192 return ret; 1193 1194 return msm_drm_init(&pdev->dev, &msm_gpu_driver, ops); 1195 } 1196 1197 void msm_gpu_remove(struct platform_device *pdev, 1198 const struct component_ops *ops) 1199 { 1200 msm_drm_uninit(&pdev->dev, ops); 1201 } 1202 1203 static int __init msm_drm_register(void) 1204 { 1205 if (!modeset) 1206 return -EINVAL; 1207 1208 DBG("init"); 1209 msm_mdp_register(); 1210 msm_dpu_register(); 1211 msm_dsi_register(); 1212 msm_hdmi_register(); 1213 msm_dp_register(); 1214 adreno_register(); 1215 msm_mdp4_register(); 1216 msm_mdss_register(); 1217 1218 return 0; 1219 } 1220 1221 static void __exit msm_drm_unregister(void) 1222 { 1223 DBG("fini"); 1224 msm_mdss_unregister(); 1225 msm_mdp4_unregister(); 1226 msm_dp_unregister(); 1227 msm_hdmi_unregister(); 1228 adreno_unregister(); 1229 msm_dsi_unregister(); 1230 msm_mdp_unregister(); 1231 msm_dpu_unregister(); 1232 } 1233 1234 module_init(msm_drm_register); 1235 module_exit(msm_drm_unregister); 1236 1237 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); 1238 MODULE_DESCRIPTION("MSM DRM Driver"); 1239 MODULE_LICENSE("GPL"); 1240