1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2017-2026 Morse Micro 4 */ 5 6 #ifndef _MM81X_HW_H_ 7 #define _MM81X_HW_H_ 8 9 #include <linux/gpio/consumer.h> 10 #include "core.h" 11 #include "command_defs.h" 12 13 /* This should be at a fixed location for a family of chipset */ 14 #define MM8108_REG_CHIP_ID 0x00002d20 15 16 #define MM81X_SDIO_RW_ADDR_BOUNDARY_MASK ((u32)0xFFFF0000) 17 18 #define MM81X_CONFIG_ACCESS_1BYTE 0 19 #define MM81X_CONFIG_ACCESS_2BYTE 1 20 #define MM81X_CONFIG_ACCESS_4BYTE 2 21 22 #define MM81X_REG_TRGR_BASE(mors) ((mors)->regs->trgr_base_address) 23 #define MM81X_REG_TRGR1_STS(mors) (MM81X_REG_TRGR_BASE(mors) + 0x00) 24 #define MM81X_REG_TRGR1_SET(mors) (MM81X_REG_TRGR_BASE(mors) + 0x04) 25 #define MM81X_REG_TRGR1_CLR(mors) (MM81X_REG_TRGR_BASE(mors) + 0x08) 26 #define MM81X_REG_TRGR1_EN(mors) (MM81X_REG_TRGR_BASE(mors) + 0x0C) 27 #define MM81X_REG_TRGR2_STS(mors) (MM81X_REG_TRGR_BASE(mors) + 0x10) 28 #define MM81X_REG_TRGR2_SET(mors) (MM81X_REG_TRGR_BASE(mors) + 0x14) 29 #define MM81X_REG_TRGR2_CLR(mors) (MM81X_REG_TRGR_BASE(mors) + 0x18) 30 #define MM81X_REG_TRGR2_EN(mors) (MM81X_REG_TRGR_BASE(mors) + 0x1C) 31 32 #define MM81X_REG_INT_BASE(mors) ((mors)->regs->irq_base_address) 33 #define MM81X_REG_INT1_STS(mors) (MM81X_REG_INT_BASE(mors) + 0x00) 34 #define MM81X_REG_INT1_SET(mors) (MM81X_REG_INT_BASE(mors) + 0x04) 35 #define MM81X_REG_INT1_CLR(mors) (MM81X_REG_INT_BASE(mors) + 0x08) 36 #define MM81X_REG_INT1_EN(mors) (MM81X_REG_INT_BASE(mors) + 0x0C) 37 #define MM81X_REG_INT2_STS(mors) (MM81X_REG_INT_BASE(mors) + 0x10) 38 #define MM81X_REG_INT2_SET(mors) (MM81X_REG_INT_BASE(mors) + 0x14) 39 #define MM81X_REG_INT2_CLR(mors) (MM81X_REG_INT_BASE(mors) + 0x18) 40 #define MM81X_REG_INT2_EN(mors) (MM81X_REG_INT_BASE(mors) + 0x1C) 41 42 #define MM81X_REG_CHIP_ID(mors) ((mors)->regs->chip_id_address) 43 44 #define MM81X_REG_MSI(mors) ((mors)->regs->msi_address) 45 #define MM81X_REG_MSI_HOST_INT(mors) ((mors)->regs->msi_value) 46 47 #define MM81X_REG_HOST_MAGIC_VALUE(mors) ((mors)->regs->magic_num_value) 48 49 #define MM81X_REG_RESET(mors) ((mors)->regs->cpu_reset_address) 50 #define MM81X_REG_RESET_VALUE(mors) ((mors)->regs->cpu_reset_value) 51 52 #define MM81X_REG_HOST_MANIFEST_PTR(mors) ((mors)->regs->manifest_ptr_address) 53 54 #define MM81X_REG_EARLY_CLK_CTRL_VALUE(mors) \ 55 ((mors)->regs->early_clk_ctrl_value) 56 57 #define MM81X_REG_CLK_CTRL(mors) ((mors)->regs->clk_ctrl_address) 58 #define MM81X_REG_CLK_CTRL_VALUE(mors) ((mors)->regs->clk_ctrl_value) 59 60 #define MM81X_REG_BOOT_ADDR(mors) ((mors)->regs->boot_address) 61 #define MM81X_REG_BOOT_ADDR_VALUE(mors) ((mors)->regs->boot_value) 62 63 #define MM81X_REG_AON_ADDR(mors) ((mors)->regs->aon) 64 #define MM81X_REG_AON_COUNT(mors) ((mors)->regs->aon_count) 65 #define MM81X_REG_AON_LATCH_ADDR(mors) ((mors)->regs->aon_latch) 66 #define MM81X_REG_AON_LATCH_MASK(mors) ((mors)->regs->aon_latch_mask) 67 #define MM81X_REG_AON_USB_RESET(mors) ((mors)->regs->aon_reset_usb_value) 68 69 /* Bit 17 to 24 reserved for the beacon VIF 0 to 7 interrupts */ 70 #define MM81X_INT_BEACON_VIF_MASK_ALL (GENMASK(24, 17)) 71 #define MM81X_INT_BEACON_BASE_NUM (17) 72 73 /* PV0 NDP probe interrupts (VIF 0 and 1). */ 74 #define MM81X_INT_NDP_PROBE_REQ_PV0_VIF_MASK_ALL (GENMASK(26, 25)) 75 #define MM81X_INT_NDP_PROBE_REQ_PV0_BASE_NUM (25) 76 77 /* Bit 27 Chip to Host stop notify */ 78 #define MM81X_INT_HW_STOP_NOTIFICATION_NUM (27) 79 #define MM81X_INT_HW_STOP_NOTIFICATION BIT(MM81X_INT_HW_STOP_NOTIFICATION_NUM) 80 81 /* Chip IDs */ 82 #define CHIP_ID_MM8108 0x809 83 84 /* 85 * Minimum time we must wait between attempting to reload the HW after a 86 * stop notification 87 */ 88 #define HW_RELOAD_AFTER_STOP_WINDOW 5 89 90 enum host_table_firmware_flags { 91 MM81X_FW_FLAGS_SUPPORT_S1G = BIT(0), 92 MM81X_FW_FLAGS_BUSY_ACTIVE_LOW = BIT(1), 93 MM81X_FW_FLAGS_REPORTS_TX_BEACON_COMPLETION = BIT(2), 94 MM81X_FW_FLAGS_SUPPORT_HW_SCAN = BIT(3), 95 MM81X_FW_FLAGS_SUPPORT_CHIP_HALT_IRQ = BIT(4), 96 }; 97 98 struct host_table { 99 __le32 magic_number; 100 __le32 fw_version_number; 101 __le32 host_flags; 102 __le32 fw_flags; 103 __le32 memcmd_cmd_addr; 104 __le32 memcmd_resp_addr; 105 __le32 ext_host_tbl_addr; 106 } __packed; 107 108 struct mm81x_regs { 109 u32 chip_id_address; 110 u32 irq_base_address; 111 u32 trgr_base_address; 112 u32 cpu_reset_address; 113 u32 cpu_reset_value; 114 u32 msi_address; 115 u32 msi_value; 116 u32 manifest_ptr_address; 117 u32 magic_num_value; 118 u32 clk_ctrl_address; 119 u32 clk_ctrl_value; 120 u32 early_clk_ctrl_value; 121 u32 boot_address; 122 u32 boot_value; 123 u32 pager_base_address; 124 u32 aon_latch; 125 u32 aon_latch_mask; 126 u32 aon_reset_usb_value; 127 u32 aon; 128 u8 aon_count; 129 }; 130 131 int mm81x_hw_otp_get_board_type(struct mm81x *mors); 132 bool mm81x_hw_otp_valid_board_type(u32 board_type); 133 int mm81x_hw_otp_get_mac_addr(struct mm81x *mors); 134 135 void mm81x_hw_irq_enable(struct mm81x *mors, u32 irq, bool enable); 136 int mm81x_hw_irq_handle(struct mm81x *mors); 137 void mm81x_hw_irq_clear(struct mm81x *mors); 138 void mm81x_hw_toggle_aon_latch(struct mm81x *mors); 139 void mm81x_hw_enable_burst_mode(struct mm81x *mors, const u8 burst_mode); 140 int mm81x_hw_digital_reset(struct mm81x *mors); 141 void mm81x_hw_pre_firmware_ndr_hook(struct mm81x *mors); 142 void mm81x_hw_post_firmware_ndr_hook(struct mm81x *mors); 143 144 enum sdio_burst_mode { 145 SDIO_WORD_BURST_DISABLE = 146 0, /* Intentionally duplicate to make it clear it's disabled */ 147 SDIO_WORD_BURST_SIZE_0 = 0, /* 000: no bursting (single 32bit word) */ 148 SDIO_WORD_BURST_SIZE_2 = 1, /* 001: bursts of 2 words */ 149 SDIO_WORD_BURST_SIZE_4 = 2, /* 010: bursts of 4 words */ 150 SDIO_WORD_BURST_SIZE_8 = 3, /* 011: bursts of 8 words */ 151 SDIO_WORD_BURST_SIZE_16 = 4, /* 100: bursts of 16 words */ 152 SDIO_WORD_BURST_MASK = 7, 153 }; 154 155 extern const struct mm81x_regs mm8108_regs; 156 157 void mm81x_hw_enable_stop_notifications(struct mm81x *mors, bool enable); 158 159 #endif /* !_MM81X_HW_H_ */ 160