1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 /* FILE POLICY AND INTENDED USAGE:
27 * This file manages link detection states and receiver states by using various
28 * link protocols. It also provides helper functions to interpret certain
29 * capabilities or status based on the states it manages or retrieve them
30 * directly from connected receivers.
31 */
32
33 #include "link_dpms.h"
34 #include "link_detection.h"
35 #include "link_hwss.h"
36 #include "protocols/link_edp_panel_control.h"
37 #include "protocols/link_ddc.h"
38 #include "protocols/link_hpd.h"
39 #include "protocols/link_dpcd.h"
40 #include "protocols/link_dp_capability.h"
41 #include "protocols/link_dp_dpia.h"
42 #include "protocols/link_dp_phy.h"
43 #include "protocols/link_dp_training.h"
44 #include "protocols/link_dp_dpia_bw.h"
45 #include "accessories/link_dp_trace.h"
46
47 #include "link_enc_cfg.h"
48 #include "dm_helpers.h"
49 #include "clk_mgr.h"
50
51 // Offset DPCD 050Eh == 0x5A
52 #define MST_HUB_ID_0x5A 0x5A
53
54 #define DC_LOGGER \
55 link->ctx->logger
56 #define DC_LOGGER_INIT(logger)
57
58 #define LINK_INFO(...) \
59 DC_LOG_HW_HOTPLUG( \
60 __VA_ARGS__)
61 /*
62 * Some receivers fail to train on first try and are good
63 * on subsequent tries. 2 retries should be plenty. If we
64 * don't have a successful training then we don't expect to
65 * ever get one.
66 */
67 #define LINK_TRAINING_MAX_VERIFY_RETRY 2
68
69 static const u8 DP_SINK_BRANCH_DEV_NAME_7580[] = "7580\x80u";
70
71 static const u8 dp_hdmi_dongle_signature_str[] = "DP-HDMI ADAPTOR";
72
get_ddc_transaction_type(enum signal_type sink_signal)73 static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal)
74 {
75 enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
76
77 switch (sink_signal) {
78 case SIGNAL_TYPE_DVI_SINGLE_LINK:
79 case SIGNAL_TYPE_DVI_DUAL_LINK:
80 case SIGNAL_TYPE_HDMI_TYPE_A:
81 case SIGNAL_TYPE_LVDS:
82 case SIGNAL_TYPE_RGB:
83 transaction_type = DDC_TRANSACTION_TYPE_I2C;
84 break;
85
86 case SIGNAL_TYPE_DISPLAY_PORT:
87 case SIGNAL_TYPE_EDP:
88 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
89 break;
90
91 case SIGNAL_TYPE_DISPLAY_PORT_MST:
92 /* MST does not use I2COverAux, but there is the
93 * SPECIAL use case for "immediate dwnstrm device
94 * access" (EPR#370830).
95 */
96 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
97 break;
98
99 default:
100 break;
101 }
102
103 return transaction_type;
104 }
105
get_basic_signal_type(struct graphics_object_id encoder,struct graphics_object_id downstream)106 static enum signal_type get_basic_signal_type(struct graphics_object_id encoder,
107 struct graphics_object_id downstream)
108 {
109 if (downstream.type == OBJECT_TYPE_CONNECTOR) {
110 switch (downstream.id) {
111 case CONNECTOR_ID_SINGLE_LINK_DVII:
112 switch (encoder.id) {
113 case ENCODER_ID_INTERNAL_DAC1:
114 case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
115 case ENCODER_ID_INTERNAL_DAC2:
116 case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
117 return SIGNAL_TYPE_RGB;
118 default:
119 return SIGNAL_TYPE_DVI_SINGLE_LINK;
120 }
121 break;
122 case CONNECTOR_ID_DUAL_LINK_DVII:
123 {
124 switch (encoder.id) {
125 case ENCODER_ID_INTERNAL_DAC1:
126 case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
127 case ENCODER_ID_INTERNAL_DAC2:
128 case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
129 return SIGNAL_TYPE_RGB;
130 default:
131 return SIGNAL_TYPE_DVI_DUAL_LINK;
132 }
133 }
134 break;
135 case CONNECTOR_ID_SINGLE_LINK_DVID:
136 return SIGNAL_TYPE_DVI_SINGLE_LINK;
137 case CONNECTOR_ID_DUAL_LINK_DVID:
138 return SIGNAL_TYPE_DVI_DUAL_LINK;
139 case CONNECTOR_ID_VGA:
140 return SIGNAL_TYPE_RGB;
141 case CONNECTOR_ID_HDMI_TYPE_A:
142 return SIGNAL_TYPE_HDMI_TYPE_A;
143 case CONNECTOR_ID_LVDS:
144 return SIGNAL_TYPE_LVDS;
145 case CONNECTOR_ID_DISPLAY_PORT:
146 case CONNECTOR_ID_USBC:
147 return SIGNAL_TYPE_DISPLAY_PORT;
148 case CONNECTOR_ID_EDP:
149 return SIGNAL_TYPE_EDP;
150 default:
151 return SIGNAL_TYPE_NONE;
152 }
153 }
154
155 return SIGNAL_TYPE_NONE;
156 }
157
158 /*
159 * @brief
160 * Detect output sink type
161 */
link_detect_sink_signal_type(struct dc_link * link,enum dc_detect_reason reason)162 static enum signal_type link_detect_sink_signal_type(struct dc_link *link,
163 enum dc_detect_reason reason)
164 {
165 enum signal_type result;
166 struct audio_support *aud_support;
167 struct graphics_object_id enc_id;
168
169 /* External DP bridges should use DP signal regardless of connector type. */
170 if (link->ext_enc_id.id)
171 return SIGNAL_TYPE_DISPLAY_PORT;
172
173 if (link->is_dig_mapping_flexible)
174 enc_id = (struct graphics_object_id){.id = ENCODER_ID_UNKNOWN};
175 else
176 enc_id = link->link_enc->id;
177 result = get_basic_signal_type(enc_id, link->link_id);
178
179 /* Use basic signal type for link without physical connector. */
180 if (link->ep_type != DISPLAY_ENDPOINT_PHY)
181 return result;
182
183 /*
184 * Internal digital encoder will detect only dongles
185 * that require digital signal
186 */
187
188 /*
189 * Detection mechanism is different
190 * for different native connectors.
191 * LVDS connector supports only LVDS signal;
192 * PCIE is a bus slot, the actual connector needs to be detected first;
193 * eDP connector supports only eDP signal;
194 * HDMI should check straps for audio
195 */
196 switch (link->link_id.id) {
197 case CONNECTOR_ID_HDMI_TYPE_A:
198 /*
199 * check audio support:
200 * if native HDMI is not supported, switch to DVI
201 */
202 aud_support = &link->dc->res_pool->audio_support;
203
204 if (!aud_support->hdmi_audio_native)
205 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
206 break;
207 case CONNECTOR_ID_DISPLAY_PORT:
208 case CONNECTOR_ID_USBC:
209 /*
210 * DP HPD short pulse. Passive DP dongle will not
211 * have short pulse
212 */
213 if (reason != DETECT_REASON_HPDRX) {
214 /*
215 * Check whether DP signal detected: if not -
216 * we assume signal is DVI; it could be corrected
217 * to HDMI after dongle detection
218 */
219 if (!dm_helpers_is_dp_sink_present(link))
220 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
221 }
222 break;
223 case CONNECTOR_ID_PCIE:
224 /* ZAZTODO implement PCIE add-on card detection */
225 break;
226 default:
227 break;
228 }
229
230 return result;
231 }
232
decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,struct audio_support * audio_support)233 static enum signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,
234 struct audio_support *audio_support)
235 {
236 enum signal_type signal = SIGNAL_TYPE_NONE;
237
238 switch (dongle_type) {
239 case DISPLAY_DONGLE_DP_HDMI_DONGLE:
240 if (audio_support->hdmi_audio_on_dongle)
241 signal = SIGNAL_TYPE_HDMI_TYPE_A;
242 else
243 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
244 break;
245 case DISPLAY_DONGLE_DP_DVI_DONGLE:
246 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
247 break;
248 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
249 if (audio_support->hdmi_audio_native)
250 signal = SIGNAL_TYPE_HDMI_TYPE_A;
251 else
252 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
253 break;
254 default:
255 signal = SIGNAL_TYPE_NONE;
256 break;
257 }
258
259 return signal;
260 }
261
read_scdc_caps(struct ddc_service * ddc_service,struct dc_sink * sink)262 static void read_scdc_caps(struct ddc_service *ddc_service,
263 struct dc_sink *sink)
264 {
265 uint8_t slave_address = HDMI_SCDC_ADDRESS;
266 uint8_t offset = HDMI_SCDC_MANUFACTURER_OUI;
267
268 if (ddc_service->link->local_sink &&
269 !ddc_service->link->local_sink->edid_caps.scdc_present)
270 return;
271
272 link_query_ddc_data(ddc_service, slave_address, &offset,
273 sizeof(offset), sink->scdc_caps.manufacturer_OUI.byte,
274 sizeof(sink->scdc_caps.manufacturer_OUI.byte));
275
276 offset = HDMI_SCDC_DEVICE_ID;
277
278 link_query_ddc_data(ddc_service, slave_address, &offset,
279 sizeof(offset), &(sink->scdc_caps.device_id.byte),
280 sizeof(sink->scdc_caps.device_id.byte));
281 }
282
i2c_read(struct ddc_service * ddc,uint32_t address,uint8_t * buffer,uint32_t len)283 static bool i2c_read(
284 struct ddc_service *ddc,
285 uint32_t address,
286 uint8_t *buffer,
287 uint32_t len)
288 {
289 uint8_t offs_data = 0;
290 struct i2c_payload payloads[2] = {
291 {
292 .write = true,
293 .address = address,
294 .length = 1,
295 .data = &offs_data },
296 {
297 .write = false,
298 .address = address,
299 .length = len,
300 .data = buffer } };
301
302 struct i2c_command command = {
303 .payloads = payloads,
304 .number_of_payloads = 2,
305 .engine = DDC_I2C_COMMAND_ENGINE,
306 .speed = ddc->ctx->dc->caps.i2c_speed_in_khz };
307
308 return dm_helpers_submit_i2c(
309 ddc->ctx,
310 ddc->link,
311 &command);
312 }
313
314 enum {
315 DP_SINK_CAP_SIZE =
316 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV + 1
317 };
318
query_dp_dual_mode_adaptor(struct ddc_service * ddc,struct display_sink_capability * sink_cap)319 static void query_dp_dual_mode_adaptor(
320 struct ddc_service *ddc,
321 struct display_sink_capability *sink_cap)
322 {
323 uint8_t i;
324 bool is_valid_hdmi_signature;
325 enum display_dongle_type *dongle = &sink_cap->dongle_type;
326 uint8_t type2_dongle_buf[DP_ADAPTOR_TYPE2_SIZE];
327 bool is_type2_dongle = false;
328 int retry_count = 2;
329 struct dp_hdmi_dongle_signature_data *dongle_signature;
330 struct dc_link *link = ddc->link;
331
332 /* Assume we have no valid DP passive dongle connected */
333 *dongle = DISPLAY_DONGLE_NONE;
334 sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK;
335
336 /* Read DP-HDMI dongle I2c (no response interpreted as DP-DVI dongle)*/
337 if (!i2c_read(
338 ddc,
339 DP_HDMI_DONGLE_ADDRESS,
340 type2_dongle_buf,
341 sizeof(type2_dongle_buf))) {
342 /* Passive HDMI dongles can sometimes fail here without retrying*/
343 while (retry_count > 0) {
344 if (i2c_read(ddc,
345 DP_HDMI_DONGLE_ADDRESS,
346 type2_dongle_buf,
347 sizeof(type2_dongle_buf)))
348 break;
349 retry_count--;
350 }
351 if (retry_count == 0) {
352 *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
353 sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK;
354
355 CONN_DATA_DETECT(link, type2_dongle_buf, sizeof(type2_dongle_buf),
356 "DP-DVI passive dongle %dMhz: ",
357 DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000);
358 return;
359 }
360 }
361
362 /* Check if Type 2 dongle.*/
363 if (type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_ID] == DP_ADAPTOR_TYPE2_ID)
364 is_type2_dongle = true;
365
366 dongle_signature =
367 (struct dp_hdmi_dongle_signature_data *)type2_dongle_buf;
368
369 is_valid_hdmi_signature = true;
370
371 /* Check EOT */
372 if (dongle_signature->eot != DP_HDMI_DONGLE_SIGNATURE_EOT) {
373 is_valid_hdmi_signature = false;
374 }
375
376 /* Check signature */
377 for (i = 0; i < sizeof(dongle_signature->id); ++i) {
378 /* If its not the right signature,
379 * skip mismatch in subversion byte.*/
380 if (dongle_signature->id[i] !=
381 dp_hdmi_dongle_signature_str[i] && i != 3) {
382
383 if (is_type2_dongle) {
384 is_valid_hdmi_signature = false;
385 break;
386 }
387
388 }
389 }
390 if (is_valid_hdmi_signature)
391 sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK;
392
393 if (is_type2_dongle) {
394 uint32_t max_tmds_clk =
395 type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_MAX_TMDS_CLK];
396
397 max_tmds_clk = max_tmds_clk * 2 + max_tmds_clk / 2;
398
399 if (0 == max_tmds_clk ||
400 max_tmds_clk < DP_ADAPTOR_TYPE2_MIN_TMDS_CLK ||
401 max_tmds_clk > DP_ADAPTOR_TYPE2_MAX_TMDS_CLK) {
402 *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
403
404 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
405 sizeof(type2_dongle_buf),
406 "DP-DVI passive dongle %dMhz: ",
407 DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000);
408 } else {
409 if (is_valid_hdmi_signature == true) {
410 *dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE;
411
412 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
413 sizeof(type2_dongle_buf),
414 "Type 2 DP-HDMI passive dongle %dMhz: ",
415 max_tmds_clk);
416 } else {
417 *dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE;
418
419 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
420 sizeof(type2_dongle_buf),
421 "Type 2 DP-HDMI passive dongle (no signature) %dMhz: ",
422 max_tmds_clk);
423
424 }
425
426 /* Multiply by 1000 to convert to kHz. */
427 sink_cap->max_hdmi_pixel_clock =
428 max_tmds_clk * 1000;
429 }
430 sink_cap->is_dongle_type_one = false;
431
432 } else {
433 if (is_valid_hdmi_signature == true) {
434 *dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE;
435
436 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
437 sizeof(type2_dongle_buf),
438 "Type 1 DP-HDMI passive dongle %dMhz: ",
439 sink_cap->max_hdmi_pixel_clock / 1000);
440 } else {
441 *dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE;
442
443 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
444 sizeof(type2_dongle_buf),
445 "Type 1 DP-HDMI passive dongle (no signature) %dMhz: ",
446 sink_cap->max_hdmi_pixel_clock / 1000);
447 }
448 sink_cap->is_dongle_type_one = true;
449 }
450
451 return;
452 }
453
dp_passive_dongle_detection(struct ddc_service * ddc,struct display_sink_capability * sink_cap,struct audio_support * audio_support)454 static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc,
455 struct display_sink_capability *sink_cap,
456 struct audio_support *audio_support)
457 {
458 query_dp_dual_mode_adaptor(ddc, sink_cap);
459
460 return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type,
461 audio_support);
462 }
463
link_disconnect_sink(struct dc_link * link)464 static void link_disconnect_sink(struct dc_link *link)
465 {
466 if (link->local_sink) {
467 dc_sink_release(link->local_sink);
468 link->local_sink = NULL;
469 }
470
471 link->dpcd_sink_count = 0;
472 //link->dpcd_caps.dpcd_rev.raw = 0;
473 }
474
link_disconnect_remap(struct dc_sink * prev_sink,struct dc_link * link)475 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
476 {
477 dc_sink_release(link->local_sink);
478 link->local_sink = prev_sink;
479 }
480
query_hdcp_capability(enum signal_type signal,struct dc_link * link)481 static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)
482 {
483 struct hdcp_protection_message msg22;
484 struct hdcp_protection_message msg14;
485
486 memset(&msg22, 0, sizeof(struct hdcp_protection_message));
487 memset(&msg14, 0, sizeof(struct hdcp_protection_message));
488 memset(link->hdcp_caps.rx_caps.raw, 0,
489 sizeof(link->hdcp_caps.rx_caps.raw));
490
491 if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
492 link->ddc->transaction_type ==
493 DDC_TRANSACTION_TYPE_I2C_OVER_AUX) ||
494 link->connector_signal == SIGNAL_TYPE_EDP) {
495 msg22.data = link->hdcp_caps.rx_caps.raw;
496 msg22.length = sizeof(link->hdcp_caps.rx_caps.raw);
497 msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS;
498 } else {
499 msg22.data = &link->hdcp_caps.rx_caps.fields.version;
500 msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version);
501 msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION;
502 }
503 msg22.version = HDCP_VERSION_22;
504 msg22.link = HDCP_LINK_PRIMARY;
505 msg22.max_retries = 5;
506 dc_process_hdcp_msg(signal, link, &msg22);
507
508 if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
509 msg14.data = &link->hdcp_caps.bcaps.raw;
510 msg14.length = sizeof(link->hdcp_caps.bcaps.raw);
511 msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS;
512 msg14.version = HDCP_VERSION_14;
513 msg14.link = HDCP_LINK_PRIMARY;
514 msg14.max_retries = 5;
515
516 dc_process_hdcp_msg(signal, link, &msg14);
517 }
518
519 }
read_current_link_settings_on_detect(struct dc_link * link)520 static void read_current_link_settings_on_detect(struct dc_link *link)
521 {
522 union lane_count_set lane_count_set = {0};
523 uint8_t link_bw_set = 0;
524 uint8_t link_rate_set = 0;
525 uint32_t read_dpcd_retry_cnt = 10;
526 enum dc_status status = DC_ERROR_UNEXPECTED;
527 int i;
528 union max_down_spread max_down_spread = {0};
529
530 // Read DPCD 00101h to find out the number of lanes currently set
531 for (i = 0; i < read_dpcd_retry_cnt; i++) {
532 status = core_link_read_dpcd(link,
533 DP_LANE_COUNT_SET,
534 &lane_count_set.raw,
535 sizeof(lane_count_set));
536 /* First DPCD read after VDD ON can fail if the particular board
537 * does not have HPD pin wired correctly. So if DPCD read fails,
538 * which it should never happen, retry a few times. Target worst
539 * case scenario of 80 ms.
540 */
541 if (status == DC_OK) {
542 link->cur_link_settings.lane_count =
543 lane_count_set.bits.LANE_COUNT_SET;
544 break;
545 }
546
547 msleep(8);
548 }
549
550 // Read DPCD 00100h to find if standard link rates are set
551 core_link_read_dpcd(link, DP_LINK_BW_SET,
552 &link_bw_set, sizeof(link_bw_set));
553
554 if (link_bw_set == 0) {
555 if (link->connector_signal == SIGNAL_TYPE_EDP) {
556 /* If standard link rates are not being used,
557 * Read DPCD 00115h to find the edp link rate set used
558 */
559 core_link_read_dpcd(link, DP_LINK_RATE_SET,
560 &link_rate_set, sizeof(link_rate_set));
561
562 // edp_supported_link_rates_count = 0 for DP
563 if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
564 link->cur_link_settings.link_rate =
565 link->dpcd_caps.edp_supported_link_rates[link_rate_set];
566 link->cur_link_settings.link_rate_set = link_rate_set;
567 link->cur_link_settings.use_link_rate_set = true;
568 }
569 } else {
570 // Link Rate not found. Seamless boot may not work.
571 ASSERT(false);
572 }
573 } else {
574 link->cur_link_settings.link_rate = link_bw_set;
575 link->cur_link_settings.use_link_rate_set = false;
576 }
577 // Read DPCD 00003h to find the max down spread.
578 core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
579 &max_down_spread.raw, sizeof(max_down_spread));
580 link->cur_link_settings.link_spread =
581 max_down_spread.bits.MAX_DOWN_SPREAD ?
582 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
583 }
584
detect_dp(struct dc_link * link,struct display_sink_capability * sink_caps,enum dc_detect_reason reason)585 static bool detect_dp(struct dc_link *link,
586 struct display_sink_capability *sink_caps,
587 enum dc_detect_reason reason)
588 {
589 struct audio_support *audio_support = &link->dc->res_pool->audio_support;
590
591 sink_caps->signal = link_detect_sink_signal_type(link, reason);
592 sink_caps->transaction_type =
593 get_ddc_transaction_type(sink_caps->signal);
594
595 if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
596 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
597 if (!detect_dp_sink_caps(link)) {
598 return false;
599 }
600
601 if (is_dp_branch_device(link))
602 /* DP SST branch */
603 link->type = dc_connection_sst_branch;
604 } else {
605 if (link->dc->debug.disable_dp_plus_plus_wa &&
606 link->link_enc->features.flags.bits.IS_UHBR20_CAPABLE)
607 return false;
608
609 /* DP passive dongles */
610 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
611 sink_caps,
612 audio_support);
613 link->dpcd_caps.dongle_type = sink_caps->dongle_type;
614 link->dpcd_caps.is_dongle_type_one = sink_caps->is_dongle_type_one;
615 link->dpcd_caps.dpcd_rev.raw = 0;
616 link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.raw = 0;
617 }
618
619 if (link->ext_enc_id.id) {
620 /* Fix number of connected sinks reported by external DP bridge */
621 link->dpcd_caps.sink_count.bits.SINK_COUNT = 1;
622 /* NUTMEG requires that we use HBR, doesn't work with RBR. */
623 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_00001A)
624 link->preferred_link_setting.link_rate = LINK_RATE_HIGH;
625 }
626
627 return true;
628 }
629
is_same_edid(struct dc_edid * old_edid,struct dc_edid * new_edid)630 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
631 {
632 if (old_edid == NULL || new_edid == NULL)
633 return false;
634
635 if (old_edid->length != new_edid->length)
636 return false;
637
638 if (new_edid->length == 0)
639 return false;
640
641 return (memcmp(old_edid->raw_edid,
642 new_edid->raw_edid, new_edid->length) == 0);
643 }
644
wait_for_entering_dp_alt_mode(struct dc_link * link)645 static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
646 {
647
648 /**
649 * something is terribly wrong if time out is > 200ms. (5Hz)
650 * 500 microseconds * 400 tries us 200 ms
651 **/
652 unsigned int sleep_time_in_microseconds = 500;
653 unsigned int tries_allowed = 400;
654 bool is_in_alt_mode;
655 unsigned long long enter_timestamp;
656 unsigned long long finish_timestamp;
657 unsigned long long time_taken_in_ns;
658 int tries_taken;
659
660 /**
661 * this function will only exist if we are on dcn21 (is_in_alt_mode is a
662 * function pointer, so checking to see if it is equal to 0 is the same
663 * as checking to see if it is null
664 **/
665 if (!link->link_enc->funcs->is_in_alt_mode)
666 return true;
667
668 is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
669 DC_LOG_DC("DP Alt mode state on HPD: %d Link=%d\n", is_in_alt_mode, link->link_index);
670
671 if (is_in_alt_mode)
672 return true;
673
674 enter_timestamp = dm_get_timestamp(link->ctx);
675
676 for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
677 udelay(sleep_time_in_microseconds);
678 /* ask the link if alt mode is enabled, if so return ok */
679 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
680 finish_timestamp = dm_get_timestamp(link->ctx);
681 time_taken_in_ns =
682 dm_get_elapse_time_in_ns(link->ctx,
683 finish_timestamp,
684 enter_timestamp);
685 DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
686 div_u64(time_taken_in_ns, 1000000));
687 return true;
688 }
689 }
690 finish_timestamp = dm_get_timestamp(link->ctx);
691 time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
692 enter_timestamp);
693 DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
694 div_u64(time_taken_in_ns, 1000000));
695 return false;
696 }
697
apply_dpia_mst_dsc_always_on_wa(struct dc_link * link)698 static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link)
699 {
700 /* Apply work around for tunneled MST on certain USB4 docks. Always use DSC if dock
701 * reports DSC support.
702 */
703 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
704 link->type == dc_connection_mst_branch &&
705 link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
706 link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_20 &&
707 link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
708 !link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around)
709 link->wa_flags.dpia_mst_dsc_always_on = true;
710
711 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
712 link->type == dc_connection_mst_branch &&
713 link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
714 link->dpcd_caps.branch_vendor_specific_data[2] == MST_HUB_ID_0x5A &&
715 link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
716 !link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around) {
717 link->wa_flags.dpia_mst_dsc_always_on = true;
718 }
719 }
720
revert_dpia_mst_dsc_always_on_wa(struct dc_link * link)721 static void revert_dpia_mst_dsc_always_on_wa(struct dc_link *link)
722 {
723 /* Disable work around which keeps DSC on for tunneled MST on certain USB4 docks. */
724 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
725 link->wa_flags.dpia_mst_dsc_always_on = false;
726 }
727
discover_dp_mst_topology(struct dc_link * link,enum dc_detect_reason reason)728 static bool discover_dp_mst_topology(struct dc_link *link, enum dc_detect_reason reason)
729 {
730 LINK_INFO("link=%d, mst branch is now Connected\n",
731 link->link_index);
732
733 link->type = dc_connection_mst_branch;
734 apply_dpia_mst_dsc_always_on_wa(link);
735
736 dm_helpers_dp_update_branch_info(link->ctx, link);
737 if (dm_helpers_dp_mst_start_top_mgr(link->ctx,
738 link, (reason == DETECT_REASON_BOOT || reason == DETECT_REASON_RESUMEFROMS3S4))) {
739 link_disconnect_sink(link);
740 } else {
741 link->type = dc_connection_sst_branch;
742 }
743
744 return link->type == dc_connection_mst_branch;
745 }
746
link_reset_cur_dp_mst_topology(struct dc_link * link)747 bool link_reset_cur_dp_mst_topology(struct dc_link *link)
748 {
749 LINK_INFO("link=%d, mst branch is now Disconnected\n",
750 link->link_index);
751
752 revert_dpia_mst_dsc_always_on_wa(link);
753 return dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
754 }
755
should_prepare_phy_clocks_for_link_verification(const struct dc * dc,enum dc_detect_reason reason)756 static bool should_prepare_phy_clocks_for_link_verification(const struct dc *dc,
757 enum dc_detect_reason reason)
758 {
759 int i;
760 bool can_apply_seamless_boot = false;
761
762 for (i = 0; i < dc->current_state->stream_count; i++) {
763 if (dc->current_state->streams[i]->apply_seamless_boot_optimization) {
764 can_apply_seamless_boot = true;
765 break;
766 }
767 }
768
769 return !can_apply_seamless_boot && reason != DETECT_REASON_BOOT;
770 }
771
prepare_phy_clocks_for_destructive_link_verification(const struct dc * dc)772 static void prepare_phy_clocks_for_destructive_link_verification(const struct dc *dc)
773 {
774 dc_z10_restore(dc);
775 clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
776 }
777
restore_phy_clocks_for_destructive_link_verification(const struct dc * dc)778 static void restore_phy_clocks_for_destructive_link_verification(const struct dc *dc)
779 {
780 clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
781 }
782
verify_link_capability_destructive(struct dc_link * link,enum dc_detect_reason reason)783 static void verify_link_capability_destructive(struct dc_link *link,
784 enum dc_detect_reason reason)
785 {
786 bool should_prepare_phy_clocks =
787 should_prepare_phy_clocks_for_link_verification(link->dc, reason);
788
789 if (should_prepare_phy_clocks)
790 prepare_phy_clocks_for_destructive_link_verification(link->dc);
791
792 if (dc_is_dp_signal(link->local_sink->sink_signal)) {
793 struct dc_link_settings known_limit_link_setting =
794 dp_get_max_link_cap(link);
795 link_set_all_streams_dpms_off_for_link(link);
796 dp_verify_link_cap_with_retries(
797 link, &known_limit_link_setting,
798 LINK_TRAINING_MAX_VERIFY_RETRY);
799 } else {
800 ASSERT(0);
801 }
802
803 if (should_prepare_phy_clocks)
804 restore_phy_clocks_for_destructive_link_verification(link->dc);
805 }
806
verify_link_capability_non_destructive(struct dc_link * link)807 static void verify_link_capability_non_destructive(struct dc_link *link)
808 {
809 if (dc_is_dp_signal(link->local_sink->sink_signal)) {
810 if (dc_is_embedded_signal(link->local_sink->sink_signal) ||
811 link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
812 /* TODO - should we check link encoder's max link caps here?
813 * How do we know which link encoder to check from?
814 */
815 link->verified_link_cap = link->reported_link_cap;
816 else
817 link->verified_link_cap = dp_get_max_link_cap(link);
818 }
819 }
820
should_verify_link_capability_destructively(struct dc_link * link,enum dc_detect_reason reason)821 static bool should_verify_link_capability_destructively(struct dc_link *link,
822 enum dc_detect_reason reason)
823 {
824 (void)reason;
825 bool destrictive = false;
826 struct dc_link_settings max_link_cap;
827 bool is_link_enc_unavailable = false;
828
829 if (!link->dc->config.unify_link_enc_assignment)
830 is_link_enc_unavailable = link->link_enc &&
831 link->dc->res_pool->funcs->link_encs_assign &&
832 !link_enc_cfg_is_link_enc_avail(
833 link->ctx->dc,
834 link->link_enc->preferred_engine,
835 link);
836
837 if (dc_is_dp_signal(link->local_sink->sink_signal)) {
838 max_link_cap = dp_get_max_link_cap(link);
839 destrictive = true;
840
841 if (link->dc->debug.skip_detection_link_training ||
842 dc_is_embedded_signal(link->local_sink->sink_signal) ||
843 (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
844 !link->dc->config.enable_dpia_pre_training)) {
845 destrictive = false;
846 } else if (link_dp_get_encoding_format(&max_link_cap) ==
847 DP_8b_10b_ENCODING) {
848 if (link->dpcd_caps.is_mst_capable ||
849 is_link_enc_unavailable) {
850 destrictive = false;
851 }
852 }
853 }
854
855 return destrictive;
856 }
857
verify_link_capability(struct dc_link * link,enum dc_detect_reason reason)858 static void verify_link_capability(struct dc_link *link,
859 enum dc_detect_reason reason)
860 {
861 if (should_verify_link_capability_destructively(link, reason))
862 verify_link_capability_destructive(link, reason);
863 else
864 verify_link_capability_non_destructive(link);
865 }
866
867 /**
868 * link_detect_evaluate_edid_header() - Evaluate if an EDID header is acceptable.
869 *
870 * Evaluates an 8-byte EDID header to check if it's good enough
871 * for the purpose of determining whether a display is connected
872 * without reading the full EDID.
873 *
874 * @edid_header: The first 8 bytes of the EDID read from DDC.
875 *
876 * Return: true if the header looks valid (>= 6 of 8 bytes match the
877 * expected 00/FF pattern), false otherwise.
878 */
link_detect_evaluate_edid_header(uint8_t edid_header[8])879 static bool link_detect_evaluate_edid_header(uint8_t edid_header[8])
880 {
881 int edid_header_score = 0;
882 int i;
883
884 for (i = 0; i < 8; ++i)
885 edid_header_score += edid_header[i] == ((i == 0 || i == 7) ? 0x00 : 0xff);
886
887 return edid_header_score >= 6;
888 }
889
890 /**
891 * link_detect_ddc_probe() - Probe the DDC to see if a display is connected.
892 *
893 * Detect whether a display is connected to DDC without reading full EDID.
894 * Reads only the EDID header (the first 8 bytes of EDID) from DDC and
895 * evaluates whether that matches.
896 *
897 * @link: DC link whose DDC/I2C is probed for the EDID header.
898 *
899 * Return: true if the EDID header was read and passes validation,
900 * false otherwise.
901 */
link_detect_ddc_probe(struct dc_link * link)902 static bool link_detect_ddc_probe(struct dc_link *link)
903 {
904 enum signal_type signal = link_detect_sink_signal_type(link, DETECT_REASON_HPD);
905 enum ddc_transaction_type transaction_type = get_ddc_transaction_type(signal);
906 uint8_t edid_header[8] = {0};
907 uint8_t zero = 0;
908 bool ddc_probed;
909
910 if (!link->ddc)
911 return false;
912
913 if (link->dc->hwss.prepare_ddc)
914 link->dc->hwss.prepare_ddc(link);
915
916 set_ddc_transaction_type(link->ddc, transaction_type);
917
918 ddc_probed = link_query_ddc_data(link->ddc, 0x50, &zero, 1, edid_header, sizeof(edid_header));
919
920 if (!ddc_probed)
921 return false;
922
923 if (!link_detect_evaluate_edid_header(edid_header))
924 return false;
925
926 return true;
927 }
928
929 /**
930 * link_detect_dac_load_detect() - Performs DAC load detection.
931 *
932 * Load detection can be used to detect the presence of an
933 * analog display when we can't read DDC. This causes a visible
934 * visual glitch so it should be used sparingly.
935 *
936 * @link: DC link to test using the DAC load-detect path.
937 *
938 * Return: true if the VBIOS load-detect call reports OK, false
939 * otherwise.
940 */
link_detect_dac_load_detect(struct dc_link * link)941 static bool link_detect_dac_load_detect(struct dc_link *link)
942 {
943 if (!link->dc->hwss.dac_load_detect)
944 return false;
945
946 return link->dc->hwss.dac_load_detect(link);
947 }
948
949 /*
950 * detect_link_and_local_sink() - Detect if a sink is attached to a given link
951 *
952 * link->local_sink is created or destroyed as needed.
953 *
954 * This does not create remote sinks.
955 */
detect_link_and_local_sink(struct dc_link * link,enum dc_detect_reason reason)956 static bool detect_link_and_local_sink(struct dc_link *link,
957 enum dc_detect_reason reason)
958 {
959 struct dc_sink_init_data sink_init_data = { 0 };
960 struct display_sink_capability sink_caps = { 0 };
961 uint32_t i;
962 bool converter_disable_audio = false;
963 struct audio_support *aud_support = &link->dc->res_pool->audio_support;
964 bool same_edid = false;
965 enum dc_edid_status edid_status;
966 struct dc_context *dc_ctx = link->ctx;
967 struct dc *dc = dc_ctx->dc;
968 struct dc_sink *sink = NULL;
969 struct dc_sink *prev_sink = NULL;
970 struct dpcd_caps prev_dpcd_caps;
971 enum dc_connection_type new_connection_type = dc_connection_none;
972 const uint32_t post_oui_delay = 30; // 30ms
973
974 if (dc_is_virtual_signal(link->connector_signal))
975 return false;
976
977 if (((link->connector_signal == SIGNAL_TYPE_LVDS ||
978 link->connector_signal == SIGNAL_TYPE_EDP) &&
979 (!link->dc->config.allow_edp_hotplug_detection)) &&
980 link->local_sink) {
981 // need to re-write OUI and brightness in resume case
982 if (link->connector_signal == SIGNAL_TYPE_EDP &&
983 (link->dpcd_sink_ext_caps.bits.oled == 1)) {
984 dpcd_set_source_specific_data(link);
985 msleep(post_oui_delay);
986 set_default_brightness_aux(link);
987 }
988
989 return true;
990 }
991
992 if (!link_detect_connection_type(link, &new_connection_type)) {
993 BREAK_TO_DEBUGGER();
994 return false;
995 }
996
997 prev_sink = link->local_sink;
998 if (prev_sink) {
999 dc_sink_retain(prev_sink);
1000 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
1001 }
1002
1003 link_disconnect_sink(link);
1004 if (new_connection_type != dc_connection_none) {
1005 link->type = new_connection_type;
1006 link->link_state_valid = false;
1007
1008 /* From Disconnected-to-Connected. */
1009 switch (link->connector_signal) {
1010 case SIGNAL_TYPE_HDMI_TYPE_A: {
1011 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1012 if (aud_support->hdmi_audio_native)
1013 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
1014 else
1015 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1016 break;
1017 }
1018
1019 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
1020 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1021 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1022 break;
1023 }
1024
1025 case SIGNAL_TYPE_DVI_DUAL_LINK: {
1026 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1027 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1028 break;
1029 }
1030
1031 case SIGNAL_TYPE_RGB: {
1032 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1033 sink_caps.signal = SIGNAL_TYPE_RGB;
1034 break;
1035 }
1036
1037 case SIGNAL_TYPE_LVDS: {
1038 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1039 sink_caps.signal = SIGNAL_TYPE_LVDS;
1040 break;
1041 }
1042
1043 case SIGNAL_TYPE_EDP: {
1044 detect_edp_sink_caps(link);
1045 read_current_link_settings_on_detect(link);
1046
1047 /* Disable power sequence on MIPI panel + converter
1048 */
1049 if (dc->config.enable_mipi_converter_optimization &&
1050 dc_ctx->dce_version == DCN_VERSION_3_01 &&
1051 link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_0022B9 &&
1052 memcmp(&link->dpcd_caps.branch_dev_name, DP_SINK_BRANCH_DEV_NAME_7580,
1053 sizeof(link->dpcd_caps.branch_dev_name)) == 0) {
1054 dc->config.edp_no_power_sequencing = true;
1055
1056 if (!link->dpcd_caps.set_power_state_capable_edp)
1057 link->wa_flags.dp_keep_receiver_powered = true;
1058 }
1059
1060 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
1061 sink_caps.signal = SIGNAL_TYPE_EDP;
1062 break;
1063 }
1064
1065 case SIGNAL_TYPE_DISPLAY_PORT: {
1066
1067 /* wa HPD high coming too early*/
1068 if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
1069 link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
1070
1071 /* if alt mode times out, return false */
1072 if (!wait_for_entering_dp_alt_mode(link))
1073 return false;
1074 }
1075
1076 if (!detect_dp(link, &sink_caps, reason)) {
1077
1078 if (prev_sink)
1079 dc_sink_release(prev_sink);
1080 return false;
1081 }
1082
1083 /* Active SST downstream branch device unplug*/
1084 if (link->type == dc_connection_sst_branch &&
1085 link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
1086 if (prev_sink)
1087 /* Downstream unplug */
1088 dc_sink_release(prev_sink);
1089 return true;
1090 }
1091
1092 /* disable audio for non DP to HDMI active sst converter */
1093 if (link->type == dc_connection_sst_branch &&
1094 is_dp_active_dongle(link) &&
1095 (link->dpcd_caps.dongle_type !=
1096 DISPLAY_DONGLE_DP_HDMI_CONVERTER))
1097 converter_disable_audio = true;
1098
1099 /* limited link rate to HBR3 for DPIA until we implement USB4 V2 */
1100 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
1101 link->reported_link_cap.link_rate > LINK_RATE_HIGH3)
1102 link->reported_link_cap.link_rate = LINK_RATE_HIGH3;
1103
1104 if (link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling
1105 && link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc
1106 && link->dpcd_caps.usb4_dp_tun_info.driver_bw_cap.bits.driver_bw_alloc_support) {
1107 if (link_dpia_enable_usb4_dp_bw_alloc_mode(link) == false)
1108 link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc = false;
1109 }
1110 break;
1111 }
1112
1113 default:
1114 DC_ERROR("Invalid connector type! signal:%d\n",
1115 link->connector_signal);
1116 if (prev_sink)
1117 dc_sink_release(prev_sink);
1118 return false;
1119 } /* switch() */
1120
1121 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
1122 link->dpcd_sink_count =
1123 link->dpcd_caps.sink_count.bits.SINK_COUNT;
1124 else
1125 link->dpcd_sink_count = 1;
1126
1127 set_ddc_transaction_type(link->ddc,
1128 sink_caps.transaction_type);
1129
1130 link->aux_mode =
1131 link_is_in_aux_transaction_mode(link->ddc);
1132
1133 sink_init_data.link = link;
1134 sink_init_data.sink_signal = sink_caps.signal;
1135
1136 sink = dc_sink_create(&sink_init_data);
1137 if (!sink) {
1138 DC_ERROR("Failed to create sink!\n");
1139 if (prev_sink)
1140 dc_sink_release(prev_sink);
1141 return false;
1142 }
1143
1144 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
1145 sink->converter_disable_audio = converter_disable_audio;
1146
1147 /* dc_sink_create returns a new reference */
1148 link->local_sink = sink;
1149
1150 edid_status = dm_helpers_read_local_edid(link->ctx,
1151 link, sink);
1152
1153 switch (edid_status) {
1154 case EDID_BAD_CHECKSUM:
1155 DC_LOG_ERROR("EDID checksum invalid.\n");
1156 break;
1157 case EDID_PARTIAL_VALID:
1158 DC_LOG_ERROR("Partial EDID valid, abandon invalid blocks.\n");
1159 break;
1160 case EDID_NO_RESPONSE:
1161 /* Analog connectors without EDID:
1162 * - old monitor that actually doesn't have EDID
1163 * - cheap DVI-A cable or adapter that doesn't connect DDC
1164 */
1165 if (dc_connector_supports_analog(link->link_id.id)) {
1166 /* If we didn't already detect a display using
1167 * DAC load detection, we know it isn't connected.
1168 */
1169 if (link->type != dc_connection_analog_load) {
1170 if (prev_sink)
1171 dc_sink_release(prev_sink);
1172 link_disconnect_sink(link);
1173 return false;
1174 }
1175
1176 LINK_INFO("link=%d, analog display detected without EDID\n",
1177 link->link_index);
1178
1179 link->type = dc_connection_analog_load;
1180 sink->edid_caps.analog = true;
1181 break;
1182 }
1183
1184 DC_LOG_ERROR("No EDID read.\n");
1185
1186 /*
1187 * Abort detection for non-DP connectors if we have
1188 * no EDID
1189 *
1190 * DP needs to report as connected if HDP is high
1191 * even if we have no EDID in order to go to
1192 * fail-safe mode
1193 */
1194 if (dc_is_hdmi_signal(link->connector_signal) ||
1195 dc_is_dvi_signal(link->connector_signal)) {
1196 if (prev_sink)
1197 dc_sink_release(prev_sink);
1198
1199 return false;
1200 }
1201
1202 if (link->type == dc_connection_sst_branch &&
1203 link->dpcd_caps.dongle_type ==
1204 DISPLAY_DONGLE_DP_VGA_CONVERTER &&
1205 reason == DETECT_REASON_HPDRX) {
1206 /* Abort detection for DP-VGA adapters when EDID
1207 * can't be read and detection reason is VGA-side
1208 * hotplug
1209 */
1210 if (prev_sink)
1211 dc_sink_release(prev_sink);
1212 link_disconnect_sink(link);
1213
1214 return true;
1215 }
1216
1217 break;
1218 default:
1219 break;
1220 }
1221
1222 // Check if edid is the same
1223 if ((prev_sink) &&
1224 (edid_status == EDID_THE_SAME || edid_status == EDID_OK))
1225 same_edid = is_same_edid(&prev_sink->dc_edid,
1226 &sink->dc_edid);
1227
1228 if (sink->edid_caps.panel_patch.skip_scdc_overwrite)
1229 link->ctx->dc->debug.hdmi20_disable = true;
1230
1231 if (sink->edid_caps.panel_patch.remove_sink_ext_caps)
1232 link->dpcd_sink_ext_caps.raw = 0;
1233
1234 if (dc_is_hdmi_signal(link->connector_signal))
1235 read_scdc_caps(link->ddc, link->local_sink);
1236
1237 /* When FreeSync is toggled through OSD,
1238 * we see same EDID no matter what. Check MCCS caps
1239 * to see if we should update FreeSync caps now.
1240 */
1241 dm_helpers_read_mccs_caps(
1242 link->ctx,
1243 link,
1244 sink);
1245
1246 if (prev_sink != NULL) {
1247 if (memcmp(&sink->mccs_caps, &prev_sink->mccs_caps, sizeof(struct mccs_caps)))
1248 same_edid = false;
1249 }
1250
1251 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1252 sink_caps.transaction_type ==
1253 DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
1254 /*
1255 * TODO debug why certain monitors don't like
1256 * two link trainings
1257 */
1258 query_hdcp_capability(sink->sink_signal, link);
1259 } else {
1260 // If edid is the same, then discard new sink and revert back to original sink
1261 if (same_edid) {
1262 link_disconnect_remap(prev_sink, link);
1263 sink = prev_sink;
1264 prev_sink = NULL;
1265 }
1266
1267 if (!sink->edid_caps.analog)
1268 query_hdcp_capability(sink->sink_signal, link);
1269 }
1270
1271 /* DVI-I connector connected to analog display. */
1272 if ((link->link_id.id == CONNECTOR_ID_DUAL_LINK_DVII ||
1273 link->link_id.id == CONNECTOR_ID_SINGLE_LINK_DVII) &&
1274 sink->edid_caps.analog)
1275 sink->sink_signal = SIGNAL_TYPE_RGB;
1276
1277 /* HDMI-DVI Dongle */
1278 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
1279 !sink->edid_caps.edid_hdmi)
1280 sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1281 else if (dc_is_dvi_signal(sink->sink_signal) &&
1282 dc_is_dvi_signal(link->connector_signal) &&
1283 aud_support->hdmi_audio_native &&
1284 sink->edid_caps.edid_hdmi)
1285 sink->sink_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1286
1287 if (link->local_sink && dc_is_dp_signal(sink_caps.signal))
1288 dp_trace_init(link);
1289
1290 /* Connectivity log: detection */
1291 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) {
1292 CONN_DATA_DETECT(link,
1293 &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE],
1294 DC_EDID_BLOCK_SIZE,
1295 "%s: [Block %d] ", sink->edid_caps.display_name, i);
1296 }
1297
1298 DC_LOG_DETECTION_EDID_PARSER("%s: "
1299 "manufacturer_id = %X, "
1300 "product_id = %X, "
1301 "serial_number = %X, "
1302 "manufacture_week = %d, "
1303 "manufacture_year = %d, "
1304 "display_name = %s, "
1305 "speaker_flag = %d, "
1306 "audio_mode_count = %d\n",
1307 __func__,
1308 sink->edid_caps.manufacturer_id,
1309 sink->edid_caps.product_id,
1310 sink->edid_caps.serial_number,
1311 sink->edid_caps.manufacture_week,
1312 sink->edid_caps.manufacture_year,
1313 sink->edid_caps.display_name,
1314 sink->edid_caps.speaker_flags,
1315 sink->edid_caps.audio_mode_count);
1316
1317 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
1318 DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
1319 "format_code = %d, "
1320 "channel_count = %d, "
1321 "sample_rate = %d, "
1322 "sample_size = %d\n",
1323 __func__,
1324 i,
1325 sink->edid_caps.audio_modes[i].format_code,
1326 sink->edid_caps.audio_modes[i].channel_count,
1327 sink->edid_caps.audio_modes[i].sample_rate,
1328 sink->edid_caps.audio_modes[i].sample_size);
1329 }
1330
1331 if (link->connector_signal == SIGNAL_TYPE_EDP) {
1332 // Init dc_panel_config by HW config
1333 if (dc_ctx->dc->res_pool->funcs->get_panel_config_defaults)
1334 dc_ctx->dc->res_pool->funcs->get_panel_config_defaults(&link->panel_config);
1335 // Pickup base DM settings
1336 dm_helpers_init_panel_settings(dc_ctx, &link->panel_config, sink);
1337 // Override dc_panel_config if system has specific settings
1338 dm_helpers_override_panel_settings(dc_ctx, link);
1339
1340 //sink only can use supported link rate table, we are foreced to enable it
1341 if (link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)
1342 link->panel_config.ilr.optimize_edp_link_rate = true;
1343 link->reported_link_cap.link_rate = get_max_edp_link_rate(link);
1344 }
1345
1346 } else {
1347 /* From Connected-to-Disconnected. */
1348 link->type = dc_connection_none;
1349 sink_caps.signal = SIGNAL_TYPE_NONE;
1350 memset(&link->hdcp_caps, 0, sizeof(struct hdcp_caps));
1351 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk
1352 * is not cleared. If we emulate a DP signal on this connection, it thinks
1353 * the dongle is still there and limits the number of modes we can emulate.
1354 * Clear dongle_max_pix_clk on disconnect to fix this
1355 */
1356 link->dongle_max_pix_clk = 0;
1357
1358 dc_link_clear_dprx_states(link);
1359 dp_trace_reset(link);
1360 }
1361
1362 LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n",
1363 link->link_index, sink,
1364 (sink_caps.signal ==
1365 SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"),
1366 prev_sink, same_edid);
1367
1368 if (prev_sink)
1369 dc_sink_release(prev_sink);
1370
1371 return true;
1372 }
1373
1374 /**
1375 * link_detect_connection_type_analog() - Determines if an analog sink is connected.
1376 *
1377 * @link: DC link to evaluate (must support analog signalling).
1378 * @type: Updated with the detected connection type:
1379 * dc_connection_single (analog via DDC),
1380 * dc_connection_analog_load (via load-detect),
1381 * or dc_connection_none.
1382 *
1383 * Return: true if detection completed.
1384 */
link_detect_connection_type_analog(struct dc_link * link,enum dc_connection_type * type)1385 static bool link_detect_connection_type_analog(struct dc_link *link, enum dc_connection_type *type)
1386 {
1387 /* Don't care about connectors that don't support an analog signal. */
1388 ASSERT(dc_connector_supports_analog(link->link_id.id));
1389
1390 if (link_detect_ddc_probe(link)) {
1391 *type = dc_connection_single;
1392 return true;
1393 }
1394
1395 if (link_detect_dac_load_detect(link)) {
1396 *type = dc_connection_analog_load;
1397 return true;
1398 }
1399
1400 *type = dc_connection_none;
1401 return true;
1402 }
1403
1404 /*
1405 * link_detect_connection_type() - Determine if there is a sink connected
1406 *
1407 * @type: Returned connection type
1408 * Does not detect downstream devices, such as MST sinks
1409 * or display connected through active dongles
1410 */
link_detect_connection_type(struct dc_link * link,enum dc_connection_type * type)1411 bool link_detect_connection_type(struct dc_link *link, enum dc_connection_type *type)
1412 {
1413 if (link->connector_signal == SIGNAL_TYPE_LVDS) {
1414 *type = dc_connection_single;
1415 return true;
1416 }
1417
1418 /* Ignore the HPD pin (if any) for analog connectors.
1419 * Instead rely on DDC and DAC.
1420 *
1421 * - VGA connectors don't have any HPD at all.
1422 * - Some DVI-A cables don't connect the HPD pin.
1423 * - Some DVI-A cables pull up the HPD pin.
1424 * (So it's high even when no display is connected.)
1425 */
1426 if (dc_connector_supports_analog(link->link_id.id))
1427 return link_detect_connection_type_analog(link, type);
1428
1429 if (link->connector_signal == SIGNAL_TYPE_EDP) {
1430 /*in case it is not on*/
1431 if (!link->dc->config.edp_no_power_sequencing)
1432 link->dc->hwss.edp_power_control(link, true);
1433 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1434 }
1435
1436 /* Link may not have physical HPD pin. */
1437 if (link->ep_type != DISPLAY_ENDPOINT_PHY) {
1438 if (link->is_hpd_pending || !dpia_query_hpd_status(link))
1439 *type = dc_connection_none;
1440 else
1441 *type = dc_connection_single;
1442
1443 return true;
1444 }
1445
1446
1447 if (link_get_hpd_state(link)) {
1448 *type = dc_connection_single;
1449 /* TODO: need to do the actual detection */
1450 } else {
1451 *type = dc_connection_none;
1452 if (link->connector_signal == SIGNAL_TYPE_EDP) {
1453 /* eDP is not connected, power down it */
1454 if (!link->dc->config.edp_no_power_sequencing)
1455 link->dc->hwss.edp_power_control(link, false);
1456 }
1457 }
1458
1459 return true;
1460 }
1461
link_detect(struct dc_link * link,enum dc_detect_reason reason)1462 bool link_detect(struct dc_link *link, enum dc_detect_reason reason)
1463 {
1464 bool is_local_sink_detect_success;
1465 bool is_delegated_to_mst_top_mgr = false;
1466 enum dc_connection_type pre_link_type = link->type;
1467
1468 is_local_sink_detect_success = detect_link_and_local_sink(link, reason);
1469
1470 if (is_local_sink_detect_success && link->local_sink) {
1471 verify_link_capability(link, reason);
1472 }
1473
1474 DC_LOG_DC("%s: link_index=%d is_local_sink_detect_success=%d pre_link_type=%d link_type=%d\n", __func__,
1475 link->link_index, is_local_sink_detect_success, pre_link_type, link->type);
1476
1477 if (is_local_sink_detect_success && link->local_sink &&
1478 dc_is_dp_signal(link->local_sink->sink_signal) &&
1479 link->dpcd_caps.is_mst_capable)
1480 is_delegated_to_mst_top_mgr = discover_dp_mst_topology(link, reason);
1481
1482 if (pre_link_type == dc_connection_mst_branch &&
1483 link->type != dc_connection_mst_branch)
1484 is_delegated_to_mst_top_mgr = link_reset_cur_dp_mst_topology(link);
1485
1486 return is_local_sink_detect_success && !is_delegated_to_mst_top_mgr;
1487 }
1488
link_clear_dprx_states(struct dc_link * link)1489 void link_clear_dprx_states(struct dc_link *link)
1490 {
1491 memset(&link->dprx_states, 0, sizeof(link->dprx_states));
1492 }
1493
link_is_hdcp14(struct dc_link * link,enum signal_type signal)1494 bool link_is_hdcp14(struct dc_link *link, enum signal_type signal)
1495 {
1496 bool ret = false;
1497
1498 switch (signal) {
1499 case SIGNAL_TYPE_DISPLAY_PORT:
1500 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1501 ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE;
1502 break;
1503 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1504 case SIGNAL_TYPE_DVI_DUAL_LINK:
1505 case SIGNAL_TYPE_HDMI_TYPE_A:
1506 /* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable,
1507 * we can poll for bksv but some displays have an issue with this. Since its so rare
1508 * for a display to not be 1.4 capable, this assumtion is ok
1509 */
1510 ret = true;
1511 break;
1512 default:
1513 break;
1514 }
1515 return ret;
1516 }
1517
link_is_hdcp22(struct dc_link * link,enum signal_type signal)1518 bool link_is_hdcp22(struct dc_link *link, enum signal_type signal)
1519 {
1520 bool ret = false;
1521
1522 switch (signal) {
1523 case SIGNAL_TYPE_DISPLAY_PORT:
1524 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1525 ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE &&
1526 link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable &&
1527 (link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0;
1528 break;
1529 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1530 case SIGNAL_TYPE_DVI_DUAL_LINK:
1531 case SIGNAL_TYPE_HDMI_TYPE_A:
1532 ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0;
1533 break;
1534 default:
1535 break;
1536 }
1537
1538 return ret;
1539 }
1540
link_get_status(const struct dc_link * link)1541 const struct dc_link_status *link_get_status(const struct dc_link *link)
1542 {
1543 return &link->link_status;
1544 }
1545
1546
link_add_remote_sink_helper(struct dc_link * dc_link,struct dc_sink * sink)1547 static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink)
1548 {
1549 if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
1550 BREAK_TO_DEBUGGER();
1551 return false;
1552 }
1553
1554 dc_sink_retain(sink);
1555
1556 dc_link->remote_sinks[dc_link->sink_count] = sink;
1557 dc_link->sink_count++;
1558
1559 return true;
1560 }
1561
link_add_remote_sink(struct dc_link * link,const uint8_t * edid,int len,struct dc_sink_init_data * init_data)1562 struct dc_sink *link_add_remote_sink(
1563 struct dc_link *link,
1564 const uint8_t *edid,
1565 int len,
1566 struct dc_sink_init_data *init_data)
1567 {
1568 struct dc_sink *dc_sink;
1569 enum dc_edid_status edid_status;
1570
1571 if (len > DC_MAX_EDID_BUFFER_SIZE) {
1572 dm_error("Max EDID buffer size breached!\n");
1573 return NULL;
1574 }
1575
1576 if (!init_data) {
1577 BREAK_TO_DEBUGGER();
1578 return NULL;
1579 }
1580
1581 if (!init_data->link) {
1582 BREAK_TO_DEBUGGER();
1583 return NULL;
1584 }
1585
1586 dc_sink = dc_sink_create(init_data);
1587
1588 if (!dc_sink)
1589 return NULL;
1590
1591 memmove(dc_sink->dc_edid.raw_edid, edid, len);
1592 dc_sink->dc_edid.length = len;
1593
1594 if (!link_add_remote_sink_helper(
1595 link,
1596 dc_sink))
1597 goto fail_add_sink;
1598
1599 edid_status = dm_helpers_parse_edid_caps(
1600 link,
1601 &dc_sink->dc_edid,
1602 &dc_sink->edid_caps);
1603
1604 /*
1605 * Treat device as no EDID device if EDID
1606 * parsing fails
1607 */
1608 if (edid_status != EDID_OK && edid_status != EDID_PARTIAL_VALID) {
1609 dc_sink->dc_edid.length = 0;
1610 dm_error("Bad EDID, status%d!\n", edid_status);
1611 }
1612
1613 return dc_sink;
1614
1615 fail_add_sink:
1616 dc_sink_release(dc_sink);
1617 return NULL;
1618 }
1619
link_remove_remote_sink(struct dc_link * link,struct dc_sink * sink)1620 void link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink)
1621 {
1622 int i;
1623
1624 if (!link->sink_count) {
1625 BREAK_TO_DEBUGGER();
1626 return;
1627 }
1628
1629 for (i = 0; i < link->sink_count; i++) {
1630 if (link->remote_sinks[i] == sink) {
1631 dc_sink_release(sink);
1632 link->remote_sinks[i] = NULL;
1633
1634 /* shrink array to remove empty place */
1635 while (i < link->sink_count - 1) {
1636 link->remote_sinks[i] = link->remote_sinks[i+1];
1637 i++;
1638 }
1639 link->remote_sinks[i] = NULL;
1640 link->sink_count--;
1641 return;
1642 }
1643 }
1644 }
1645