1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Copyright (c) 2021 MediaTek Inc. 4 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 5 6 #include <linux/clk-provider.h> 7 #include <linux/mod_devicetable.h> 8 #include <linux/platform_device.h> 9 10 #include "clk-mtk.h" 11 #include "clk-gate.h" 12 13 #include <dt-bindings/clock/mt8192-clk.h> 14 15 static const struct mtk_gate_regs msdc_top_cg_regs = { 16 .set_ofs = 0x0, 17 .clr_ofs = 0x0, 18 .sta_ofs = 0x0, 19 }; 20 21 #define GATE_MSDC_TOP(_id, _name, _parent, _shift) \ 22 GATE_MTK(_id, _name, _parent, &msdc_top_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 23 24 static const struct mtk_gate msdc_top_clks[] = { 25 GATE_MSDC_TOP(CLK_MSDC_TOP_AES_0P, "msdc_top_aes_0p", "aes_msdcfde_sel", 0), 26 GATE_MSDC_TOP(CLK_MSDC_TOP_SRC_0P, "msdc_top_src_0p", "infra_msdc0_src", 1), 27 GATE_MSDC_TOP(CLK_MSDC_TOP_SRC_1P, "msdc_top_src_1p", "infra_msdc1_src", 2), 28 GATE_MSDC_TOP(CLK_MSDC_TOP_SRC_2P, "msdc_top_src_2p", "infra_msdc2_src", 3), 29 GATE_MSDC_TOP(CLK_MSDC_TOP_P_MSDC0, "msdc_top_p_msdc0", "axi_sel", 4), 30 GATE_MSDC_TOP(CLK_MSDC_TOP_P_MSDC1, "msdc_top_p_msdc1", "axi_sel", 5), 31 GATE_MSDC_TOP(CLK_MSDC_TOP_P_MSDC2, "msdc_top_p_msdc2", "axi_sel", 6), 32 GATE_MSDC_TOP(CLK_MSDC_TOP_P_CFG, "msdc_top_p_cfg", "axi_sel", 7), 33 GATE_MSDC_TOP(CLK_MSDC_TOP_AXI, "msdc_top_axi", "axi_sel", 8), 34 GATE_MSDC_TOP(CLK_MSDC_TOP_H_MST_0P, "msdc_top_h_mst_0p", "infra_msdc0", 9), 35 GATE_MSDC_TOP(CLK_MSDC_TOP_H_MST_1P, "msdc_top_h_mst_1p", "infra_msdc1", 10), 36 GATE_MSDC_TOP(CLK_MSDC_TOP_H_MST_2P, "msdc_top_h_mst_2p", "infra_msdc2", 11), 37 GATE_MSDC_TOP(CLK_MSDC_TOP_MEM_OFF_DLY_26M, "msdc_top_mem_off_dly_26m", "clk26m", 12), 38 GATE_MSDC_TOP(CLK_MSDC_TOP_32K, "msdc_top_32k", "clk32k", 13), 39 GATE_MSDC_TOP(CLK_MSDC_TOP_AHB2AXI_BRG_AXI, "msdc_top_ahb2axi_brg_axi", "axi_sel", 14), 40 }; 41 42 static const struct mtk_clk_desc msdc_top_desc = { 43 .clks = msdc_top_clks, 44 .num_clks = ARRAY_SIZE(msdc_top_clks), 45 }; 46 47 static const struct of_device_id of_match_clk_mt8192_msdc[] = { 48 { 49 .compatible = "mediatek,mt8192-msdc_top", 50 .data = &msdc_top_desc, 51 }, { 52 /* sentinel */ 53 } 54 }; 55 MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_msdc); 56 57 static struct platform_driver clk_mt8192_msdc_drv = { 58 .probe = mtk_clk_simple_probe, 59 .remove = mtk_clk_simple_remove, 60 .driver = { 61 .name = "clk-mt8192-msdc", 62 .of_match_table = of_match_clk_mt8192_msdc, 63 }, 64 }; 65 module_platform_driver(clk_mt8192_msdc_drv); 66 67 MODULE_DESCRIPTION("MediaTek MT8192 MMC/SD Controller clocks driver"); 68 MODULE_LICENSE("GPL"); 69