1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2018-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/printk.h> 26 #include <linux/slab.h> 27 #include <linux/uaccess.h> 28 #include "kfd_priv.h" 29 #include "kfd_mqd_manager.h" 30 #include "v10_structs.h" 31 #include "gc/gc_10_1_0_offset.h" 32 #include "gc/gc_10_1_0_sh_mask.h" 33 #include "amdgpu_amdkfd.h" 34 35 static inline struct v10_compute_mqd *get_mqd(void *mqd) 36 { 37 return (struct v10_compute_mqd *)mqd; 38 } 39 40 static inline struct v10_sdma_mqd *get_sdma_mqd(void *mqd) 41 { 42 return (struct v10_sdma_mqd *)mqd; 43 } 44 45 static void update_cu_mask(struct mqd_manager *mm, void *mqd, 46 struct mqd_update_info *minfo) 47 { 48 struct v10_compute_mqd *m; 49 uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */ 50 51 if (!minfo || !minfo->cu_mask.ptr) 52 return; 53 54 mqd_symmetrically_map_cu_mask(mm, 55 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, 0); 56 57 m = get_mqd(mqd); 58 m->compute_static_thread_mgmt_se0 = se_mask[0]; 59 m->compute_static_thread_mgmt_se1 = se_mask[1]; 60 m->compute_static_thread_mgmt_se2 = se_mask[2]; 61 m->compute_static_thread_mgmt_se3 = se_mask[3]; 62 63 pr_debug("update cu mask to %#x %#x %#x %#x\n", 64 m->compute_static_thread_mgmt_se0, 65 m->compute_static_thread_mgmt_se1, 66 m->compute_static_thread_mgmt_se2, 67 m->compute_static_thread_mgmt_se3); 68 } 69 70 static void set_priority(struct v10_compute_mqd *m, struct queue_properties *q) 71 { 72 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; 73 m->cp_hqd_queue_priority = q->priority; 74 } 75 76 static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, 77 struct queue_properties *q) 78 { 79 struct kfd_node *kfd = mm->dev; 80 struct kfd_mem_obj *mqd_mem_obj; 81 82 if (kfd_gtt_sa_allocate(kfd, sizeof(struct v10_compute_mqd), 83 &mqd_mem_obj)) 84 return NULL; 85 86 return mqd_mem_obj; 87 } 88 89 static void init_mqd(struct mqd_manager *mm, void **mqd, 90 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 91 struct queue_properties *q) 92 { 93 uint64_t addr; 94 struct v10_compute_mqd *m; 95 96 m = (struct v10_compute_mqd *) mqd_mem_obj->cpu_ptr; 97 addr = mqd_mem_obj->gpu_addr; 98 99 memset(m, 0, sizeof(struct v10_compute_mqd)); 100 101 m->header = 0xC0310800; 102 m->compute_pipelinestat_enable = 1; 103 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; 104 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; 105 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; 106 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; 107 108 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | 109 0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; 110 111 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 112 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; 113 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; 114 115 m->cp_mqd_base_addr_lo = lower_32_bits(addr); 116 m->cp_mqd_base_addr_hi = upper_32_bits(addr); 117 118 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT | 119 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT | 120 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT; 121 122 /* Set cp_hqd_hq_scheduler0 bit 14 to 1 to have the CP set up the 123 * DISPATCH_PTR. This is required for the kfd debugger 124 */ 125 m->cp_hqd_hq_scheduler0 = 1 << 14; 126 127 if (q->format == KFD_QUEUE_FORMAT_AQL) { 128 m->cp_hqd_aql_control = 129 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; 130 } 131 132 if (mm->dev->kfd->cwsr_enabled) { 133 m->cp_hqd_persistent_state |= 134 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT); 135 m->cp_hqd_ctx_save_base_addr_lo = 136 lower_32_bits(q->ctx_save_restore_area_address); 137 m->cp_hqd_ctx_save_base_addr_hi = 138 upper_32_bits(q->ctx_save_restore_area_address); 139 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; 140 m->cp_hqd_cntl_stack_size = q->ctl_stack_size; 141 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; 142 m->cp_hqd_wg_state_offset = q->ctl_stack_size; 143 } 144 145 *mqd = m; 146 if (gart_addr) 147 *gart_addr = addr; 148 mm->update_mqd(mm, m, q, NULL); 149 } 150 151 static int load_mqd(struct mqd_manager *mm, void *mqd, 152 uint32_t pipe_id, uint32_t queue_id, 153 struct queue_properties *p, struct mm_struct *mms) 154 { 155 int r = 0; 156 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 157 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 158 159 r = mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id, 160 (uint32_t __user *)p->write_ptr, 161 wptr_shift, 0, mms, 0); 162 return r; 163 } 164 165 static void update_mqd(struct mqd_manager *mm, void *mqd, 166 struct queue_properties *q, 167 struct mqd_update_info *minfo) 168 { 169 struct v10_compute_mqd *m; 170 171 m = get_mqd(mqd); 172 173 m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK; 174 m->cp_hqd_pq_control |= 175 ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1; 176 177 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); 178 179 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 180 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 181 182 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 183 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 184 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 185 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 186 187 m->cp_hqd_pq_doorbell_control = 188 q->doorbell_off << 189 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 190 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 191 m->cp_hqd_pq_doorbell_control); 192 193 m->cp_hqd_ib_control = 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT; 194 195 /* 196 * HW does not clamp this field correctly. Maximum EOP queue size 197 * is constrained by per-SE EOP done signal count, which is 8-bit. 198 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit 199 * more than (EOP entry count - 1) so a queue size of 0x800 dwords 200 * is safe, giving a maximum field value of 0xA. 201 */ 202 m->cp_hqd_eop_control = min(0xA, 203 ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1); 204 m->cp_hqd_eop_base_addr_lo = 205 lower_32_bits(q->eop_ring_buffer_address >> 8); 206 m->cp_hqd_eop_base_addr_hi = 207 upper_32_bits(q->eop_ring_buffer_address >> 8); 208 209 m->cp_hqd_iq_timer = 0; 210 211 m->cp_hqd_vmid = q->vmid; 212 213 if (q->format == KFD_QUEUE_FORMAT_AQL) { 214 /* GC 10 removed WPP_CLAMP from PQ Control */ 215 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 216 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT | 217 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT; 218 m->cp_hqd_pq_doorbell_control |= 219 1 << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT; 220 } 221 if (mm->dev->kfd->cwsr_enabled) 222 m->cp_hqd_ctx_save_control = 0; 223 224 update_cu_mask(mm, mqd, minfo); 225 set_priority(m, q); 226 227 q->is_active = QUEUE_IS_ACTIVE(*q); 228 } 229 230 static bool check_preemption_failed(struct mqd_manager *mm, void *mqd) 231 { 232 struct v10_compute_mqd *m = (struct v10_compute_mqd *)mqd; 233 234 return kfd_check_hiq_mqd_doorbell_id(mm->dev, m->queue_doorbell_id0, 0); 235 } 236 237 static int get_wave_state(struct mqd_manager *mm, void *mqd, 238 struct queue_properties *q, 239 void __user *ctl_stack, 240 u32 *ctl_stack_used_size, 241 u32 *save_area_used_size) 242 { 243 struct v10_compute_mqd *m; 244 struct kfd_context_save_area_header header; 245 246 m = get_mqd(mqd); 247 248 /* Control stack is written backwards, while workgroup context data 249 * is written forwards. Both starts from m->cp_hqd_cntl_stack_size. 250 * Current position is at m->cp_hqd_cntl_stack_offset and 251 * m->cp_hqd_wg_state_offset, respectively. 252 */ 253 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - 254 m->cp_hqd_cntl_stack_offset; 255 *save_area_used_size = m->cp_hqd_wg_state_offset - 256 m->cp_hqd_cntl_stack_size; 257 258 /* Control stack is not copied to user mode for GFXv10 because 259 * it's part of the context save area that is already 260 * accessible to user mode 261 */ 262 263 header.wave_state.control_stack_size = *ctl_stack_used_size; 264 header.wave_state.wave_state_size = *save_area_used_size; 265 266 header.wave_state.wave_state_offset = m->cp_hqd_wg_state_offset; 267 header.wave_state.control_stack_offset = m->cp_hqd_cntl_stack_offset; 268 269 if (copy_to_user(ctl_stack, &header, sizeof(header.wave_state))) 270 return -EFAULT; 271 272 return 0; 273 } 274 275 static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst) 276 { 277 struct v10_compute_mqd *m; 278 279 m = get_mqd(mqd); 280 281 memcpy(mqd_dst, m, sizeof(struct v10_compute_mqd)); 282 } 283 284 static void restore_mqd(struct mqd_manager *mm, void **mqd, 285 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 286 struct queue_properties *qp, 287 const void *mqd_src, 288 const void *ctl_stack_src, const u32 ctl_stack_size) 289 { 290 uint64_t addr; 291 struct v10_compute_mqd *m; 292 293 m = (struct v10_compute_mqd *) mqd_mem_obj->cpu_ptr; 294 addr = mqd_mem_obj->gpu_addr; 295 296 memcpy(m, mqd_src, sizeof(*m)); 297 298 *mqd = m; 299 if (gart_addr) 300 *gart_addr = addr; 301 302 m->cp_hqd_pq_doorbell_control = 303 qp->doorbell_off << 304 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 305 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 306 m->cp_hqd_pq_doorbell_control); 307 308 qp->is_active = 0; 309 } 310 311 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd, 312 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 313 struct queue_properties *q) 314 { 315 struct v10_compute_mqd *m; 316 317 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q); 318 319 m = get_mqd(*mqd); 320 321 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 322 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 323 } 324 325 static int destroy_hiq_mqd(struct mqd_manager *mm, void *mqd, 326 enum kfd_preempt_type type, unsigned int timeout, 327 uint32_t pipe_id, uint32_t queue_id) 328 { 329 int err; 330 struct v10_compute_mqd *m; 331 u32 doorbell_off; 332 333 m = get_mqd(mqd); 334 335 doorbell_off = m->cp_hqd_pq_doorbell_control >> 336 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 337 338 err = amdgpu_amdkfd_unmap_hiq(mm->dev->adev, doorbell_off, 0); 339 if (err) 340 pr_debug("Destroy HIQ MQD failed: %d\n", err); 341 342 return err; 343 } 344 345 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd, 346 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 347 struct queue_properties *q) 348 { 349 struct v10_sdma_mqd *m; 350 351 m = (struct v10_sdma_mqd *) mqd_mem_obj->cpu_ptr; 352 353 memset(m, 0, sizeof(struct v10_sdma_mqd)); 354 355 *mqd = m; 356 if (gart_addr) 357 *gart_addr = mqd_mem_obj->gpu_addr; 358 359 mm->update_mqd(mm, m, q, NULL); 360 } 361 362 #define SDMA_RLC_DUMMY_DEFAULT 0xf 363 364 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, 365 struct queue_properties *q, 366 struct mqd_update_info *minfo) 367 { 368 struct v10_sdma_mqd *m; 369 370 m = get_sdma_mqd(mqd); 371 m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1) 372 << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 373 q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | 374 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 375 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT; 376 377 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); 378 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); 379 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 380 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 381 m->sdmax_rlcx_doorbell_offset = 382 q->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 383 384 m->sdma_engine_id = q->sdma_engine_id; 385 m->sdma_queue_id = q->sdma_queue_id; 386 m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT; 387 388 q->is_active = QUEUE_IS_ACTIVE(*q); 389 } 390 391 static void checkpoint_mqd_sdma(struct mqd_manager *mm, 392 void *mqd, 393 void *mqd_dst, 394 void *ctl_stack_dst) 395 { 396 struct v10_sdma_mqd *m; 397 398 m = get_sdma_mqd(mqd); 399 400 memcpy(mqd_dst, m, sizeof(struct v10_sdma_mqd)); 401 } 402 403 static void restore_mqd_sdma(struct mqd_manager *mm, void **mqd, 404 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 405 struct queue_properties *qp, 406 const void *mqd_src, 407 const void *ctl_stack_src, 408 const u32 ctl_stack_size) 409 { 410 uint64_t addr; 411 struct v10_sdma_mqd *m; 412 413 m = (struct v10_sdma_mqd *) mqd_mem_obj->cpu_ptr; 414 addr = mqd_mem_obj->gpu_addr; 415 416 memcpy(m, mqd_src, sizeof(*m)); 417 418 m->sdmax_rlcx_doorbell_offset = 419 qp->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 420 421 *mqd = m; 422 if (gart_addr) 423 *gart_addr = addr; 424 425 qp->is_active = 0; 426 } 427 428 #if defined(CONFIG_DEBUG_FS) 429 430 static int debugfs_show_mqd(struct seq_file *m, void *data) 431 { 432 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 433 data, sizeof(struct v10_compute_mqd), false); 434 return 0; 435 } 436 437 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) 438 { 439 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 440 data, sizeof(struct v10_sdma_mqd), false); 441 return 0; 442 } 443 444 #endif 445 446 struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type, 447 struct kfd_node *dev) 448 { 449 struct mqd_manager *mqd; 450 451 if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) 452 return NULL; 453 454 mqd = kzalloc(sizeof(*mqd), GFP_KERNEL); 455 if (!mqd) 456 return NULL; 457 458 mqd->dev = dev; 459 460 switch (type) { 461 case KFD_MQD_TYPE_CP: 462 pr_debug("%s@%i\n", __func__, __LINE__); 463 mqd->allocate_mqd = allocate_mqd; 464 mqd->init_mqd = init_mqd; 465 mqd->free_mqd = kfd_free_mqd_cp; 466 mqd->load_mqd = load_mqd; 467 mqd->update_mqd = update_mqd; 468 mqd->destroy_mqd = kfd_destroy_mqd_cp; 469 mqd->is_occupied = kfd_is_occupied_cp; 470 mqd->mqd_size = sizeof(struct v10_compute_mqd); 471 mqd->get_wave_state = get_wave_state; 472 mqd->checkpoint_mqd = checkpoint_mqd; 473 mqd->restore_mqd = restore_mqd; 474 mqd->mqd_stride = kfd_mqd_stride; 475 #if defined(CONFIG_DEBUG_FS) 476 mqd->debugfs_show_mqd = debugfs_show_mqd; 477 #endif 478 pr_debug("%s@%i\n", __func__, __LINE__); 479 break; 480 case KFD_MQD_TYPE_HIQ: 481 pr_debug("%s@%i\n", __func__, __LINE__); 482 mqd->allocate_mqd = allocate_hiq_mqd; 483 mqd->init_mqd = init_mqd_hiq; 484 mqd->free_mqd = free_mqd_hiq_sdma; 485 mqd->load_mqd = kfd_hiq_load_mqd_kiq; 486 mqd->update_mqd = update_mqd; 487 mqd->destroy_mqd = destroy_hiq_mqd; 488 mqd->is_occupied = kfd_is_occupied_cp; 489 mqd->mqd_size = sizeof(struct v10_compute_mqd); 490 mqd->mqd_stride = kfd_mqd_stride; 491 #if defined(CONFIG_DEBUG_FS) 492 mqd->debugfs_show_mqd = debugfs_show_mqd; 493 #endif 494 mqd->check_preemption_failed = check_preemption_failed; 495 pr_debug("%s@%i\n", __func__, __LINE__); 496 break; 497 case KFD_MQD_TYPE_DIQ: 498 mqd->allocate_mqd = allocate_mqd; 499 mqd->init_mqd = init_mqd_hiq; 500 mqd->free_mqd = kfd_free_mqd_cp; 501 mqd->load_mqd = load_mqd; 502 mqd->update_mqd = update_mqd; 503 mqd->destroy_mqd = kfd_destroy_mqd_cp; 504 mqd->is_occupied = kfd_is_occupied_cp; 505 mqd->mqd_size = sizeof(struct v10_compute_mqd); 506 #if defined(CONFIG_DEBUG_FS) 507 mqd->debugfs_show_mqd = debugfs_show_mqd; 508 #endif 509 break; 510 case KFD_MQD_TYPE_SDMA: 511 pr_debug("%s@%i\n", __func__, __LINE__); 512 mqd->allocate_mqd = allocate_sdma_mqd; 513 mqd->init_mqd = init_mqd_sdma; 514 mqd->free_mqd = free_mqd_hiq_sdma; 515 mqd->load_mqd = kfd_load_mqd_sdma; 516 mqd->update_mqd = update_mqd_sdma; 517 mqd->destroy_mqd = kfd_destroy_mqd_sdma; 518 mqd->is_occupied = kfd_is_occupied_sdma; 519 mqd->checkpoint_mqd = checkpoint_mqd_sdma; 520 mqd->restore_mqd = restore_mqd_sdma; 521 mqd->mqd_size = sizeof(struct v10_sdma_mqd); 522 mqd->mqd_stride = kfd_mqd_stride; 523 #if defined(CONFIG_DEBUG_FS) 524 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; 525 #endif 526 pr_debug("%s@%i\n", __func__, __LINE__); 527 break; 528 default: 529 kfree(mqd); 530 return NULL; 531 } 532 533 return mqd; 534 } 535