1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef __AMDGPU_DM_H__ 28 #define __AMDGPU_DM_H__ 29 30 #include <drm/display/drm_dp_mst_helper.h> 31 #include <drm/drm_atomic.h> 32 #include <drm/drm_connector.h> 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_plane.h> 35 #include "link_service_types.h" 36 #include <drm/drm_writeback.h> 37 38 /* 39 * This file contains the definition for amdgpu_display_manager 40 * and its API for amdgpu driver's use. 41 * This component provides all the display related functionality 42 * and this is the only component that calls DAL API. 43 * The API contained here intended for amdgpu driver use. 44 * The API that is called directly from KMS framework is located 45 * in amdgpu_dm_kms.h file 46 */ 47 48 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 49 50 #define AMDGPU_DM_MAX_CRTC 6 51 52 #define AMDGPU_DM_MAX_NUM_EDP 2 53 54 #define AMDGPU_DMUB_NOTIFICATION_MAX 8 55 56 #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID 0x00001A 57 #define AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE 0x40 58 #define AMD_VDSB_VERSION_3_PANEL_TYPE_MASK 0xC0 59 #define AMD_VDSB_VERSION_3_PANEL_TYPE_SHIFT 6 60 #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3 0x3 61 62 enum amd_vsdb_panel_type { 63 AMD_VSDB_PANEL_TYPE_DEFAULT = 0, 64 AMD_VSDB_PANEL_TYPE_MINILED, 65 AMD_VSDB_PANEL_TYPE_OLED, 66 AMD_VSDB_PANEL_TYPE_RESERVED, 67 }; 68 69 #define AMDGPU_HDR_MULT_DEFAULT (0x100000000LL) 70 71 /* 72 * Maximum HDMI HPD debounce delay in milliseconds 73 */ 74 #define AMDGPU_DM_MAX_HDMI_HPD_DEBOUNCE_MS 5000 75 /* 76 #include "include/amdgpu_dal_power_if.h" 77 #include "amdgpu_dm_irq.h" 78 */ 79 80 #include "irq_types.h" 81 #include "signal_types.h" 82 #include "amdgpu_dm_crc.h" 83 #include "mod_info_packet.h" 84 struct aux_payload; 85 struct set_config_cmd_payload; 86 enum aux_return_code_type; 87 enum set_config_status; 88 89 /* Forward declarations */ 90 struct amdgpu_device; 91 struct amdgpu_crtc; 92 struct drm_device; 93 struct dc; 94 struct amdgpu_bo; 95 struct dmub_srv; 96 struct dc_plane_state; 97 struct dmub_notification; 98 struct dmub_cmd_fused_request; 99 100 struct amd_vsdb_block { 101 unsigned char ieee_id[3]; 102 unsigned char version; 103 unsigned char feature_caps; 104 unsigned char reserved[3]; 105 unsigned char color_space_eotf_support; 106 }; 107 108 struct common_irq_params { 109 struct amdgpu_device *adev; 110 enum dc_irq_source irq_src; 111 atomic64_t previous_timestamp; 112 }; 113 114 /** 115 * struct dm_compressor_info - Buffer info used by frame buffer compression 116 * @cpu_addr: MMIO cpu addr 117 * @bo_ptr: Pointer to the buffer object 118 * @gpu_addr: MMIO gpu addr 119 */ 120 struct dm_compressor_info { 121 void *cpu_addr; 122 struct amdgpu_bo *bo_ptr; 123 uint64_t gpu_addr; 124 }; 125 126 /** 127 * struct dm_boot_time_crc_info - Buffer info used by boot time CRC 128 * @cpu_addr: MMIO cpu addr 129 * @bo_ptr: Pointer to the buffer object 130 * @gpu_addr: MMIO gpu addr 131 * @size: Size of the buffer 132 */ 133 struct dm_boot_time_crc_info { 134 void *cpu_addr; 135 struct amdgpu_bo *bo_ptr; 136 uint64_t gpu_addr; 137 uint32_t size; 138 }; 139 140 typedef void (*dmub_notify_interrupt_callback_t)(struct amdgpu_device *adev, struct dmub_notification *notify); 141 142 /** 143 * struct dmub_hpd_work - Handle time consuming work in low priority outbox IRQ 144 * 145 * @handle_hpd_work: Work to be executed in a separate thread to handle hpd_low_irq 146 * @dmub_notify: notification for callback function 147 * @adev: amdgpu_device pointer 148 */ 149 struct dmub_hpd_work { 150 struct work_struct handle_hpd_work; 151 struct dmub_notification *dmub_notify; 152 struct amdgpu_device *adev; 153 }; 154 155 /** 156 * struct vblank_control_work - Work data for vblank control 157 * @work: Kernel work data for the work event 158 * @dm: amdgpu display manager device 159 * @acrtc: amdgpu CRTC instance for which the event has occurred 160 * @stream: DC stream for which the event has occurred 161 * @enable: true if enabling vblank 162 */ 163 struct vblank_control_work { 164 struct work_struct work; 165 struct amdgpu_display_manager *dm; 166 struct amdgpu_crtc *acrtc; 167 struct dc_stream_state *stream; 168 bool enable; 169 }; 170 171 /** 172 * struct idle_workqueue - Work data for periodic action in idle 173 * @work: Kernel work data for the work event 174 * @dm: amdgpu display manager device 175 * @enable: true if idle worker is enabled 176 * @running: true if idle worker is running 177 */ 178 struct idle_workqueue { 179 struct work_struct work; 180 struct amdgpu_display_manager *dm; 181 bool enable; 182 bool running; 183 }; 184 185 /** 186 * struct vupdate_offload_work - Work data for offloading task from vupdate handler 187 * @work: Kernel work data for the work event 188 * @adev: amdgpu_device back pointer 189 * @stream: DC stream associated with the crtc 190 * @adjust: DC CRTC timing adjust to be applied to the crtc 191 */ 192 struct vupdate_offload_work { 193 struct work_struct work; 194 struct amdgpu_device *adev; 195 struct dc_stream_state *stream; 196 struct dc_crtc_timing_adjust *adjust; 197 }; 198 199 #define MAX_LUMINANCE_DATA_POINTS 99 200 201 /** 202 * struct amdgpu_dm_luminance_data - Custom luminance data 203 * @luminance: Luminance in percent 204 * @input_signal: Input signal in range 0-255 205 */ 206 struct amdgpu_dm_luminance_data { 207 u8 luminance; 208 u8 input_signal; 209 } __packed; 210 211 /** 212 * struct amdgpu_dm_backlight_caps - Information about backlight 213 * 214 * Describe the backlight support for ACPI or eDP AUX. 215 */ 216 struct amdgpu_dm_backlight_caps { 217 /** 218 * @ext_caps: Keep the data struct with all the information about the 219 * display support for HDR. 220 */ 221 union dpcd_sink_ext_caps *ext_caps; 222 /** 223 * @aux_min_input_signal: Min brightness value supported by the display 224 */ 225 u32 aux_min_input_signal; 226 /** 227 * @aux_max_input_signal: Max brightness value supported by the display 228 * in nits. 229 */ 230 u32 aux_max_input_signal; 231 /** 232 * @min_input_signal: minimum possible input in range 0-255. 233 */ 234 int min_input_signal; 235 /** 236 * @max_input_signal: maximum possible input in range 0-255. 237 */ 238 int max_input_signal; 239 /** 240 * @caps_valid: true if these values are from the ACPI interface. 241 */ 242 bool caps_valid; 243 /** 244 * @aux_support: Describes if the display supports AUX backlight. 245 */ 246 bool aux_support; 247 /** 248 * @brightness_mask: After deriving brightness, OR it with this mask. 249 * Workaround for panels with issues with certain brightness values. 250 */ 251 u32 brightness_mask; 252 /** 253 * @ac_level: the default brightness if booted on AC 254 */ 255 u8 ac_level; 256 /** 257 * @dc_level: the default brightness if booted on DC 258 */ 259 u8 dc_level; 260 /** 261 * @data_points: the number of custom luminance data points 262 */ 263 u8 data_points; 264 /** 265 * @luminance_data: custom luminance data 266 */ 267 struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS]; 268 }; 269 270 /** 271 * struct dal_allocation - Tracks mapped FB memory for SMU communication 272 * @list: list of dal allocations 273 * @bo: GPU buffer object 274 * @cpu_ptr: CPU virtual address of the GPU buffer object 275 * @gpu_addr: GPU virtual address of the GPU buffer object 276 */ 277 struct dal_allocation { 278 struct list_head list; 279 struct amdgpu_bo *bo; 280 void *cpu_ptr; 281 u64 gpu_addr; 282 }; 283 284 /** 285 * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq 286 * offload work 287 */ 288 struct hpd_rx_irq_offload_work_queue { 289 /** 290 * @wq: workqueue structure to queue offload work. 291 */ 292 struct workqueue_struct *wq; 293 /** 294 * @offload_lock: To protect fields of offload work queue. 295 */ 296 spinlock_t offload_lock; 297 /** 298 * @is_handling_link_loss: Used to prevent inserting link loss event when 299 * we're handling link loss 300 */ 301 bool is_handling_link_loss; 302 /** 303 * @is_handling_mst_msg_rdy_event: Used to prevent inserting mst message 304 * ready event when we're already handling mst message ready event 305 */ 306 bool is_handling_mst_msg_rdy_event; 307 /** 308 * @aconnector: The aconnector that this work queue is attached to 309 */ 310 struct amdgpu_dm_connector *aconnector; 311 }; 312 313 /** 314 * struct hpd_rx_irq_offload_work - hpd_rx_irq offload work structure 315 */ 316 struct hpd_rx_irq_offload_work { 317 /** 318 * @work: offload work 319 */ 320 struct work_struct work; 321 /** 322 * @data: reference irq data which is used while handling offload work 323 */ 324 union hpd_irq_data data; 325 /** 326 * @offload_wq: offload work queue that this work is queued to 327 */ 328 struct hpd_rx_irq_offload_work_queue *offload_wq; 329 /** 330 * @adev: amdgpu_device pointer 331 */ 332 struct amdgpu_device *adev; 333 }; 334 335 /** 336 * struct amdgpu_display_manager - Central amdgpu display manager device 337 * 338 * @dc: Display Core control structure 339 * @adev: AMDGPU base driver structure 340 * @ddev: DRM base driver structure 341 * @display_indexes_num: Max number of display streams supported 342 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 343 * @backlight_dev: Backlight control device 344 * @backlight_link: Link on which to control backlight 345 * @backlight_caps: Capabilities of the backlight device 346 * @freesync_module: Module handling freesync calculations 347 * @hdcp_workqueue: AMDGPU content protection queue 348 * @fw_dmcu: Reference to DMCU firmware 349 * @dmcu_fw_version: Version of the DMCU firmware 350 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 351 * @cached_state: Caches device atomic state for suspend/resume 352 * @cached_dc_state: Cached state of content streams 353 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info 354 * @force_timing_sync: set via debugfs. When set, indicates that all connected 355 * displays will be forced to synchronize. 356 * @dmcub_trace_event_en: enable dmcub trace events 357 * @dmub_outbox_params: DMUB Outbox parameters 358 * @num_of_edps: number of backlight eDPs 359 * @disable_hpd_irq: disables all HPD and HPD RX interrupt handling in the 360 * driver when true 361 * @dmub_aux_transfer_done: struct completion used to indicate when DMUB 362 * transfers are done 363 * @delayed_hpd_wq: work queue used to delay DMUB HPD work 364 */ 365 struct amdgpu_display_manager { 366 367 struct dc *dc; 368 369 /** 370 * @dmub_srv: 371 * 372 * DMUB service, used for controlling the DMUB on hardware 373 * that supports it. The pointer to the dmub_srv will be 374 * NULL on hardware that does not support it. 375 */ 376 struct dmub_srv *dmub_srv; 377 378 /** 379 * @dmub_notify: 380 * 381 * Notification from DMUB. 382 */ 383 384 struct dmub_notification *dmub_notify; 385 386 /** 387 * @dmub_callback: 388 * 389 * Callback functions to handle notification from DMUB. 390 */ 391 392 dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX]; 393 394 /** 395 * @dmub_thread_offload: 396 * 397 * Flag to indicate if callback is offload. 398 */ 399 400 bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX]; 401 402 /** 403 * @dmub_fb_info: 404 * 405 * Framebuffer regions for the DMUB. 406 */ 407 struct dmub_srv_fb_info *dmub_fb_info; 408 409 /** 410 * @dmub_fw: 411 * 412 * DMUB firmware, required on hardware that has DMUB support. 413 */ 414 const struct firmware *dmub_fw; 415 416 /** 417 * @dmub_bo: 418 * 419 * Buffer object for the DMUB. 420 */ 421 struct amdgpu_bo *dmub_bo; 422 423 /** 424 * @dmub_bo_gpu_addr: 425 * 426 * GPU virtual address for the DMUB buffer object. 427 */ 428 u64 dmub_bo_gpu_addr; 429 430 /** 431 * @dmub_bo_cpu_addr: 432 * 433 * CPU address for the DMUB buffer object. 434 */ 435 void *dmub_bo_cpu_addr; 436 437 /** 438 * @dmcub_fw_version: 439 * 440 * DMCUB firmware version. 441 */ 442 uint32_t dmcub_fw_version; 443 444 /** 445 * @fw_inst_size: 446 * 447 * Size of the firmware instruction buffer. 448 */ 449 uint32_t fw_inst_size; 450 451 /** 452 * @cgs_device: 453 * 454 * The Common Graphics Services device. It provides an interface for 455 * accessing registers. 456 */ 457 struct cgs_device *cgs_device; 458 459 struct amdgpu_device *adev; 460 struct drm_device *ddev; 461 u16 display_indexes_num; 462 463 /** 464 * @atomic_obj: 465 * 466 * In combination with &dm_atomic_state it helps manage 467 * global atomic state that doesn't map cleanly into existing 468 * drm resources, like &dc_context. 469 */ 470 struct drm_private_obj atomic_obj; 471 472 /** 473 * @dc_lock: 474 * 475 * Guards access to DC functions that can issue register write 476 * sequences. 477 */ 478 struct mutex dc_lock; 479 480 /** 481 * @audio_lock: 482 * 483 * Guards access to audio instance changes. 484 */ 485 struct mutex audio_lock; 486 487 /** 488 * @audio_component: 489 * 490 * Used to notify ELD changes to sound driver. 491 */ 492 struct drm_audio_component *audio_component; 493 494 /** 495 * @audio_registered: 496 * 497 * True if the audio component has been registered 498 * successfully, false otherwise. 499 */ 500 bool audio_registered; 501 502 /** 503 * @irq_handler_list_low_tab: 504 * 505 * Low priority IRQ handler table. 506 * 507 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 508 * source. Low priority IRQ handlers are deferred to a workqueue to be 509 * processed. Hence, they can sleep. 510 * 511 * Note that handlers are called in the same order as they were 512 * registered (FIFO). 513 */ 514 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 515 516 /** 517 * @irq_handler_list_high_tab: 518 * 519 * High priority IRQ handler table. 520 * 521 * It is a n*m table, same as &irq_handler_list_low_tab. However, 522 * handlers in this table are not deferred and are called immediately. 523 */ 524 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 525 526 /** 527 * @pflip_params: 528 * 529 * Page flip IRQ parameters, passed to registered handlers when 530 * triggered. 531 */ 532 struct common_irq_params 533 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 534 535 /** 536 * @vblank_params: 537 * 538 * Vertical blanking IRQ parameters, passed to registered handlers when 539 * triggered. 540 */ 541 struct common_irq_params 542 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 543 544 /** 545 * @vline0_params: 546 * 547 * OTG vertical interrupt0 IRQ parameters, passed to registered 548 * handlers when triggered. 549 */ 550 struct common_irq_params 551 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; 552 553 /** 554 * @vupdate_params: 555 * 556 * Vertical update IRQ parameters, passed to registered handlers when 557 * triggered. 558 */ 559 struct common_irq_params 560 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 561 562 /** 563 * @dmub_trace_params: 564 * 565 * DMUB trace event IRQ parameters, passed to registered handlers when 566 * triggered. 567 */ 568 struct common_irq_params 569 dmub_trace_params[1]; 570 571 struct common_irq_params 572 dmub_outbox_params[1]; 573 574 spinlock_t irq_handler_list_table_lock; 575 576 struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; 577 578 const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; 579 580 uint8_t num_of_edps; 581 582 struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; 583 584 struct mod_freesync *freesync_module; 585 struct hdcp_workqueue *hdcp_workqueue; 586 587 /** 588 * @vblank_control_workqueue: 589 * 590 * Deferred work for vblank control events. 591 */ 592 struct workqueue_struct *vblank_control_workqueue; 593 594 /** 595 * @idle_workqueue: 596 * 597 * Periodic work for idle events. 598 */ 599 struct idle_workqueue *idle_workqueue; 600 601 struct drm_atomic_state *cached_state; 602 struct dc_state *cached_dc_state; 603 604 struct dm_compressor_info compressor; 605 606 const struct firmware *fw_dmcu; 607 uint32_t dmcu_fw_version; 608 /** 609 * @soc_bounding_box: 610 * 611 * gpu_info FW provided soc bounding box struct or 0 if not 612 * available in FW 613 */ 614 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 615 616 /** 617 * @active_vblank_irq_count: 618 * 619 * number of currently active vblank irqs 620 */ 621 uint32_t active_vblank_irq_count; 622 623 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 624 /** 625 * @secure_display_ctx: 626 * 627 * Store secure display relevant info. e.g. the ROI information 628 * , the work_struct to command dmub, etc. 629 */ 630 struct secure_display_context secure_display_ctx; 631 #endif 632 /** 633 * @hpd_rx_offload_wq: 634 * 635 * Work queue to offload works of hpd_rx_irq 636 */ 637 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq; 638 /** 639 * @mst_encoders: 640 * 641 * fake encoders used for DP MST. 642 */ 643 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; 644 bool force_timing_sync; 645 bool disable_hpd_irq; 646 bool dmcub_trace_event_en; 647 /** 648 * @da_list: 649 * 650 * DAL fb memory allocation list, for communication with SMU. 651 */ 652 struct list_head da_list; 653 struct completion dmub_aux_transfer_done; 654 struct workqueue_struct *delayed_hpd_wq; 655 656 /** 657 * @brightness: 658 * 659 * cached backlight values. 660 */ 661 u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; 662 /** 663 * @actual_brightness: 664 * 665 * last successfully applied backlight values. 666 */ 667 u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; 668 669 /** 670 * @aux_hpd_discon_quirk: 671 * 672 * quirk for hpd discon while aux is on-going. 673 * occurred on certain intel platform 674 */ 675 bool aux_hpd_discon_quirk; 676 677 /** 678 * @edp0_on_dp1_quirk: 679 * 680 * quirk for platforms that put edp0 on DP1. 681 */ 682 bool edp0_on_dp1_quirk; 683 684 /** 685 * @dpia_aux_lock: 686 * 687 * Guards access to DPIA AUX 688 */ 689 struct mutex dpia_aux_lock; 690 691 /** 692 * @bb_from_dmub: 693 * 694 * Bounding box data read from dmub during early initialization for DCN4+ 695 * Data is stored as a byte array that should be casted to the appropriate bb struct 696 */ 697 void *bb_from_dmub; 698 699 /** 700 * @oem_i2c: 701 * 702 * OEM i2c bus 703 */ 704 struct amdgpu_i2c_adapter *oem_i2c; 705 706 /** 707 * @fused_io: 708 * 709 * dmub fused io interface 710 */ 711 struct fused_io_sync { 712 struct completion replied; 713 char reply_data[0x40]; // Cannot include dmub_cmd here 714 } fused_io[8]; 715 716 /** 717 * @dm_boot_time_crc_info: 718 * 719 * Buffer info for the boot time crc. 720 */ 721 struct dm_boot_time_crc_info boot_time_crc_info; 722 }; 723 724 enum dsc_clock_force_state { 725 DSC_CLK_FORCE_DEFAULT = 0, 726 DSC_CLK_FORCE_ENABLE, 727 DSC_CLK_FORCE_DISABLE, 728 }; 729 730 struct dsc_preferred_settings { 731 enum dsc_clock_force_state dsc_force_enable; 732 uint32_t dsc_num_slices_v; 733 uint32_t dsc_num_slices_h; 734 uint32_t dsc_bits_per_pixel; 735 bool dsc_force_disable_passthrough; 736 }; 737 738 enum mst_progress_status { 739 MST_STATUS_DEFAULT = 0, 740 MST_PROBE = BIT(0), 741 MST_REMOTE_EDID = BIT(1), 742 MST_ALLOCATE_NEW_PAYLOAD = BIT(2), 743 MST_CLEAR_ALLOCATED_PAYLOAD = BIT(3), 744 }; 745 746 /** 747 * struct amdgpu_hdmi_vsdb_info - Keep track of the VSDB info 748 * 749 * AMDGPU supports FreeSync over HDMI by using the VSDB section, and this 750 * struct is useful to keep track of the display-specific information about 751 * FreeSync. 752 */ 753 struct amdgpu_hdmi_vsdb_info { 754 /** 755 * @amd_vsdb_version: Vendor Specific Data Block Version, should be 756 * used to determine which Vendor Specific InfoFrame (VSIF) to send. 757 */ 758 unsigned int amd_vsdb_version; 759 760 /** 761 * @freesync_supported: FreeSync Supported. 762 */ 763 bool freesync_supported; 764 765 /** 766 * @min_refresh_rate_hz: FreeSync Minimum Refresh Rate in Hz. 767 */ 768 unsigned int min_refresh_rate_hz; 769 770 /** 771 * @max_refresh_rate_hz: FreeSync Maximum Refresh Rate in Hz 772 */ 773 unsigned int max_refresh_rate_hz; 774 775 /** 776 * @replay_mode: Replay supported 777 */ 778 bool replay_mode; 779 }; 780 781 struct amdgpu_dm_connector { 782 783 struct drm_connector base; 784 uint32_t connector_id; 785 int bl_idx; 786 787 struct cec_notifier *notifier; 788 789 /* we need to mind the EDID between detect 790 and get modes due to analog/digital/tvencoder */ 791 const struct drm_edid *drm_edid; 792 793 /* shared with amdgpu */ 794 struct amdgpu_hpd hpd; 795 796 /* number of modes generated from EDID at 'dc_sink' */ 797 int num_modes; 798 799 /* The 'old' sink - before an HPD. 800 * The 'current' sink is in dc_link->sink. */ 801 struct dc_sink *dc_sink; 802 struct dc_link *dc_link; 803 804 /** 805 * @dc_em_sink: Reference to the emulated (virtual) sink. 806 */ 807 struct dc_sink *dc_em_sink; 808 809 /* DM only */ 810 struct drm_dp_mst_topology_mgr mst_mgr; 811 struct amdgpu_dm_dp_aux dm_dp_aux; 812 struct drm_dp_mst_port *mst_output_port; 813 struct amdgpu_dm_connector *mst_root; 814 struct drm_dp_aux *dsc_aux; 815 uint32_t mst_local_bw; 816 uint16_t vc_full_pbn; 817 struct mutex handle_mst_msg_ready; 818 819 /* branch device specific data */ 820 uint32_t branch_ieee_oui; 821 822 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 823 struct amdgpu_i2c_adapter *i2c; 824 825 /* Monitor range limits */ 826 /** 827 * @min_vfreq: Minimal frequency supported by the display in Hz. This 828 * value is set to zero when there is no FreeSync support. 829 */ 830 int min_vfreq; 831 832 /** 833 * @max_vfreq: Maximum frequency supported by the display in Hz. This 834 * value is set to zero when there is no FreeSync support. 835 */ 836 int max_vfreq ; 837 838 /* Audio instance - protected by audio_lock. */ 839 int audio_inst; 840 841 struct mutex hpd_lock; 842 843 bool fake_enable; 844 bool force_yuv420_output; 845 bool force_yuv422_output; 846 struct dsc_preferred_settings dsc_settings; 847 union dp_downstream_port_present mst_downstream_port_present; 848 /* Cached display modes */ 849 struct drm_display_mode freesync_vid_base; 850 851 int sr_skip_count; 852 bool disallow_edp_enter_psr; 853 bool disallow_edp_enter_replay; 854 855 /* Record progress status of mst*/ 856 uint8_t mst_status; 857 858 /* Automated testing */ 859 bool timing_changed; 860 struct dc_crtc_timing *timing_requested; 861 862 /* Adaptive Sync */ 863 bool pack_sdp_v1_3; 864 enum adaptive_sync_type as_type; 865 struct amdgpu_hdmi_vsdb_info vsdb_info; 866 867 /* HDMI HPD debounce support */ 868 unsigned int hdmi_hpd_debounce_delay_ms; 869 struct delayed_work hdmi_hpd_debounce_work; 870 struct dc_sink *hdmi_prev_sink; 871 }; 872 873 static inline void amdgpu_dm_set_mst_status(uint8_t *status, 874 uint8_t flags, bool set) 875 { 876 if (set) 877 *status |= flags; 878 else 879 *status &= ~flags; 880 } 881 882 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 883 884 struct amdgpu_dm_wb_connector { 885 struct drm_writeback_connector base; 886 struct dc_link *link; 887 }; 888 889 #define to_amdgpu_dm_wb_connector(x) container_of(x, struct amdgpu_dm_wb_connector, base) 890 891 extern const struct amdgpu_ip_block_version dm_ip_block; 892 893 /* enum amdgpu_transfer_function: pre-defined transfer function supported by AMD. 894 * 895 * It includes standardized transfer functions and pure power functions. The 896 * transfer function coefficients are available at modules/color/color_gamma.c 897 */ 898 enum amdgpu_transfer_function { 899 AMDGPU_TRANSFER_FUNCTION_DEFAULT, 900 AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF, 901 AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF, 902 AMDGPU_TRANSFER_FUNCTION_PQ_EOTF, 903 AMDGPU_TRANSFER_FUNCTION_IDENTITY, 904 AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF, 905 AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF, 906 AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF, 907 AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF, 908 AMDGPU_TRANSFER_FUNCTION_BT709_OETF, 909 AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF, 910 AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF, 911 AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF, 912 AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF, 913 AMDGPU_TRANSFER_FUNCTION_COUNT 914 }; 915 916 struct dm_plane_state { 917 struct drm_plane_state base; 918 struct dc_plane_state *dc_state; 919 920 /* Plane color mgmt */ 921 /** 922 * @degamma_lut: 923 * 924 * 1D LUT for mapping framebuffer/plane pixel data before sampling or 925 * blending operations. It's usually applied to linearize input space. 926 * The blob (if not NULL) is an array of &struct drm_color_lut. 927 */ 928 struct drm_property_blob *degamma_lut; 929 /** 930 * @degamma_tf: 931 * 932 * Predefined transfer function to tell DC driver the input space to 933 * linearize. 934 */ 935 enum amdgpu_transfer_function degamma_tf; 936 /** 937 * @hdr_mult: 938 * 939 * Multiplier to 'gain' the plane. When PQ is decoded using the fixed 940 * func transfer function to the internal FP16 fb, 1.0 -> 80 nits (on 941 * AMD at least). When sRGB is decoded, 1.0 -> 1.0, obviously. 942 * Therefore, 1.0 multiplier = 80 nits for SDR content. So if you 943 * want, 203 nits for SDR content, pass in (203.0 / 80.0). Format is 944 * S31.32 sign-magnitude. 945 * 946 * HDR multiplier can wide range beyond [0.0, 1.0]. This means that PQ 947 * TF is needed for any subsequent linear-to-non-linear transforms. 948 */ 949 __u64 hdr_mult; 950 /** 951 * @ctm: 952 * 953 * Color transformation matrix. The blob (if not NULL) is a &struct 954 * drm_color_ctm_3x4. 955 */ 956 struct drm_property_blob *ctm; 957 /** 958 * @shaper_lut: shaper lookup table blob. The blob (if not NULL) is an 959 * array of &struct drm_color_lut. 960 */ 961 struct drm_property_blob *shaper_lut; 962 /** 963 * @shaper_tf: 964 * 965 * Predefined transfer function to delinearize color space. 966 */ 967 enum amdgpu_transfer_function shaper_tf; 968 /** 969 * @lut3d: 3D lookup table blob. The blob (if not NULL) is an array of 970 * &struct drm_color_lut. 971 */ 972 struct drm_property_blob *lut3d; 973 /** 974 * @blend_lut: blend lut lookup table blob. The blob (if not NULL) is an 975 * array of &struct drm_color_lut. 976 */ 977 struct drm_property_blob *blend_lut; 978 /** 979 * @blend_tf: 980 * 981 * Pre-defined transfer function for converting plane pixel data before 982 * applying blend LUT. 983 */ 984 enum amdgpu_transfer_function blend_tf; 985 }; 986 987 enum amdgpu_dm_cursor_mode { 988 DM_CURSOR_NATIVE_MODE = 0, 989 DM_CURSOR_OVERLAY_MODE, 990 }; 991 992 struct dm_crtc_state { 993 struct drm_crtc_state base; 994 struct dc_stream_state *stream; 995 996 bool cm_has_degamma; 997 bool cm_is_degamma_srgb; 998 999 bool mpo_requested; 1000 1001 int update_type; 1002 int active_planes; 1003 1004 int crc_skip_count; 1005 1006 bool freesync_vrr_info_changed; 1007 1008 bool mode_changed_independent_from_dsc; 1009 bool dsc_force_changed; 1010 bool vrr_supported; 1011 struct mod_freesync_config freesync_config; 1012 struct dc_info_packet vrr_infopacket; 1013 1014 int abm_level; 1015 1016 /** 1017 * @regamma_tf: 1018 * 1019 * Pre-defined transfer function for converting internal FB -> wire 1020 * encoding. 1021 */ 1022 enum amdgpu_transfer_function regamma_tf; 1023 1024 enum amdgpu_dm_cursor_mode cursor_mode; 1025 }; 1026 1027 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 1028 1029 struct dm_atomic_state { 1030 struct drm_private_state base; 1031 1032 struct dc_state *context; 1033 }; 1034 1035 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 1036 1037 struct dm_connector_state { 1038 struct drm_connector_state base; 1039 1040 enum amdgpu_rmx_type scaling; 1041 uint8_t underscan_vborder; 1042 uint8_t underscan_hborder; 1043 bool underscan_enable; 1044 bool freesync_capable; 1045 bool update_hdcp; 1046 bool abm_sysfs_forbidden; 1047 uint8_t abm_level; 1048 int vcpi_slots; 1049 uint64_t pbn; 1050 }; 1051 1052 #define to_dm_connector_state(x)\ 1053 container_of((x), struct dm_connector_state, base) 1054 1055 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 1056 struct drm_connector_state * 1057 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 1058 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 1059 struct drm_connector_state *state, 1060 struct drm_property *property, 1061 uint64_t val); 1062 1063 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 1064 const struct drm_connector_state *state, 1065 struct drm_property *property, 1066 uint64_t *val); 1067 1068 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 1069 1070 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 1071 struct amdgpu_dm_connector *aconnector, 1072 int connector_type, 1073 struct dc_link *link, 1074 int link_index); 1075 1076 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 1077 const struct drm_display_mode *mode); 1078 1079 void dm_restore_drm_connector_state(struct drm_device *dev, 1080 struct drm_connector *connector); 1081 1082 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 1083 const struct drm_edid *drm_edid); 1084 1085 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); 1086 1087 /* 3D LUT max size is 17x17x17 (4913 entries) */ 1088 #define MAX_COLOR_3DLUT_SIZE 17 1089 #define MAX_COLOR_3DLUT_BITDEPTH 12 1090 int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev, 1091 struct drm_plane_state *plane_state); 1092 /* 1D LUT size */ 1093 #define MAX_COLOR_LUT_ENTRIES 4096 1094 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 1095 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 1096 1097 void amdgpu_dm_init_color_mod(void); 1098 int amdgpu_dm_create_color_properties(struct amdgpu_device *adev); 1099 int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); 1100 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 1101 int amdgpu_dm_check_crtc_color_mgmt(struct dm_crtc_state *crtc, 1102 bool check_only); 1103 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 1104 struct drm_plane_state *plane_state, 1105 struct dc_plane_state *dc_plane_state); 1106 1107 void amdgpu_dm_update_connector_after_detect( 1108 struct amdgpu_dm_connector *aconnector); 1109 1110 void populate_hdmi_info_from_connector(struct drm_hdmi_info *info, 1111 struct dc_edid_caps *edid_caps); 1112 1113 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 1114 1115 int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int link_index, 1116 struct aux_payload *payload, enum aux_return_code_type *operation_result); 1117 1118 bool amdgpu_dm_execute_fused_io( 1119 struct amdgpu_device *dev, 1120 struct dc_link *link, 1121 union dmub_rb_cmd *commands, 1122 uint8_t count, 1123 uint32_t timeout_us 1124 ); 1125 1126 int amdgpu_dm_process_dmub_set_config_sync(struct dc_context *ctx, unsigned int link_index, 1127 struct set_config_cmd_payload *payload, enum set_config_status *operation_result); 1128 1129 struct dc_stream_state * 1130 create_validate_stream_for_sink(struct drm_connector *connector, 1131 const struct drm_display_mode *drm_mode, 1132 const struct dm_connector_state *dm_state, 1133 const struct dc_stream_state *old_stream); 1134 1135 int dm_atomic_get_state(struct drm_atomic_state *state, 1136 struct dm_atomic_state **dm_state); 1137 1138 struct drm_connector * 1139 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 1140 struct drm_crtc *crtc); 1141 1142 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth); 1143 struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev); 1144 1145 void *dm_allocate_gpu_mem(struct amdgpu_device *adev, 1146 enum dc_gpu_mem_alloc_type type, 1147 size_t size, 1148 long long *addr); 1149 void dm_free_gpu_mem(struct amdgpu_device *adev, 1150 enum dc_gpu_mem_alloc_type type, 1151 void *addr); 1152 1153 bool amdgpu_dm_is_headless(struct amdgpu_device *adev); 1154 1155 void hdmi_cec_set_edid(struct amdgpu_dm_connector *aconnector); 1156 void hdmi_cec_unset_edid(struct amdgpu_dm_connector *aconnector); 1157 int amdgpu_dm_initialize_hdmi_connector(struct amdgpu_dm_connector *aconnector); 1158 1159 void retrieve_dmi_info(struct amdgpu_display_manager *dm); 1160 1161 #endif /* __AMDGPU_DM_H__ */ 1162