1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * rt5665.c -- RT5665/RT5658 ALSA SoC audio codec driver 4 * 5 * Copyright 2016 Realtek Semiconductor Corp. 6 * Author: Bard Liao <bardliao@realtek.com> 7 */ 8 9 #include <linux/cleanup.h> 10 #include <linux/module.h> 11 #include <linux/moduleparam.h> 12 #include <linux/init.h> 13 #include <linux/delay.h> 14 #include <linux/pm.h> 15 #include <linux/i2c.h> 16 #include <linux/platform_device.h> 17 #include <linux/spi/spi.h> 18 #include <linux/acpi.h> 19 #include <linux/gpio/consumer.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/mutex.h> 22 #include <sound/core.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/jack.h> 26 #include <sound/soc.h> 27 #include <sound/soc-dapm.h> 28 #include <sound/initval.h> 29 #include <sound/tlv.h> 30 #include <sound/rt5665.h> 31 32 #include "rl6231.h" 33 #include "rt5665.h" 34 35 static const char * const rt5665_supply_names[] = { 36 "AVDD", 37 "MICVDD", 38 "VBAT", 39 }; 40 41 struct rt5665_priv { 42 struct snd_soc_component *component; 43 struct rt5665_platform_data pdata; 44 struct regmap *regmap; 45 struct gpio_desc *gpiod_ldo1_en; 46 struct gpio_desc *gpiod_reset; 47 struct snd_soc_jack *hs_jack; 48 struct delayed_work jack_detect_work; 49 struct delayed_work calibrate_work; 50 struct delayed_work jd_check_work; 51 struct mutex calibrate_mutex; 52 53 int sysclk; 54 int sysclk_src; 55 int lrck[RT5665_AIFS]; 56 int bclk[RT5665_AIFS]; 57 int master[RT5665_AIFS]; 58 int id; 59 60 int pll_src; 61 int pll_in; 62 int pll_out; 63 64 int jack_type; 65 int irq_work_delay_time; 66 unsigned int sar_adc_value; 67 bool calibration_done; 68 }; 69 70 static const struct reg_default rt5665_reg[] = { 71 {0x0000, 0x0000}, 72 {0x0001, 0xc8c8}, 73 {0x0002, 0x8080}, 74 {0x0003, 0x8000}, 75 {0x0004, 0xc80a}, 76 {0x0005, 0x0000}, 77 {0x0006, 0x0000}, 78 {0x0007, 0x0000}, 79 {0x000a, 0x0000}, 80 {0x000b, 0x0000}, 81 {0x000c, 0x0000}, 82 {0x000d, 0x0000}, 83 {0x000f, 0x0808}, 84 {0x0010, 0x4040}, 85 {0x0011, 0x0000}, 86 {0x0012, 0x1404}, 87 {0x0013, 0x1000}, 88 {0x0014, 0xa00a}, 89 {0x0015, 0x0404}, 90 {0x0016, 0x0404}, 91 {0x0017, 0x0011}, 92 {0x0018, 0xafaf}, 93 {0x0019, 0xafaf}, 94 {0x001a, 0xafaf}, 95 {0x001b, 0x0011}, 96 {0x001c, 0x2f2f}, 97 {0x001d, 0x2f2f}, 98 {0x001e, 0x2f2f}, 99 {0x001f, 0x0000}, 100 {0x0020, 0x0000}, 101 {0x0021, 0x0000}, 102 {0x0022, 0x5757}, 103 {0x0023, 0x0039}, 104 {0x0026, 0xc0c0}, 105 {0x0027, 0xc0c0}, 106 {0x0028, 0xc0c0}, 107 {0x0029, 0x8080}, 108 {0x002a, 0xaaaa}, 109 {0x002b, 0xaaaa}, 110 {0x002c, 0xaba8}, 111 {0x002d, 0x0000}, 112 {0x002e, 0x0000}, 113 {0x002f, 0x0000}, 114 {0x0030, 0x0000}, 115 {0x0031, 0x5000}, 116 {0x0032, 0x0000}, 117 {0x0033, 0x0000}, 118 {0x0034, 0x0000}, 119 {0x0035, 0x0000}, 120 {0x003a, 0x0000}, 121 {0x003b, 0x0000}, 122 {0x003c, 0x00ff}, 123 {0x003d, 0x0000}, 124 {0x003e, 0x00ff}, 125 {0x003f, 0x0000}, 126 {0x0040, 0x0000}, 127 {0x0041, 0x00ff}, 128 {0x0042, 0x0000}, 129 {0x0043, 0x00ff}, 130 {0x0044, 0x0c0c}, 131 {0x0049, 0xc00b}, 132 {0x004a, 0x0000}, 133 {0x004b, 0x031f}, 134 {0x004d, 0x0000}, 135 {0x004e, 0x001f}, 136 {0x004f, 0x0000}, 137 {0x0050, 0x001f}, 138 {0x0052, 0xf000}, 139 {0x0061, 0x0000}, 140 {0x0062, 0x0000}, 141 {0x0063, 0x003e}, 142 {0x0064, 0x0000}, 143 {0x0065, 0x0000}, 144 {0x0066, 0x003f}, 145 {0x0067, 0x0000}, 146 {0x006b, 0x0000}, 147 {0x006d, 0xff00}, 148 {0x006e, 0x2808}, 149 {0x006f, 0x000a}, 150 {0x0070, 0x8000}, 151 {0x0071, 0x8000}, 152 {0x0072, 0x8000}, 153 {0x0073, 0x7000}, 154 {0x0074, 0x7770}, 155 {0x0075, 0x0002}, 156 {0x0076, 0x0001}, 157 {0x0078, 0x00f0}, 158 {0x0079, 0x0000}, 159 {0x007a, 0x0000}, 160 {0x007b, 0x0000}, 161 {0x007c, 0x0000}, 162 {0x007d, 0x0123}, 163 {0x007e, 0x4500}, 164 {0x007f, 0x8003}, 165 {0x0080, 0x0000}, 166 {0x0081, 0x0000}, 167 {0x0082, 0x0000}, 168 {0x0083, 0x0000}, 169 {0x0084, 0x0000}, 170 {0x0085, 0x0000}, 171 {0x0086, 0x0008}, 172 {0x0087, 0x0000}, 173 {0x0088, 0x0000}, 174 {0x0089, 0x0000}, 175 {0x008a, 0x0000}, 176 {0x008b, 0x0000}, 177 {0x008c, 0x0003}, 178 {0x008e, 0x0060}, 179 {0x008f, 0x1000}, 180 {0x0091, 0x0c26}, 181 {0x0092, 0x0073}, 182 {0x0093, 0x0000}, 183 {0x0094, 0x0080}, 184 {0x0098, 0x0000}, 185 {0x0099, 0x0000}, 186 {0x009a, 0x0007}, 187 {0x009f, 0x0000}, 188 {0x00a0, 0x0000}, 189 {0x00a1, 0x0002}, 190 {0x00a2, 0x0001}, 191 {0x00a3, 0x0002}, 192 {0x00a4, 0x0001}, 193 {0x00ae, 0x2040}, 194 {0x00af, 0x0000}, 195 {0x00b6, 0x0000}, 196 {0x00b7, 0x0000}, 197 {0x00b8, 0x0000}, 198 {0x00b9, 0x0000}, 199 {0x00ba, 0x0002}, 200 {0x00bb, 0x0000}, 201 {0x00be, 0x0000}, 202 {0x00c0, 0x0000}, 203 {0x00c1, 0x0aaa}, 204 {0x00c2, 0xaa80}, 205 {0x00c3, 0x0003}, 206 {0x00c4, 0x0000}, 207 {0x00d0, 0x0000}, 208 {0x00d1, 0x2244}, 209 {0x00d3, 0x3300}, 210 {0x00d4, 0x2200}, 211 {0x00d9, 0x0809}, 212 {0x00da, 0x0000}, 213 {0x00db, 0x0008}, 214 {0x00dc, 0x00c0}, 215 {0x00dd, 0x6724}, 216 {0x00de, 0x3131}, 217 {0x00df, 0x0008}, 218 {0x00e0, 0x4000}, 219 {0x00e1, 0x3131}, 220 {0x00e2, 0x600c}, 221 {0x00ea, 0xb320}, 222 {0x00eb, 0x0000}, 223 {0x00ec, 0xb300}, 224 {0x00ed, 0x0000}, 225 {0x00ee, 0xb320}, 226 {0x00ef, 0x0000}, 227 {0x00f0, 0x0201}, 228 {0x00f1, 0x0ddd}, 229 {0x00f2, 0x0ddd}, 230 {0x00f6, 0x0000}, 231 {0x00f7, 0x0000}, 232 {0x00f8, 0x0000}, 233 {0x00fa, 0x0000}, 234 {0x00fb, 0x0000}, 235 {0x00fc, 0x0000}, 236 {0x00fd, 0x0000}, 237 {0x00fe, 0x10ec}, 238 {0x00ff, 0x6451}, 239 {0x0100, 0xaaaa}, 240 {0x0101, 0x000a}, 241 {0x010a, 0xaaaa}, 242 {0x010b, 0xa0a0}, 243 {0x010c, 0xaeae}, 244 {0x010d, 0xaaaa}, 245 {0x010e, 0xaaaa}, 246 {0x010f, 0xaaaa}, 247 {0x0110, 0xe002}, 248 {0x0111, 0xa402}, 249 {0x0112, 0xaaaa}, 250 {0x0113, 0x2000}, 251 {0x0117, 0x0f00}, 252 {0x0125, 0x0410}, 253 {0x0132, 0x0000}, 254 {0x0133, 0x0000}, 255 {0x0137, 0x5540}, 256 {0x0138, 0x3700}, 257 {0x0139, 0x79a1}, 258 {0x013a, 0x2020}, 259 {0x013b, 0x2020}, 260 {0x013c, 0x2005}, 261 {0x013f, 0x0000}, 262 {0x0145, 0x0002}, 263 {0x0146, 0x0000}, 264 {0x0147, 0x0000}, 265 {0x0148, 0x0000}, 266 {0x0150, 0x0000}, 267 {0x0160, 0x4eff}, 268 {0x0161, 0x0080}, 269 {0x0162, 0x0200}, 270 {0x0163, 0x0800}, 271 {0x0164, 0x0000}, 272 {0x0165, 0x0000}, 273 {0x0166, 0x0000}, 274 {0x0167, 0x000f}, 275 {0x0170, 0x4e87}, 276 {0x0171, 0x0080}, 277 {0x0172, 0x0200}, 278 {0x0173, 0x0800}, 279 {0x0174, 0x00ff}, 280 {0x0175, 0x0000}, 281 {0x0190, 0x413d}, 282 {0x0191, 0x4139}, 283 {0x0192, 0x4135}, 284 {0x0193, 0x413d}, 285 {0x0194, 0x0000}, 286 {0x0195, 0x0000}, 287 {0x0196, 0x0000}, 288 {0x0197, 0x0000}, 289 {0x0198, 0x0000}, 290 {0x0199, 0x0000}, 291 {0x01a0, 0x1e64}, 292 {0x01a1, 0x06a3}, 293 {0x01a2, 0x0000}, 294 {0x01a3, 0x0000}, 295 {0x01a4, 0x0000}, 296 {0x01a5, 0x0000}, 297 {0x01a6, 0x0000}, 298 {0x01a7, 0x8000}, 299 {0x01a8, 0x0000}, 300 {0x01a9, 0x0000}, 301 {0x01aa, 0x0000}, 302 {0x01ab, 0x0000}, 303 {0x01b5, 0x0000}, 304 {0x01b6, 0x01c3}, 305 {0x01b7, 0x02a0}, 306 {0x01b8, 0x03e9}, 307 {0x01b9, 0x1389}, 308 {0x01ba, 0xc351}, 309 {0x01bb, 0x0009}, 310 {0x01bc, 0x0018}, 311 {0x01bd, 0x002a}, 312 {0x01be, 0x004c}, 313 {0x01bf, 0x0097}, 314 {0x01c0, 0x433d}, 315 {0x01c1, 0x0000}, 316 {0x01c2, 0x0000}, 317 {0x01c3, 0x0000}, 318 {0x01c4, 0x0000}, 319 {0x01c5, 0x0000}, 320 {0x01c6, 0x0000}, 321 {0x01c7, 0x0000}, 322 {0x01c8, 0x40af}, 323 {0x01c9, 0x0702}, 324 {0x01ca, 0x0000}, 325 {0x01cb, 0x0000}, 326 {0x01cc, 0x5757}, 327 {0x01cd, 0x5757}, 328 {0x01ce, 0x5757}, 329 {0x01cf, 0x5757}, 330 {0x01d0, 0x5757}, 331 {0x01d1, 0x5757}, 332 {0x01d2, 0x5757}, 333 {0x01d3, 0x5757}, 334 {0x01d4, 0x5757}, 335 {0x01d5, 0x5757}, 336 {0x01d6, 0x003c}, 337 {0x01da, 0x0000}, 338 {0x01db, 0x0000}, 339 {0x01dc, 0x0000}, 340 {0x01de, 0x7c00}, 341 {0x01df, 0x0320}, 342 {0x01e0, 0x06a1}, 343 {0x01e1, 0x0000}, 344 {0x01e2, 0x0000}, 345 {0x01e3, 0x0000}, 346 {0x01e4, 0x0000}, 347 {0x01e6, 0x0001}, 348 {0x01e7, 0x0000}, 349 {0x01e8, 0x0000}, 350 {0x01ea, 0xbf3f}, 351 {0x01eb, 0x0000}, 352 {0x01ec, 0x0000}, 353 {0x01ed, 0x0000}, 354 {0x01ee, 0x0000}, 355 {0x01ef, 0x0000}, 356 {0x01f0, 0x0000}, 357 {0x01f1, 0x0000}, 358 {0x01f2, 0x0000}, 359 {0x01f3, 0x0000}, 360 {0x01f4, 0x0000}, 361 {0x0200, 0x0000}, 362 {0x0201, 0x0000}, 363 {0x0202, 0x0000}, 364 {0x0203, 0x0000}, 365 {0x0204, 0x0000}, 366 {0x0205, 0x0000}, 367 {0x0206, 0x0000}, 368 {0x0207, 0x0000}, 369 {0x0208, 0x0000}, 370 {0x0210, 0x60b1}, 371 {0x0211, 0xa005}, 372 {0x0212, 0x024c}, 373 {0x0213, 0xf7ff}, 374 {0x0214, 0x024c}, 375 {0x0215, 0x0102}, 376 {0x0216, 0x00a3}, 377 {0x0217, 0x0048}, 378 {0x0218, 0xa2c0}, 379 {0x0219, 0x0400}, 380 {0x021a, 0x00c8}, 381 {0x021b, 0x00c0}, 382 {0x02ff, 0x0110}, 383 {0x0300, 0x001f}, 384 {0x0301, 0x032c}, 385 {0x0302, 0x5f21}, 386 {0x0303, 0x4000}, 387 {0x0304, 0x4000}, 388 {0x0305, 0x06d5}, 389 {0x0306, 0x8000}, 390 {0x0307, 0x0700}, 391 {0x0310, 0x4560}, 392 {0x0311, 0xa4a8}, 393 {0x0312, 0x7418}, 394 {0x0313, 0x0000}, 395 {0x0314, 0x0006}, 396 {0x0315, 0xffff}, 397 {0x0316, 0xc400}, 398 {0x0317, 0x0000}, 399 {0x0330, 0x00a6}, 400 {0x0331, 0x04c3}, 401 {0x0332, 0x27c8}, 402 {0x0333, 0xbf50}, 403 {0x0334, 0x0045}, 404 {0x0335, 0x0007}, 405 {0x0336, 0x7418}, 406 {0x0337, 0x0501}, 407 {0x0338, 0x0000}, 408 {0x0339, 0x0010}, 409 {0x033a, 0x1010}, 410 {0x03c0, 0x7e00}, 411 {0x03c1, 0x8000}, 412 {0x03c2, 0x8000}, 413 {0x03c3, 0x8000}, 414 {0x03c4, 0x8000}, 415 {0x03c5, 0x8000}, 416 {0x03c6, 0x8000}, 417 {0x03c7, 0x8000}, 418 {0x03c8, 0x8000}, 419 {0x03c9, 0x8000}, 420 {0x03ca, 0x8000}, 421 {0x03cb, 0x8000}, 422 {0x03cc, 0x8000}, 423 {0x03d0, 0x0000}, 424 {0x03d1, 0x0000}, 425 {0x03d2, 0x0000}, 426 {0x03d3, 0x0000}, 427 {0x03d4, 0x2000}, 428 {0x03d5, 0x2000}, 429 {0x03d6, 0x0000}, 430 {0x03d7, 0x0000}, 431 {0x03d8, 0x2000}, 432 {0x03d9, 0x2000}, 433 {0x03da, 0x2000}, 434 {0x03db, 0x2000}, 435 {0x03dc, 0x0000}, 436 {0x03dd, 0x0000}, 437 {0x03de, 0x0000}, 438 {0x03df, 0x2000}, 439 {0x03e0, 0x0000}, 440 {0x03e1, 0x0000}, 441 {0x03e2, 0x0000}, 442 {0x03e3, 0x0000}, 443 {0x03e4, 0x0000}, 444 {0x03e5, 0x0000}, 445 {0x03e6, 0x0000}, 446 {0x03e7, 0x0000}, 447 {0x03e8, 0x0000}, 448 {0x03e9, 0x0000}, 449 {0x03ea, 0x0000}, 450 {0x03eb, 0x0000}, 451 {0x03ec, 0x0000}, 452 {0x03ed, 0x0000}, 453 {0x03ee, 0x0000}, 454 {0x03ef, 0x0000}, 455 {0x03f0, 0x0800}, 456 {0x03f1, 0x0800}, 457 {0x03f2, 0x0800}, 458 {0x03f3, 0x0800}, 459 }; 460 461 static bool rt5665_volatile_register(struct device *dev, unsigned int reg) 462 { 463 switch (reg) { 464 case RT5665_RESET: 465 case RT5665_EJD_CTRL_2: 466 case RT5665_GPIO_STA: 467 case RT5665_INT_ST_1: 468 case RT5665_IL_CMD_1: 469 case RT5665_4BTN_IL_CMD_1: 470 case RT5665_PSV_IL_CMD_1: 471 case RT5665_AJD1_CTRL: 472 case RT5665_JD_CTRL_3: 473 case RT5665_STO_NG2_CTRL_1: 474 case RT5665_SAR_IL_CMD_4: 475 case RT5665_DEVICE_ID: 476 case RT5665_STO1_DAC_SIL_DET ... RT5665_STO2_DAC_SIL_DET: 477 case RT5665_MONO_AMP_CALIB_STA1 ... RT5665_MONO_AMP_CALIB_STA6: 478 case RT5665_HP_IMP_SENS_CTRL_12 ... RT5665_HP_IMP_SENS_CTRL_15: 479 case RT5665_HP_CALIB_STA_1 ... RT5665_HP_CALIB_STA_11: 480 return true; 481 default: 482 return false; 483 } 484 } 485 486 static bool rt5665_readable_register(struct device *dev, unsigned int reg) 487 { 488 switch (reg) { 489 case RT5665_RESET: 490 case RT5665_VENDOR_ID: 491 case RT5665_VENDOR_ID_1: 492 case RT5665_DEVICE_ID: 493 case RT5665_LOUT: 494 case RT5665_HP_CTRL_1: 495 case RT5665_HP_CTRL_2: 496 case RT5665_MONO_OUT: 497 case RT5665_HPL_GAIN: 498 case RT5665_HPR_GAIN: 499 case RT5665_MONO_GAIN: 500 case RT5665_CAL_BST_CTRL: 501 case RT5665_CBJ_BST_CTRL: 502 case RT5665_IN1_IN2: 503 case RT5665_IN3_IN4: 504 case RT5665_INL1_INR1_VOL: 505 case RT5665_EJD_CTRL_1: 506 case RT5665_EJD_CTRL_2: 507 case RT5665_EJD_CTRL_3: 508 case RT5665_EJD_CTRL_4: 509 case RT5665_EJD_CTRL_5: 510 case RT5665_EJD_CTRL_6: 511 case RT5665_EJD_CTRL_7: 512 case RT5665_DAC2_CTRL: 513 case RT5665_DAC2_DIG_VOL: 514 case RT5665_DAC1_DIG_VOL: 515 case RT5665_DAC3_DIG_VOL: 516 case RT5665_DAC3_CTRL: 517 case RT5665_STO1_ADC_DIG_VOL: 518 case RT5665_MONO_ADC_DIG_VOL: 519 case RT5665_STO2_ADC_DIG_VOL: 520 case RT5665_STO1_ADC_BOOST: 521 case RT5665_MONO_ADC_BOOST: 522 case RT5665_STO2_ADC_BOOST: 523 case RT5665_HP_IMP_GAIN_1: 524 case RT5665_HP_IMP_GAIN_2: 525 case RT5665_STO1_ADC_MIXER: 526 case RT5665_MONO_ADC_MIXER: 527 case RT5665_STO2_ADC_MIXER: 528 case RT5665_AD_DA_MIXER: 529 case RT5665_STO1_DAC_MIXER: 530 case RT5665_MONO_DAC_MIXER: 531 case RT5665_STO2_DAC_MIXER: 532 case RT5665_A_DAC1_MUX: 533 case RT5665_A_DAC2_MUX: 534 case RT5665_DIG_INF2_DATA: 535 case RT5665_DIG_INF3_DATA: 536 case RT5665_PDM_OUT_CTRL: 537 case RT5665_PDM_DATA_CTRL_1: 538 case RT5665_PDM_DATA_CTRL_2: 539 case RT5665_PDM_DATA_CTRL_3: 540 case RT5665_PDM_DATA_CTRL_4: 541 case RT5665_REC1_GAIN: 542 case RT5665_REC1_L1_MIXER: 543 case RT5665_REC1_L2_MIXER: 544 case RT5665_REC1_R1_MIXER: 545 case RT5665_REC1_R2_MIXER: 546 case RT5665_REC2_GAIN: 547 case RT5665_REC2_L1_MIXER: 548 case RT5665_REC2_L2_MIXER: 549 case RT5665_REC2_R1_MIXER: 550 case RT5665_REC2_R2_MIXER: 551 case RT5665_CAL_REC: 552 case RT5665_ALC_BACK_GAIN: 553 case RT5665_MONOMIX_GAIN: 554 case RT5665_MONOMIX_IN_GAIN: 555 case RT5665_OUT_L_GAIN: 556 case RT5665_OUT_L_MIXER: 557 case RT5665_OUT_R_GAIN: 558 case RT5665_OUT_R_MIXER: 559 case RT5665_LOUT_MIXER: 560 case RT5665_PWR_DIG_1: 561 case RT5665_PWR_DIG_2: 562 case RT5665_PWR_ANLG_1: 563 case RT5665_PWR_ANLG_2: 564 case RT5665_PWR_ANLG_3: 565 case RT5665_PWR_MIXER: 566 case RT5665_PWR_VOL: 567 case RT5665_CLK_DET: 568 case RT5665_HPF_CTRL1: 569 case RT5665_DMIC_CTRL_1: 570 case RT5665_DMIC_CTRL_2: 571 case RT5665_I2S1_SDP: 572 case RT5665_I2S2_SDP: 573 case RT5665_I2S3_SDP: 574 case RT5665_ADDA_CLK_1: 575 case RT5665_ADDA_CLK_2: 576 case RT5665_I2S1_F_DIV_CTRL_1: 577 case RT5665_I2S1_F_DIV_CTRL_2: 578 case RT5665_TDM_CTRL_1: 579 case RT5665_TDM_CTRL_2: 580 case RT5665_TDM_CTRL_3: 581 case RT5665_TDM_CTRL_4: 582 case RT5665_TDM_CTRL_5: 583 case RT5665_TDM_CTRL_6: 584 case RT5665_TDM_CTRL_7: 585 case RT5665_TDM_CTRL_8: 586 case RT5665_GLB_CLK: 587 case RT5665_PLL_CTRL_1: 588 case RT5665_PLL_CTRL_2: 589 case RT5665_ASRC_1: 590 case RT5665_ASRC_2: 591 case RT5665_ASRC_3: 592 case RT5665_ASRC_4: 593 case RT5665_ASRC_5: 594 case RT5665_ASRC_6: 595 case RT5665_ASRC_7: 596 case RT5665_ASRC_8: 597 case RT5665_ASRC_9: 598 case RT5665_ASRC_10: 599 case RT5665_DEPOP_1: 600 case RT5665_DEPOP_2: 601 case RT5665_HP_CHARGE_PUMP_1: 602 case RT5665_HP_CHARGE_PUMP_2: 603 case RT5665_MICBIAS_1: 604 case RT5665_MICBIAS_2: 605 case RT5665_ASRC_12: 606 case RT5665_ASRC_13: 607 case RT5665_ASRC_14: 608 case RT5665_RC_CLK_CTRL: 609 case RT5665_I2S_M_CLK_CTRL_1: 610 case RT5665_I2S2_F_DIV_CTRL_1: 611 case RT5665_I2S2_F_DIV_CTRL_2: 612 case RT5665_I2S3_F_DIV_CTRL_1: 613 case RT5665_I2S3_F_DIV_CTRL_2: 614 case RT5665_EQ_CTRL_1: 615 case RT5665_EQ_CTRL_2: 616 case RT5665_IRQ_CTRL_1: 617 case RT5665_IRQ_CTRL_2: 618 case RT5665_IRQ_CTRL_3: 619 case RT5665_IRQ_CTRL_4: 620 case RT5665_IRQ_CTRL_5: 621 case RT5665_IRQ_CTRL_6: 622 case RT5665_INT_ST_1: 623 case RT5665_GPIO_CTRL_1: 624 case RT5665_GPIO_CTRL_2: 625 case RT5665_GPIO_CTRL_3: 626 case RT5665_GPIO_CTRL_4: 627 case RT5665_GPIO_STA: 628 case RT5665_HP_AMP_DET_CTRL_1: 629 case RT5665_HP_AMP_DET_CTRL_2: 630 case RT5665_MID_HP_AMP_DET: 631 case RT5665_LOW_HP_AMP_DET: 632 case RT5665_SV_ZCD_1: 633 case RT5665_SV_ZCD_2: 634 case RT5665_IL_CMD_1: 635 case RT5665_IL_CMD_2: 636 case RT5665_IL_CMD_3: 637 case RT5665_IL_CMD_4: 638 case RT5665_4BTN_IL_CMD_1: 639 case RT5665_4BTN_IL_CMD_2: 640 case RT5665_4BTN_IL_CMD_3: 641 case RT5665_PSV_IL_CMD_1: 642 case RT5665_ADC_STO1_HP_CTRL_1: 643 case RT5665_ADC_STO1_HP_CTRL_2: 644 case RT5665_ADC_MONO_HP_CTRL_1: 645 case RT5665_ADC_MONO_HP_CTRL_2: 646 case RT5665_ADC_STO2_HP_CTRL_1: 647 case RT5665_ADC_STO2_HP_CTRL_2: 648 case RT5665_AJD1_CTRL: 649 case RT5665_JD1_THD: 650 case RT5665_JD2_THD: 651 case RT5665_JD_CTRL_1: 652 case RT5665_JD_CTRL_2: 653 case RT5665_JD_CTRL_3: 654 case RT5665_DIG_MISC: 655 case RT5665_DUMMY_2: 656 case RT5665_DUMMY_3: 657 case RT5665_DAC_ADC_DIG_VOL1: 658 case RT5665_DAC_ADC_DIG_VOL2: 659 case RT5665_BIAS_CUR_CTRL_1: 660 case RT5665_BIAS_CUR_CTRL_2: 661 case RT5665_BIAS_CUR_CTRL_3: 662 case RT5665_BIAS_CUR_CTRL_4: 663 case RT5665_BIAS_CUR_CTRL_5: 664 case RT5665_BIAS_CUR_CTRL_6: 665 case RT5665_BIAS_CUR_CTRL_7: 666 case RT5665_BIAS_CUR_CTRL_8: 667 case RT5665_BIAS_CUR_CTRL_9: 668 case RT5665_BIAS_CUR_CTRL_10: 669 case RT5665_VREF_REC_OP_FB_CAP_CTRL: 670 case RT5665_CHARGE_PUMP_1: 671 case RT5665_DIG_IN_CTRL_1: 672 case RT5665_DIG_IN_CTRL_2: 673 case RT5665_PAD_DRIVING_CTRL: 674 case RT5665_SOFT_RAMP_DEPOP: 675 case RT5665_PLL: 676 case RT5665_CHOP_DAC: 677 case RT5665_CHOP_ADC: 678 case RT5665_CALIB_ADC_CTRL: 679 case RT5665_VOL_TEST: 680 case RT5665_TEST_MODE_CTRL_1: 681 case RT5665_TEST_MODE_CTRL_2: 682 case RT5665_TEST_MODE_CTRL_3: 683 case RT5665_TEST_MODE_CTRL_4: 684 case RT5665_BASSBACK_CTRL: 685 case RT5665_STO_NG2_CTRL_1: 686 case RT5665_STO_NG2_CTRL_2: 687 case RT5665_STO_NG2_CTRL_3: 688 case RT5665_STO_NG2_CTRL_4: 689 case RT5665_STO_NG2_CTRL_5: 690 case RT5665_STO_NG2_CTRL_6: 691 case RT5665_STO_NG2_CTRL_7: 692 case RT5665_STO_NG2_CTRL_8: 693 case RT5665_MONO_NG2_CTRL_1: 694 case RT5665_MONO_NG2_CTRL_2: 695 case RT5665_MONO_NG2_CTRL_3: 696 case RT5665_MONO_NG2_CTRL_4: 697 case RT5665_MONO_NG2_CTRL_5: 698 case RT5665_MONO_NG2_CTRL_6: 699 case RT5665_STO1_DAC_SIL_DET: 700 case RT5665_MONOL_DAC_SIL_DET: 701 case RT5665_MONOR_DAC_SIL_DET: 702 case RT5665_STO2_DAC_SIL_DET: 703 case RT5665_SIL_PSV_CTRL1: 704 case RT5665_SIL_PSV_CTRL2: 705 case RT5665_SIL_PSV_CTRL3: 706 case RT5665_SIL_PSV_CTRL4: 707 case RT5665_SIL_PSV_CTRL5: 708 case RT5665_SIL_PSV_CTRL6: 709 case RT5665_MONO_AMP_CALIB_CTRL_1: 710 case RT5665_MONO_AMP_CALIB_CTRL_2: 711 case RT5665_MONO_AMP_CALIB_CTRL_3: 712 case RT5665_MONO_AMP_CALIB_CTRL_4: 713 case RT5665_MONO_AMP_CALIB_CTRL_5: 714 case RT5665_MONO_AMP_CALIB_CTRL_6: 715 case RT5665_MONO_AMP_CALIB_CTRL_7: 716 case RT5665_MONO_AMP_CALIB_STA1: 717 case RT5665_MONO_AMP_CALIB_STA2: 718 case RT5665_MONO_AMP_CALIB_STA3: 719 case RT5665_MONO_AMP_CALIB_STA4: 720 case RT5665_MONO_AMP_CALIB_STA6: 721 case RT5665_HP_IMP_SENS_CTRL_01: 722 case RT5665_HP_IMP_SENS_CTRL_02: 723 case RT5665_HP_IMP_SENS_CTRL_03: 724 case RT5665_HP_IMP_SENS_CTRL_04: 725 case RT5665_HP_IMP_SENS_CTRL_05: 726 case RT5665_HP_IMP_SENS_CTRL_06: 727 case RT5665_HP_IMP_SENS_CTRL_07: 728 case RT5665_HP_IMP_SENS_CTRL_08: 729 case RT5665_HP_IMP_SENS_CTRL_09: 730 case RT5665_HP_IMP_SENS_CTRL_10: 731 case RT5665_HP_IMP_SENS_CTRL_11: 732 case RT5665_HP_IMP_SENS_CTRL_12: 733 case RT5665_HP_IMP_SENS_CTRL_13: 734 case RT5665_HP_IMP_SENS_CTRL_14: 735 case RT5665_HP_IMP_SENS_CTRL_15: 736 case RT5665_HP_IMP_SENS_CTRL_16: 737 case RT5665_HP_IMP_SENS_CTRL_17: 738 case RT5665_HP_IMP_SENS_CTRL_18: 739 case RT5665_HP_IMP_SENS_CTRL_19: 740 case RT5665_HP_IMP_SENS_CTRL_20: 741 case RT5665_HP_IMP_SENS_CTRL_21: 742 case RT5665_HP_IMP_SENS_CTRL_22: 743 case RT5665_HP_IMP_SENS_CTRL_23: 744 case RT5665_HP_IMP_SENS_CTRL_24: 745 case RT5665_HP_IMP_SENS_CTRL_25: 746 case RT5665_HP_IMP_SENS_CTRL_26: 747 case RT5665_HP_IMP_SENS_CTRL_27: 748 case RT5665_HP_IMP_SENS_CTRL_28: 749 case RT5665_HP_IMP_SENS_CTRL_29: 750 case RT5665_HP_IMP_SENS_CTRL_30: 751 case RT5665_HP_IMP_SENS_CTRL_31: 752 case RT5665_HP_IMP_SENS_CTRL_32: 753 case RT5665_HP_IMP_SENS_CTRL_33: 754 case RT5665_HP_IMP_SENS_CTRL_34: 755 case RT5665_HP_LOGIC_CTRL_1: 756 case RT5665_HP_LOGIC_CTRL_2: 757 case RT5665_HP_LOGIC_CTRL_3: 758 case RT5665_HP_CALIB_CTRL_1: 759 case RT5665_HP_CALIB_CTRL_2: 760 case RT5665_HP_CALIB_CTRL_3: 761 case RT5665_HP_CALIB_CTRL_4: 762 case RT5665_HP_CALIB_CTRL_5: 763 case RT5665_HP_CALIB_CTRL_6: 764 case RT5665_HP_CALIB_CTRL_7: 765 case RT5665_HP_CALIB_CTRL_9: 766 case RT5665_HP_CALIB_CTRL_10: 767 case RT5665_HP_CALIB_CTRL_11: 768 case RT5665_HP_CALIB_STA_1: 769 case RT5665_HP_CALIB_STA_2: 770 case RT5665_HP_CALIB_STA_3: 771 case RT5665_HP_CALIB_STA_4: 772 case RT5665_HP_CALIB_STA_5: 773 case RT5665_HP_CALIB_STA_6: 774 case RT5665_HP_CALIB_STA_7: 775 case RT5665_HP_CALIB_STA_8: 776 case RT5665_HP_CALIB_STA_9: 777 case RT5665_HP_CALIB_STA_10: 778 case RT5665_HP_CALIB_STA_11: 779 case RT5665_PGM_TAB_CTRL1: 780 case RT5665_PGM_TAB_CTRL2: 781 case RT5665_PGM_TAB_CTRL3: 782 case RT5665_PGM_TAB_CTRL4: 783 case RT5665_PGM_TAB_CTRL5: 784 case RT5665_PGM_TAB_CTRL6: 785 case RT5665_PGM_TAB_CTRL7: 786 case RT5665_PGM_TAB_CTRL8: 787 case RT5665_PGM_TAB_CTRL9: 788 case RT5665_SAR_IL_CMD_1: 789 case RT5665_SAR_IL_CMD_2: 790 case RT5665_SAR_IL_CMD_3: 791 case RT5665_SAR_IL_CMD_4: 792 case RT5665_SAR_IL_CMD_5: 793 case RT5665_SAR_IL_CMD_6: 794 case RT5665_SAR_IL_CMD_7: 795 case RT5665_SAR_IL_CMD_8: 796 case RT5665_SAR_IL_CMD_9: 797 case RT5665_SAR_IL_CMD_10: 798 case RT5665_SAR_IL_CMD_11: 799 case RT5665_SAR_IL_CMD_12: 800 case RT5665_DRC1_CTRL_0: 801 case RT5665_DRC1_CTRL_1: 802 case RT5665_DRC1_CTRL_2: 803 case RT5665_DRC1_CTRL_3: 804 case RT5665_DRC1_CTRL_4: 805 case RT5665_DRC1_CTRL_5: 806 case RT5665_DRC1_CTRL_6: 807 case RT5665_DRC1_HARD_LMT_CTRL_1: 808 case RT5665_DRC1_HARD_LMT_CTRL_2: 809 case RT5665_DRC1_PRIV_1: 810 case RT5665_DRC1_PRIV_2: 811 case RT5665_DRC1_PRIV_3: 812 case RT5665_DRC1_PRIV_4: 813 case RT5665_DRC1_PRIV_5: 814 case RT5665_DRC1_PRIV_6: 815 case RT5665_DRC1_PRIV_7: 816 case RT5665_DRC1_PRIV_8: 817 case RT5665_ALC_PGA_CTRL_1: 818 case RT5665_ALC_PGA_CTRL_2: 819 case RT5665_ALC_PGA_CTRL_3: 820 case RT5665_ALC_PGA_CTRL_4: 821 case RT5665_ALC_PGA_CTRL_5: 822 case RT5665_ALC_PGA_CTRL_6: 823 case RT5665_ALC_PGA_CTRL_7: 824 case RT5665_ALC_PGA_CTRL_8: 825 case RT5665_ALC_PGA_STA_1: 826 case RT5665_ALC_PGA_STA_2: 827 case RT5665_ALC_PGA_STA_3: 828 case RT5665_EQ_AUTO_RCV_CTRL1: 829 case RT5665_EQ_AUTO_RCV_CTRL2: 830 case RT5665_EQ_AUTO_RCV_CTRL3: 831 case RT5665_EQ_AUTO_RCV_CTRL4: 832 case RT5665_EQ_AUTO_RCV_CTRL5: 833 case RT5665_EQ_AUTO_RCV_CTRL6: 834 case RT5665_EQ_AUTO_RCV_CTRL7: 835 case RT5665_EQ_AUTO_RCV_CTRL8: 836 case RT5665_EQ_AUTO_RCV_CTRL9: 837 case RT5665_EQ_AUTO_RCV_CTRL10: 838 case RT5665_EQ_AUTO_RCV_CTRL11: 839 case RT5665_EQ_AUTO_RCV_CTRL12: 840 case RT5665_EQ_AUTO_RCV_CTRL13: 841 case RT5665_ADC_L_EQ_LPF1_A1: 842 case RT5665_R_EQ_LPF1_A1: 843 case RT5665_L_EQ_LPF1_H0: 844 case RT5665_R_EQ_LPF1_H0: 845 case RT5665_L_EQ_BPF1_A1: 846 case RT5665_R_EQ_BPF1_A1: 847 case RT5665_L_EQ_BPF1_A2: 848 case RT5665_R_EQ_BPF1_A2: 849 case RT5665_L_EQ_BPF1_H0: 850 case RT5665_R_EQ_BPF1_H0: 851 case RT5665_L_EQ_BPF2_A1: 852 case RT5665_R_EQ_BPF2_A1: 853 case RT5665_L_EQ_BPF2_A2: 854 case RT5665_R_EQ_BPF2_A2: 855 case RT5665_L_EQ_BPF2_H0: 856 case RT5665_R_EQ_BPF2_H0: 857 case RT5665_L_EQ_BPF3_A1: 858 case RT5665_R_EQ_BPF3_A1: 859 case RT5665_L_EQ_BPF3_A2: 860 case RT5665_R_EQ_BPF3_A2: 861 case RT5665_L_EQ_BPF3_H0: 862 case RT5665_R_EQ_BPF3_H0: 863 case RT5665_L_EQ_BPF4_A1: 864 case RT5665_R_EQ_BPF4_A1: 865 case RT5665_L_EQ_BPF4_A2: 866 case RT5665_R_EQ_BPF4_A2: 867 case RT5665_L_EQ_BPF4_H0: 868 case RT5665_R_EQ_BPF4_H0: 869 case RT5665_L_EQ_HPF1_A1: 870 case RT5665_R_EQ_HPF1_A1: 871 case RT5665_L_EQ_HPF1_H0: 872 case RT5665_R_EQ_HPF1_H0: 873 case RT5665_L_EQ_PRE_VOL: 874 case RT5665_R_EQ_PRE_VOL: 875 case RT5665_L_EQ_POST_VOL: 876 case RT5665_R_EQ_POST_VOL: 877 case RT5665_SCAN_MODE_CTRL: 878 case RT5665_I2C_MODE: 879 return true; 880 default: 881 return false; 882 } 883 } 884 885 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0); 886 static const DECLARE_TLV_DB_SCALE(mono_vol_tlv, -1400, 150, 0); 887 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0); 888 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0); 889 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0); 890 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0); 891 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 892 static const DECLARE_TLV_DB_SCALE(in_bst_tlv, -1200, 75, 0); 893 894 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 895 static const DECLARE_TLV_DB_RANGE(bst_tlv, 896 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 897 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 898 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 899 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 900 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 901 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 902 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 903 ); 904 905 /* Interface data select */ 906 static const char * const rt5665_data_select[] = { 907 "L/R", "R/L", "L/L", "R/R" 908 }; 909 910 static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_01_adc_enum, 911 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT01_SFT, rt5665_data_select); 912 913 static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_23_adc_enum, 914 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT23_SFT, rt5665_data_select); 915 916 static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_45_adc_enum, 917 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT45_SFT, rt5665_data_select); 918 919 static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_67_adc_enum, 920 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT67_SFT, rt5665_data_select); 921 922 static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_01_adc_enum, 923 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT01_SFT, rt5665_data_select); 924 925 static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_23_adc_enum, 926 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT23_SFT, rt5665_data_select); 927 928 static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_45_adc_enum, 929 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT45_SFT, rt5665_data_select); 930 931 static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_67_adc_enum, 932 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT67_SFT, rt5665_data_select); 933 934 static SOC_ENUM_SINGLE_DECL(rt5665_if2_1_dac_enum, 935 RT5665_DIG_INF2_DATA, RT5665_IF2_1_DAC_SEL_SFT, rt5665_data_select); 936 937 static SOC_ENUM_SINGLE_DECL(rt5665_if2_1_adc_enum, 938 RT5665_DIG_INF2_DATA, RT5665_IF2_1_ADC_SEL_SFT, rt5665_data_select); 939 940 static SOC_ENUM_SINGLE_DECL(rt5665_if2_2_dac_enum, 941 RT5665_DIG_INF2_DATA, RT5665_IF2_2_DAC_SEL_SFT, rt5665_data_select); 942 943 static SOC_ENUM_SINGLE_DECL(rt5665_if2_2_adc_enum, 944 RT5665_DIG_INF2_DATA, RT5665_IF2_2_ADC_SEL_SFT, rt5665_data_select); 945 946 static SOC_ENUM_SINGLE_DECL(rt5665_if3_dac_enum, 947 RT5665_DIG_INF3_DATA, RT5665_IF3_DAC_SEL_SFT, rt5665_data_select); 948 949 static SOC_ENUM_SINGLE_DECL(rt5665_if3_adc_enum, 950 RT5665_DIG_INF3_DATA, RT5665_IF3_ADC_SEL_SFT, rt5665_data_select); 951 952 static const struct snd_kcontrol_new rt5665_if1_1_01_adc_swap_mux = 953 SOC_DAPM_ENUM("IF1_1 01 ADC Swap Mux", rt5665_if1_1_01_adc_enum); 954 955 static const struct snd_kcontrol_new rt5665_if1_1_23_adc_swap_mux = 956 SOC_DAPM_ENUM("IF1_1 23 ADC Swap Mux", rt5665_if1_1_23_adc_enum); 957 958 static const struct snd_kcontrol_new rt5665_if1_1_45_adc_swap_mux = 959 SOC_DAPM_ENUM("IF1_1 45 ADC Swap Mux", rt5665_if1_1_45_adc_enum); 960 961 static const struct snd_kcontrol_new rt5665_if1_1_67_adc_swap_mux = 962 SOC_DAPM_ENUM("IF1_1 67 ADC Swap Mux", rt5665_if1_1_67_adc_enum); 963 964 static const struct snd_kcontrol_new rt5665_if1_2_01_adc_swap_mux = 965 SOC_DAPM_ENUM("IF1_2 01 ADC Swap Mux", rt5665_if1_2_01_adc_enum); 966 967 static const struct snd_kcontrol_new rt5665_if1_2_23_adc_swap_mux = 968 SOC_DAPM_ENUM("IF1_2 23 ADC1 Swap Mux", rt5665_if1_2_23_adc_enum); 969 970 static const struct snd_kcontrol_new rt5665_if1_2_45_adc_swap_mux = 971 SOC_DAPM_ENUM("IF1_2 45 ADC1 Swap Mux", rt5665_if1_2_45_adc_enum); 972 973 static const struct snd_kcontrol_new rt5665_if1_2_67_adc_swap_mux = 974 SOC_DAPM_ENUM("IF1_2 67 ADC1 Swap Mux", rt5665_if1_2_67_adc_enum); 975 976 static const struct snd_kcontrol_new rt5665_if2_1_dac_swap_mux = 977 SOC_DAPM_ENUM("IF2_1 DAC Swap Source", rt5665_if2_1_dac_enum); 978 979 static const struct snd_kcontrol_new rt5665_if2_1_adc_swap_mux = 980 SOC_DAPM_ENUM("IF2_1 ADC Swap Source", rt5665_if2_1_adc_enum); 981 982 static const struct snd_kcontrol_new rt5665_if2_2_dac_swap_mux = 983 SOC_DAPM_ENUM("IF2_2 DAC Swap Source", rt5665_if2_2_dac_enum); 984 985 static const struct snd_kcontrol_new rt5665_if2_2_adc_swap_mux = 986 SOC_DAPM_ENUM("IF2_2 ADC Swap Source", rt5665_if2_2_adc_enum); 987 988 static const struct snd_kcontrol_new rt5665_if3_dac_swap_mux = 989 SOC_DAPM_ENUM("IF3 DAC Swap Source", rt5665_if3_dac_enum); 990 991 static const struct snd_kcontrol_new rt5665_if3_adc_swap_mux = 992 SOC_DAPM_ENUM("IF3 ADC Swap Source", rt5665_if3_adc_enum); 993 994 static int rt5665_hp_vol_put(struct snd_kcontrol *kcontrol, 995 struct snd_ctl_elem_value *ucontrol) 996 { 997 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 998 int ret = snd_soc_put_volsw(kcontrol, ucontrol); 999 1000 if (snd_soc_component_read(component, RT5665_STO_NG2_CTRL_1) & RT5665_NG2_EN) { 1001 snd_soc_component_update_bits(component, RT5665_STO_NG2_CTRL_1, 1002 RT5665_NG2_EN_MASK, RT5665_NG2_DIS); 1003 snd_soc_component_update_bits(component, RT5665_STO_NG2_CTRL_1, 1004 RT5665_NG2_EN_MASK, RT5665_NG2_EN); 1005 } 1006 1007 return ret; 1008 } 1009 1010 static int rt5665_mono_vol_put(struct snd_kcontrol *kcontrol, 1011 struct snd_ctl_elem_value *ucontrol) 1012 { 1013 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1014 int ret = snd_soc_put_volsw(kcontrol, ucontrol); 1015 1016 if (snd_soc_component_read(component, RT5665_MONO_NG2_CTRL_1) & RT5665_NG2_EN) { 1017 snd_soc_component_update_bits(component, RT5665_MONO_NG2_CTRL_1, 1018 RT5665_NG2_EN_MASK, RT5665_NG2_DIS); 1019 snd_soc_component_update_bits(component, RT5665_MONO_NG2_CTRL_1, 1020 RT5665_NG2_EN_MASK, RT5665_NG2_EN); 1021 } 1022 1023 return ret; 1024 } 1025 1026 static int rt5665_button_detect(struct snd_soc_component *component) 1027 { 1028 int btn_type, val; 1029 1030 val = snd_soc_component_read(component, RT5665_4BTN_IL_CMD_1); 1031 btn_type = val & 0xfff0; 1032 snd_soc_component_write(component, RT5665_4BTN_IL_CMD_1, val); 1033 1034 return btn_type; 1035 } 1036 1037 static void rt5665_enable_push_button_irq(struct snd_soc_component *component, 1038 bool enable) 1039 { 1040 if (enable) { 1041 snd_soc_component_write(component, RT5665_4BTN_IL_CMD_1, 0x0003); 1042 snd_soc_component_update_bits(component, RT5665_SAR_IL_CMD_9, 0x1, 0x1); 1043 snd_soc_component_write(component, RT5665_IL_CMD_1, 0x0048); 1044 snd_soc_component_update_bits(component, RT5665_4BTN_IL_CMD_2, 1045 RT5665_4BTN_IL_MASK | RT5665_4BTN_IL_RST_MASK, 1046 RT5665_4BTN_IL_EN | RT5665_4BTN_IL_NOR); 1047 snd_soc_component_update_bits(component, RT5665_IRQ_CTRL_3, 1048 RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_EN); 1049 } else { 1050 snd_soc_component_update_bits(component, RT5665_IRQ_CTRL_3, 1051 RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_DIS); 1052 snd_soc_component_update_bits(component, RT5665_4BTN_IL_CMD_2, 1053 RT5665_4BTN_IL_MASK, RT5665_4BTN_IL_DIS); 1054 snd_soc_component_update_bits(component, RT5665_4BTN_IL_CMD_2, 1055 RT5665_4BTN_IL_RST_MASK, RT5665_4BTN_IL_RST); 1056 } 1057 } 1058 1059 /** 1060 * rt5665_headset_detect - Detect headset. 1061 * @component: SoC audio component device. 1062 * @jack_insert: Jack insert or not. 1063 * 1064 * Detect whether is headset or not when jack inserted. 1065 * 1066 * Returns detect status. 1067 */ 1068 static int rt5665_headset_detect(struct snd_soc_component *component, int jack_insert) 1069 { 1070 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component); 1071 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 1072 unsigned int sar_hs_type, val; 1073 1074 if (jack_insert) { 1075 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1"); 1076 snd_soc_dapm_sync(dapm); 1077 1078 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100, 1079 0x100); 1080 1081 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val); 1082 if (val & 0x4) { 1083 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1, 1084 0x100, 0); 1085 1086 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val); 1087 while (val & 0x4) { 1088 usleep_range(10000, 15000); 1089 regmap_read(rt5665->regmap, RT5665_GPIO_STA, 1090 &val); 1091 } 1092 } 1093 1094 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1, 1095 0x1a0, 0x120); 1096 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_3, 0x3424); 1097 regmap_write(rt5665->regmap, RT5665_IL_CMD_1, 0x0048); 1098 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0xa291); 1099 1100 usleep_range(10000, 15000); 1101 1102 rt5665->sar_adc_value = snd_soc_component_read(rt5665->component, 1103 RT5665_SAR_IL_CMD_4) & 0x7ff; 1104 1105 sar_hs_type = rt5665->pdata.sar_hs_type ? 1106 rt5665->pdata.sar_hs_type : 729; 1107 1108 if (rt5665->sar_adc_value > sar_hs_type) { 1109 rt5665->jack_type = SND_JACK_HEADSET; 1110 rt5665_enable_push_button_irq(component, true); 1111 } else { 1112 rt5665->jack_type = SND_JACK_HEADPHONE; 1113 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 1114 0x2291); 1115 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 1116 0x100, 0); 1117 snd_soc_dapm_disable_pin(dapm, "MICBIAS1"); 1118 snd_soc_dapm_sync(dapm); 1119 } 1120 } else { 1121 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0x2291); 1122 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100, 0); 1123 snd_soc_dapm_disable_pin(dapm, "MICBIAS1"); 1124 snd_soc_dapm_sync(dapm); 1125 if (rt5665->jack_type == SND_JACK_HEADSET) 1126 rt5665_enable_push_button_irq(component, false); 1127 rt5665->jack_type = 0; 1128 } 1129 1130 dev_dbg(component->dev, "jack_type = %d\n", rt5665->jack_type); 1131 return rt5665->jack_type; 1132 } 1133 1134 static irqreturn_t rt5665_irq(int irq, void *data) 1135 { 1136 struct rt5665_priv *rt5665 = data; 1137 1138 mod_delayed_work(system_power_efficient_wq, 1139 &rt5665->jack_detect_work, msecs_to_jiffies(250)); 1140 1141 return IRQ_HANDLED; 1142 } 1143 1144 static void rt5665_jd_check_handler(struct work_struct *work) 1145 { 1146 struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv, 1147 jd_check_work.work); 1148 1149 if (snd_soc_component_read(rt5665->component, RT5665_AJD1_CTRL) & 0x0010) { 1150 /* jack out */ 1151 rt5665->jack_type = rt5665_headset_detect(rt5665->component, 0); 1152 1153 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type, 1154 SND_JACK_HEADSET | 1155 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1156 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1157 } else { 1158 schedule_delayed_work(&rt5665->jd_check_work, 500); 1159 } 1160 } 1161 1162 static int rt5665_set_jack_detect(struct snd_soc_component *component, 1163 struct snd_soc_jack *hs_jack, void *data) 1164 { 1165 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component); 1166 1167 switch (rt5665->pdata.jd_src) { 1168 case RT5665_JD1: 1169 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1, 1170 RT5665_GP1_PIN_MASK, RT5665_GP1_PIN_IRQ); 1171 regmap_update_bits(rt5665->regmap, RT5665_RC_CLK_CTRL, 1172 0xc000, 0xc000); 1173 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_2, 1174 RT5665_PWR_JD1, RT5665_PWR_JD1); 1175 regmap_update_bits(rt5665->regmap, RT5665_IRQ_CTRL_1, 0x8, 0x8); 1176 break; 1177 1178 case RT5665_JD_NULL: 1179 break; 1180 1181 default: 1182 dev_warn(component->dev, "Wrong JD source\n"); 1183 break; 1184 } 1185 1186 rt5665->hs_jack = hs_jack; 1187 1188 return 0; 1189 } 1190 1191 static void rt5665_jack_detect_handler(struct work_struct *work) 1192 { 1193 struct rt5665_priv *rt5665 = 1194 container_of(work, struct rt5665_priv, jack_detect_work.work); 1195 int val, btn_type; 1196 1197 while (!rt5665->component) { 1198 pr_debug("%s codec = null\n", __func__); 1199 usleep_range(10000, 15000); 1200 } 1201 1202 while (!snd_soc_card_is_instantiated(rt5665->component->card)) { 1203 pr_debug("%s\n", __func__); 1204 usleep_range(10000, 15000); 1205 } 1206 1207 while (!rt5665->calibration_done) { 1208 pr_debug("%s calibration not ready\n", __func__); 1209 usleep_range(10000, 15000); 1210 } 1211 1212 guard(mutex)(&rt5665->calibrate_mutex); 1213 1214 val = snd_soc_component_read(rt5665->component, RT5665_AJD1_CTRL) & 0x0010; 1215 if (!val) { 1216 /* jack in */ 1217 if (rt5665->jack_type == 0) { 1218 /* jack was out, report jack type */ 1219 rt5665->jack_type = 1220 rt5665_headset_detect(rt5665->component, 1); 1221 } else { 1222 /* jack is already in, report button event */ 1223 rt5665->jack_type = SND_JACK_HEADSET; 1224 btn_type = rt5665_button_detect(rt5665->component); 1225 /** 1226 * rt5665 can report three kinds of button behavior, 1227 * one click, double click and hold. However, 1228 * currently we will report button pressed/released 1229 * event. So all the three button behaviors are 1230 * treated as button pressed. 1231 */ 1232 switch (btn_type) { 1233 case 0x8000: 1234 case 0x4000: 1235 case 0x2000: 1236 rt5665->jack_type |= SND_JACK_BTN_0; 1237 break; 1238 case 0x1000: 1239 case 0x0800: 1240 case 0x0400: 1241 rt5665->jack_type |= SND_JACK_BTN_1; 1242 break; 1243 case 0x0200: 1244 case 0x0100: 1245 case 0x0080: 1246 rt5665->jack_type |= SND_JACK_BTN_2; 1247 break; 1248 case 0x0040: 1249 case 0x0020: 1250 case 0x0010: 1251 rt5665->jack_type |= SND_JACK_BTN_3; 1252 break; 1253 case 0x0000: /* unpressed */ 1254 break; 1255 default: 1256 btn_type = 0; 1257 dev_err(rt5665->component->dev, 1258 "Unexpected button code 0x%04x\n", 1259 btn_type); 1260 break; 1261 } 1262 } 1263 } else { 1264 /* jack out */ 1265 rt5665->jack_type = rt5665_headset_detect(rt5665->component, 0); 1266 } 1267 1268 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type, 1269 SND_JACK_HEADSET | 1270 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1271 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1272 1273 if (rt5665->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1274 SND_JACK_BTN_2 | SND_JACK_BTN_3)) 1275 schedule_delayed_work(&rt5665->jd_check_work, 0); 1276 else 1277 cancel_delayed_work_sync(&rt5665->jd_check_work); 1278 } 1279 1280 static const char * const rt5665_clk_sync[] = { 1281 "I2S1_1", "I2S1_2", "I2S2", "I2S3", "IF2 Slave", "IF3 Slave" 1282 }; 1283 1284 static const struct soc_enum rt5665_enum[] = { 1285 SOC_ENUM_SINGLE(RT5665_I2S1_SDP, 11, 5, rt5665_clk_sync), 1286 SOC_ENUM_SINGLE(RT5665_I2S2_SDP, 11, 5, rt5665_clk_sync), 1287 SOC_ENUM_SINGLE(RT5665_I2S3_SDP, 11, 5, rt5665_clk_sync), 1288 }; 1289 1290 static const struct snd_kcontrol_new rt5665_snd_controls[] = { 1291 /* Headphone Output Volume */ 1292 SOC_DOUBLE_R_EXT_TLV("Headphone Playback Volume", RT5665_HPL_GAIN, 1293 RT5665_HPR_GAIN, RT5665_G_HP_SFT, 15, 1, snd_soc_get_volsw, 1294 rt5665_hp_vol_put, hp_vol_tlv), 1295 1296 /* Mono Output Volume */ 1297 SOC_SINGLE_EXT_TLV("Mono Playback Volume", RT5665_MONO_GAIN, 1298 RT5665_L_VOL_SFT, 15, 1, snd_soc_get_volsw, 1299 rt5665_mono_vol_put, mono_vol_tlv), 1300 1301 SOC_SINGLE_TLV("MONOVOL Playback Volume", RT5665_MONO_OUT, 1302 RT5665_L_VOL_SFT, 39, 1, out_vol_tlv), 1303 1304 /* Output Volume */ 1305 SOC_DOUBLE_TLV("OUT Playback Volume", RT5665_LOUT, RT5665_L_VOL_SFT, 1306 RT5665_R_VOL_SFT, 39, 1, out_vol_tlv), 1307 1308 /* DAC Digital Volume */ 1309 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5665_DAC1_DIG_VOL, 1310 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv), 1311 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5665_DAC2_DIG_VOL, 1312 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv), 1313 SOC_DOUBLE("DAC2 Playback Switch", RT5665_DAC2_CTRL, 1314 RT5665_M_DAC2_L_VOL_SFT, RT5665_M_DAC2_R_VOL_SFT, 1, 1), 1315 1316 /* IN1/IN2/IN3/IN4 Volume */ 1317 SOC_SINGLE_TLV("IN1 Boost Volume", RT5665_IN1_IN2, 1318 RT5665_BST1_SFT, 69, 0, in_bst_tlv), 1319 SOC_SINGLE_TLV("IN2 Boost Volume", RT5665_IN1_IN2, 1320 RT5665_BST2_SFT, 69, 0, in_bst_tlv), 1321 SOC_SINGLE_TLV("IN3 Boost Volume", RT5665_IN3_IN4, 1322 RT5665_BST3_SFT, 69, 0, in_bst_tlv), 1323 SOC_SINGLE_TLV("IN4 Boost Volume", RT5665_IN3_IN4, 1324 RT5665_BST4_SFT, 69, 0, in_bst_tlv), 1325 SOC_SINGLE_TLV("CBJ Boost Volume", RT5665_CBJ_BST_CTRL, 1326 RT5665_BST_CBJ_SFT, 8, 0, bst_tlv), 1327 1328 /* INL/INR Volume Control */ 1329 SOC_DOUBLE_TLV("IN Capture Volume", RT5665_INL1_INR1_VOL, 1330 RT5665_INL_VOL_SFT, RT5665_INR_VOL_SFT, 31, 1, in_vol_tlv), 1331 1332 /* ADC Digital Volume Control */ 1333 SOC_DOUBLE("STO1 ADC Capture Switch", RT5665_STO1_ADC_DIG_VOL, 1334 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1), 1335 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5665_STO1_ADC_DIG_VOL, 1336 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv), 1337 SOC_DOUBLE("Mono ADC Capture Switch", RT5665_MONO_ADC_DIG_VOL, 1338 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1), 1339 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5665_MONO_ADC_DIG_VOL, 1340 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv), 1341 SOC_DOUBLE("STO2 ADC Capture Switch", RT5665_STO2_ADC_DIG_VOL, 1342 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1), 1343 SOC_DOUBLE_TLV("STO2 ADC Capture Volume", RT5665_STO2_ADC_DIG_VOL, 1344 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv), 1345 1346 /* ADC Boost Volume Control */ 1347 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5665_STO1_ADC_BOOST, 1348 RT5665_STO1_ADC_L_BST_SFT, RT5665_STO1_ADC_R_BST_SFT, 1349 3, 0, adc_bst_tlv), 1350 1351 SOC_DOUBLE_TLV("Mono ADC Boost Gain Volume", RT5665_MONO_ADC_BOOST, 1352 RT5665_MONO_ADC_L_BST_SFT, RT5665_MONO_ADC_R_BST_SFT, 1353 3, 0, adc_bst_tlv), 1354 1355 SOC_DOUBLE_TLV("STO2 ADC Boost Gain Volume", RT5665_STO2_ADC_BOOST, 1356 RT5665_STO2_ADC_L_BST_SFT, RT5665_STO2_ADC_R_BST_SFT, 1357 3, 0, adc_bst_tlv), 1358 1359 /* I2S3 CLK Source */ 1360 SOC_ENUM("I2S1 Master Clk Sel", rt5665_enum[0]), 1361 SOC_ENUM("I2S2 Master Clk Sel", rt5665_enum[1]), 1362 SOC_ENUM("I2S3 Master Clk Sel", rt5665_enum[2]), 1363 }; 1364 1365 /** 1366 * set_dmic_clk - Set parameter of dmic. 1367 * 1368 * @w: DAPM widget. 1369 * @kcontrol: The kcontrol of this widget. 1370 * @event: Event id. 1371 * 1372 * Choose dmic clock between 1MHz and 3MHz. 1373 * It is better for clock to approximate 3MHz. 1374 */ 1375 static int set_dmic_clk(struct snd_soc_dapm_widget *w, 1376 struct snd_kcontrol *kcontrol, int event) 1377 { 1378 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1379 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component); 1380 int pd, idx; 1381 1382 pd = rl6231_get_pre_div(rt5665->regmap, 1383 RT5665_ADDA_CLK_1, RT5665_I2S_PD1_SFT); 1384 idx = rl6231_calc_dmic_clk(rt5665->sysclk / pd); 1385 1386 if (idx < 0) 1387 dev_err(component->dev, "Failed to set DMIC clock\n"); 1388 else { 1389 snd_soc_component_update_bits(component, RT5665_DMIC_CTRL_1, 1390 RT5665_DMIC_CLK_MASK, idx << RT5665_DMIC_CLK_SFT); 1391 } 1392 return idx; 1393 } 1394 1395 static int rt5665_charge_pump_event(struct snd_soc_dapm_widget *w, 1396 struct snd_kcontrol *kcontrol, int event) 1397 { 1398 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1399 1400 switch (event) { 1401 case SND_SOC_DAPM_PRE_PMU: 1402 snd_soc_component_update_bits(component, RT5665_HP_CHARGE_PUMP_1, 1403 RT5665_PM_HP_MASK | RT5665_OSW_L_MASK, 1404 RT5665_PM_HP_HV | RT5665_OSW_L_EN); 1405 break; 1406 case SND_SOC_DAPM_POST_PMD: 1407 snd_soc_component_update_bits(component, RT5665_HP_CHARGE_PUMP_1, 1408 RT5665_PM_HP_MASK | RT5665_OSW_L_MASK, 1409 RT5665_PM_HP_LV | RT5665_OSW_L_DIS); 1410 break; 1411 default: 1412 return 0; 1413 } 1414 1415 return 0; 1416 } 1417 1418 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *w, 1419 struct snd_soc_dapm_widget *sink) 1420 { 1421 unsigned int val; 1422 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1423 1424 val = snd_soc_component_read(component, RT5665_GLB_CLK); 1425 val &= RT5665_SCLK_SRC_MASK; 1426 if (val == RT5665_SCLK_SRC_PLL1) 1427 return 1; 1428 else 1429 return 0; 1430 } 1431 1432 static int is_using_asrc(struct snd_soc_dapm_widget *w, 1433 struct snd_soc_dapm_widget *sink) 1434 { 1435 unsigned int reg, shift, val; 1436 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1437 1438 switch (w->shift) { 1439 case RT5665_ADC_MONO_R_ASRC_SFT: 1440 reg = RT5665_ASRC_3; 1441 shift = RT5665_AD_MONOR_CLK_SEL_SFT; 1442 break; 1443 case RT5665_ADC_MONO_L_ASRC_SFT: 1444 reg = RT5665_ASRC_3; 1445 shift = RT5665_AD_MONOL_CLK_SEL_SFT; 1446 break; 1447 case RT5665_ADC_STO1_ASRC_SFT: 1448 reg = RT5665_ASRC_3; 1449 shift = RT5665_AD_STO1_CLK_SEL_SFT; 1450 break; 1451 case RT5665_ADC_STO2_ASRC_SFT: 1452 reg = RT5665_ASRC_3; 1453 shift = RT5665_AD_STO2_CLK_SEL_SFT; 1454 break; 1455 case RT5665_DAC_MONO_R_ASRC_SFT: 1456 reg = RT5665_ASRC_2; 1457 shift = RT5665_DA_MONOR_CLK_SEL_SFT; 1458 break; 1459 case RT5665_DAC_MONO_L_ASRC_SFT: 1460 reg = RT5665_ASRC_2; 1461 shift = RT5665_DA_MONOL_CLK_SEL_SFT; 1462 break; 1463 case RT5665_DAC_STO1_ASRC_SFT: 1464 reg = RT5665_ASRC_2; 1465 shift = RT5665_DA_STO1_CLK_SEL_SFT; 1466 break; 1467 case RT5665_DAC_STO2_ASRC_SFT: 1468 reg = RT5665_ASRC_2; 1469 shift = RT5665_DA_STO2_CLK_SEL_SFT; 1470 break; 1471 default: 1472 return 0; 1473 } 1474 1475 val = (snd_soc_component_read(component, reg) >> shift) & 0xf; 1476 switch (val) { 1477 case RT5665_CLK_SEL_I2S1_ASRC: 1478 case RT5665_CLK_SEL_I2S2_ASRC: 1479 case RT5665_CLK_SEL_I2S3_ASRC: 1480 /* I2S_Pre_Div1 should be 1 in asrc mode */ 1481 snd_soc_component_update_bits(component, RT5665_ADDA_CLK_1, 1482 RT5665_I2S_PD1_MASK, RT5665_I2S_PD1_2); 1483 return 1; 1484 default: 1485 return 0; 1486 } 1487 1488 } 1489 1490 /* Digital Mixer */ 1491 static const struct snd_kcontrol_new rt5665_sto1_adc_l_mix[] = { 1492 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER, 1493 RT5665_M_STO1_ADC_L1_SFT, 1, 1), 1494 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER, 1495 RT5665_M_STO1_ADC_L2_SFT, 1, 1), 1496 }; 1497 1498 static const struct snd_kcontrol_new rt5665_sto1_adc_r_mix[] = { 1499 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER, 1500 RT5665_M_STO1_ADC_R1_SFT, 1, 1), 1501 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER, 1502 RT5665_M_STO1_ADC_R2_SFT, 1, 1), 1503 }; 1504 1505 static const struct snd_kcontrol_new rt5665_sto2_adc_l_mix[] = { 1506 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER, 1507 RT5665_M_STO2_ADC_L1_SFT, 1, 1), 1508 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER, 1509 RT5665_M_STO2_ADC_L2_SFT, 1, 1), 1510 }; 1511 1512 static const struct snd_kcontrol_new rt5665_sto2_adc_r_mix[] = { 1513 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER, 1514 RT5665_M_STO2_ADC_R1_SFT, 1, 1), 1515 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER, 1516 RT5665_M_STO2_ADC_R2_SFT, 1, 1), 1517 }; 1518 1519 static const struct snd_kcontrol_new rt5665_mono_adc_l_mix[] = { 1520 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER, 1521 RT5665_M_MONO_ADC_L1_SFT, 1, 1), 1522 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER, 1523 RT5665_M_MONO_ADC_L2_SFT, 1, 1), 1524 }; 1525 1526 static const struct snd_kcontrol_new rt5665_mono_adc_r_mix[] = { 1527 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER, 1528 RT5665_M_MONO_ADC_R1_SFT, 1, 1), 1529 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER, 1530 RT5665_M_MONO_ADC_R2_SFT, 1, 1), 1531 }; 1532 1533 static const struct snd_kcontrol_new rt5665_dac_l_mix[] = { 1534 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER, 1535 RT5665_M_ADCMIX_L_SFT, 1, 1), 1536 SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER, 1537 RT5665_M_DAC1_L_SFT, 1, 1), 1538 }; 1539 1540 static const struct snd_kcontrol_new rt5665_dac_r_mix[] = { 1541 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER, 1542 RT5665_M_ADCMIX_R_SFT, 1, 1), 1543 SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER, 1544 RT5665_M_DAC1_R_SFT, 1, 1), 1545 }; 1546 1547 static const struct snd_kcontrol_new rt5665_sto1_dac_l_mix[] = { 1548 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER, 1549 RT5665_M_DAC_L1_STO_L_SFT, 1, 1), 1550 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER, 1551 RT5665_M_DAC_R1_STO_L_SFT, 1, 1), 1552 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER, 1553 RT5665_M_DAC_L2_STO_L_SFT, 1, 1), 1554 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER, 1555 RT5665_M_DAC_R2_STO_L_SFT, 1, 1), 1556 }; 1557 1558 static const struct snd_kcontrol_new rt5665_sto1_dac_r_mix[] = { 1559 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER, 1560 RT5665_M_DAC_L1_STO_R_SFT, 1, 1), 1561 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER, 1562 RT5665_M_DAC_R1_STO_R_SFT, 1, 1), 1563 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER, 1564 RT5665_M_DAC_L2_STO_R_SFT, 1, 1), 1565 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER, 1566 RT5665_M_DAC_R2_STO_R_SFT, 1, 1), 1567 }; 1568 1569 static const struct snd_kcontrol_new rt5665_sto2_dac_l_mix[] = { 1570 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO2_DAC_MIXER, 1571 RT5665_M_DAC_L1_STO2_L_SFT, 1, 1), 1572 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO2_DAC_MIXER, 1573 RT5665_M_DAC_L2_STO2_L_SFT, 1, 1), 1574 SOC_DAPM_SINGLE("DAC L3 Switch", RT5665_STO2_DAC_MIXER, 1575 RT5665_M_DAC_L3_STO2_L_SFT, 1, 1), 1576 }; 1577 1578 static const struct snd_kcontrol_new rt5665_sto2_dac_r_mix[] = { 1579 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO2_DAC_MIXER, 1580 RT5665_M_DAC_R1_STO2_R_SFT, 1, 1), 1581 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO2_DAC_MIXER, 1582 RT5665_M_DAC_R2_STO2_R_SFT, 1, 1), 1583 SOC_DAPM_SINGLE("DAC R3 Switch", RT5665_STO2_DAC_MIXER, 1584 RT5665_M_DAC_R3_STO2_R_SFT, 1, 1), 1585 }; 1586 1587 static const struct snd_kcontrol_new rt5665_mono_dac_l_mix[] = { 1588 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER, 1589 RT5665_M_DAC_L1_MONO_L_SFT, 1, 1), 1590 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER, 1591 RT5665_M_DAC_R1_MONO_L_SFT, 1, 1), 1592 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER, 1593 RT5665_M_DAC_L2_MONO_L_SFT, 1, 1), 1594 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER, 1595 RT5665_M_DAC_R2_MONO_L_SFT, 1, 1), 1596 }; 1597 1598 static const struct snd_kcontrol_new rt5665_mono_dac_r_mix[] = { 1599 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER, 1600 RT5665_M_DAC_L1_MONO_R_SFT, 1, 1), 1601 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER, 1602 RT5665_M_DAC_R1_MONO_R_SFT, 1, 1), 1603 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER, 1604 RT5665_M_DAC_L2_MONO_R_SFT, 1, 1), 1605 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER, 1606 RT5665_M_DAC_R2_MONO_R_SFT, 1, 1), 1607 }; 1608 1609 /* Analog Input Mixer */ 1610 static const struct snd_kcontrol_new rt5665_rec1_l_mix[] = { 1611 SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC1_L2_MIXER, 1612 RT5665_M_CBJ_RM1_L_SFT, 1, 1), 1613 SOC_DAPM_SINGLE("INL Switch", RT5665_REC1_L2_MIXER, 1614 RT5665_M_INL_RM1_L_SFT, 1, 1), 1615 SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_L2_MIXER, 1616 RT5665_M_INR_RM1_L_SFT, 1, 1), 1617 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_L2_MIXER, 1618 RT5665_M_BST4_RM1_L_SFT, 1, 1), 1619 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_L2_MIXER, 1620 RT5665_M_BST3_RM1_L_SFT, 1, 1), 1621 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_L2_MIXER, 1622 RT5665_M_BST2_RM1_L_SFT, 1, 1), 1623 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_L2_MIXER, 1624 RT5665_M_BST1_RM1_L_SFT, 1, 1), 1625 }; 1626 1627 static const struct snd_kcontrol_new rt5665_rec1_r_mix[] = { 1628 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC1_R2_MIXER, 1629 RT5665_M_AEC_REF_RM1_R_SFT, 1, 1), 1630 SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_R2_MIXER, 1631 RT5665_M_INR_RM1_R_SFT, 1, 1), 1632 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_R2_MIXER, 1633 RT5665_M_BST4_RM1_R_SFT, 1, 1), 1634 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_R2_MIXER, 1635 RT5665_M_BST3_RM1_R_SFT, 1, 1), 1636 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_R2_MIXER, 1637 RT5665_M_BST2_RM1_R_SFT, 1, 1), 1638 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_R2_MIXER, 1639 RT5665_M_BST1_RM1_R_SFT, 1, 1), 1640 }; 1641 1642 static const struct snd_kcontrol_new rt5665_rec2_l_mix[] = { 1643 SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_L2_MIXER, 1644 RT5665_M_INL_RM2_L_SFT, 1, 1), 1645 SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_L2_MIXER, 1646 RT5665_M_INR_RM2_L_SFT, 1, 1), 1647 SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC2_L2_MIXER, 1648 RT5665_M_CBJ_RM2_L_SFT, 1, 1), 1649 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_L2_MIXER, 1650 RT5665_M_BST4_RM2_L_SFT, 1, 1), 1651 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_L2_MIXER, 1652 RT5665_M_BST3_RM2_L_SFT, 1, 1), 1653 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_L2_MIXER, 1654 RT5665_M_BST2_RM2_L_SFT, 1, 1), 1655 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_L2_MIXER, 1656 RT5665_M_BST1_RM2_L_SFT, 1, 1), 1657 }; 1658 1659 static const struct snd_kcontrol_new rt5665_rec2_r_mix[] = { 1660 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC2_R2_MIXER, 1661 RT5665_M_MONOVOL_RM2_R_SFT, 1, 1), 1662 SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_R2_MIXER, 1663 RT5665_M_INL_RM2_R_SFT, 1, 1), 1664 SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_R2_MIXER, 1665 RT5665_M_INR_RM2_R_SFT, 1, 1), 1666 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_R2_MIXER, 1667 RT5665_M_BST4_RM2_R_SFT, 1, 1), 1668 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_R2_MIXER, 1669 RT5665_M_BST3_RM2_R_SFT, 1, 1), 1670 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_R2_MIXER, 1671 RT5665_M_BST2_RM2_R_SFT, 1, 1), 1672 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_R2_MIXER, 1673 RT5665_M_BST1_RM2_R_SFT, 1, 1), 1674 }; 1675 1676 static const struct snd_kcontrol_new rt5665_monovol_mix[] = { 1677 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN, 1678 RT5665_M_DAC_L2_MM_SFT, 1, 1), 1679 SOC_DAPM_SINGLE("RECMIX2L Switch", RT5665_MONOMIX_IN_GAIN, 1680 RT5665_M_RECMIC2L_MM_SFT, 1, 1), 1681 SOC_DAPM_SINGLE("BST1 Switch", RT5665_MONOMIX_IN_GAIN, 1682 RT5665_M_BST1_MM_SFT, 1, 1), 1683 SOC_DAPM_SINGLE("BST2 Switch", RT5665_MONOMIX_IN_GAIN, 1684 RT5665_M_BST2_MM_SFT, 1, 1), 1685 SOC_DAPM_SINGLE("BST3 Switch", RT5665_MONOMIX_IN_GAIN, 1686 RT5665_M_BST3_MM_SFT, 1, 1), 1687 }; 1688 1689 static const struct snd_kcontrol_new rt5665_out_l_mix[] = { 1690 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_OUT_L_MIXER, 1691 RT5665_M_DAC_L2_OM_L_SFT, 1, 1), 1692 SOC_DAPM_SINGLE("INL Switch", RT5665_OUT_L_MIXER, 1693 RT5665_M_IN_L_OM_L_SFT, 1, 1), 1694 SOC_DAPM_SINGLE("BST1 Switch", RT5665_OUT_L_MIXER, 1695 RT5665_M_BST1_OM_L_SFT, 1, 1), 1696 SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_L_MIXER, 1697 RT5665_M_BST2_OM_L_SFT, 1, 1), 1698 SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_L_MIXER, 1699 RT5665_M_BST3_OM_L_SFT, 1, 1), 1700 }; 1701 1702 static const struct snd_kcontrol_new rt5665_out_r_mix[] = { 1703 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_OUT_R_MIXER, 1704 RT5665_M_DAC_R2_OM_R_SFT, 1, 1), 1705 SOC_DAPM_SINGLE("INR Switch", RT5665_OUT_R_MIXER, 1706 RT5665_M_IN_R_OM_R_SFT, 1, 1), 1707 SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_R_MIXER, 1708 RT5665_M_BST2_OM_R_SFT, 1, 1), 1709 SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_R_MIXER, 1710 RT5665_M_BST3_OM_R_SFT, 1, 1), 1711 SOC_DAPM_SINGLE("BST4 Switch", RT5665_OUT_R_MIXER, 1712 RT5665_M_BST4_OM_R_SFT, 1, 1), 1713 }; 1714 1715 static const struct snd_kcontrol_new rt5665_mono_mix[] = { 1716 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN, 1717 RT5665_M_DAC_L2_MA_SFT, 1, 1), 1718 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_MONOMIX_IN_GAIN, 1719 RT5665_M_MONOVOL_MA_SFT, 1, 1), 1720 }; 1721 1722 static const struct snd_kcontrol_new rt5665_lout_l_mix[] = { 1723 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_LOUT_MIXER, 1724 RT5665_M_DAC_L2_LM_SFT, 1, 1), 1725 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5665_LOUT_MIXER, 1726 RT5665_M_OV_L_LM_SFT, 1, 1), 1727 }; 1728 1729 static const struct snd_kcontrol_new rt5665_lout_r_mix[] = { 1730 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_LOUT_MIXER, 1731 RT5665_M_DAC_R2_LM_SFT, 1, 1), 1732 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5665_LOUT_MIXER, 1733 RT5665_M_OV_R_LM_SFT, 1, 1), 1734 }; 1735 1736 /*DAC L2, DAC R2*/ 1737 /*MX-17 [6:4], MX-17 [2:0]*/ 1738 static const char * const rt5665_dac2_src[] = { 1739 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "Mono ADC MIX" 1740 }; 1741 1742 static SOC_ENUM_SINGLE_DECL( 1743 rt5665_dac_l2_enum, RT5665_DAC2_CTRL, 1744 RT5665_DAC_L2_SEL_SFT, rt5665_dac2_src); 1745 1746 static const struct snd_kcontrol_new rt5665_dac_l2_mux = 1747 SOC_DAPM_ENUM("Digital DAC L2 Source", rt5665_dac_l2_enum); 1748 1749 static SOC_ENUM_SINGLE_DECL( 1750 rt5665_dac_r2_enum, RT5665_DAC2_CTRL, 1751 RT5665_DAC_R2_SEL_SFT, rt5665_dac2_src); 1752 1753 static const struct snd_kcontrol_new rt5665_dac_r2_mux = 1754 SOC_DAPM_ENUM("Digital DAC R2 Source", rt5665_dac_r2_enum); 1755 1756 /*DAC L3, DAC R3*/ 1757 /*MX-1B [6:4], MX-1B [2:0]*/ 1758 static const char * const rt5665_dac3_src[] = { 1759 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "STO2 ADC MIX" 1760 }; 1761 1762 static SOC_ENUM_SINGLE_DECL( 1763 rt5665_dac_l3_enum, RT5665_DAC3_CTRL, 1764 RT5665_DAC_L3_SEL_SFT, rt5665_dac3_src); 1765 1766 static const struct snd_kcontrol_new rt5665_dac_l3_mux = 1767 SOC_DAPM_ENUM("Digital DAC L3 Source", rt5665_dac_l3_enum); 1768 1769 static SOC_ENUM_SINGLE_DECL( 1770 rt5665_dac_r3_enum, RT5665_DAC3_CTRL, 1771 RT5665_DAC_R3_SEL_SFT, rt5665_dac3_src); 1772 1773 static const struct snd_kcontrol_new rt5665_dac_r3_mux = 1774 SOC_DAPM_ENUM("Digital DAC R3 Source", rt5665_dac_r3_enum); 1775 1776 /* STO1 ADC1 Source */ 1777 /* MX-26 [13] [5] */ 1778 static const char * const rt5665_sto1_adc1_src[] = { 1779 "DD Mux", "ADC" 1780 }; 1781 1782 static SOC_ENUM_SINGLE_DECL( 1783 rt5665_sto1_adc1l_enum, RT5665_STO1_ADC_MIXER, 1784 RT5665_STO1_ADC1L_SRC_SFT, rt5665_sto1_adc1_src); 1785 1786 static const struct snd_kcontrol_new rt5665_sto1_adc1l_mux = 1787 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1l_enum); 1788 1789 static SOC_ENUM_SINGLE_DECL( 1790 rt5665_sto1_adc1r_enum, RT5665_STO1_ADC_MIXER, 1791 RT5665_STO1_ADC1R_SRC_SFT, rt5665_sto1_adc1_src); 1792 1793 static const struct snd_kcontrol_new rt5665_sto1_adc1r_mux = 1794 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1r_enum); 1795 1796 /* STO1 ADC Source */ 1797 /* MX-26 [11:10] [3:2] */ 1798 static const char * const rt5665_sto1_adc_src[] = { 1799 "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R" 1800 }; 1801 1802 static SOC_ENUM_SINGLE_DECL( 1803 rt5665_sto1_adcl_enum, RT5665_STO1_ADC_MIXER, 1804 RT5665_STO1_ADCL_SRC_SFT, rt5665_sto1_adc_src); 1805 1806 static const struct snd_kcontrol_new rt5665_sto1_adcl_mux = 1807 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5665_sto1_adcl_enum); 1808 1809 static SOC_ENUM_SINGLE_DECL( 1810 rt5665_sto1_adcr_enum, RT5665_STO1_ADC_MIXER, 1811 RT5665_STO1_ADCR_SRC_SFT, rt5665_sto1_adc_src); 1812 1813 static const struct snd_kcontrol_new rt5665_sto1_adcr_mux = 1814 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5665_sto1_adcr_enum); 1815 1816 /* STO1 ADC2 Source */ 1817 /* MX-26 [12] [4] */ 1818 static const char * const rt5665_sto1_adc2_src[] = { 1819 "DAC MIX", "DMIC" 1820 }; 1821 1822 static SOC_ENUM_SINGLE_DECL( 1823 rt5665_sto1_adc2l_enum, RT5665_STO1_ADC_MIXER, 1824 RT5665_STO1_ADC2L_SRC_SFT, rt5665_sto1_adc2_src); 1825 1826 static const struct snd_kcontrol_new rt5665_sto1_adc2l_mux = 1827 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5665_sto1_adc2l_enum); 1828 1829 static SOC_ENUM_SINGLE_DECL( 1830 rt5665_sto1_adc2r_enum, RT5665_STO1_ADC_MIXER, 1831 RT5665_STO1_ADC2R_SRC_SFT, rt5665_sto1_adc2_src); 1832 1833 static const struct snd_kcontrol_new rt5665_sto1_adc2r_mux = 1834 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5665_sto1_adc2r_enum); 1835 1836 /* STO1 DMIC Source */ 1837 /* MX-26 [8] */ 1838 static const char * const rt5665_sto1_dmic_src[] = { 1839 "DMIC1", "DMIC2" 1840 }; 1841 1842 static SOC_ENUM_SINGLE_DECL( 1843 rt5665_sto1_dmic_enum, RT5665_STO1_ADC_MIXER, 1844 RT5665_STO1_DMIC_SRC_SFT, rt5665_sto1_dmic_src); 1845 1846 static const struct snd_kcontrol_new rt5665_sto1_dmic_mux = 1847 SOC_DAPM_ENUM("Stereo1 DMIC Mux", rt5665_sto1_dmic_enum); 1848 1849 /* MX-26 [9] */ 1850 static const char * const rt5665_sto1_dd_l_src[] = { 1851 "STO2 DAC", "MONO DAC" 1852 }; 1853 1854 static SOC_ENUM_SINGLE_DECL( 1855 rt5665_sto1_dd_l_enum, RT5665_STO1_ADC_MIXER, 1856 RT5665_STO1_DD_L_SRC_SFT, rt5665_sto1_dd_l_src); 1857 1858 static const struct snd_kcontrol_new rt5665_sto1_dd_l_mux = 1859 SOC_DAPM_ENUM("Stereo1 DD L Source", rt5665_sto1_dd_l_enum); 1860 1861 /* MX-26 [1:0] */ 1862 static const char * const rt5665_sto1_dd_r_src[] = { 1863 "STO2 DAC", "MONO DAC", "AEC REF" 1864 }; 1865 1866 static SOC_ENUM_SINGLE_DECL( 1867 rt5665_sto1_dd_r_enum, RT5665_STO1_ADC_MIXER, 1868 RT5665_STO1_DD_R_SRC_SFT, rt5665_sto1_dd_r_src); 1869 1870 static const struct snd_kcontrol_new rt5665_sto1_dd_r_mux = 1871 SOC_DAPM_ENUM("Stereo1 DD R Source", rt5665_sto1_dd_r_enum); 1872 1873 /* MONO ADC L2 Source */ 1874 /* MX-27 [12] */ 1875 static const char * const rt5665_mono_adc_l2_src[] = { 1876 "DAC MIXL", "DMIC" 1877 }; 1878 1879 static SOC_ENUM_SINGLE_DECL( 1880 rt5665_mono_adc_l2_enum, RT5665_MONO_ADC_MIXER, 1881 RT5665_MONO_ADC_L2_SRC_SFT, rt5665_mono_adc_l2_src); 1882 1883 static const struct snd_kcontrol_new rt5665_mono_adc_l2_mux = 1884 SOC_DAPM_ENUM("Mono ADC L2 Source", rt5665_mono_adc_l2_enum); 1885 1886 1887 /* MONO ADC L1 Source */ 1888 /* MX-27 [13] */ 1889 static const char * const rt5665_mono_adc_l1_src[] = { 1890 "DD Mux", "ADC" 1891 }; 1892 1893 static SOC_ENUM_SINGLE_DECL( 1894 rt5665_mono_adc_l1_enum, RT5665_MONO_ADC_MIXER, 1895 RT5665_MONO_ADC_L1_SRC_SFT, rt5665_mono_adc_l1_src); 1896 1897 static const struct snd_kcontrol_new rt5665_mono_adc_l1_mux = 1898 SOC_DAPM_ENUM("Mono ADC L1 Source", rt5665_mono_adc_l1_enum); 1899 1900 /* MX-27 [9][1]*/ 1901 static const char * const rt5665_mono_dd_src[] = { 1902 "STO2 DAC", "MONO DAC" 1903 }; 1904 1905 static SOC_ENUM_SINGLE_DECL( 1906 rt5665_mono_dd_l_enum, RT5665_MONO_ADC_MIXER, 1907 RT5665_MONO_DD_L_SRC_SFT, rt5665_mono_dd_src); 1908 1909 static const struct snd_kcontrol_new rt5665_mono_dd_l_mux = 1910 SOC_DAPM_ENUM("Mono DD L Source", rt5665_mono_dd_l_enum); 1911 1912 static SOC_ENUM_SINGLE_DECL( 1913 rt5665_mono_dd_r_enum, RT5665_MONO_ADC_MIXER, 1914 RT5665_MONO_DD_R_SRC_SFT, rt5665_mono_dd_src); 1915 1916 static const struct snd_kcontrol_new rt5665_mono_dd_r_mux = 1917 SOC_DAPM_ENUM("Mono DD R Source", rt5665_mono_dd_r_enum); 1918 1919 /* MONO ADC L Source, MONO ADC R Source*/ 1920 /* MX-27 [11:10], MX-27 [3:2] */ 1921 static const char * const rt5665_mono_adc_src[] = { 1922 "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R" 1923 }; 1924 1925 static SOC_ENUM_SINGLE_DECL( 1926 rt5665_mono_adc_l_enum, RT5665_MONO_ADC_MIXER, 1927 RT5665_MONO_ADC_L_SRC_SFT, rt5665_mono_adc_src); 1928 1929 static const struct snd_kcontrol_new rt5665_mono_adc_l_mux = 1930 SOC_DAPM_ENUM("Mono ADC L Source", rt5665_mono_adc_l_enum); 1931 1932 static SOC_ENUM_SINGLE_DECL( 1933 rt5665_mono_adcr_enum, RT5665_MONO_ADC_MIXER, 1934 RT5665_MONO_ADC_R_SRC_SFT, rt5665_mono_adc_src); 1935 1936 static const struct snd_kcontrol_new rt5665_mono_adc_r_mux = 1937 SOC_DAPM_ENUM("Mono ADC R Source", rt5665_mono_adcr_enum); 1938 1939 /* MONO DMIC L Source */ 1940 /* MX-27 [8] */ 1941 static const char * const rt5665_mono_dmic_l_src[] = { 1942 "DMIC1 L", "DMIC2 L" 1943 }; 1944 1945 static SOC_ENUM_SINGLE_DECL( 1946 rt5665_mono_dmic_l_enum, RT5665_MONO_ADC_MIXER, 1947 RT5665_MONO_DMIC_L_SRC_SFT, rt5665_mono_dmic_l_src); 1948 1949 static const struct snd_kcontrol_new rt5665_mono_dmic_l_mux = 1950 SOC_DAPM_ENUM("Mono DMIC L Source", rt5665_mono_dmic_l_enum); 1951 1952 /* MONO ADC R2 Source */ 1953 /* MX-27 [4] */ 1954 static const char * const rt5665_mono_adc_r2_src[] = { 1955 "DAC MIXR", "DMIC" 1956 }; 1957 1958 static SOC_ENUM_SINGLE_DECL( 1959 rt5665_mono_adc_r2_enum, RT5665_MONO_ADC_MIXER, 1960 RT5665_MONO_ADC_R2_SRC_SFT, rt5665_mono_adc_r2_src); 1961 1962 static const struct snd_kcontrol_new rt5665_mono_adc_r2_mux = 1963 SOC_DAPM_ENUM("Mono ADC R2 Source", rt5665_mono_adc_r2_enum); 1964 1965 /* MONO ADC R1 Source */ 1966 /* MX-27 [5] */ 1967 static const char * const rt5665_mono_adc_r1_src[] = { 1968 "DD Mux", "ADC" 1969 }; 1970 1971 static SOC_ENUM_SINGLE_DECL( 1972 rt5665_mono_adc_r1_enum, RT5665_MONO_ADC_MIXER, 1973 RT5665_MONO_ADC_R1_SRC_SFT, rt5665_mono_adc_r1_src); 1974 1975 static const struct snd_kcontrol_new rt5665_mono_adc_r1_mux = 1976 SOC_DAPM_ENUM("Mono ADC R1 Source", rt5665_mono_adc_r1_enum); 1977 1978 /* MONO DMIC R Source */ 1979 /* MX-27 [0] */ 1980 static const char * const rt5665_mono_dmic_r_src[] = { 1981 "DMIC1 R", "DMIC2 R" 1982 }; 1983 1984 static SOC_ENUM_SINGLE_DECL( 1985 rt5665_mono_dmic_r_enum, RT5665_MONO_ADC_MIXER, 1986 RT5665_MONO_DMIC_R_SRC_SFT, rt5665_mono_dmic_r_src); 1987 1988 static const struct snd_kcontrol_new rt5665_mono_dmic_r_mux = 1989 SOC_DAPM_ENUM("Mono DMIC R Source", rt5665_mono_dmic_r_enum); 1990 1991 1992 /* STO2 ADC1 Source */ 1993 /* MX-28 [13] [5] */ 1994 static const char * const rt5665_sto2_adc1_src[] = { 1995 "DD Mux", "ADC" 1996 }; 1997 1998 static SOC_ENUM_SINGLE_DECL( 1999 rt5665_sto2_adc1l_enum, RT5665_STO2_ADC_MIXER, 2000 RT5665_STO2_ADC1L_SRC_SFT, rt5665_sto2_adc1_src); 2001 2002 static const struct snd_kcontrol_new rt5665_sto2_adc1l_mux = 2003 SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1l_enum); 2004 2005 static SOC_ENUM_SINGLE_DECL( 2006 rt5665_sto2_adc1r_enum, RT5665_STO2_ADC_MIXER, 2007 RT5665_STO2_ADC1R_SRC_SFT, rt5665_sto2_adc1_src); 2008 2009 static const struct snd_kcontrol_new rt5665_sto2_adc1r_mux = 2010 SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1r_enum); 2011 2012 /* STO2 ADC Source */ 2013 /* MX-28 [11:10] [3:2] */ 2014 static const char * const rt5665_sto2_adc_src[] = { 2015 "ADC1 L", "ADC1 R", "ADC2 L" 2016 }; 2017 2018 static SOC_ENUM_SINGLE_DECL( 2019 rt5665_sto2_adcl_enum, RT5665_STO2_ADC_MIXER, 2020 RT5665_STO2_ADCL_SRC_SFT, rt5665_sto2_adc_src); 2021 2022 static const struct snd_kcontrol_new rt5665_sto2_adcl_mux = 2023 SOC_DAPM_ENUM("Stereo2 ADCL Source", rt5665_sto2_adcl_enum); 2024 2025 static SOC_ENUM_SINGLE_DECL( 2026 rt5665_sto2_adcr_enum, RT5665_STO2_ADC_MIXER, 2027 RT5665_STO2_ADCR_SRC_SFT, rt5665_sto2_adc_src); 2028 2029 static const struct snd_kcontrol_new rt5665_sto2_adcr_mux = 2030 SOC_DAPM_ENUM("Stereo2 ADCR Source", rt5665_sto2_adcr_enum); 2031 2032 /* STO2 ADC2 Source */ 2033 /* MX-28 [12] [4] */ 2034 static const char * const rt5665_sto2_adc2_src[] = { 2035 "DAC MIX", "DMIC" 2036 }; 2037 2038 static SOC_ENUM_SINGLE_DECL( 2039 rt5665_sto2_adc2l_enum, RT5665_STO2_ADC_MIXER, 2040 RT5665_STO2_ADC2L_SRC_SFT, rt5665_sto2_adc2_src); 2041 2042 static const struct snd_kcontrol_new rt5665_sto2_adc2l_mux = 2043 SOC_DAPM_ENUM("Stereo2 ADC2L Source", rt5665_sto2_adc2l_enum); 2044 2045 static SOC_ENUM_SINGLE_DECL( 2046 rt5665_sto2_adc2r_enum, RT5665_STO2_ADC_MIXER, 2047 RT5665_STO2_ADC2R_SRC_SFT, rt5665_sto2_adc2_src); 2048 2049 static const struct snd_kcontrol_new rt5665_sto2_adc2r_mux = 2050 SOC_DAPM_ENUM("Stereo2 ADC2R Source", rt5665_sto2_adc2r_enum); 2051 2052 /* STO2 DMIC Source */ 2053 /* MX-28 [8] */ 2054 static const char * const rt5665_sto2_dmic_src[] = { 2055 "DMIC1", "DMIC2" 2056 }; 2057 2058 static SOC_ENUM_SINGLE_DECL( 2059 rt5665_sto2_dmic_enum, RT5665_STO2_ADC_MIXER, 2060 RT5665_STO2_DMIC_SRC_SFT, rt5665_sto2_dmic_src); 2061 2062 static const struct snd_kcontrol_new rt5665_sto2_dmic_mux = 2063 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5665_sto2_dmic_enum); 2064 2065 /* MX-28 [9] */ 2066 static const char * const rt5665_sto2_dd_l_src[] = { 2067 "STO2 DAC", "MONO DAC" 2068 }; 2069 2070 static SOC_ENUM_SINGLE_DECL( 2071 rt5665_sto2_dd_l_enum, RT5665_STO2_ADC_MIXER, 2072 RT5665_STO2_DD_L_SRC_SFT, rt5665_sto2_dd_l_src); 2073 2074 static const struct snd_kcontrol_new rt5665_sto2_dd_l_mux = 2075 SOC_DAPM_ENUM("Stereo2 DD L Source", rt5665_sto2_dd_l_enum); 2076 2077 /* MX-28 [1] */ 2078 static const char * const rt5665_sto2_dd_r_src[] = { 2079 "STO2 DAC", "MONO DAC" 2080 }; 2081 2082 static SOC_ENUM_SINGLE_DECL( 2083 rt5665_sto2_dd_r_enum, RT5665_STO2_ADC_MIXER, 2084 RT5665_STO2_DD_R_SRC_SFT, rt5665_sto2_dd_r_src); 2085 2086 static const struct snd_kcontrol_new rt5665_sto2_dd_r_mux = 2087 SOC_DAPM_ENUM("Stereo2 DD R Source", rt5665_sto2_dd_r_enum); 2088 2089 /* DAC R1 Source, DAC L1 Source*/ 2090 /* MX-29 [11:10], MX-29 [9:8]*/ 2091 static const char * const rt5665_dac1_src[] = { 2092 "IF1 DAC1", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC" 2093 }; 2094 2095 static SOC_ENUM_SINGLE_DECL( 2096 rt5665_dac_r1_enum, RT5665_AD_DA_MIXER, 2097 RT5665_DAC1_R_SEL_SFT, rt5665_dac1_src); 2098 2099 static const struct snd_kcontrol_new rt5665_dac_r1_mux = 2100 SOC_DAPM_ENUM("DAC R1 Source", rt5665_dac_r1_enum); 2101 2102 static SOC_ENUM_SINGLE_DECL( 2103 rt5665_dac_l1_enum, RT5665_AD_DA_MIXER, 2104 RT5665_DAC1_L_SEL_SFT, rt5665_dac1_src); 2105 2106 static const struct snd_kcontrol_new rt5665_dac_l1_mux = 2107 SOC_DAPM_ENUM("DAC L1 Source", rt5665_dac_l1_enum); 2108 2109 /* DAC Digital Mixer L Source, DAC Digital Mixer R Source*/ 2110 /* MX-2D [13:12], MX-2D [9:8]*/ 2111 static const char * const rt5665_dig_dac_mix_src[] = { 2112 "Stereo1 DAC Mixer", "Stereo2 DAC Mixer", "Mono DAC Mixer" 2113 }; 2114 2115 static SOC_ENUM_SINGLE_DECL( 2116 rt5665_dig_dac_mixl_enum, RT5665_A_DAC1_MUX, 2117 RT5665_DAC_MIX_L_SFT, rt5665_dig_dac_mix_src); 2118 2119 static const struct snd_kcontrol_new rt5665_dig_dac_mixl_mux = 2120 SOC_DAPM_ENUM("DAC Digital Mixer L Source", rt5665_dig_dac_mixl_enum); 2121 2122 static SOC_ENUM_SINGLE_DECL( 2123 rt5665_dig_dac_mixr_enum, RT5665_A_DAC1_MUX, 2124 RT5665_DAC_MIX_R_SFT, rt5665_dig_dac_mix_src); 2125 2126 static const struct snd_kcontrol_new rt5665_dig_dac_mixr_mux = 2127 SOC_DAPM_ENUM("DAC Digital Mixer R Source", rt5665_dig_dac_mixr_enum); 2128 2129 /* Analog DAC L1 Source, Analog DAC R1 Source*/ 2130 /* MX-2D [5:4], MX-2D [1:0]*/ 2131 static const char * const rt5665_alg_dac1_src[] = { 2132 "Stereo1 DAC Mixer", "DAC1", "DMIC1" 2133 }; 2134 2135 static SOC_ENUM_SINGLE_DECL( 2136 rt5665_alg_dac_l1_enum, RT5665_A_DAC1_MUX, 2137 RT5665_A_DACL1_SFT, rt5665_alg_dac1_src); 2138 2139 static const struct snd_kcontrol_new rt5665_alg_dac_l1_mux = 2140 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5665_alg_dac_l1_enum); 2141 2142 static SOC_ENUM_SINGLE_DECL( 2143 rt5665_alg_dac_r1_enum, RT5665_A_DAC1_MUX, 2144 RT5665_A_DACR1_SFT, rt5665_alg_dac1_src); 2145 2146 static const struct snd_kcontrol_new rt5665_alg_dac_r1_mux = 2147 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5665_alg_dac_r1_enum); 2148 2149 /* Analog DAC LR Source, Analog DAC R2 Source*/ 2150 /* MX-2E [5:4], MX-2E [0]*/ 2151 static const char * const rt5665_alg_dac2_src[] = { 2152 "Mono DAC Mixer", "DAC2" 2153 }; 2154 2155 static SOC_ENUM_SINGLE_DECL( 2156 rt5665_alg_dac_l2_enum, RT5665_A_DAC2_MUX, 2157 RT5665_A_DACL2_SFT, rt5665_alg_dac2_src); 2158 2159 static const struct snd_kcontrol_new rt5665_alg_dac_l2_mux = 2160 SOC_DAPM_ENUM("Analog DAC L2 Source", rt5665_alg_dac_l2_enum); 2161 2162 static SOC_ENUM_SINGLE_DECL( 2163 rt5665_alg_dac_r2_enum, RT5665_A_DAC2_MUX, 2164 RT5665_A_DACR2_SFT, rt5665_alg_dac2_src); 2165 2166 static const struct snd_kcontrol_new rt5665_alg_dac_r2_mux = 2167 SOC_DAPM_ENUM("Analog DAC R2 Source", rt5665_alg_dac_r2_enum); 2168 2169 /* Interface2 ADC Data Input*/ 2170 /* MX-2F [14:12] */ 2171 static const char * const rt5665_if2_1_adc_in_src[] = { 2172 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1", 2173 "IF1 DAC2", "IF2_2 DAC", "IF3 DAC", "DAC1 MIX" 2174 }; 2175 2176 static SOC_ENUM_SINGLE_DECL( 2177 rt5665_if2_1_adc_in_enum, RT5665_DIG_INF2_DATA, 2178 RT5665_IF2_1_ADC_IN_SFT, rt5665_if2_1_adc_in_src); 2179 2180 static const struct snd_kcontrol_new rt5665_if2_1_adc_in_mux = 2181 SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_1_adc_in_enum); 2182 2183 /* MX-2F [6:4] */ 2184 static const char * const rt5665_if2_2_adc_in_src[] = { 2185 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1", 2186 "IF1 DAC2", "IF2_1 DAC", "IF3 DAC", "DAC1 MIX" 2187 }; 2188 2189 static SOC_ENUM_SINGLE_DECL( 2190 rt5665_if2_2_adc_in_enum, RT5665_DIG_INF2_DATA, 2191 RT5665_IF2_2_ADC_IN_SFT, rt5665_if2_2_adc_in_src); 2192 2193 static const struct snd_kcontrol_new rt5665_if2_2_adc_in_mux = 2194 SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_2_adc_in_enum); 2195 2196 /* Interface3 ADC Data Input*/ 2197 /* MX-30 [6:4] */ 2198 static const char * const rt5665_if3_adc_in_src[] = { 2199 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1", 2200 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "DAC1 MIX" 2201 }; 2202 2203 static SOC_ENUM_SINGLE_DECL( 2204 rt5665_if3_adc_in_enum, RT5665_DIG_INF3_DATA, 2205 RT5665_IF3_ADC_IN_SFT, rt5665_if3_adc_in_src); 2206 2207 static const struct snd_kcontrol_new rt5665_if3_adc_in_mux = 2208 SOC_DAPM_ENUM("IF3 ADC IN Source", rt5665_if3_adc_in_enum); 2209 2210 /* PDM 1 L/R*/ 2211 /* MX-31 [11:10] [9:8] */ 2212 static const char * const rt5665_pdm_src[] = { 2213 "Stereo1 DAC", "Stereo2 DAC", "Mono DAC" 2214 }; 2215 2216 static SOC_ENUM_SINGLE_DECL( 2217 rt5665_pdm_l_enum, RT5665_PDM_OUT_CTRL, 2218 RT5665_PDM1_L_SFT, rt5665_pdm_src); 2219 2220 static const struct snd_kcontrol_new rt5665_pdm_l_mux = 2221 SOC_DAPM_ENUM("PDM L Source", rt5665_pdm_l_enum); 2222 2223 static SOC_ENUM_SINGLE_DECL( 2224 rt5665_pdm_r_enum, RT5665_PDM_OUT_CTRL, 2225 RT5665_PDM1_R_SFT, rt5665_pdm_src); 2226 2227 static const struct snd_kcontrol_new rt5665_pdm_r_mux = 2228 SOC_DAPM_ENUM("PDM R Source", rt5665_pdm_r_enum); 2229 2230 2231 /* I2S1 TDM ADCDAT Source */ 2232 /* MX-7a[10] */ 2233 static const char * const rt5665_if1_1_adc1_data_src[] = { 2234 "STO1 ADC", "IF2_1 DAC", 2235 }; 2236 2237 static SOC_ENUM_SINGLE_DECL( 2238 rt5665_if1_1_adc1_data_enum, RT5665_TDM_CTRL_3, 2239 RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_1_adc1_data_src); 2240 2241 static const struct snd_kcontrol_new rt5665_if1_1_adc1_mux = 2242 SOC_DAPM_ENUM("IF1_1 ADC1 Source", rt5665_if1_1_adc1_data_enum); 2243 2244 /* MX-7a[9] */ 2245 static const char * const rt5665_if1_1_adc2_data_src[] = { 2246 "STO2 ADC", "IF2_2 DAC", 2247 }; 2248 2249 static SOC_ENUM_SINGLE_DECL( 2250 rt5665_if1_1_adc2_data_enum, RT5665_TDM_CTRL_3, 2251 RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_1_adc2_data_src); 2252 2253 static const struct snd_kcontrol_new rt5665_if1_1_adc2_mux = 2254 SOC_DAPM_ENUM("IF1_1 ADC2 Source", rt5665_if1_1_adc2_data_enum); 2255 2256 /* MX-7a[8] */ 2257 static const char * const rt5665_if1_1_adc3_data_src[] = { 2258 "MONO ADC", "IF3 DAC", 2259 }; 2260 2261 static SOC_ENUM_SINGLE_DECL( 2262 rt5665_if1_1_adc3_data_enum, RT5665_TDM_CTRL_3, 2263 RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_1_adc3_data_src); 2264 2265 static const struct snd_kcontrol_new rt5665_if1_1_adc3_mux = 2266 SOC_DAPM_ENUM("IF1_1 ADC3 Source", rt5665_if1_1_adc3_data_enum); 2267 2268 /* MX-7b[10] */ 2269 static const char * const rt5665_if1_2_adc1_data_src[] = { 2270 "STO1 ADC", "IF1 DAC", 2271 }; 2272 2273 static SOC_ENUM_SINGLE_DECL( 2274 rt5665_if1_2_adc1_data_enum, RT5665_TDM_CTRL_4, 2275 RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_2_adc1_data_src); 2276 2277 static const struct snd_kcontrol_new rt5665_if1_2_adc1_mux = 2278 SOC_DAPM_ENUM("IF1_2 ADC1 Source", rt5665_if1_2_adc1_data_enum); 2279 2280 /* MX-7b[9] */ 2281 static const char * const rt5665_if1_2_adc2_data_src[] = { 2282 "STO2 ADC", "IF2_1 DAC", 2283 }; 2284 2285 static SOC_ENUM_SINGLE_DECL( 2286 rt5665_if1_2_adc2_data_enum, RT5665_TDM_CTRL_4, 2287 RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_2_adc2_data_src); 2288 2289 static const struct snd_kcontrol_new rt5665_if1_2_adc2_mux = 2290 SOC_DAPM_ENUM("IF1_2 ADC2 Source", rt5665_if1_2_adc2_data_enum); 2291 2292 /* MX-7b[8] */ 2293 static const char * const rt5665_if1_2_adc3_data_src[] = { 2294 "MONO ADC", "IF2_2 DAC", 2295 }; 2296 2297 static SOC_ENUM_SINGLE_DECL( 2298 rt5665_if1_2_adc3_data_enum, RT5665_TDM_CTRL_4, 2299 RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_2_adc3_data_src); 2300 2301 static const struct snd_kcontrol_new rt5665_if1_2_adc3_mux = 2302 SOC_DAPM_ENUM("IF1_2 ADC3 Source", rt5665_if1_2_adc3_data_enum); 2303 2304 /* MX-7b[7] */ 2305 static const char * const rt5665_if1_2_adc4_data_src[] = { 2306 "DAC1", "IF3 DAC", 2307 }; 2308 2309 static SOC_ENUM_SINGLE_DECL( 2310 rt5665_if1_2_adc4_data_enum, RT5665_TDM_CTRL_4, 2311 RT5665_IF1_ADC4_SEL_SFT, rt5665_if1_2_adc4_data_src); 2312 2313 static const struct snd_kcontrol_new rt5665_if1_2_adc4_mux = 2314 SOC_DAPM_ENUM("IF1_2 ADC4 Source", rt5665_if1_2_adc4_data_enum); 2315 2316 /* MX-7a[4:0] MX-7b[4:0] */ 2317 static const char * const rt5665_tdm_adc_data_src[] = { 2318 "1234", "1243", "1324", "1342", "1432", "1423", 2319 "2134", "2143", "2314", "2341", "2431", "2413", 2320 "3124", "3142", "3214", "3241", "3412", "3421", 2321 "4123", "4132", "4213", "4231", "4312", "4321" 2322 }; 2323 2324 static SOC_ENUM_SINGLE_DECL( 2325 rt5665_tdm1_adc_data_enum, RT5665_TDM_CTRL_3, 2326 RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src); 2327 2328 static const struct snd_kcontrol_new rt5665_tdm1_adc_mux = 2329 SOC_DAPM_ENUM("TDM1 ADC Mux", rt5665_tdm1_adc_data_enum); 2330 2331 static SOC_ENUM_SINGLE_DECL( 2332 rt5665_tdm2_adc_data_enum, RT5665_TDM_CTRL_4, 2333 RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src); 2334 2335 static const struct snd_kcontrol_new rt5665_tdm2_adc_mux = 2336 SOC_DAPM_ENUM("TDM2 ADCDAT Source", rt5665_tdm2_adc_data_enum); 2337 2338 /* Out Volume Switch */ 2339 static const struct snd_kcontrol_new monovol_switch = 2340 SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_VOL_L_SFT, 1, 1); 2341 2342 static const struct snd_kcontrol_new outvol_l_switch = 2343 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_L_SFT, 1, 1); 2344 2345 static const struct snd_kcontrol_new outvol_r_switch = 2346 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_R_SFT, 1, 1); 2347 2348 /* Out Switch */ 2349 static const struct snd_kcontrol_new mono_switch = 2350 SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_L_MUTE_SFT, 1, 1); 2351 2352 static const struct snd_kcontrol_new hpo_switch = 2353 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5665_HP_CTRL_2, 2354 RT5665_VOL_L_SFT, 1, 0); 2355 2356 static const struct snd_kcontrol_new lout_l_switch = 2357 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_L_MUTE_SFT, 1, 1); 2358 2359 static const struct snd_kcontrol_new lout_r_switch = 2360 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_R_MUTE_SFT, 1, 1); 2361 2362 static const struct snd_kcontrol_new pdm_l_switch = 2363 SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL, 2364 RT5665_M_PDM1_L_SFT, 1, 1); 2365 2366 static const struct snd_kcontrol_new pdm_r_switch = 2367 SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL, 2368 RT5665_M_PDM1_R_SFT, 1, 1); 2369 2370 static int rt5665_mono_event(struct snd_soc_dapm_widget *w, 2371 struct snd_kcontrol *kcontrol, int event) 2372 { 2373 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2374 2375 switch (event) { 2376 case SND_SOC_DAPM_PRE_PMU: 2377 snd_soc_component_update_bits(component, RT5665_MONO_NG2_CTRL_1, 2378 RT5665_NG2_EN_MASK, RT5665_NG2_EN); 2379 snd_soc_component_update_bits(component, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40, 2380 0x0); 2381 snd_soc_component_update_bits(component, RT5665_MONO_OUT, 0x10, 0x10); 2382 snd_soc_component_update_bits(component, RT5665_MONO_OUT, 0x20, 0x20); 2383 break; 2384 2385 case SND_SOC_DAPM_POST_PMD: 2386 snd_soc_component_update_bits(component, RT5665_MONO_OUT, 0x20, 0); 2387 snd_soc_component_update_bits(component, RT5665_MONO_OUT, 0x10, 0); 2388 snd_soc_component_update_bits(component, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40, 2389 0x40); 2390 snd_soc_component_update_bits(component, RT5665_MONO_NG2_CTRL_1, 2391 RT5665_NG2_EN_MASK, RT5665_NG2_DIS); 2392 break; 2393 2394 default: 2395 return 0; 2396 } 2397 2398 return 0; 2399 2400 } 2401 2402 static int rt5665_hp_event(struct snd_soc_dapm_widget *w, 2403 struct snd_kcontrol *kcontrol, int event) 2404 { 2405 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2406 2407 switch (event) { 2408 case SND_SOC_DAPM_PRE_PMU: 2409 snd_soc_component_update_bits(component, RT5665_STO_NG2_CTRL_1, 2410 RT5665_NG2_EN_MASK, RT5665_NG2_EN); 2411 snd_soc_component_write(component, RT5665_HP_LOGIC_CTRL_2, 0x0003); 2412 break; 2413 2414 case SND_SOC_DAPM_POST_PMD: 2415 snd_soc_component_write(component, RT5665_HP_LOGIC_CTRL_2, 0x0002); 2416 snd_soc_component_update_bits(component, RT5665_STO_NG2_CTRL_1, 2417 RT5665_NG2_EN_MASK, RT5665_NG2_DIS); 2418 break; 2419 2420 default: 2421 return 0; 2422 } 2423 2424 return 0; 2425 2426 } 2427 2428 static int rt5665_lout_event(struct snd_soc_dapm_widget *w, 2429 struct snd_kcontrol *kcontrol, int event) 2430 { 2431 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2432 2433 switch (event) { 2434 case SND_SOC_DAPM_POST_PMU: 2435 snd_soc_component_update_bits(component, RT5665_DEPOP_1, 2436 RT5665_PUMP_EN, RT5665_PUMP_EN); 2437 break; 2438 2439 case SND_SOC_DAPM_PRE_PMD: 2440 snd_soc_component_update_bits(component, RT5665_DEPOP_1, 2441 RT5665_PUMP_EN, 0); 2442 break; 2443 2444 default: 2445 return 0; 2446 } 2447 2448 return 0; 2449 2450 } 2451 2452 static int set_dmic_power(struct snd_soc_dapm_widget *w, 2453 struct snd_kcontrol *kcontrol, int event) 2454 { 2455 switch (event) { 2456 case SND_SOC_DAPM_POST_PMU: 2457 /*Add delay to avoid pop noise*/ 2458 msleep(150); 2459 break; 2460 2461 default: 2462 return 0; 2463 } 2464 2465 return 0; 2466 } 2467 2468 static int rt5665_set_verf(struct snd_soc_dapm_widget *w, 2469 struct snd_kcontrol *kcontrol, int event) 2470 { 2471 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2472 2473 switch (event) { 2474 case SND_SOC_DAPM_PRE_PMU: 2475 switch (w->shift) { 2476 case RT5665_PWR_VREF1_BIT: 2477 snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1, 2478 RT5665_PWR_FV1, 0); 2479 break; 2480 2481 case RT5665_PWR_VREF2_BIT: 2482 snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1, 2483 RT5665_PWR_FV2, 0); 2484 break; 2485 2486 case RT5665_PWR_VREF3_BIT: 2487 snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1, 2488 RT5665_PWR_FV3, 0); 2489 break; 2490 2491 default: 2492 break; 2493 } 2494 break; 2495 2496 case SND_SOC_DAPM_POST_PMU: 2497 usleep_range(15000, 20000); 2498 switch (w->shift) { 2499 case RT5665_PWR_VREF1_BIT: 2500 snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1, 2501 RT5665_PWR_FV1, RT5665_PWR_FV1); 2502 break; 2503 2504 case RT5665_PWR_VREF2_BIT: 2505 snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1, 2506 RT5665_PWR_FV2, RT5665_PWR_FV2); 2507 break; 2508 2509 case RT5665_PWR_VREF3_BIT: 2510 snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1, 2511 RT5665_PWR_FV3, RT5665_PWR_FV3); 2512 break; 2513 2514 default: 2515 break; 2516 } 2517 break; 2518 2519 default: 2520 return 0; 2521 } 2522 2523 return 0; 2524 } 2525 2526 static int rt5665_i2s_pin_event(struct snd_soc_dapm_widget *w, 2527 struct snd_kcontrol *kcontrol, int event) 2528 { 2529 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2530 unsigned int val1, val2, mask1 = 0, mask2 = 0; 2531 2532 switch (w->shift) { 2533 case RT5665_PWR_I2S2_1_BIT: 2534 mask1 = RT5665_GP2_PIN_MASK | RT5665_GP3_PIN_MASK | 2535 RT5665_GP4_PIN_MASK | RT5665_GP5_PIN_MASK; 2536 val1 = RT5665_GP2_PIN_BCLK2 | RT5665_GP3_PIN_LRCK2 | 2537 RT5665_GP4_PIN_DACDAT2_1 | RT5665_GP5_PIN_ADCDAT2_1; 2538 break; 2539 case RT5665_PWR_I2S2_2_BIT: 2540 mask1 = RT5665_GP2_PIN_MASK | RT5665_GP3_PIN_MASK | 2541 RT5665_GP8_PIN_MASK; 2542 val1 = RT5665_GP2_PIN_BCLK2 | RT5665_GP3_PIN_LRCK2 | 2543 RT5665_GP8_PIN_DACDAT2_2; 2544 mask2 = RT5665_GP9_PIN_MASK; 2545 val2 = RT5665_GP9_PIN_ADCDAT2_2; 2546 break; 2547 case RT5665_PWR_I2S3_BIT: 2548 mask1 = RT5665_GP6_PIN_MASK | RT5665_GP7_PIN_MASK | 2549 RT5665_GP8_PIN_MASK; 2550 val1 = RT5665_GP6_PIN_BCLK3 | RT5665_GP7_PIN_LRCK3 | 2551 RT5665_GP8_PIN_DACDAT3; 2552 mask2 = RT5665_GP9_PIN_MASK; 2553 val2 = RT5665_GP9_PIN_ADCDAT3; 2554 break; 2555 } 2556 switch (event) { 2557 case SND_SOC_DAPM_PRE_PMU: 2558 if (mask1) 2559 snd_soc_component_update_bits(component, RT5665_GPIO_CTRL_1, 2560 mask1, val1); 2561 if (mask2) 2562 snd_soc_component_update_bits(component, RT5665_GPIO_CTRL_2, 2563 mask2, val2); 2564 break; 2565 case SND_SOC_DAPM_POST_PMD: 2566 if (mask1) 2567 snd_soc_component_update_bits(component, RT5665_GPIO_CTRL_1, 2568 mask1, 0); 2569 if (mask2) 2570 snd_soc_component_update_bits(component, RT5665_GPIO_CTRL_2, 2571 mask2, 0); 2572 break; 2573 default: 2574 return 0; 2575 } 2576 2577 return 0; 2578 } 2579 2580 static const struct snd_soc_dapm_widget rt5665_dapm_widgets[] = { 2581 SND_SOC_DAPM_SUPPLY("LDO2", RT5665_PWR_ANLG_3, RT5665_PWR_LDO2_BIT, 0, 2582 NULL, 0), 2583 SND_SOC_DAPM_SUPPLY("PLL", RT5665_PWR_ANLG_3, RT5665_PWR_PLL_BIT, 0, 2584 NULL, 0), 2585 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5665_PWR_VOL, 2586 RT5665_PWR_MIC_DET_BIT, 0, NULL, 0), 2587 SND_SOC_DAPM_SUPPLY("Vref1", RT5665_PWR_ANLG_1, RT5665_PWR_VREF1_BIT, 0, 2588 rt5665_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 2589 SND_SOC_DAPM_SUPPLY("Vref2", RT5665_PWR_ANLG_1, RT5665_PWR_VREF2_BIT, 0, 2590 rt5665_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 2591 SND_SOC_DAPM_SUPPLY("Vref3", RT5665_PWR_ANLG_1, RT5665_PWR_VREF3_BIT, 0, 2592 rt5665_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 2593 2594 /* ASRC */ 2595 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5665_ASRC_1, 2596 RT5665_I2S1_ASRC_SFT, 0, NULL, 0), 2597 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5665_ASRC_1, 2598 RT5665_I2S2_ASRC_SFT, 0, NULL, 0), 2599 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5665_ASRC_1, 2600 RT5665_I2S3_ASRC_SFT, 0, NULL, 0), 2601 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5665_ASRC_1, 2602 RT5665_DAC_STO1_ASRC_SFT, 0, NULL, 0), 2603 SND_SOC_DAPM_SUPPLY_S("DAC STO2 ASRC", 1, RT5665_ASRC_1, 2604 RT5665_DAC_STO2_ASRC_SFT, 0, NULL, 0), 2605 SND_SOC_DAPM_SUPPLY_S("DAC Mono L ASRC", 1, RT5665_ASRC_1, 2606 RT5665_DAC_MONO_L_ASRC_SFT, 0, NULL, 0), 2607 SND_SOC_DAPM_SUPPLY_S("DAC Mono R ASRC", 1, RT5665_ASRC_1, 2608 RT5665_DAC_MONO_R_ASRC_SFT, 0, NULL, 0), 2609 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5665_ASRC_1, 2610 RT5665_ADC_STO1_ASRC_SFT, 0, NULL, 0), 2611 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5665_ASRC_1, 2612 RT5665_ADC_STO2_ASRC_SFT, 0, NULL, 0), 2613 SND_SOC_DAPM_SUPPLY_S("ADC Mono L ASRC", 1, RT5665_ASRC_1, 2614 RT5665_ADC_MONO_L_ASRC_SFT, 0, NULL, 0), 2615 SND_SOC_DAPM_SUPPLY_S("ADC Mono R ASRC", 1, RT5665_ASRC_1, 2616 RT5665_ADC_MONO_R_ASRC_SFT, 0, NULL, 0), 2617 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5665_ASRC_1, 2618 RT5665_DMIC_STO1_ASRC_SFT, 0, NULL, 0), 2619 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5665_ASRC_1, 2620 RT5665_DMIC_STO2_ASRC_SFT, 0, NULL, 0), 2621 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5665_ASRC_1, 2622 RT5665_DMIC_MONO_L_ASRC_SFT, 0, NULL, 0), 2623 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5665_ASRC_1, 2624 RT5665_DMIC_MONO_R_ASRC_SFT, 0, NULL, 0), 2625 2626 /* Input Side */ 2627 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5665_PWR_ANLG_2, RT5665_PWR_MB1_BIT, 2628 0, NULL, 0), 2629 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5665_PWR_ANLG_2, RT5665_PWR_MB2_BIT, 2630 0, NULL, 0), 2631 SND_SOC_DAPM_SUPPLY("MICBIAS3", RT5665_PWR_ANLG_2, RT5665_PWR_MB3_BIT, 2632 0, NULL, 0), 2633 2634 /* Input Lines */ 2635 SND_SOC_DAPM_INPUT("DMIC L1"), 2636 SND_SOC_DAPM_INPUT("DMIC R1"), 2637 SND_SOC_DAPM_INPUT("DMIC L2"), 2638 SND_SOC_DAPM_INPUT("DMIC R2"), 2639 2640 SND_SOC_DAPM_INPUT("IN1P"), 2641 SND_SOC_DAPM_INPUT("IN1N"), 2642 SND_SOC_DAPM_INPUT("IN2P"), 2643 SND_SOC_DAPM_INPUT("IN2N"), 2644 SND_SOC_DAPM_INPUT("IN3P"), 2645 SND_SOC_DAPM_INPUT("IN3N"), 2646 SND_SOC_DAPM_INPUT("IN4P"), 2647 SND_SOC_DAPM_INPUT("IN4N"), 2648 2649 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2650 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2651 2652 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 2653 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 2654 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5665_DMIC_CTRL_1, 2655 RT5665_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU), 2656 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5665_DMIC_CTRL_1, 2657 RT5665_DMIC_2_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU), 2658 2659 /* Boost */ 2660 SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM, 2661 0, 0, NULL, 0), 2662 SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM, 2663 0, 0, NULL, 0), 2664 SND_SOC_DAPM_PGA("BST3", SND_SOC_NOPM, 2665 0, 0, NULL, 0), 2666 SND_SOC_DAPM_PGA("BST4", SND_SOC_NOPM, 2667 0, 0, NULL, 0), 2668 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 2669 0, 0, NULL, 0), 2670 SND_SOC_DAPM_SUPPLY("BST1 Power", RT5665_PWR_ANLG_2, 2671 RT5665_PWR_BST1_BIT, 0, NULL, 0), 2672 SND_SOC_DAPM_SUPPLY("BST2 Power", RT5665_PWR_ANLG_2, 2673 RT5665_PWR_BST2_BIT, 0, NULL, 0), 2674 SND_SOC_DAPM_SUPPLY("BST3 Power", RT5665_PWR_ANLG_2, 2675 RT5665_PWR_BST3_BIT, 0, NULL, 0), 2676 SND_SOC_DAPM_SUPPLY("BST4 Power", RT5665_PWR_ANLG_2, 2677 RT5665_PWR_BST4_BIT, 0, NULL, 0), 2678 SND_SOC_DAPM_SUPPLY("BST1P Power", RT5665_PWR_ANLG_2, 2679 RT5665_PWR_BST1_P_BIT, 0, NULL, 0), 2680 SND_SOC_DAPM_SUPPLY("BST2P Power", RT5665_PWR_ANLG_2, 2681 RT5665_PWR_BST2_P_BIT, 0, NULL, 0), 2682 SND_SOC_DAPM_SUPPLY("BST3P Power", RT5665_PWR_ANLG_2, 2683 RT5665_PWR_BST3_P_BIT, 0, NULL, 0), 2684 SND_SOC_DAPM_SUPPLY("BST4P Power", RT5665_PWR_ANLG_2, 2685 RT5665_PWR_BST4_P_BIT, 0, NULL, 0), 2686 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5665_PWR_ANLG_3, 2687 RT5665_PWR_CBJ_BIT, 0, NULL, 0), 2688 2689 2690 /* Input Volume */ 2691 SND_SOC_DAPM_PGA("INL VOL", RT5665_PWR_VOL, RT5665_PWR_IN_L_BIT, 2692 0, NULL, 0), 2693 SND_SOC_DAPM_PGA("INR VOL", RT5665_PWR_VOL, RT5665_PWR_IN_R_BIT, 2694 0, NULL, 0), 2695 2696 /* REC Mixer */ 2697 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5665_rec1_l_mix, 2698 ARRAY_SIZE(rt5665_rec1_l_mix)), 2699 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5665_rec1_r_mix, 2700 ARRAY_SIZE(rt5665_rec1_r_mix)), 2701 SND_SOC_DAPM_MIXER("RECMIX2L", SND_SOC_NOPM, 0, 0, rt5665_rec2_l_mix, 2702 ARRAY_SIZE(rt5665_rec2_l_mix)), 2703 SND_SOC_DAPM_MIXER("RECMIX2R", SND_SOC_NOPM, 0, 0, rt5665_rec2_r_mix, 2704 ARRAY_SIZE(rt5665_rec2_r_mix)), 2705 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5665_PWR_ANLG_2, 2706 RT5665_PWR_RM1_L_BIT, 0, NULL, 0), 2707 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5665_PWR_ANLG_2, 2708 RT5665_PWR_RM1_R_BIT, 0, NULL, 0), 2709 SND_SOC_DAPM_SUPPLY("RECMIX2L Power", RT5665_PWR_MIXER, 2710 RT5665_PWR_RM2_L_BIT, 0, NULL, 0), 2711 SND_SOC_DAPM_SUPPLY("RECMIX2R Power", RT5665_PWR_MIXER, 2712 RT5665_PWR_RM2_R_BIT, 0, NULL, 0), 2713 2714 /* ADCs */ 2715 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0), 2716 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0), 2717 SND_SOC_DAPM_ADC("ADC2 L", NULL, SND_SOC_NOPM, 0, 0), 2718 SND_SOC_DAPM_ADC("ADC2 R", NULL, SND_SOC_NOPM, 0, 0), 2719 2720 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5665_PWR_DIG_1, 2721 RT5665_PWR_ADC_L1_BIT, 0, NULL, 0), 2722 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5665_PWR_DIG_1, 2723 RT5665_PWR_ADC_R1_BIT, 0, NULL, 0), 2724 SND_SOC_DAPM_SUPPLY("ADC2 L Power", RT5665_PWR_DIG_1, 2725 RT5665_PWR_ADC_L2_BIT, 0, NULL, 0), 2726 SND_SOC_DAPM_SUPPLY("ADC2 R Power", RT5665_PWR_DIG_1, 2727 RT5665_PWR_ADC_R2_BIT, 0, NULL, 0), 2728 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5665_CHOP_ADC, 2729 RT5665_CKGEN_ADC1_SFT, 0, NULL, 0), 2730 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5665_CHOP_ADC, 2731 RT5665_CKGEN_ADC2_SFT, 0, NULL, 0), 2732 2733 /* ADC Mux */ 2734 SND_SOC_DAPM_MUX("Stereo1 DMIC L Mux", SND_SOC_NOPM, 0, 0, 2735 &rt5665_sto1_dmic_mux), 2736 SND_SOC_DAPM_MUX("Stereo1 DMIC R Mux", SND_SOC_NOPM, 0, 0, 2737 &rt5665_sto1_dmic_mux), 2738 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0, 2739 &rt5665_sto1_adc1l_mux), 2740 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0, 2741 &rt5665_sto1_adc1r_mux), 2742 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0, 2743 &rt5665_sto1_adc2l_mux), 2744 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0, 2745 &rt5665_sto1_adc2r_mux), 2746 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0, 2747 &rt5665_sto1_adcl_mux), 2748 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0, 2749 &rt5665_sto1_adcr_mux), 2750 SND_SOC_DAPM_MUX("Stereo1 DD L Mux", SND_SOC_NOPM, 0, 0, 2751 &rt5665_sto1_dd_l_mux), 2752 SND_SOC_DAPM_MUX("Stereo1 DD R Mux", SND_SOC_NOPM, 0, 0, 2753 &rt5665_sto1_dd_r_mux), 2754 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0, 2755 &rt5665_mono_adc_l2_mux), 2756 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0, 2757 &rt5665_mono_adc_r2_mux), 2758 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0, 2759 &rt5665_mono_adc_l1_mux), 2760 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0, 2761 &rt5665_mono_adc_r1_mux), 2762 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0, 2763 &rt5665_mono_dmic_l_mux), 2764 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0, 2765 &rt5665_mono_dmic_r_mux), 2766 SND_SOC_DAPM_MUX("Mono ADC L Mux", SND_SOC_NOPM, 0, 0, 2767 &rt5665_mono_adc_l_mux), 2768 SND_SOC_DAPM_MUX("Mono ADC R Mux", SND_SOC_NOPM, 0, 0, 2769 &rt5665_mono_adc_r_mux), 2770 SND_SOC_DAPM_MUX("Mono DD L Mux", SND_SOC_NOPM, 0, 0, 2771 &rt5665_mono_dd_l_mux), 2772 SND_SOC_DAPM_MUX("Mono DD R Mux", SND_SOC_NOPM, 0, 0, 2773 &rt5665_mono_dd_r_mux), 2774 SND_SOC_DAPM_MUX("Stereo2 DMIC L Mux", SND_SOC_NOPM, 0, 0, 2775 &rt5665_sto2_dmic_mux), 2776 SND_SOC_DAPM_MUX("Stereo2 DMIC R Mux", SND_SOC_NOPM, 0, 0, 2777 &rt5665_sto2_dmic_mux), 2778 SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0, 2779 &rt5665_sto2_adc1l_mux), 2780 SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0, 2781 &rt5665_sto2_adc1r_mux), 2782 SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0, 2783 &rt5665_sto2_adc2l_mux), 2784 SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0, 2785 &rt5665_sto2_adc2r_mux), 2786 SND_SOC_DAPM_MUX("Stereo2 ADC L Mux", SND_SOC_NOPM, 0, 0, 2787 &rt5665_sto2_adcl_mux), 2788 SND_SOC_DAPM_MUX("Stereo2 ADC R Mux", SND_SOC_NOPM, 0, 0, 2789 &rt5665_sto2_adcr_mux), 2790 SND_SOC_DAPM_MUX("Stereo2 DD L Mux", SND_SOC_NOPM, 0, 0, 2791 &rt5665_sto2_dd_l_mux), 2792 SND_SOC_DAPM_MUX("Stereo2 DD R Mux", SND_SOC_NOPM, 0, 0, 2793 &rt5665_sto2_dd_r_mux), 2794 /* ADC Mixer */ 2795 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5665_PWR_DIG_2, 2796 RT5665_PWR_ADC_S1F_BIT, 0, NULL, 0), 2797 SND_SOC_DAPM_SUPPLY("ADC Stereo2 Filter", RT5665_PWR_DIG_2, 2798 RT5665_PWR_ADC_S2F_BIT, 0, NULL, 0), 2799 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5665_STO1_ADC_DIG_VOL, 2800 RT5665_L_MUTE_SFT, 1, rt5665_sto1_adc_l_mix, 2801 ARRAY_SIZE(rt5665_sto1_adc_l_mix)), 2802 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5665_STO1_ADC_DIG_VOL, 2803 RT5665_R_MUTE_SFT, 1, rt5665_sto1_adc_r_mix, 2804 ARRAY_SIZE(rt5665_sto1_adc_r_mix)), 2805 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXL", RT5665_STO2_ADC_DIG_VOL, 2806 RT5665_L_MUTE_SFT, 1, rt5665_sto2_adc_l_mix, 2807 ARRAY_SIZE(rt5665_sto2_adc_l_mix)), 2808 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXR", RT5665_STO2_ADC_DIG_VOL, 2809 RT5665_R_MUTE_SFT, 1, rt5665_sto2_adc_r_mix, 2810 ARRAY_SIZE(rt5665_sto2_adc_r_mix)), 2811 SND_SOC_DAPM_SUPPLY("ADC Mono Left Filter", RT5665_PWR_DIG_2, 2812 RT5665_PWR_ADC_MF_L_BIT, 0, NULL, 0), 2813 SND_SOC_DAPM_MIXER("Mono ADC MIXL", RT5665_MONO_ADC_DIG_VOL, 2814 RT5665_L_MUTE_SFT, 1, rt5665_mono_adc_l_mix, 2815 ARRAY_SIZE(rt5665_mono_adc_l_mix)), 2816 SND_SOC_DAPM_SUPPLY("ADC Mono Right Filter", RT5665_PWR_DIG_2, 2817 RT5665_PWR_ADC_MF_R_BIT, 0, NULL, 0), 2818 SND_SOC_DAPM_MIXER("Mono ADC MIXR", RT5665_MONO_ADC_DIG_VOL, 2819 RT5665_R_MUTE_SFT, 1, rt5665_mono_adc_r_mix, 2820 ARRAY_SIZE(rt5665_mono_adc_r_mix)), 2821 2822 /* ADC PGA */ 2823 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2824 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2825 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2826 2827 /* Digital Interface */ 2828 SND_SOC_DAPM_SUPPLY("I2S1_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_1_BIT, 2829 0, NULL, 0), 2830 SND_SOC_DAPM_SUPPLY("I2S1_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_2_BIT, 2831 0, NULL, 0), 2832 SND_SOC_DAPM_SUPPLY("I2S2_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_1_BIT, 2833 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU | 2834 SND_SOC_DAPM_POST_PMD), 2835 SND_SOC_DAPM_SUPPLY("I2S2_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_2_BIT, 2836 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU | 2837 SND_SOC_DAPM_POST_PMD), 2838 SND_SOC_DAPM_SUPPLY("I2S3", RT5665_PWR_DIG_1, RT5665_PWR_I2S3_BIT, 2839 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU | 2840 SND_SOC_DAPM_POST_PMD), 2841 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2842 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2843 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2844 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0), 2845 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0), 2846 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0), 2847 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0), 2848 SND_SOC_DAPM_PGA("IF1 DAC3 L", SND_SOC_NOPM, 0, 0, NULL, 0), 2849 SND_SOC_DAPM_PGA("IF1 DAC3 R", SND_SOC_NOPM, 0, 0, NULL, 0), 2850 2851 SND_SOC_DAPM_PGA("IF2_1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 2852 SND_SOC_DAPM_PGA("IF2_2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 2853 SND_SOC_DAPM_PGA("IF2_1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 2854 SND_SOC_DAPM_PGA("IF2_1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 2855 SND_SOC_DAPM_PGA("IF2_2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 2856 SND_SOC_DAPM_PGA("IF2_2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 2857 SND_SOC_DAPM_PGA("IF2_1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2858 SND_SOC_DAPM_PGA("IF2_2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2859 2860 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 2861 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 2862 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 2863 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2864 2865 /* Digital Interface Select */ 2866 SND_SOC_DAPM_MUX("IF1_1_ADC1 Mux", SND_SOC_NOPM, 0, 0, 2867 &rt5665_if1_1_adc1_mux), 2868 SND_SOC_DAPM_MUX("IF1_1_ADC2 Mux", SND_SOC_NOPM, 0, 0, 2869 &rt5665_if1_1_adc2_mux), 2870 SND_SOC_DAPM_MUX("IF1_1_ADC3 Mux", SND_SOC_NOPM, 0, 0, 2871 &rt5665_if1_1_adc3_mux), 2872 SND_SOC_DAPM_PGA("IF1_1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), 2873 SND_SOC_DAPM_MUX("IF1_2_ADC1 Mux", SND_SOC_NOPM, 0, 0, 2874 &rt5665_if1_2_adc1_mux), 2875 SND_SOC_DAPM_MUX("IF1_2_ADC2 Mux", SND_SOC_NOPM, 0, 0, 2876 &rt5665_if1_2_adc2_mux), 2877 SND_SOC_DAPM_MUX("IF1_2_ADC3 Mux", SND_SOC_NOPM, 0, 0, 2878 &rt5665_if1_2_adc3_mux), 2879 SND_SOC_DAPM_MUX("IF1_2_ADC4 Mux", SND_SOC_NOPM, 0, 0, 2880 &rt5665_if1_2_adc4_mux), 2881 SND_SOC_DAPM_MUX("TDM1 slot 01 Data Mux", SND_SOC_NOPM, 0, 0, 2882 &rt5665_tdm1_adc_mux), 2883 SND_SOC_DAPM_MUX("TDM1 slot 23 Data Mux", SND_SOC_NOPM, 0, 0, 2884 &rt5665_tdm1_adc_mux), 2885 SND_SOC_DAPM_MUX("TDM1 slot 45 Data Mux", SND_SOC_NOPM, 0, 0, 2886 &rt5665_tdm1_adc_mux), 2887 SND_SOC_DAPM_MUX("TDM1 slot 67 Data Mux", SND_SOC_NOPM, 0, 0, 2888 &rt5665_tdm1_adc_mux), 2889 SND_SOC_DAPM_MUX("TDM2 slot 01 Data Mux", SND_SOC_NOPM, 0, 0, 2890 &rt5665_tdm2_adc_mux), 2891 SND_SOC_DAPM_MUX("TDM2 slot 23 Data Mux", SND_SOC_NOPM, 0, 0, 2892 &rt5665_tdm2_adc_mux), 2893 SND_SOC_DAPM_MUX("TDM2 slot 45 Data Mux", SND_SOC_NOPM, 0, 0, 2894 &rt5665_tdm2_adc_mux), 2895 SND_SOC_DAPM_MUX("TDM2 slot 67 Data Mux", SND_SOC_NOPM, 0, 0, 2896 &rt5665_tdm2_adc_mux), 2897 SND_SOC_DAPM_MUX("IF2_1 ADC Mux", SND_SOC_NOPM, 0, 0, 2898 &rt5665_if2_1_adc_in_mux), 2899 SND_SOC_DAPM_MUX("IF2_2 ADC Mux", SND_SOC_NOPM, 0, 0, 2900 &rt5665_if2_2_adc_in_mux), 2901 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0, 2902 &rt5665_if3_adc_in_mux), 2903 SND_SOC_DAPM_MUX("IF1_1 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 2904 &rt5665_if1_1_01_adc_swap_mux), 2905 SND_SOC_DAPM_MUX("IF1_1 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 2906 &rt5665_if1_1_01_adc_swap_mux), 2907 SND_SOC_DAPM_MUX("IF1_1 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 2908 &rt5665_if1_1_23_adc_swap_mux), 2909 SND_SOC_DAPM_MUX("IF1_1 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 2910 &rt5665_if1_1_23_adc_swap_mux), 2911 SND_SOC_DAPM_MUX("IF1_1 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 2912 &rt5665_if1_1_45_adc_swap_mux), 2913 SND_SOC_DAPM_MUX("IF1_1 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 2914 &rt5665_if1_1_45_adc_swap_mux), 2915 SND_SOC_DAPM_MUX("IF1_1 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 2916 &rt5665_if1_1_67_adc_swap_mux), 2917 SND_SOC_DAPM_MUX("IF1_1 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 2918 &rt5665_if1_1_67_adc_swap_mux), 2919 SND_SOC_DAPM_MUX("IF1_2 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 2920 &rt5665_if1_2_01_adc_swap_mux), 2921 SND_SOC_DAPM_MUX("IF1_2 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 2922 &rt5665_if1_2_01_adc_swap_mux), 2923 SND_SOC_DAPM_MUX("IF1_2 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 2924 &rt5665_if1_2_23_adc_swap_mux), 2925 SND_SOC_DAPM_MUX("IF1_2 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 2926 &rt5665_if1_2_23_adc_swap_mux), 2927 SND_SOC_DAPM_MUX("IF1_2 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 2928 &rt5665_if1_2_45_adc_swap_mux), 2929 SND_SOC_DAPM_MUX("IF1_2 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 2930 &rt5665_if1_2_45_adc_swap_mux), 2931 SND_SOC_DAPM_MUX("IF1_2 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 2932 &rt5665_if1_2_67_adc_swap_mux), 2933 SND_SOC_DAPM_MUX("IF1_2 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 2934 &rt5665_if1_2_67_adc_swap_mux), 2935 SND_SOC_DAPM_MUX("IF2_1 DAC Swap Mux", SND_SOC_NOPM, 0, 0, 2936 &rt5665_if2_1_dac_swap_mux), 2937 SND_SOC_DAPM_MUX("IF2_1 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 2938 &rt5665_if2_1_adc_swap_mux), 2939 SND_SOC_DAPM_MUX("IF2_2 DAC Swap Mux", SND_SOC_NOPM, 0, 0, 2940 &rt5665_if2_2_dac_swap_mux), 2941 SND_SOC_DAPM_MUX("IF2_2 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 2942 &rt5665_if2_2_adc_swap_mux), 2943 SND_SOC_DAPM_MUX("IF3 DAC Swap Mux", SND_SOC_NOPM, 0, 0, 2944 &rt5665_if3_dac_swap_mux), 2945 SND_SOC_DAPM_MUX("IF3 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 2946 &rt5665_if3_adc_swap_mux), 2947 2948 /* Audio Interface */ 2949 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 0", "AIF1_1 Capture", 2950 0, SND_SOC_NOPM, 0, 0), 2951 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 1", "AIF1_1 Capture", 2952 1, SND_SOC_NOPM, 0, 0), 2953 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 2", "AIF1_1 Capture", 2954 2, SND_SOC_NOPM, 0, 0), 2955 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 3", "AIF1_1 Capture", 2956 3, SND_SOC_NOPM, 0, 0), 2957 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 4", "AIF1_1 Capture", 2958 4, SND_SOC_NOPM, 0, 0), 2959 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 5", "AIF1_1 Capture", 2960 5, SND_SOC_NOPM, 0, 0), 2961 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 6", "AIF1_1 Capture", 2962 6, SND_SOC_NOPM, 0, 0), 2963 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 7", "AIF1_1 Capture", 2964 7, SND_SOC_NOPM, 0, 0), 2965 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 0", "AIF1_2 Capture", 2966 0, SND_SOC_NOPM, 0, 0), 2967 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 1", "AIF1_2 Capture", 2968 1, SND_SOC_NOPM, 0, 0), 2969 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 2", "AIF1_2 Capture", 2970 2, SND_SOC_NOPM, 0, 0), 2971 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 3", "AIF1_2 Capture", 2972 3, SND_SOC_NOPM, 0, 0), 2973 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 4", "AIF1_2 Capture", 2974 4, SND_SOC_NOPM, 0, 0), 2975 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 5", "AIF1_2 Capture", 2976 5, SND_SOC_NOPM, 0, 0), 2977 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 6", "AIF1_2 Capture", 2978 6, SND_SOC_NOPM, 0, 0), 2979 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 7", "AIF1_2 Capture", 2980 7, SND_SOC_NOPM, 0, 0), 2981 SND_SOC_DAPM_AIF_OUT("AIF2_1TX", "AIF2_1 Capture", 2982 0, SND_SOC_NOPM, 0, 0), 2983 SND_SOC_DAPM_AIF_OUT("AIF2_2TX", "AIF2_2 Capture", 2984 0, SND_SOC_NOPM, 0, 0), 2985 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 2986 0, SND_SOC_NOPM, 0, 0), 2987 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 2988 0, SND_SOC_NOPM, 0, 0), 2989 SND_SOC_DAPM_AIF_IN("AIF2_1RX", "AIF2_1 Playback", 2990 0, SND_SOC_NOPM, 0, 0), 2991 SND_SOC_DAPM_AIF_IN("AIF2_2RX", "AIF2_2 Playback", 2992 0, SND_SOC_NOPM, 0, 0), 2993 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 2994 0, SND_SOC_NOPM, 0, 0), 2995 2996 /* Output Side */ 2997 /* DAC mixer before sound effect */ 2998 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 2999 rt5665_dac_l_mix, ARRAY_SIZE(rt5665_dac_l_mix)), 3000 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 3001 rt5665_dac_r_mix, ARRAY_SIZE(rt5665_dac_r_mix)), 3002 3003 /* DAC channel Mux */ 3004 SND_SOC_DAPM_MUX("DAC L1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l1_mux), 3005 SND_SOC_DAPM_MUX("DAC R1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r1_mux), 3006 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l2_mux), 3007 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r2_mux), 3008 SND_SOC_DAPM_MUX("DAC L3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l3_mux), 3009 SND_SOC_DAPM_MUX("DAC R3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r3_mux), 3010 3011 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0, 3012 &rt5665_alg_dac_l1_mux), 3013 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0, 3014 &rt5665_alg_dac_r1_mux), 3015 SND_SOC_DAPM_MUX("DAC L2 Source", SND_SOC_NOPM, 0, 0, 3016 &rt5665_alg_dac_l2_mux), 3017 SND_SOC_DAPM_MUX("DAC R2 Source", SND_SOC_NOPM, 0, 0, 3018 &rt5665_alg_dac_r2_mux), 3019 3020 /* DAC Mixer */ 3021 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5665_PWR_DIG_2, 3022 RT5665_PWR_DAC_S1F_BIT, 0, NULL, 0), 3023 SND_SOC_DAPM_SUPPLY("DAC Stereo2 Filter", RT5665_PWR_DIG_2, 3024 RT5665_PWR_DAC_S2F_BIT, 0, NULL, 0), 3025 SND_SOC_DAPM_SUPPLY("DAC Mono Left Filter", RT5665_PWR_DIG_2, 3026 RT5665_PWR_DAC_MF_L_BIT, 0, NULL, 0), 3027 SND_SOC_DAPM_SUPPLY("DAC Mono Right Filter", RT5665_PWR_DIG_2, 3028 RT5665_PWR_DAC_MF_R_BIT, 0, NULL, 0), 3029 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0, 3030 rt5665_sto1_dac_l_mix, ARRAY_SIZE(rt5665_sto1_dac_l_mix)), 3031 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0, 3032 rt5665_sto1_dac_r_mix, ARRAY_SIZE(rt5665_sto1_dac_r_mix)), 3033 SND_SOC_DAPM_MIXER("Stereo2 DAC MIXL", SND_SOC_NOPM, 0, 0, 3034 rt5665_sto2_dac_l_mix, ARRAY_SIZE(rt5665_sto2_dac_l_mix)), 3035 SND_SOC_DAPM_MIXER("Stereo2 DAC MIXR", SND_SOC_NOPM, 0, 0, 3036 rt5665_sto2_dac_r_mix, ARRAY_SIZE(rt5665_sto2_dac_r_mix)), 3037 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0, 3038 rt5665_mono_dac_l_mix, ARRAY_SIZE(rt5665_mono_dac_l_mix)), 3039 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0, 3040 rt5665_mono_dac_r_mix, ARRAY_SIZE(rt5665_mono_dac_r_mix)), 3041 SND_SOC_DAPM_MUX("DAC MIXL", SND_SOC_NOPM, 0, 0, 3042 &rt5665_dig_dac_mixl_mux), 3043 SND_SOC_DAPM_MUX("DAC MIXR", SND_SOC_NOPM, 0, 0, 3044 &rt5665_dig_dac_mixr_mux), 3045 3046 /* DACs */ 3047 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0), 3048 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0), 3049 3050 SND_SOC_DAPM_SUPPLY("DAC L2 Power", RT5665_PWR_DIG_1, 3051 RT5665_PWR_DAC_L2_BIT, 0, NULL, 0), 3052 SND_SOC_DAPM_SUPPLY("DAC R2 Power", RT5665_PWR_DIG_1, 3053 RT5665_PWR_DAC_R2_BIT, 0, NULL, 0), 3054 SND_SOC_DAPM_DAC("DAC L2", NULL, SND_SOC_NOPM, 0, 0), 3055 SND_SOC_DAPM_DAC("DAC R2", NULL, SND_SOC_NOPM, 0, 0), 3056 SND_SOC_DAPM_PGA("DAC1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 3057 3058 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 1, RT5665_CHOP_DAC, 3059 RT5665_CKGEN_DAC1_SFT, 0, NULL, 0), 3060 SND_SOC_DAPM_SUPPLY_S("DAC 2 Clock", 1, RT5665_CHOP_DAC, 3061 RT5665_CKGEN_DAC2_SFT, 0, NULL, 0), 3062 3063 /* OUT Mixer */ 3064 SND_SOC_DAPM_MIXER("MONOVOL MIX", RT5665_PWR_MIXER, RT5665_PWR_MM_BIT, 3065 0, rt5665_monovol_mix, ARRAY_SIZE(rt5665_monovol_mix)), 3066 SND_SOC_DAPM_MIXER("OUT MIXL", RT5665_PWR_MIXER, RT5665_PWR_OM_L_BIT, 3067 0, rt5665_out_l_mix, ARRAY_SIZE(rt5665_out_l_mix)), 3068 SND_SOC_DAPM_MIXER("OUT MIXR", RT5665_PWR_MIXER, RT5665_PWR_OM_R_BIT, 3069 0, rt5665_out_r_mix, ARRAY_SIZE(rt5665_out_r_mix)), 3070 3071 /* Output Volume */ 3072 SND_SOC_DAPM_SWITCH("MONOVOL", RT5665_PWR_VOL, RT5665_PWR_MV_BIT, 0, 3073 &monovol_switch), 3074 SND_SOC_DAPM_SWITCH("OUTVOL L", RT5665_PWR_VOL, RT5665_PWR_OV_L_BIT, 0, 3075 &outvol_l_switch), 3076 SND_SOC_DAPM_SWITCH("OUTVOL R", RT5665_PWR_VOL, RT5665_PWR_OV_R_BIT, 0, 3077 &outvol_r_switch), 3078 3079 /* MONO/HPO/LOUT */ 3080 SND_SOC_DAPM_MIXER("Mono MIX", SND_SOC_NOPM, 0, 0, rt5665_mono_mix, 3081 ARRAY_SIZE(rt5665_mono_mix)), 3082 SND_SOC_DAPM_MIXER("LOUT L MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_l_mix, 3083 ARRAY_SIZE(rt5665_lout_l_mix)), 3084 SND_SOC_DAPM_MIXER("LOUT R MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_r_mix, 3085 ARRAY_SIZE(rt5665_lout_r_mix)), 3086 SND_SOC_DAPM_PGA_S("Mono Amp", 1, RT5665_PWR_ANLG_1, RT5665_PWR_MA_BIT, 3087 0, rt5665_mono_event, SND_SOC_DAPM_POST_PMD | 3088 SND_SOC_DAPM_PRE_PMU), 3089 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5665_hp_event, 3090 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU), 3091 SND_SOC_DAPM_PGA_S("LOUT Amp", 1, RT5665_PWR_ANLG_1, 3092 RT5665_PWR_LM_BIT, 0, rt5665_lout_event, 3093 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD | 3094 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU), 3095 3096 SND_SOC_DAPM_SUPPLY("Charge Pump", SND_SOC_NOPM, 0, 0, 3097 rt5665_charge_pump_event, SND_SOC_DAPM_PRE_PMU | 3098 SND_SOC_DAPM_POST_PMD), 3099 3100 SND_SOC_DAPM_SWITCH("Mono Playback", SND_SOC_NOPM, 0, 0, 3101 &mono_switch), 3102 SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0, 3103 &hpo_switch), 3104 SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0, 3105 &lout_l_switch), 3106 SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0, 3107 &lout_r_switch), 3108 SND_SOC_DAPM_SWITCH("PDM L Playback", SND_SOC_NOPM, 0, 0, 3109 &pdm_l_switch), 3110 SND_SOC_DAPM_SWITCH("PDM R Playback", SND_SOC_NOPM, 0, 0, 3111 &pdm_r_switch), 3112 3113 /* PDM */ 3114 SND_SOC_DAPM_SUPPLY("PDM Power", RT5665_PWR_DIG_2, 3115 RT5665_PWR_PDM1_BIT, 0, NULL, 0), 3116 SND_SOC_DAPM_MUX("PDM L Mux", SND_SOC_NOPM, 3117 0, 1, &rt5665_pdm_l_mux), 3118 SND_SOC_DAPM_MUX("PDM R Mux", SND_SOC_NOPM, 3119 0, 1, &rt5665_pdm_r_mux), 3120 3121 /* CLK DET */ 3122 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5665_CLK_DET, RT5665_SYS_CLK_DET, 3123 0, NULL, 0), 3124 SND_SOC_DAPM_SUPPLY("CLKDET HP", RT5665_CLK_DET, RT5665_HP_CLK_DET, 3125 0, NULL, 0), 3126 SND_SOC_DAPM_SUPPLY("CLKDET MONO", RT5665_CLK_DET, RT5665_MONO_CLK_DET, 3127 0, NULL, 0), 3128 SND_SOC_DAPM_SUPPLY("CLKDET LOUT", RT5665_CLK_DET, RT5665_LOUT_CLK_DET, 3129 0, NULL, 0), 3130 SND_SOC_DAPM_SUPPLY("CLKDET", RT5665_CLK_DET, RT5665_POW_CLK_DET, 3131 0, NULL, 0), 3132 3133 /* Output Lines */ 3134 SND_SOC_DAPM_OUTPUT("HPOL"), 3135 SND_SOC_DAPM_OUTPUT("HPOR"), 3136 SND_SOC_DAPM_OUTPUT("LOUTL"), 3137 SND_SOC_DAPM_OUTPUT("LOUTR"), 3138 SND_SOC_DAPM_OUTPUT("MONOOUT"), 3139 SND_SOC_DAPM_OUTPUT("PDML"), 3140 SND_SOC_DAPM_OUTPUT("PDMR"), 3141 }; 3142 3143 static const struct snd_soc_dapm_route rt5665_dapm_routes[] = { 3144 /*PLL*/ 3145 {"ADC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll}, 3146 {"ADC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll}, 3147 {"ADC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll}, 3148 {"ADC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll}, 3149 {"DAC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll}, 3150 {"DAC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll}, 3151 {"DAC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll}, 3152 {"DAC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll}, 3153 3154 /*ASRC*/ 3155 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc}, 3156 {"ADC Stereo2 Filter", NULL, "ADC STO2 ASRC", is_using_asrc}, 3157 {"ADC Mono Left Filter", NULL, "ADC Mono L ASRC", is_using_asrc}, 3158 {"ADC Mono Right Filter", NULL, "ADC Mono R ASRC", is_using_asrc}, 3159 {"DAC Mono Left Filter", NULL, "DAC Mono L ASRC", is_using_asrc}, 3160 {"DAC Mono Right Filter", NULL, "DAC Mono R ASRC", is_using_asrc}, 3161 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc}, 3162 {"DAC Stereo2 Filter", NULL, "DAC STO2 ASRC", is_using_asrc}, 3163 {"I2S1 ASRC", NULL, "CLKDET"}, 3164 {"I2S2 ASRC", NULL, "CLKDET"}, 3165 {"I2S3 ASRC", NULL, "CLKDET"}, 3166 3167 /*Vref*/ 3168 {"Mic Det Power", NULL, "Vref2"}, 3169 {"MICBIAS1", NULL, "Vref1"}, 3170 {"MICBIAS1", NULL, "Vref2"}, 3171 {"MICBIAS2", NULL, "Vref1"}, 3172 {"MICBIAS2", NULL, "Vref2"}, 3173 {"MICBIAS3", NULL, "Vref1"}, 3174 {"MICBIAS3", NULL, "Vref2"}, 3175 3176 {"Stereo1 DMIC L Mux", NULL, "DMIC STO1 ASRC"}, 3177 {"Stereo1 DMIC R Mux", NULL, "DMIC STO1 ASRC"}, 3178 {"Stereo2 DMIC L Mux", NULL, "DMIC STO2 ASRC"}, 3179 {"Stereo2 DMIC R Mux", NULL, "DMIC STO2 ASRC"}, 3180 {"Mono DMIC L Mux", NULL, "DMIC MONO L ASRC"}, 3181 {"Mono DMIC R Mux", NULL, "DMIC MONO R ASRC"}, 3182 3183 {"I2S1_1", NULL, "I2S1 ASRC"}, 3184 {"I2S1_2", NULL, "I2S1 ASRC"}, 3185 {"I2S2_1", NULL, "I2S2 ASRC"}, 3186 {"I2S2_2", NULL, "I2S2 ASRC"}, 3187 {"I2S3", NULL, "I2S3 ASRC"}, 3188 3189 {"CLKDET SYS", NULL, "CLKDET"}, 3190 {"CLKDET HP", NULL, "CLKDET"}, 3191 {"CLKDET MONO", NULL, "CLKDET"}, 3192 {"CLKDET LOUT", NULL, "CLKDET"}, 3193 3194 {"IN1P", NULL, "LDO2"}, 3195 {"IN2P", NULL, "LDO2"}, 3196 {"IN3P", NULL, "LDO2"}, 3197 {"IN4P", NULL, "LDO2"}, 3198 3199 {"DMIC1", NULL, "DMIC L1"}, 3200 {"DMIC1", NULL, "DMIC R1"}, 3201 {"DMIC2", NULL, "DMIC L2"}, 3202 {"DMIC2", NULL, "DMIC R2"}, 3203 3204 {"BST1", NULL, "IN1P"}, 3205 {"BST1", NULL, "IN1N"}, 3206 {"BST1", NULL, "BST1 Power"}, 3207 {"BST1", NULL, "BST1P Power"}, 3208 {"BST2", NULL, "IN2P"}, 3209 {"BST2", NULL, "IN2N"}, 3210 {"BST2", NULL, "BST2 Power"}, 3211 {"BST2", NULL, "BST2P Power"}, 3212 {"BST3", NULL, "IN3P"}, 3213 {"BST3", NULL, "IN3N"}, 3214 {"BST3", NULL, "BST3 Power"}, 3215 {"BST3", NULL, "BST3P Power"}, 3216 {"BST4", NULL, "IN4P"}, 3217 {"BST4", NULL, "IN4N"}, 3218 {"BST4", NULL, "BST4 Power"}, 3219 {"BST4", NULL, "BST4P Power"}, 3220 {"BST1 CBJ", NULL, "IN1P"}, 3221 {"BST1 CBJ", NULL, "IN1N"}, 3222 {"BST1 CBJ", NULL, "CBJ Power"}, 3223 {"CBJ Power", NULL, "Vref2"}, 3224 3225 {"INL VOL", NULL, "IN3P"}, 3226 {"INR VOL", NULL, "IN3N"}, 3227 3228 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"}, 3229 {"RECMIX1L", "INL Switch", "INL VOL"}, 3230 {"RECMIX1L", "INR Switch", "INR VOL"}, 3231 {"RECMIX1L", "BST4 Switch", "BST4"}, 3232 {"RECMIX1L", "BST3 Switch", "BST3"}, 3233 {"RECMIX1L", "BST2 Switch", "BST2"}, 3234 {"RECMIX1L", "BST1 Switch", "BST1"}, 3235 {"RECMIX1L", NULL, "RECMIX1L Power"}, 3236 3237 {"RECMIX1R", "MONOVOL Switch", "MONOVOL"}, 3238 {"RECMIX1R", "INR Switch", "INR VOL"}, 3239 {"RECMIX1R", "BST4 Switch", "BST4"}, 3240 {"RECMIX1R", "BST3 Switch", "BST3"}, 3241 {"RECMIX1R", "BST2 Switch", "BST2"}, 3242 {"RECMIX1R", "BST1 Switch", "BST1"}, 3243 {"RECMIX1R", NULL, "RECMIX1R Power"}, 3244 3245 {"RECMIX2L", "CBJ Switch", "BST1 CBJ"}, 3246 {"RECMIX2L", "INL Switch", "INL VOL"}, 3247 {"RECMIX2L", "INR Switch", "INR VOL"}, 3248 {"RECMIX2L", "BST4 Switch", "BST4"}, 3249 {"RECMIX2L", "BST3 Switch", "BST3"}, 3250 {"RECMIX2L", "BST2 Switch", "BST2"}, 3251 {"RECMIX2L", "BST1 Switch", "BST1"}, 3252 {"RECMIX2L", NULL, "RECMIX2L Power"}, 3253 3254 {"RECMIX2R", "MONOVOL Switch", "MONOVOL"}, 3255 {"RECMIX2R", "INL Switch", "INL VOL"}, 3256 {"RECMIX2R", "INR Switch", "INR VOL"}, 3257 {"RECMIX2R", "BST4 Switch", "BST4"}, 3258 {"RECMIX2R", "BST3 Switch", "BST3"}, 3259 {"RECMIX2R", "BST2 Switch", "BST2"}, 3260 {"RECMIX2R", "BST1 Switch", "BST1"}, 3261 {"RECMIX2R", NULL, "RECMIX2R Power"}, 3262 3263 {"ADC1 L", NULL, "RECMIX1L"}, 3264 {"ADC1 L", NULL, "ADC1 L Power"}, 3265 {"ADC1 L", NULL, "ADC1 clock"}, 3266 {"ADC1 R", NULL, "RECMIX1R"}, 3267 {"ADC1 R", NULL, "ADC1 R Power"}, 3268 {"ADC1 R", NULL, "ADC1 clock"}, 3269 3270 {"ADC2 L", NULL, "RECMIX2L"}, 3271 {"ADC2 L", NULL, "ADC2 L Power"}, 3272 {"ADC2 L", NULL, "ADC2 clock"}, 3273 {"ADC2 R", NULL, "RECMIX2R"}, 3274 {"ADC2 R", NULL, "ADC2 R Power"}, 3275 {"ADC2 R", NULL, "ADC2 clock"}, 3276 3277 {"DMIC L1", NULL, "DMIC CLK"}, 3278 {"DMIC L1", NULL, "DMIC1 Power"}, 3279 {"DMIC R1", NULL, "DMIC CLK"}, 3280 {"DMIC R1", NULL, "DMIC1 Power"}, 3281 {"DMIC L2", NULL, "DMIC CLK"}, 3282 {"DMIC L2", NULL, "DMIC2 Power"}, 3283 {"DMIC R2", NULL, "DMIC CLK"}, 3284 {"DMIC R2", NULL, "DMIC2 Power"}, 3285 3286 {"Stereo1 DMIC L Mux", "DMIC1", "DMIC L1"}, 3287 {"Stereo1 DMIC L Mux", "DMIC2", "DMIC L2"}, 3288 3289 {"Stereo1 DMIC R Mux", "DMIC1", "DMIC R1"}, 3290 {"Stereo1 DMIC R Mux", "DMIC2", "DMIC R2"}, 3291 3292 {"Mono DMIC L Mux", "DMIC1 L", "DMIC L1"}, 3293 {"Mono DMIC L Mux", "DMIC2 L", "DMIC L2"}, 3294 3295 {"Mono DMIC R Mux", "DMIC1 R", "DMIC R1"}, 3296 {"Mono DMIC R Mux", "DMIC2 R", "DMIC R2"}, 3297 3298 {"Stereo2 DMIC L Mux", "DMIC1", "DMIC L1"}, 3299 {"Stereo2 DMIC L Mux", "DMIC2", "DMIC L2"}, 3300 3301 {"Stereo2 DMIC R Mux", "DMIC1", "DMIC R1"}, 3302 {"Stereo2 DMIC R Mux", "DMIC2", "DMIC R2"}, 3303 3304 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"}, 3305 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"}, 3306 {"Stereo1 ADC L Mux", "ADC2 L", "ADC2 L"}, 3307 {"Stereo1 ADC L Mux", "ADC2 R", "ADC2 R"}, 3308 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"}, 3309 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"}, 3310 {"Stereo1 ADC R Mux", "ADC2 L", "ADC2 L"}, 3311 {"Stereo1 ADC R Mux", "ADC2 R", "ADC2 R"}, 3312 3313 {"Stereo1 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"}, 3314 {"Stereo1 DD L Mux", "MONO DAC", "Mono DAC MIXL"}, 3315 3316 {"Stereo1 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"}, 3317 {"Stereo1 DD R Mux", "MONO DAC", "Mono DAC MIXR"}, 3318 3319 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"}, 3320 {"Stereo1 ADC L1 Mux", "DD Mux", "Stereo1 DD L Mux"}, 3321 {"Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC L Mux"}, 3322 {"Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL"}, 3323 3324 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"}, 3325 {"Stereo1 ADC R1 Mux", "DD Mux", "Stereo1 DD R Mux"}, 3326 {"Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC R Mux"}, 3327 {"Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR"}, 3328 3329 {"Mono ADC L Mux", "ADC1 L", "ADC1 L"}, 3330 {"Mono ADC L Mux", "ADC1 R", "ADC1 R"}, 3331 {"Mono ADC L Mux", "ADC2 L", "ADC2 L"}, 3332 {"Mono ADC L Mux", "ADC2 R", "ADC2 R"}, 3333 3334 {"Mono ADC R Mux", "ADC1 L", "ADC1 L"}, 3335 {"Mono ADC R Mux", "ADC1 R", "ADC1 R"}, 3336 {"Mono ADC R Mux", "ADC2 L", "ADC2 L"}, 3337 {"Mono ADC R Mux", "ADC2 R", "ADC2 R"}, 3338 3339 {"Mono DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"}, 3340 {"Mono DD L Mux", "MONO DAC", "Mono DAC MIXL"}, 3341 3342 {"Mono DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"}, 3343 {"Mono DD R Mux", "MONO DAC", "Mono DAC MIXR"}, 3344 3345 {"Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux"}, 3346 {"Mono ADC L2 Mux", "DAC MIXL", "DAC MIXL"}, 3347 {"Mono ADC L1 Mux", "DD Mux", "Mono DD L Mux"}, 3348 {"Mono ADC L1 Mux", "ADC", "Mono ADC L Mux"}, 3349 3350 {"Mono ADC R1 Mux", "DD Mux", "Mono DD R Mux"}, 3351 {"Mono ADC R1 Mux", "ADC", "Mono ADC R Mux"}, 3352 {"Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux"}, 3353 {"Mono ADC R2 Mux", "DAC MIXR", "DAC MIXR"}, 3354 3355 {"Stereo2 ADC L Mux", "ADC1 L", "ADC1 L"}, 3356 {"Stereo2 ADC L Mux", "ADC2 L", "ADC2 L"}, 3357 {"Stereo2 ADC L Mux", "ADC1 R", "ADC1 R"}, 3358 {"Stereo2 ADC R Mux", "ADC1 L", "ADC1 L"}, 3359 {"Stereo2 ADC R Mux", "ADC2 L", "ADC2 L"}, 3360 {"Stereo2 ADC R Mux", "ADC1 R", "ADC1 R"}, 3361 3362 {"Stereo2 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"}, 3363 {"Stereo2 DD L Mux", "MONO DAC", "Mono DAC MIXL"}, 3364 3365 {"Stereo2 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"}, 3366 {"Stereo2 DD R Mux", "MONO DAC", "Mono DAC MIXR"}, 3367 3368 {"Stereo2 ADC L1 Mux", "ADC", "Stereo2 ADC L Mux"}, 3369 {"Stereo2 ADC L1 Mux", "DD Mux", "Stereo2 DD L Mux"}, 3370 {"Stereo2 ADC L2 Mux", "DMIC", "Stereo2 DMIC L Mux"}, 3371 {"Stereo2 ADC L2 Mux", "DAC MIX", "DAC MIXL"}, 3372 3373 {"Stereo2 ADC R1 Mux", "ADC", "Stereo2 ADC R Mux"}, 3374 {"Stereo2 ADC R1 Mux", "DD Mux", "Stereo2 DD R Mux"}, 3375 {"Stereo2 ADC R2 Mux", "DMIC", "Stereo2 DMIC R Mux"}, 3376 {"Stereo2 ADC R2 Mux", "DAC MIX", "DAC MIXR"}, 3377 3378 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"}, 3379 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"}, 3380 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"}, 3381 3382 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"}, 3383 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"}, 3384 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"}, 3385 3386 {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"}, 3387 {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"}, 3388 {"Mono ADC MIXL", NULL, "ADC Mono Left Filter"}, 3389 3390 {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"}, 3391 {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"}, 3392 {"Mono ADC MIXR", NULL, "ADC Mono Right Filter"}, 3393 3394 {"Stereo2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux"}, 3395 {"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"}, 3396 {"Stereo2 ADC MIXL", NULL, "ADC Stereo2 Filter"}, 3397 3398 {"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"}, 3399 {"Stereo2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux"}, 3400 {"Stereo2 ADC MIXR", NULL, "ADC Stereo2 Filter"}, 3401 3402 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"}, 3403 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"}, 3404 {"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL"}, 3405 {"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR"}, 3406 {"Mono ADC MIX", NULL, "Mono ADC MIXL"}, 3407 {"Mono ADC MIX", NULL, "Mono ADC MIXR"}, 3408 3409 {"IF1_1_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"}, 3410 {"IF1_1_ADC1 Mux", "IF2_1 DAC", "IF2_1 DAC"}, 3411 {"IF1_1_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"}, 3412 {"IF1_1_ADC2 Mux", "IF2_2 DAC", "IF2_2 DAC"}, 3413 {"IF1_1_ADC3 Mux", "MONO ADC", "Mono ADC MIX"}, 3414 {"IF1_1_ADC3 Mux", "IF3 DAC", "IF3 DAC"}, 3415 {"IF1_1_ADC4", NULL, "DAC1 MIX"}, 3416 3417 {"IF1_2_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"}, 3418 {"IF1_2_ADC1 Mux", "IF1 DAC", "IF1 DAC1"}, 3419 {"IF1_2_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"}, 3420 {"IF1_2_ADC2 Mux", "IF2_1 DAC", "IF2_1 DAC"}, 3421 {"IF1_2_ADC3 Mux", "MONO ADC", "Mono ADC MIX"}, 3422 {"IF1_2_ADC3 Mux", "IF2_2 DAC", "IF2_2 DAC"}, 3423 {"IF1_2_ADC4 Mux", "DAC1", "DAC1 MIX"}, 3424 {"IF1_2_ADC4 Mux", "IF3 DAC", "IF3 DAC"}, 3425 3426 {"TDM1 slot 01 Data Mux", "1234", "IF1_1_ADC1 Mux"}, 3427 {"TDM1 slot 01 Data Mux", "1243", "IF1_1_ADC1 Mux"}, 3428 {"TDM1 slot 01 Data Mux", "1324", "IF1_1_ADC1 Mux"}, 3429 {"TDM1 slot 01 Data Mux", "1342", "IF1_1_ADC1 Mux"}, 3430 {"TDM1 slot 01 Data Mux", "1432", "IF1_1_ADC1 Mux"}, 3431 {"TDM1 slot 01 Data Mux", "1423", "IF1_1_ADC1 Mux"}, 3432 {"TDM1 slot 01 Data Mux", "2134", "IF1_1_ADC2 Mux"}, 3433 {"TDM1 slot 01 Data Mux", "2143", "IF1_1_ADC2 Mux"}, 3434 {"TDM1 slot 01 Data Mux", "2314", "IF1_1_ADC2 Mux"}, 3435 {"TDM1 slot 01 Data Mux", "2341", "IF1_1_ADC2 Mux"}, 3436 {"TDM1 slot 01 Data Mux", "2431", "IF1_1_ADC2 Mux"}, 3437 {"TDM1 slot 01 Data Mux", "2413", "IF1_1_ADC2 Mux"}, 3438 {"TDM1 slot 01 Data Mux", "3124", "IF1_1_ADC3 Mux"}, 3439 {"TDM1 slot 01 Data Mux", "3142", "IF1_1_ADC3 Mux"}, 3440 {"TDM1 slot 01 Data Mux", "3214", "IF1_1_ADC3 Mux"}, 3441 {"TDM1 slot 01 Data Mux", "3241", "IF1_1_ADC3 Mux"}, 3442 {"TDM1 slot 01 Data Mux", "3412", "IF1_1_ADC3 Mux"}, 3443 {"TDM1 slot 01 Data Mux", "3421", "IF1_1_ADC3 Mux"}, 3444 {"TDM1 slot 01 Data Mux", "4123", "IF1_1_ADC4"}, 3445 {"TDM1 slot 01 Data Mux", "4132", "IF1_1_ADC4"}, 3446 {"TDM1 slot 01 Data Mux", "4213", "IF1_1_ADC4"}, 3447 {"TDM1 slot 01 Data Mux", "4231", "IF1_1_ADC4"}, 3448 {"TDM1 slot 01 Data Mux", "4312", "IF1_1_ADC4"}, 3449 {"TDM1 slot 01 Data Mux", "4321", "IF1_1_ADC4"}, 3450 {"TDM1 slot 01 Data Mux", NULL, "I2S1_1"}, 3451 3452 {"TDM1 slot 23 Data Mux", "1234", "IF1_1_ADC2 Mux"}, 3453 {"TDM1 slot 23 Data Mux", "1243", "IF1_1_ADC2 Mux"}, 3454 {"TDM1 slot 23 Data Mux", "1324", "IF1_1_ADC3 Mux"}, 3455 {"TDM1 slot 23 Data Mux", "1342", "IF1_1_ADC3 Mux"}, 3456 {"TDM1 slot 23 Data Mux", "1432", "IF1_1_ADC4"}, 3457 {"TDM1 slot 23 Data Mux", "1423", "IF1_1_ADC4"}, 3458 {"TDM1 slot 23 Data Mux", "2134", "IF1_1_ADC1 Mux"}, 3459 {"TDM1 slot 23 Data Mux", "2143", "IF1_1_ADC1 Mux"}, 3460 {"TDM1 slot 23 Data Mux", "2314", "IF1_1_ADC3 Mux"}, 3461 {"TDM1 slot 23 Data Mux", "2341", "IF1_1_ADC3 Mux"}, 3462 {"TDM1 slot 23 Data Mux", "2431", "IF1_1_ADC4"}, 3463 {"TDM1 slot 23 Data Mux", "2413", "IF1_1_ADC4"}, 3464 {"TDM1 slot 23 Data Mux", "3124", "IF1_1_ADC1 Mux"}, 3465 {"TDM1 slot 23 Data Mux", "3142", "IF1_1_ADC1 Mux"}, 3466 {"TDM1 slot 23 Data Mux", "3214", "IF1_1_ADC2 Mux"}, 3467 {"TDM1 slot 23 Data Mux", "3241", "IF1_1_ADC2 Mux"}, 3468 {"TDM1 slot 23 Data Mux", "3412", "IF1_1_ADC4"}, 3469 {"TDM1 slot 23 Data Mux", "3421", "IF1_1_ADC4"}, 3470 {"TDM1 slot 23 Data Mux", "4123", "IF1_1_ADC1 Mux"}, 3471 {"TDM1 slot 23 Data Mux", "4132", "IF1_1_ADC1 Mux"}, 3472 {"TDM1 slot 23 Data Mux", "4213", "IF1_1_ADC2 Mux"}, 3473 {"TDM1 slot 23 Data Mux", "4231", "IF1_1_ADC2 Mux"}, 3474 {"TDM1 slot 23 Data Mux", "4312", "IF1_1_ADC3 Mux"}, 3475 {"TDM1 slot 23 Data Mux", "4321", "IF1_1_ADC3 Mux"}, 3476 {"TDM1 slot 23 Data Mux", NULL, "I2S1_1"}, 3477 3478 {"TDM1 slot 45 Data Mux", "1234", "IF1_1_ADC3 Mux"}, 3479 {"TDM1 slot 45 Data Mux", "1243", "IF1_1_ADC4"}, 3480 {"TDM1 slot 45 Data Mux", "1324", "IF1_1_ADC2 Mux"}, 3481 {"TDM1 slot 45 Data Mux", "1342", "IF1_1_ADC4"}, 3482 {"TDM1 slot 45 Data Mux", "1432", "IF1_1_ADC3 Mux"}, 3483 {"TDM1 slot 45 Data Mux", "1423", "IF1_1_ADC2 Mux"}, 3484 {"TDM1 slot 45 Data Mux", "2134", "IF1_1_ADC3 Mux"}, 3485 {"TDM1 slot 45 Data Mux", "2143", "IF1_1_ADC4"}, 3486 {"TDM1 slot 45 Data Mux", "2314", "IF1_1_ADC1 Mux"}, 3487 {"TDM1 slot 45 Data Mux", "2341", "IF1_1_ADC4"}, 3488 {"TDM1 slot 45 Data Mux", "2431", "IF1_1_ADC3 Mux"}, 3489 {"TDM1 slot 45 Data Mux", "2413", "IF1_1_ADC1 Mux"}, 3490 {"TDM1 slot 45 Data Mux", "3124", "IF1_1_ADC2 Mux"}, 3491 {"TDM1 slot 45 Data Mux", "3142", "IF1_1_ADC4"}, 3492 {"TDM1 slot 45 Data Mux", "3214", "IF1_1_ADC1 Mux"}, 3493 {"TDM1 slot 45 Data Mux", "3241", "IF1_1_ADC4"}, 3494 {"TDM1 slot 45 Data Mux", "3412", "IF1_1_ADC1 Mux"}, 3495 {"TDM1 slot 45 Data Mux", "3421", "IF1_1_ADC2 Mux"}, 3496 {"TDM1 slot 45 Data Mux", "4123", "IF1_1_ADC2 Mux"}, 3497 {"TDM1 slot 45 Data Mux", "4132", "IF1_1_ADC3 Mux"}, 3498 {"TDM1 slot 45 Data Mux", "4213", "IF1_1_ADC1 Mux"}, 3499 {"TDM1 slot 45 Data Mux", "4231", "IF1_1_ADC3 Mux"}, 3500 {"TDM1 slot 45 Data Mux", "4312", "IF1_1_ADC1 Mux"}, 3501 {"TDM1 slot 45 Data Mux", "4321", "IF1_1_ADC2 Mux"}, 3502 {"TDM1 slot 45 Data Mux", NULL, "I2S1_1"}, 3503 3504 {"TDM1 slot 67 Data Mux", "1234", "IF1_1_ADC4"}, 3505 {"TDM1 slot 67 Data Mux", "1243", "IF1_1_ADC3 Mux"}, 3506 {"TDM1 slot 67 Data Mux", "1324", "IF1_1_ADC4"}, 3507 {"TDM1 slot 67 Data Mux", "1342", "IF1_1_ADC2 Mux"}, 3508 {"TDM1 slot 67 Data Mux", "1432", "IF1_1_ADC2 Mux"}, 3509 {"TDM1 slot 67 Data Mux", "1423", "IF1_1_ADC3 Mux"}, 3510 {"TDM1 slot 67 Data Mux", "2134", "IF1_1_ADC4"}, 3511 {"TDM1 slot 67 Data Mux", "2143", "IF1_1_ADC3 Mux"}, 3512 {"TDM1 slot 67 Data Mux", "2314", "IF1_1_ADC4"}, 3513 {"TDM1 slot 67 Data Mux", "2341", "IF1_1_ADC1 Mux"}, 3514 {"TDM1 slot 67 Data Mux", "2431", "IF1_1_ADC1 Mux"}, 3515 {"TDM1 slot 67 Data Mux", "2413", "IF1_1_ADC3 Mux"}, 3516 {"TDM1 slot 67 Data Mux", "3124", "IF1_1_ADC4"}, 3517 {"TDM1 slot 67 Data Mux", "3142", "IF1_1_ADC2 Mux"}, 3518 {"TDM1 slot 67 Data Mux", "3214", "IF1_1_ADC4"}, 3519 {"TDM1 slot 67 Data Mux", "3241", "IF1_1_ADC1 Mux"}, 3520 {"TDM1 slot 67 Data Mux", "3412", "IF1_1_ADC2 Mux"}, 3521 {"TDM1 slot 67 Data Mux", "3421", "IF1_1_ADC1 Mux"}, 3522 {"TDM1 slot 67 Data Mux", "4123", "IF1_1_ADC3 Mux"}, 3523 {"TDM1 slot 67 Data Mux", "4132", "IF1_1_ADC2 Mux"}, 3524 {"TDM1 slot 67 Data Mux", "4213", "IF1_1_ADC3 Mux"}, 3525 {"TDM1 slot 67 Data Mux", "4231", "IF1_1_ADC1 Mux"}, 3526 {"TDM1 slot 67 Data Mux", "4312", "IF1_1_ADC2 Mux"}, 3527 {"TDM1 slot 67 Data Mux", "4321", "IF1_1_ADC1 Mux"}, 3528 {"TDM1 slot 67 Data Mux", NULL, "I2S1_1"}, 3529 3530 3531 {"TDM2 slot 01 Data Mux", "1234", "IF1_2_ADC1 Mux"}, 3532 {"TDM2 slot 01 Data Mux", "1243", "IF1_2_ADC1 Mux"}, 3533 {"TDM2 slot 01 Data Mux", "1324", "IF1_2_ADC1 Mux"}, 3534 {"TDM2 slot 01 Data Mux", "1342", "IF1_2_ADC1 Mux"}, 3535 {"TDM2 slot 01 Data Mux", "1432", "IF1_2_ADC1 Mux"}, 3536 {"TDM2 slot 01 Data Mux", "1423", "IF1_2_ADC1 Mux"}, 3537 {"TDM2 slot 01 Data Mux", "2134", "IF1_2_ADC2 Mux"}, 3538 {"TDM2 slot 01 Data Mux", "2143", "IF1_2_ADC2 Mux"}, 3539 {"TDM2 slot 01 Data Mux", "2314", "IF1_2_ADC2 Mux"}, 3540 {"TDM2 slot 01 Data Mux", "2341", "IF1_2_ADC2 Mux"}, 3541 {"TDM2 slot 01 Data Mux", "2431", "IF1_2_ADC2 Mux"}, 3542 {"TDM2 slot 01 Data Mux", "2413", "IF1_2_ADC2 Mux"}, 3543 {"TDM2 slot 01 Data Mux", "3124", "IF1_2_ADC3 Mux"}, 3544 {"TDM2 slot 01 Data Mux", "3142", "IF1_2_ADC3 Mux"}, 3545 {"TDM2 slot 01 Data Mux", "3214", "IF1_2_ADC3 Mux"}, 3546 {"TDM2 slot 01 Data Mux", "3241", "IF1_2_ADC3 Mux"}, 3547 {"TDM2 slot 01 Data Mux", "3412", "IF1_2_ADC3 Mux"}, 3548 {"TDM2 slot 01 Data Mux", "3421", "IF1_2_ADC3 Mux"}, 3549 {"TDM2 slot 01 Data Mux", "4123", "IF1_2_ADC4 Mux"}, 3550 {"TDM2 slot 01 Data Mux", "4132", "IF1_2_ADC4 Mux"}, 3551 {"TDM2 slot 01 Data Mux", "4213", "IF1_2_ADC4 Mux"}, 3552 {"TDM2 slot 01 Data Mux", "4231", "IF1_2_ADC4 Mux"}, 3553 {"TDM2 slot 01 Data Mux", "4312", "IF1_2_ADC4 Mux"}, 3554 {"TDM2 slot 01 Data Mux", "4321", "IF1_2_ADC4 Mux"}, 3555 {"TDM2 slot 01 Data Mux", NULL, "I2S1_2"}, 3556 3557 {"TDM2 slot 23 Data Mux", "1234", "IF1_2_ADC2 Mux"}, 3558 {"TDM2 slot 23 Data Mux", "1243", "IF1_2_ADC2 Mux"}, 3559 {"TDM2 slot 23 Data Mux", "1324", "IF1_2_ADC3 Mux"}, 3560 {"TDM2 slot 23 Data Mux", "1342", "IF1_2_ADC3 Mux"}, 3561 {"TDM2 slot 23 Data Mux", "1432", "IF1_2_ADC4 Mux"}, 3562 {"TDM2 slot 23 Data Mux", "1423", "IF1_2_ADC4 Mux"}, 3563 {"TDM2 slot 23 Data Mux", "2134", "IF1_2_ADC1 Mux"}, 3564 {"TDM2 slot 23 Data Mux", "2143", "IF1_2_ADC1 Mux"}, 3565 {"TDM2 slot 23 Data Mux", "2314", "IF1_2_ADC3 Mux"}, 3566 {"TDM2 slot 23 Data Mux", "2341", "IF1_2_ADC3 Mux"}, 3567 {"TDM2 slot 23 Data Mux", "2431", "IF1_2_ADC4 Mux"}, 3568 {"TDM2 slot 23 Data Mux", "2413", "IF1_2_ADC4 Mux"}, 3569 {"TDM2 slot 23 Data Mux", "3124", "IF1_2_ADC1 Mux"}, 3570 {"TDM2 slot 23 Data Mux", "3142", "IF1_2_ADC1 Mux"}, 3571 {"TDM2 slot 23 Data Mux", "3214", "IF1_2_ADC2 Mux"}, 3572 {"TDM2 slot 23 Data Mux", "3241", "IF1_2_ADC2 Mux"}, 3573 {"TDM2 slot 23 Data Mux", "3412", "IF1_2_ADC4 Mux"}, 3574 {"TDM2 slot 23 Data Mux", "3421", "IF1_2_ADC4 Mux"}, 3575 {"TDM2 slot 23 Data Mux", "4123", "IF1_2_ADC1 Mux"}, 3576 {"TDM2 slot 23 Data Mux", "4132", "IF1_2_ADC1 Mux"}, 3577 {"TDM2 slot 23 Data Mux", "4213", "IF1_2_ADC2 Mux"}, 3578 {"TDM2 slot 23 Data Mux", "4231", "IF1_2_ADC2 Mux"}, 3579 {"TDM2 slot 23 Data Mux", "4312", "IF1_2_ADC3 Mux"}, 3580 {"TDM2 slot 23 Data Mux", "4321", "IF1_2_ADC3 Mux"}, 3581 {"TDM2 slot 23 Data Mux", NULL, "I2S1_2"}, 3582 3583 {"TDM2 slot 45 Data Mux", "1234", "IF1_2_ADC3 Mux"}, 3584 {"TDM2 slot 45 Data Mux", "1243", "IF1_2_ADC4 Mux"}, 3585 {"TDM2 slot 45 Data Mux", "1324", "IF1_2_ADC2 Mux"}, 3586 {"TDM2 slot 45 Data Mux", "1342", "IF1_2_ADC4 Mux"}, 3587 {"TDM2 slot 45 Data Mux", "1432", "IF1_2_ADC3 Mux"}, 3588 {"TDM2 slot 45 Data Mux", "1423", "IF1_2_ADC2 Mux"}, 3589 {"TDM2 slot 45 Data Mux", "2134", "IF1_2_ADC3 Mux"}, 3590 {"TDM2 slot 45 Data Mux", "2143", "IF1_2_ADC4 Mux"}, 3591 {"TDM2 slot 45 Data Mux", "2314", "IF1_2_ADC1 Mux"}, 3592 {"TDM2 slot 45 Data Mux", "2341", "IF1_2_ADC4 Mux"}, 3593 {"TDM2 slot 45 Data Mux", "2431", "IF1_2_ADC3 Mux"}, 3594 {"TDM2 slot 45 Data Mux", "2413", "IF1_2_ADC1 Mux"}, 3595 {"TDM2 slot 45 Data Mux", "3124", "IF1_2_ADC2 Mux"}, 3596 {"TDM2 slot 45 Data Mux", "3142", "IF1_2_ADC4 Mux"}, 3597 {"TDM2 slot 45 Data Mux", "3214", "IF1_2_ADC1 Mux"}, 3598 {"TDM2 slot 45 Data Mux", "3241", "IF1_2_ADC4 Mux"}, 3599 {"TDM2 slot 45 Data Mux", "3412", "IF1_2_ADC1 Mux"}, 3600 {"TDM2 slot 45 Data Mux", "3421", "IF1_2_ADC2 Mux"}, 3601 {"TDM2 slot 45 Data Mux", "4123", "IF1_2_ADC2 Mux"}, 3602 {"TDM2 slot 45 Data Mux", "4132", "IF1_2_ADC3 Mux"}, 3603 {"TDM2 slot 45 Data Mux", "4213", "IF1_2_ADC1 Mux"}, 3604 {"TDM2 slot 45 Data Mux", "4231", "IF1_2_ADC3 Mux"}, 3605 {"TDM2 slot 45 Data Mux", "4312", "IF1_2_ADC1 Mux"}, 3606 {"TDM2 slot 45 Data Mux", "4321", "IF1_2_ADC2 Mux"}, 3607 {"TDM2 slot 45 Data Mux", NULL, "I2S1_2"}, 3608 3609 {"TDM2 slot 67 Data Mux", "1234", "IF1_2_ADC4 Mux"}, 3610 {"TDM2 slot 67 Data Mux", "1243", "IF1_2_ADC3 Mux"}, 3611 {"TDM2 slot 67 Data Mux", "1324", "IF1_2_ADC4 Mux"}, 3612 {"TDM2 slot 67 Data Mux", "1342", "IF1_2_ADC2 Mux"}, 3613 {"TDM2 slot 67 Data Mux", "1432", "IF1_2_ADC2 Mux"}, 3614 {"TDM2 slot 67 Data Mux", "1423", "IF1_2_ADC3 Mux"}, 3615 {"TDM2 slot 67 Data Mux", "2134", "IF1_2_ADC4 Mux"}, 3616 {"TDM2 slot 67 Data Mux", "2143", "IF1_2_ADC3 Mux"}, 3617 {"TDM2 slot 67 Data Mux", "2314", "IF1_2_ADC4 Mux"}, 3618 {"TDM2 slot 67 Data Mux", "2341", "IF1_2_ADC1 Mux"}, 3619 {"TDM2 slot 67 Data Mux", "2431", "IF1_2_ADC1 Mux"}, 3620 {"TDM2 slot 67 Data Mux", "2413", "IF1_2_ADC3 Mux"}, 3621 {"TDM2 slot 67 Data Mux", "3124", "IF1_2_ADC4 Mux"}, 3622 {"TDM2 slot 67 Data Mux", "3142", "IF1_2_ADC2 Mux"}, 3623 {"TDM2 slot 67 Data Mux", "3214", "IF1_2_ADC4 Mux"}, 3624 {"TDM2 slot 67 Data Mux", "3241", "IF1_2_ADC1 Mux"}, 3625 {"TDM2 slot 67 Data Mux", "3412", "IF1_2_ADC2 Mux"}, 3626 {"TDM2 slot 67 Data Mux", "3421", "IF1_2_ADC1 Mux"}, 3627 {"TDM2 slot 67 Data Mux", "4123", "IF1_2_ADC3 Mux"}, 3628 {"TDM2 slot 67 Data Mux", "4132", "IF1_2_ADC2 Mux"}, 3629 {"TDM2 slot 67 Data Mux", "4213", "IF1_2_ADC3 Mux"}, 3630 {"TDM2 slot 67 Data Mux", "4231", "IF1_2_ADC1 Mux"}, 3631 {"TDM2 slot 67 Data Mux", "4312", "IF1_2_ADC2 Mux"}, 3632 {"TDM2 slot 67 Data Mux", "4321", "IF1_2_ADC1 Mux"}, 3633 {"TDM2 slot 67 Data Mux", NULL, "I2S1_2"}, 3634 3635 {"IF1_1 0 ADC Swap Mux", "L/R", "TDM1 slot 01 Data Mux"}, 3636 {"IF1_1 0 ADC Swap Mux", "L/L", "TDM1 slot 01 Data Mux"}, 3637 {"IF1_1 1 ADC Swap Mux", "R/L", "TDM1 slot 01 Data Mux"}, 3638 {"IF1_1 1 ADC Swap Mux", "R/R", "TDM1 slot 01 Data Mux"}, 3639 {"IF1_1 2 ADC Swap Mux", "L/R", "TDM1 slot 23 Data Mux"}, 3640 {"IF1_1 2 ADC Swap Mux", "R/L", "TDM1 slot 23 Data Mux"}, 3641 {"IF1_1 3 ADC Swap Mux", "L/L", "TDM1 slot 23 Data Mux"}, 3642 {"IF1_1 3 ADC Swap Mux", "R/R", "TDM1 slot 23 Data Mux"}, 3643 {"IF1_1 4 ADC Swap Mux", "L/R", "TDM1 slot 45 Data Mux"}, 3644 {"IF1_1 4 ADC Swap Mux", "R/L", "TDM1 slot 45 Data Mux"}, 3645 {"IF1_1 5 ADC Swap Mux", "L/L", "TDM1 slot 45 Data Mux"}, 3646 {"IF1_1 5 ADC Swap Mux", "R/R", "TDM1 slot 45 Data Mux"}, 3647 {"IF1_1 6 ADC Swap Mux", "L/R", "TDM1 slot 67 Data Mux"}, 3648 {"IF1_1 6 ADC Swap Mux", "R/L", "TDM1 slot 67 Data Mux"}, 3649 {"IF1_1 7 ADC Swap Mux", "L/L", "TDM1 slot 67 Data Mux"}, 3650 {"IF1_1 7 ADC Swap Mux", "R/R", "TDM1 slot 67 Data Mux"}, 3651 {"IF1_2 0 ADC Swap Mux", "L/R", "TDM2 slot 01 Data Mux"}, 3652 {"IF1_2 0 ADC Swap Mux", "R/L", "TDM2 slot 01 Data Mux"}, 3653 {"IF1_2 1 ADC Swap Mux", "L/L", "TDM2 slot 01 Data Mux"}, 3654 {"IF1_2 1 ADC Swap Mux", "R/R", "TDM2 slot 01 Data Mux"}, 3655 {"IF1_2 2 ADC Swap Mux", "L/R", "TDM2 slot 23 Data Mux"}, 3656 {"IF1_2 2 ADC Swap Mux", "R/L", "TDM2 slot 23 Data Mux"}, 3657 {"IF1_2 3 ADC Swap Mux", "L/L", "TDM2 slot 23 Data Mux"}, 3658 {"IF1_2 3 ADC Swap Mux", "R/R", "TDM2 slot 23 Data Mux"}, 3659 {"IF1_2 4 ADC Swap Mux", "L/R", "TDM2 slot 45 Data Mux"}, 3660 {"IF1_2 4 ADC Swap Mux", "R/L", "TDM2 slot 45 Data Mux"}, 3661 {"IF1_2 5 ADC Swap Mux", "L/L", "TDM2 slot 45 Data Mux"}, 3662 {"IF1_2 5 ADC Swap Mux", "R/R", "TDM2 slot 45 Data Mux"}, 3663 {"IF1_2 6 ADC Swap Mux", "L/R", "TDM2 slot 67 Data Mux"}, 3664 {"IF1_2 6 ADC Swap Mux", "R/L", "TDM2 slot 67 Data Mux"}, 3665 {"IF1_2 7 ADC Swap Mux", "L/L", "TDM2 slot 67 Data Mux"}, 3666 {"IF1_2 7 ADC Swap Mux", "R/R", "TDM2 slot 67 Data Mux"}, 3667 3668 {"IF2_1 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"}, 3669 {"IF2_1 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"}, 3670 {"IF2_1 ADC Mux", "MONO ADC", "Mono ADC MIX"}, 3671 {"IF2_1 ADC Mux", "IF1 DAC1", "IF1 DAC1"}, 3672 {"IF2_1 ADC Mux", "IF1 DAC2", "IF1 DAC2"}, 3673 {"IF2_1 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"}, 3674 {"IF2_1 ADC Mux", "IF3 DAC", "IF3 DAC"}, 3675 {"IF2_1 ADC Mux", "DAC1 MIX", "DAC1 MIX"}, 3676 {"IF2_1 ADC", NULL, "IF2_1 ADC Mux"}, 3677 {"IF2_1 ADC", NULL, "I2S2_1"}, 3678 3679 {"IF2_2 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"}, 3680 {"IF2_2 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"}, 3681 {"IF2_2 ADC Mux", "MONO ADC", "Mono ADC MIX"}, 3682 {"IF2_2 ADC Mux", "IF1 DAC1", "IF1 DAC1"}, 3683 {"IF2_2 ADC Mux", "IF1 DAC2", "IF1 DAC2"}, 3684 {"IF2_2 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"}, 3685 {"IF2_2 ADC Mux", "IF3 DAC", "IF3 DAC"}, 3686 {"IF2_2 ADC Mux", "DAC1 MIX", "DAC1 MIX"}, 3687 {"IF2_2 ADC", NULL, "IF2_2 ADC Mux"}, 3688 {"IF2_2 ADC", NULL, "I2S2_2"}, 3689 3690 {"IF3 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"}, 3691 {"IF3 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"}, 3692 {"IF3 ADC Mux", "MONO ADC", "Mono ADC MIX"}, 3693 {"IF3 ADC Mux", "IF1 DAC1", "IF1 DAC1"}, 3694 {"IF3 ADC Mux", "IF1 DAC2", "IF1 DAC2"}, 3695 {"IF3 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"}, 3696 {"IF3 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"}, 3697 {"IF3 ADC Mux", "DAC1 MIX", "DAC1 MIX"}, 3698 {"IF3 ADC", NULL, "IF3 ADC Mux"}, 3699 {"IF3 ADC", NULL, "I2S3"}, 3700 3701 {"AIF1_1TX slot 0", NULL, "IF1_1 0 ADC Swap Mux"}, 3702 {"AIF1_1TX slot 1", NULL, "IF1_1 1 ADC Swap Mux"}, 3703 {"AIF1_1TX slot 2", NULL, "IF1_1 2 ADC Swap Mux"}, 3704 {"AIF1_1TX slot 3", NULL, "IF1_1 3 ADC Swap Mux"}, 3705 {"AIF1_1TX slot 4", NULL, "IF1_1 4 ADC Swap Mux"}, 3706 {"AIF1_1TX slot 5", NULL, "IF1_1 5 ADC Swap Mux"}, 3707 {"AIF1_1TX slot 6", NULL, "IF1_1 6 ADC Swap Mux"}, 3708 {"AIF1_1TX slot 7", NULL, "IF1_1 7 ADC Swap Mux"}, 3709 {"AIF1_2TX slot 0", NULL, "IF1_2 0 ADC Swap Mux"}, 3710 {"AIF1_2TX slot 1", NULL, "IF1_2 1 ADC Swap Mux"}, 3711 {"AIF1_2TX slot 2", NULL, "IF1_2 2 ADC Swap Mux"}, 3712 {"AIF1_2TX slot 3", NULL, "IF1_2 3 ADC Swap Mux"}, 3713 {"AIF1_2TX slot 4", NULL, "IF1_2 4 ADC Swap Mux"}, 3714 {"AIF1_2TX slot 5", NULL, "IF1_2 5 ADC Swap Mux"}, 3715 {"AIF1_2TX slot 6", NULL, "IF1_2 6 ADC Swap Mux"}, 3716 {"AIF1_2TX slot 7", NULL, "IF1_2 7 ADC Swap Mux"}, 3717 {"IF2_1 ADC Swap Mux", "L/R", "IF2_1 ADC"}, 3718 {"IF2_1 ADC Swap Mux", "R/L", "IF2_1 ADC"}, 3719 {"IF2_1 ADC Swap Mux", "L/L", "IF2_1 ADC"}, 3720 {"IF2_1 ADC Swap Mux", "R/R", "IF2_1 ADC"}, 3721 {"AIF2_1TX", NULL, "IF2_1 ADC Swap Mux"}, 3722 {"IF2_2 ADC Swap Mux", "L/R", "IF2_2 ADC"}, 3723 {"IF2_2 ADC Swap Mux", "R/L", "IF2_2 ADC"}, 3724 {"IF2_2 ADC Swap Mux", "L/L", "IF2_2 ADC"}, 3725 {"IF2_2 ADC Swap Mux", "R/R", "IF2_2 ADC"}, 3726 {"AIF2_2TX", NULL, "IF2_2 ADC Swap Mux"}, 3727 {"IF3 ADC Swap Mux", "L/R", "IF3 ADC"}, 3728 {"IF3 ADC Swap Mux", "R/L", "IF3 ADC"}, 3729 {"IF3 ADC Swap Mux", "L/L", "IF3 ADC"}, 3730 {"IF3 ADC Swap Mux", "R/R", "IF3 ADC"}, 3731 {"AIF3TX", NULL, "IF3 ADC Swap Mux"}, 3732 3733 {"IF1 DAC1", NULL, "AIF1RX"}, 3734 {"IF1 DAC2", NULL, "AIF1RX"}, 3735 {"IF1 DAC3", NULL, "AIF1RX"}, 3736 {"IF2_1 DAC Swap Mux", "L/R", "AIF2_1RX"}, 3737 {"IF2_1 DAC Swap Mux", "R/L", "AIF2_1RX"}, 3738 {"IF2_1 DAC Swap Mux", "L/L", "AIF2_1RX"}, 3739 {"IF2_1 DAC Swap Mux", "R/R", "AIF2_1RX"}, 3740 {"IF2_2 DAC Swap Mux", "L/R", "AIF2_2RX"}, 3741 {"IF2_2 DAC Swap Mux", "R/L", "AIF2_2RX"}, 3742 {"IF2_2 DAC Swap Mux", "L/L", "AIF2_2RX"}, 3743 {"IF2_2 DAC Swap Mux", "R/R", "AIF2_2RX"}, 3744 {"IF2_1 DAC", NULL, "IF2_1 DAC Swap Mux"}, 3745 {"IF2_2 DAC", NULL, "IF2_2 DAC Swap Mux"}, 3746 {"IF3 DAC Swap Mux", "L/R", "AIF3RX"}, 3747 {"IF3 DAC Swap Mux", "R/L", "AIF3RX"}, 3748 {"IF3 DAC Swap Mux", "L/L", "AIF3RX"}, 3749 {"IF3 DAC Swap Mux", "R/R", "AIF3RX"}, 3750 {"IF3 DAC", NULL, "IF3 DAC Swap Mux"}, 3751 3752 {"IF1 DAC1", NULL, "I2S1_1"}, 3753 {"IF1 DAC2", NULL, "I2S1_1"}, 3754 {"IF1 DAC3", NULL, "I2S1_1"}, 3755 {"IF2_1 DAC", NULL, "I2S2_1"}, 3756 {"IF2_2 DAC", NULL, "I2S2_2"}, 3757 {"IF3 DAC", NULL, "I2S3"}, 3758 3759 {"IF1 DAC1 L", NULL, "IF1 DAC1"}, 3760 {"IF1 DAC1 R", NULL, "IF1 DAC1"}, 3761 {"IF1 DAC2 L", NULL, "IF1 DAC2"}, 3762 {"IF1 DAC2 R", NULL, "IF1 DAC2"}, 3763 {"IF1 DAC3 L", NULL, "IF1 DAC3"}, 3764 {"IF1 DAC3 R", NULL, "IF1 DAC3"}, 3765 {"IF2_1 DAC L", NULL, "IF2_1 DAC"}, 3766 {"IF2_1 DAC R", NULL, "IF2_1 DAC"}, 3767 {"IF2_2 DAC L", NULL, "IF2_2 DAC"}, 3768 {"IF2_2 DAC R", NULL, "IF2_2 DAC"}, 3769 {"IF3 DAC L", NULL, "IF3 DAC"}, 3770 {"IF3 DAC R", NULL, "IF3 DAC"}, 3771 3772 {"DAC L1 Mux", "IF1 DAC1", "IF1 DAC1 L"}, 3773 {"DAC L1 Mux", "IF2_1 DAC", "IF2_1 DAC L"}, 3774 {"DAC L1 Mux", "IF2_2 DAC", "IF2_2 DAC L"}, 3775 {"DAC L1 Mux", "IF3 DAC", "IF3 DAC L"}, 3776 {"DAC L1 Mux", NULL, "DAC Stereo1 Filter"}, 3777 3778 {"DAC R1 Mux", "IF1 DAC1", "IF1 DAC1 R"}, 3779 {"DAC R1 Mux", "IF2_1 DAC", "IF2_1 DAC R"}, 3780 {"DAC R1 Mux", "IF2_2 DAC", "IF2_2 DAC R"}, 3781 {"DAC R1 Mux", "IF3 DAC", "IF3 DAC R"}, 3782 {"DAC R1 Mux", NULL, "DAC Stereo1 Filter"}, 3783 3784 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"}, 3785 {"DAC1 MIXL", "DAC1 Switch", "DAC L1 Mux"}, 3786 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"}, 3787 {"DAC1 MIXR", "DAC1 Switch", "DAC R1 Mux"}, 3788 3789 {"DAC1 MIX", NULL, "DAC1 MIXL"}, 3790 {"DAC1 MIX", NULL, "DAC1 MIXR"}, 3791 3792 {"DAC L2 Mux", "IF1 DAC2", "IF1 DAC2 L"}, 3793 {"DAC L2 Mux", "IF2_1 DAC", "IF2_1 DAC L"}, 3794 {"DAC L2 Mux", "IF2_2 DAC", "IF2_2 DAC L"}, 3795 {"DAC L2 Mux", "IF3 DAC", "IF3 DAC L"}, 3796 {"DAC L2 Mux", "Mono ADC MIX", "Mono ADC MIXL"}, 3797 {"DAC L2 Mux", NULL, "DAC Mono Left Filter"}, 3798 3799 {"DAC R2 Mux", "IF1 DAC2", "IF1 DAC2 R"}, 3800 {"DAC R2 Mux", "IF2_1 DAC", "IF2_1 DAC R"}, 3801 {"DAC R2 Mux", "IF2_2 DAC", "IF2_2 DAC R"}, 3802 {"DAC R2 Mux", "IF3 DAC", "IF3 DAC R"}, 3803 {"DAC R2 Mux", "Mono ADC MIX", "Mono ADC MIXR"}, 3804 {"DAC R2 Mux", NULL, "DAC Mono Right Filter"}, 3805 3806 {"DAC L3 Mux", "IF1 DAC2", "IF1 DAC2 L"}, 3807 {"DAC L3 Mux", "IF2_1 DAC", "IF2_1 DAC L"}, 3808 {"DAC L3 Mux", "IF2_2 DAC", "IF2_2 DAC L"}, 3809 {"DAC L3 Mux", "IF3 DAC", "IF3 DAC L"}, 3810 {"DAC L3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXL"}, 3811 {"DAC L3 Mux", NULL, "DAC Stereo2 Filter"}, 3812 3813 {"DAC R3 Mux", "IF1 DAC2", "IF1 DAC2 R"}, 3814 {"DAC R3 Mux", "IF2_1 DAC", "IF2_1 DAC R"}, 3815 {"DAC R3 Mux", "IF2_2 DAC", "IF2_2 DAC R"}, 3816 {"DAC R3 Mux", "IF3 DAC", "IF3 DAC R"}, 3817 {"DAC R3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXR"}, 3818 {"DAC R3 Mux", NULL, "DAC Stereo2 Filter"}, 3819 3820 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"}, 3821 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"}, 3822 {"Stereo1 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"}, 3823 {"Stereo1 DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"}, 3824 3825 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"}, 3826 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"}, 3827 {"Stereo1 DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"}, 3828 {"Stereo1 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"}, 3829 3830 {"Stereo2 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"}, 3831 {"Stereo2 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"}, 3832 {"Stereo2 DAC MIXL", "DAC L3 Switch", "DAC L3 Mux"}, 3833 3834 {"Stereo2 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"}, 3835 {"Stereo2 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"}, 3836 {"Stereo2 DAC MIXR", "DAC R3 Switch", "DAC R3 Mux"}, 3837 3838 {"Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"}, 3839 {"Mono DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"}, 3840 {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"}, 3841 {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"}, 3842 {"Mono DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"}, 3843 {"Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"}, 3844 {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"}, 3845 {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"}, 3846 3847 {"DAC MIXL", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"}, 3848 {"DAC MIXL", "Stereo2 DAC Mixer", "Stereo2 DAC MIXL"}, 3849 {"DAC MIXL", "Mono DAC Mixer", "Mono DAC MIXL"}, 3850 {"DAC MIXR", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"}, 3851 {"DAC MIXR", "Stereo2 DAC Mixer", "Stereo2 DAC MIXR"}, 3852 {"DAC MIXR", "Mono DAC Mixer", "Mono DAC MIXR"}, 3853 3854 {"DAC L1 Source", "DAC1", "DAC1 MIXL"}, 3855 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"}, 3856 {"DAC L1 Source", "DMIC1", "DMIC L1"}, 3857 {"DAC R1 Source", "DAC1", "DAC1 MIXR"}, 3858 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"}, 3859 {"DAC R1 Source", "DMIC1", "DMIC R1"}, 3860 3861 {"DAC L2 Source", "DAC2", "DAC L2 Mux"}, 3862 {"DAC L2 Source", "Mono DAC Mixer", "Mono DAC MIXL"}, 3863 {"DAC L2 Source", NULL, "DAC L2 Power"}, 3864 {"DAC R2 Source", "DAC2", "DAC R2 Mux"}, 3865 {"DAC R2 Source", "Mono DAC Mixer", "Mono DAC MIXR"}, 3866 {"DAC R2 Source", NULL, "DAC R2 Power"}, 3867 3868 {"DAC L1", NULL, "DAC L1 Source"}, 3869 {"DAC R1", NULL, "DAC R1 Source"}, 3870 {"DAC L2", NULL, "DAC L2 Source"}, 3871 {"DAC R2", NULL, "DAC R2 Source"}, 3872 3873 {"DAC L1", NULL, "DAC 1 Clock"}, 3874 {"DAC R1", NULL, "DAC 1 Clock"}, 3875 {"DAC L2", NULL, "DAC 2 Clock"}, 3876 {"DAC R2", NULL, "DAC 2 Clock"}, 3877 3878 {"MONOVOL MIX", "DAC L2 Switch", "DAC L2"}, 3879 {"MONOVOL MIX", "RECMIX2L Switch", "RECMIX2L"}, 3880 {"MONOVOL MIX", "BST1 Switch", "BST1"}, 3881 {"MONOVOL MIX", "BST2 Switch", "BST2"}, 3882 {"MONOVOL MIX", "BST3 Switch", "BST3"}, 3883 3884 {"OUT MIXL", "DAC L2 Switch", "DAC L2"}, 3885 {"OUT MIXL", "INL Switch", "INL VOL"}, 3886 {"OUT MIXL", "BST1 Switch", "BST1"}, 3887 {"OUT MIXL", "BST2 Switch", "BST2"}, 3888 {"OUT MIXL", "BST3 Switch", "BST3"}, 3889 {"OUT MIXR", "DAC R2 Switch", "DAC R2"}, 3890 {"OUT MIXR", "INR Switch", "INR VOL"}, 3891 {"OUT MIXR", "BST2 Switch", "BST2"}, 3892 {"OUT MIXR", "BST3 Switch", "BST3"}, 3893 {"OUT MIXR", "BST4 Switch", "BST4"}, 3894 3895 {"MONOVOL", "Switch", "MONOVOL MIX"}, 3896 {"Mono MIX", "DAC L2 Switch", "DAC L2"}, 3897 {"Mono MIX", "MONOVOL Switch", "MONOVOL"}, 3898 {"Mono Amp", NULL, "Mono MIX"}, 3899 {"Mono Amp", NULL, "Vref2"}, 3900 {"Mono Amp", NULL, "Vref3"}, 3901 {"Mono Amp", NULL, "CLKDET SYS"}, 3902 {"Mono Amp", NULL, "CLKDET MONO"}, 3903 {"Mono Playback", "Switch", "Mono Amp"}, 3904 {"MONOOUT", NULL, "Mono Playback"}, 3905 3906 {"HP Amp", NULL, "DAC L1"}, 3907 {"HP Amp", NULL, "DAC R1"}, 3908 {"HP Amp", NULL, "Charge Pump"}, 3909 {"HP Amp", NULL, "CLKDET SYS"}, 3910 {"HP Amp", NULL, "CLKDET HP"}, 3911 {"HP Amp", NULL, "CBJ Power"}, 3912 {"HP Amp", NULL, "Vref2"}, 3913 {"HPO Playback", "Switch", "HP Amp"}, 3914 {"HPOL", NULL, "HPO Playback"}, 3915 {"HPOR", NULL, "HPO Playback"}, 3916 3917 {"OUTVOL L", "Switch", "OUT MIXL"}, 3918 {"OUTVOL R", "Switch", "OUT MIXR"}, 3919 {"LOUT L MIX", "DAC L2 Switch", "DAC L2"}, 3920 {"LOUT L MIX", "OUTVOL L Switch", "OUTVOL L"}, 3921 {"LOUT R MIX", "DAC R2 Switch", "DAC R2"}, 3922 {"LOUT R MIX", "OUTVOL R Switch", "OUTVOL R"}, 3923 {"LOUT Amp", NULL, "LOUT L MIX"}, 3924 {"LOUT Amp", NULL, "LOUT R MIX"}, 3925 {"LOUT Amp", NULL, "Vref1"}, 3926 {"LOUT Amp", NULL, "Vref2"}, 3927 {"LOUT Amp", NULL, "CLKDET SYS"}, 3928 {"LOUT Amp", NULL, "CLKDET LOUT"}, 3929 {"LOUT L Playback", "Switch", "LOUT Amp"}, 3930 {"LOUT R Playback", "Switch", "LOUT Amp"}, 3931 {"LOUTL", NULL, "LOUT L Playback"}, 3932 {"LOUTR", NULL, "LOUT R Playback"}, 3933 3934 {"PDM L Mux", "Mono DAC", "Mono DAC MIXL"}, 3935 {"PDM L Mux", "Stereo1 DAC", "Stereo1 DAC MIXL"}, 3936 {"PDM L Mux", "Stereo2 DAC", "Stereo2 DAC MIXL"}, 3937 {"PDM L Mux", NULL, "PDM Power"}, 3938 {"PDM R Mux", "Mono DAC", "Mono DAC MIXR"}, 3939 {"PDM R Mux", "Stereo1 DAC", "Stereo1 DAC MIXR"}, 3940 {"PDM R Mux", "Stereo2 DAC", "Stereo2 DAC MIXR"}, 3941 {"PDM R Mux", NULL, "PDM Power"}, 3942 {"PDM L Playback", "Switch", "PDM L Mux"}, 3943 {"PDM R Playback", "Switch", "PDM R Mux"}, 3944 {"PDML", NULL, "PDM L Playback"}, 3945 {"PDMR", NULL, "PDM R Playback"}, 3946 }; 3947 3948 static int rt5665_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 3949 unsigned int rx_mask, int slots, int slot_width) 3950 { 3951 struct snd_soc_component *component = dai->component; 3952 unsigned int val = 0; 3953 3954 if (rx_mask || tx_mask) 3955 val |= RT5665_I2S1_MODE_TDM; 3956 3957 switch (slots) { 3958 case 4: 3959 val |= RT5665_TDM_IN_CH_4; 3960 val |= RT5665_TDM_OUT_CH_4; 3961 break; 3962 case 6: 3963 val |= RT5665_TDM_IN_CH_6; 3964 val |= RT5665_TDM_OUT_CH_6; 3965 break; 3966 case 8: 3967 val |= RT5665_TDM_IN_CH_8; 3968 val |= RT5665_TDM_OUT_CH_8; 3969 break; 3970 case 2: 3971 break; 3972 default: 3973 return -EINVAL; 3974 } 3975 3976 switch (slot_width) { 3977 case 20: 3978 val |= RT5665_TDM_IN_LEN_20; 3979 val |= RT5665_TDM_OUT_LEN_20; 3980 break; 3981 case 24: 3982 val |= RT5665_TDM_IN_LEN_24; 3983 val |= RT5665_TDM_OUT_LEN_24; 3984 break; 3985 case 32: 3986 val |= RT5665_TDM_IN_LEN_32; 3987 val |= RT5665_TDM_OUT_LEN_32; 3988 break; 3989 case 16: 3990 break; 3991 default: 3992 return -EINVAL; 3993 } 3994 3995 snd_soc_component_update_bits(component, RT5665_TDM_CTRL_1, 3996 RT5665_I2S1_MODE_MASK | RT5665_TDM_IN_CH_MASK | 3997 RT5665_TDM_OUT_CH_MASK | RT5665_TDM_IN_LEN_MASK | 3998 RT5665_TDM_OUT_LEN_MASK, val); 3999 4000 return 0; 4001 } 4002 4003 4004 static int rt5665_hw_params(struct snd_pcm_substream *substream, 4005 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 4006 { 4007 struct snd_soc_component *component = dai->component; 4008 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component); 4009 unsigned int val_len = 0, val_clk, reg_clk, mask_clk, val_bits = 0x0100; 4010 int pre_div, frame_size; 4011 4012 rt5665->lrck[dai->id] = params_rate(params); 4013 pre_div = rl6231_get_clk_info(rt5665->sysclk, rt5665->lrck[dai->id]); 4014 if (pre_div < 0) { 4015 dev_warn(component->dev, "Force using PLL"); 4016 snd_soc_component_set_pll(component, 0, RT5665_PLL1_S_MCLK, 4017 rt5665->sysclk, rt5665->lrck[dai->id] * 512); 4018 snd_soc_component_set_sysclk(component, RT5665_SCLK_S_PLL1, 0, 4019 rt5665->lrck[dai->id] * 512, 0); 4020 pre_div = 1; 4021 } 4022 frame_size = snd_soc_params_to_frame_size(params); 4023 if (frame_size < 0) { 4024 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size); 4025 return -EINVAL; 4026 } 4027 4028 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n", 4029 rt5665->lrck[dai->id], pre_div, dai->id); 4030 4031 switch (params_width(params)) { 4032 case 16: 4033 val_bits = 0x0100; 4034 break; 4035 case 20: 4036 val_len |= RT5665_I2S_DL_20; 4037 val_bits = 0x1300; 4038 break; 4039 case 24: 4040 val_len |= RT5665_I2S_DL_24; 4041 val_bits = 0x2500; 4042 break; 4043 case 8: 4044 val_len |= RT5665_I2S_DL_8; 4045 break; 4046 default: 4047 return -EINVAL; 4048 } 4049 4050 switch (dai->id) { 4051 case RT5665_AIF1_1: 4052 case RT5665_AIF1_2: 4053 if (params_channels(params) > 2) 4054 rt5665_set_tdm_slot(dai, 0xf, 0xf, 4055 params_channels(params), params_width(params)); 4056 reg_clk = RT5665_ADDA_CLK_1; 4057 mask_clk = RT5665_I2S_PD1_MASK; 4058 val_clk = pre_div << RT5665_I2S_PD1_SFT; 4059 snd_soc_component_update_bits(component, RT5665_I2S1_SDP, 4060 RT5665_I2S_DL_MASK, val_len); 4061 break; 4062 case RT5665_AIF2_1: 4063 case RT5665_AIF2_2: 4064 reg_clk = RT5665_ADDA_CLK_2; 4065 mask_clk = RT5665_I2S_PD2_MASK; 4066 val_clk = pre_div << RT5665_I2S_PD2_SFT; 4067 snd_soc_component_update_bits(component, RT5665_I2S2_SDP, 4068 RT5665_I2S_DL_MASK, val_len); 4069 break; 4070 case RT5665_AIF3: 4071 reg_clk = RT5665_ADDA_CLK_2; 4072 mask_clk = RT5665_I2S_PD3_MASK; 4073 val_clk = pre_div << RT5665_I2S_PD3_SFT; 4074 snd_soc_component_update_bits(component, RT5665_I2S3_SDP, 4075 RT5665_I2S_DL_MASK, val_len); 4076 break; 4077 default: 4078 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 4079 return -EINVAL; 4080 } 4081 4082 snd_soc_component_update_bits(component, reg_clk, mask_clk, val_clk); 4083 snd_soc_component_update_bits(component, RT5665_STO1_DAC_SIL_DET, 0x3700, val_bits); 4084 4085 switch (rt5665->lrck[dai->id]) { 4086 case 192000: 4087 snd_soc_component_update_bits(component, RT5665_ADDA_CLK_1, 4088 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK, 4089 RT5665_DAC_OSR_32 | RT5665_ADC_OSR_32); 4090 break; 4091 case 96000: 4092 snd_soc_component_update_bits(component, RT5665_ADDA_CLK_1, 4093 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK, 4094 RT5665_DAC_OSR_64 | RT5665_ADC_OSR_64); 4095 break; 4096 default: 4097 snd_soc_component_update_bits(component, RT5665_ADDA_CLK_1, 4098 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK, 4099 RT5665_DAC_OSR_128 | RT5665_ADC_OSR_128); 4100 break; 4101 } 4102 4103 if (rt5665->master[RT5665_AIF2_1] || rt5665->master[RT5665_AIF2_2]) { 4104 snd_soc_component_update_bits(component, RT5665_I2S_M_CLK_CTRL_1, 4105 RT5665_I2S2_M_PD_MASK, pre_div << RT5665_I2S2_M_PD_SFT); 4106 } 4107 if (rt5665->master[RT5665_AIF3]) { 4108 snd_soc_component_update_bits(component, RT5665_I2S_M_CLK_CTRL_1, 4109 RT5665_I2S3_M_PD_MASK, pre_div << RT5665_I2S3_M_PD_SFT); 4110 } 4111 4112 return 0; 4113 } 4114 4115 static int rt5665_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 4116 { 4117 struct snd_soc_component *component = dai->component; 4118 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component); 4119 unsigned int reg_val = 0; 4120 4121 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 4122 case SND_SOC_DAIFMT_CBP_CFP: 4123 rt5665->master[dai->id] = 1; 4124 break; 4125 case SND_SOC_DAIFMT_CBC_CFC: 4126 reg_val |= RT5665_I2S_MS_S; 4127 rt5665->master[dai->id] = 0; 4128 break; 4129 default: 4130 return -EINVAL; 4131 } 4132 4133 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 4134 case SND_SOC_DAIFMT_NB_NF: 4135 break; 4136 case SND_SOC_DAIFMT_IB_NF: 4137 reg_val |= RT5665_I2S_BP_INV; 4138 break; 4139 default: 4140 return -EINVAL; 4141 } 4142 4143 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 4144 case SND_SOC_DAIFMT_I2S: 4145 break; 4146 case SND_SOC_DAIFMT_LEFT_J: 4147 reg_val |= RT5665_I2S_DF_LEFT; 4148 break; 4149 case SND_SOC_DAIFMT_DSP_A: 4150 reg_val |= RT5665_I2S_DF_PCM_A; 4151 break; 4152 case SND_SOC_DAIFMT_DSP_B: 4153 reg_val |= RT5665_I2S_DF_PCM_B; 4154 break; 4155 default: 4156 return -EINVAL; 4157 } 4158 4159 switch (dai->id) { 4160 case RT5665_AIF1_1: 4161 case RT5665_AIF1_2: 4162 snd_soc_component_update_bits(component, RT5665_I2S1_SDP, 4163 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK | 4164 RT5665_I2S_DF_MASK, reg_val); 4165 break; 4166 case RT5665_AIF2_1: 4167 case RT5665_AIF2_2: 4168 snd_soc_component_update_bits(component, RT5665_I2S2_SDP, 4169 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK | 4170 RT5665_I2S_DF_MASK, reg_val); 4171 break; 4172 case RT5665_AIF3: 4173 snd_soc_component_update_bits(component, RT5665_I2S3_SDP, 4174 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK | 4175 RT5665_I2S_DF_MASK, reg_val); 4176 break; 4177 default: 4178 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 4179 return -EINVAL; 4180 } 4181 return 0; 4182 } 4183 4184 static int rt5665_set_component_sysclk(struct snd_soc_component *component, int clk_id, 4185 int source, unsigned int freq, int dir) 4186 { 4187 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component); 4188 unsigned int reg_val = 0, src = 0; 4189 4190 if (freq == rt5665->sysclk && clk_id == rt5665->sysclk_src) 4191 return 0; 4192 4193 switch (clk_id) { 4194 case RT5665_SCLK_S_MCLK: 4195 reg_val |= RT5665_SCLK_SRC_MCLK; 4196 src = RT5665_CLK_SRC_MCLK; 4197 break; 4198 case RT5665_SCLK_S_PLL1: 4199 reg_val |= RT5665_SCLK_SRC_PLL1; 4200 src = RT5665_CLK_SRC_PLL1; 4201 break; 4202 case RT5665_SCLK_S_RCCLK: 4203 reg_val |= RT5665_SCLK_SRC_RCCLK; 4204 src = RT5665_CLK_SRC_RCCLK; 4205 break; 4206 default: 4207 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 4208 return -EINVAL; 4209 } 4210 snd_soc_component_update_bits(component, RT5665_GLB_CLK, 4211 RT5665_SCLK_SRC_MASK, reg_val); 4212 4213 if (rt5665->master[RT5665_AIF2_1] || rt5665->master[RT5665_AIF2_2]) { 4214 snd_soc_component_update_bits(component, RT5665_I2S_M_CLK_CTRL_1, 4215 RT5665_I2S2_SRC_MASK, src << RT5665_I2S2_SRC_SFT); 4216 } 4217 if (rt5665->master[RT5665_AIF3]) { 4218 snd_soc_component_update_bits(component, RT5665_I2S_M_CLK_CTRL_1, 4219 RT5665_I2S3_SRC_MASK, src << RT5665_I2S3_SRC_SFT); 4220 } 4221 4222 rt5665->sysclk = freq; 4223 rt5665->sysclk_src = clk_id; 4224 4225 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); 4226 4227 return 0; 4228 } 4229 4230 static int rt5665_set_component_pll(struct snd_soc_component *component, int pll_id, 4231 int source, unsigned int freq_in, 4232 unsigned int freq_out) 4233 { 4234 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component); 4235 struct rl6231_pll_code pll_code; 4236 int ret; 4237 4238 if (source == rt5665->pll_src && freq_in == rt5665->pll_in && 4239 freq_out == rt5665->pll_out) 4240 return 0; 4241 4242 if (!freq_in || !freq_out) { 4243 dev_dbg(component->dev, "PLL disabled\n"); 4244 4245 rt5665->pll_in = 0; 4246 rt5665->pll_out = 0; 4247 snd_soc_component_update_bits(component, RT5665_GLB_CLK, 4248 RT5665_SCLK_SRC_MASK, RT5665_SCLK_SRC_MCLK); 4249 return 0; 4250 } 4251 4252 switch (source) { 4253 case RT5665_PLL1_S_MCLK: 4254 snd_soc_component_update_bits(component, RT5665_GLB_CLK, 4255 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_MCLK); 4256 break; 4257 case RT5665_PLL1_S_BCLK1: 4258 snd_soc_component_update_bits(component, RT5665_GLB_CLK, 4259 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK1); 4260 break; 4261 case RT5665_PLL1_S_BCLK2: 4262 snd_soc_component_update_bits(component, RT5665_GLB_CLK, 4263 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK2); 4264 break; 4265 case RT5665_PLL1_S_BCLK3: 4266 snd_soc_component_update_bits(component, RT5665_GLB_CLK, 4267 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK3); 4268 break; 4269 default: 4270 dev_err(component->dev, "Unknown PLL Source %d\n", source); 4271 return -EINVAL; 4272 } 4273 4274 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 4275 if (ret < 0) { 4276 dev_err(component->dev, "Unsupported input clock %d\n", freq_in); 4277 return ret; 4278 } 4279 4280 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 4281 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 4282 pll_code.n_code, pll_code.k_code); 4283 4284 snd_soc_component_write(component, RT5665_PLL_CTRL_1, 4285 pll_code.n_code << RT5665_PLL_N_SFT | pll_code.k_code); 4286 snd_soc_component_write(component, RT5665_PLL_CTRL_2, 4287 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5665_PLL_M_SFT) | 4288 (pll_code.m_bp << RT5665_PLL_M_BP_SFT)); 4289 4290 rt5665->pll_in = freq_in; 4291 rt5665->pll_out = freq_out; 4292 rt5665->pll_src = source; 4293 4294 return 0; 4295 } 4296 4297 static int rt5665_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) 4298 { 4299 struct snd_soc_component *component = dai->component; 4300 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component); 4301 4302 dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio); 4303 4304 rt5665->bclk[dai->id] = ratio; 4305 4306 if (ratio == 64) { 4307 switch (dai->id) { 4308 case RT5665_AIF2_1: 4309 case RT5665_AIF2_2: 4310 snd_soc_component_update_bits(component, RT5665_ADDA_CLK_2, 4311 RT5665_I2S_BCLK_MS2_MASK, 4312 RT5665_I2S_BCLK_MS2_64); 4313 break; 4314 case RT5665_AIF3: 4315 snd_soc_component_update_bits(component, RT5665_ADDA_CLK_2, 4316 RT5665_I2S_BCLK_MS3_MASK, 4317 RT5665_I2S_BCLK_MS3_64); 4318 break; 4319 } 4320 } 4321 4322 return 0; 4323 } 4324 4325 static int rt5665_set_bias_level(struct snd_soc_component *component, 4326 enum snd_soc_bias_level level) 4327 { 4328 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component); 4329 4330 switch (level) { 4331 case SND_SOC_BIAS_PREPARE: 4332 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC, 4333 RT5665_DIG_GATE_CTRL, RT5665_DIG_GATE_CTRL); 4334 break; 4335 4336 case SND_SOC_BIAS_STANDBY: 4337 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1, 4338 RT5665_PWR_LDO, RT5665_PWR_LDO); 4339 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1, 4340 RT5665_PWR_MB, RT5665_PWR_MB); 4341 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC, 4342 RT5665_DIG_GATE_CTRL, 0); 4343 break; 4344 case SND_SOC_BIAS_OFF: 4345 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1, 4346 RT5665_PWR_LDO, 0); 4347 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1, 4348 RT5665_PWR_MB, 0); 4349 break; 4350 4351 default: 4352 break; 4353 } 4354 4355 return 0; 4356 } 4357 4358 static int rt5665_probe(struct snd_soc_component *component) 4359 { 4360 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component); 4361 4362 rt5665->component = component; 4363 4364 schedule_delayed_work(&rt5665->calibrate_work, msecs_to_jiffies(100)); 4365 4366 return 0; 4367 } 4368 4369 static void rt5665_remove(struct snd_soc_component *component) 4370 { 4371 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component); 4372 4373 regmap_write(rt5665->regmap, RT5665_RESET, 0); 4374 } 4375 4376 #ifdef CONFIG_PM 4377 static int rt5665_suspend(struct snd_soc_component *component) 4378 { 4379 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component); 4380 4381 regcache_cache_only(rt5665->regmap, true); 4382 regcache_mark_dirty(rt5665->regmap); 4383 return 0; 4384 } 4385 4386 static int rt5665_resume(struct snd_soc_component *component) 4387 { 4388 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component); 4389 4390 regcache_cache_only(rt5665->regmap, false); 4391 regcache_sync(rt5665->regmap); 4392 4393 return 0; 4394 } 4395 #else 4396 #define rt5665_suspend NULL 4397 #define rt5665_resume NULL 4398 #endif 4399 4400 #define RT5665_STEREO_RATES SNDRV_PCM_RATE_8000_192000 4401 #define RT5665_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 4402 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 4403 4404 static const struct snd_soc_dai_ops rt5665_aif_dai_ops = { 4405 .hw_params = rt5665_hw_params, 4406 .set_fmt = rt5665_set_dai_fmt, 4407 .set_tdm_slot = rt5665_set_tdm_slot, 4408 .set_bclk_ratio = rt5665_set_bclk_ratio, 4409 }; 4410 4411 static struct snd_soc_dai_driver rt5665_dai[] = { 4412 { 4413 .name = "rt5665-aif1_1", 4414 .id = RT5665_AIF1_1, 4415 .playback = { 4416 .stream_name = "AIF1 Playback", 4417 .channels_min = 1, 4418 .channels_max = 8, 4419 .rates = RT5665_STEREO_RATES, 4420 .formats = RT5665_FORMATS, 4421 }, 4422 .capture = { 4423 .stream_name = "AIF1_1 Capture", 4424 .channels_min = 1, 4425 .channels_max = 8, 4426 .rates = RT5665_STEREO_RATES, 4427 .formats = RT5665_FORMATS, 4428 }, 4429 .ops = &rt5665_aif_dai_ops, 4430 }, 4431 { 4432 .name = "rt5665-aif1_2", 4433 .id = RT5665_AIF1_2, 4434 .capture = { 4435 .stream_name = "AIF1_2 Capture", 4436 .channels_min = 1, 4437 .channels_max = 8, 4438 .rates = RT5665_STEREO_RATES, 4439 .formats = RT5665_FORMATS, 4440 }, 4441 .ops = &rt5665_aif_dai_ops, 4442 }, 4443 { 4444 .name = "rt5665-aif2_1", 4445 .id = RT5665_AIF2_1, 4446 .playback = { 4447 .stream_name = "AIF2_1 Playback", 4448 .channels_min = 1, 4449 .channels_max = 2, 4450 .rates = RT5665_STEREO_RATES, 4451 .formats = RT5665_FORMATS, 4452 }, 4453 .capture = { 4454 .stream_name = "AIF2_1 Capture", 4455 .channels_min = 1, 4456 .channels_max = 2, 4457 .rates = RT5665_STEREO_RATES, 4458 .formats = RT5665_FORMATS, 4459 }, 4460 .ops = &rt5665_aif_dai_ops, 4461 }, 4462 { 4463 .name = "rt5665-aif2_2", 4464 .id = RT5665_AIF2_2, 4465 .playback = { 4466 .stream_name = "AIF2_2 Playback", 4467 .channels_min = 1, 4468 .channels_max = 2, 4469 .rates = RT5665_STEREO_RATES, 4470 .formats = RT5665_FORMATS, 4471 }, 4472 .capture = { 4473 .stream_name = "AIF2_2 Capture", 4474 .channels_min = 1, 4475 .channels_max = 2, 4476 .rates = RT5665_STEREO_RATES, 4477 .formats = RT5665_FORMATS, 4478 }, 4479 .ops = &rt5665_aif_dai_ops, 4480 }, 4481 { 4482 .name = "rt5665-aif3", 4483 .id = RT5665_AIF3, 4484 .playback = { 4485 .stream_name = "AIF3 Playback", 4486 .channels_min = 1, 4487 .channels_max = 2, 4488 .rates = RT5665_STEREO_RATES, 4489 .formats = RT5665_FORMATS, 4490 }, 4491 .capture = { 4492 .stream_name = "AIF3 Capture", 4493 .channels_min = 1, 4494 .channels_max = 2, 4495 .rates = RT5665_STEREO_RATES, 4496 .formats = RT5665_FORMATS, 4497 }, 4498 .ops = &rt5665_aif_dai_ops, 4499 }, 4500 }; 4501 4502 static const struct snd_soc_component_driver soc_component_dev_rt5665 = { 4503 .probe = rt5665_probe, 4504 .remove = rt5665_remove, 4505 .suspend = rt5665_suspend, 4506 .resume = rt5665_resume, 4507 .set_bias_level = rt5665_set_bias_level, 4508 .controls = rt5665_snd_controls, 4509 .num_controls = ARRAY_SIZE(rt5665_snd_controls), 4510 .dapm_widgets = rt5665_dapm_widgets, 4511 .num_dapm_widgets = ARRAY_SIZE(rt5665_dapm_widgets), 4512 .dapm_routes = rt5665_dapm_routes, 4513 .num_dapm_routes = ARRAY_SIZE(rt5665_dapm_routes), 4514 .set_sysclk = rt5665_set_component_sysclk, 4515 .set_pll = rt5665_set_component_pll, 4516 .set_jack = rt5665_set_jack_detect, 4517 .use_pmdown_time = 1, 4518 .endianness = 1, 4519 }; 4520 4521 4522 static const struct regmap_config rt5665_regmap = { 4523 .reg_bits = 16, 4524 .val_bits = 16, 4525 .max_register = 0x0400, 4526 .volatile_reg = rt5665_volatile_register, 4527 .readable_reg = rt5665_readable_register, 4528 .cache_type = REGCACHE_MAPLE, 4529 .reg_defaults = rt5665_reg, 4530 .num_reg_defaults = ARRAY_SIZE(rt5665_reg), 4531 .use_single_read = true, 4532 .use_single_write = true, 4533 }; 4534 4535 static const struct i2c_device_id rt5665_i2c_id[] = { 4536 { .name = "rt5665" }, 4537 { } 4538 }; 4539 MODULE_DEVICE_TABLE(i2c, rt5665_i2c_id); 4540 4541 static int rt5665_parse_dt(struct rt5665_priv *rt5665, struct device *dev) 4542 { 4543 rt5665->pdata.in1_diff = of_property_read_bool(dev->of_node, 4544 "realtek,in1-differential"); 4545 rt5665->pdata.in2_diff = of_property_read_bool(dev->of_node, 4546 "realtek,in2-differential"); 4547 rt5665->pdata.in3_diff = of_property_read_bool(dev->of_node, 4548 "realtek,in3-differential"); 4549 rt5665->pdata.in4_diff = of_property_read_bool(dev->of_node, 4550 "realtek,in4-differential"); 4551 4552 of_property_read_u32(dev->of_node, "realtek,dmic1-data-pin", 4553 &rt5665->pdata.dmic1_data_pin); 4554 of_property_read_u32(dev->of_node, "realtek,dmic2-data-pin", 4555 &rt5665->pdata.dmic2_data_pin); 4556 of_property_read_u32(dev->of_node, "realtek,jd-src", 4557 &rt5665->pdata.jd_src); 4558 4559 return 0; 4560 } 4561 4562 static void rt5665_calibrate(struct rt5665_priv *rt5665) 4563 { 4564 int value, count; 4565 4566 guard(mutex)(&rt5665->calibrate_mutex); 4567 4568 regcache_cache_bypass(rt5665->regmap, true); 4569 4570 regmap_write(rt5665->regmap, RT5665_RESET, 0); 4571 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602); 4572 regmap_write(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1, 0x0c26); 4573 regmap_write(rt5665->regmap, RT5665_MONOMIX_IN_GAIN, 0x021f); 4574 regmap_write(rt5665->regmap, RT5665_MONO_OUT, 0x480a); 4575 regmap_write(rt5665->regmap, RT5665_PWR_MIXER, 0x083f); 4576 regmap_write(rt5665->regmap, RT5665_PWR_DIG_1, 0x0180); 4577 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_1, 0x4040); 4578 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0000); 4579 regmap_write(rt5665->regmap, RT5665_DIG_MISC, 0x0001); 4580 regmap_write(rt5665->regmap, RT5665_MICBIAS_2, 0x0380); 4581 regmap_write(rt5665->regmap, RT5665_GLB_CLK, 0x8000); 4582 regmap_write(rt5665->regmap, RT5665_ADDA_CLK_1, 0x1000); 4583 regmap_write(rt5665->regmap, RT5665_CHOP_DAC, 0x3030); 4584 regmap_write(rt5665->regmap, RT5665_CALIB_ADC_CTRL, 0x3c05); 4585 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xaa3e); 4586 usleep_range(15000, 20000); 4587 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xfe7e); 4588 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_2, 0x0321); 4589 4590 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_1, 0xfc00); 4591 count = 0; 4592 while (true) { 4593 regmap_read(rt5665->regmap, RT5665_HP_CALIB_STA_1, &value); 4594 if (value & 0x8000) 4595 usleep_range(10000, 10005); 4596 else 4597 break; 4598 4599 if (count > 60) { 4600 pr_err("HP Calibration Failure\n"); 4601 regmap_write(rt5665->regmap, RT5665_RESET, 0); 4602 regcache_cache_bypass(rt5665->regmap, false); 4603 rt5665->calibration_done = true; 4604 return; 4605 } 4606 4607 count++; 4608 } 4609 4610 regmap_write(rt5665->regmap, RT5665_MONO_AMP_CALIB_CTRL_1, 0x9e24); 4611 count = 0; 4612 while (true) { 4613 regmap_read(rt5665->regmap, RT5665_MONO_AMP_CALIB_STA1, &value); 4614 if (value & 0x8000) 4615 usleep_range(10000, 10005); 4616 else 4617 break; 4618 4619 if (count > 60) { 4620 pr_err("MONO Calibration Failure\n"); 4621 regmap_write(rt5665->regmap, RT5665_RESET, 0); 4622 regcache_cache_bypass(rt5665->regmap, false); 4623 rt5665->calibration_done = true; 4624 return; 4625 } 4626 4627 count++; 4628 } 4629 4630 regmap_write(rt5665->regmap, RT5665_RESET, 0); 4631 regcache_cache_bypass(rt5665->regmap, false); 4632 4633 regcache_mark_dirty(rt5665->regmap); 4634 regcache_sync(rt5665->regmap); 4635 4636 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602); 4637 regmap_write(rt5665->regmap, RT5665_ASRC_8, 0x0120); 4638 4639 rt5665->calibration_done = true; 4640 } 4641 4642 static void rt5665_calibrate_handler(struct work_struct *work) 4643 { 4644 struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv, 4645 calibrate_work.work); 4646 4647 while (!snd_soc_card_is_instantiated(rt5665->component->card)) { 4648 pr_debug("%s\n", __func__); 4649 usleep_range(10000, 15000); 4650 } 4651 4652 rt5665_calibrate(rt5665); 4653 } 4654 4655 static int rt5665_i2c_probe(struct i2c_client *i2c) 4656 { 4657 struct rt5665_platform_data *pdata = dev_get_platdata(&i2c->dev); 4658 struct rt5665_priv *rt5665; 4659 int ret; 4660 unsigned int val; 4661 4662 rt5665 = devm_kzalloc(&i2c->dev, sizeof(struct rt5665_priv), 4663 GFP_KERNEL); 4664 4665 if (rt5665 == NULL) 4666 return -ENOMEM; 4667 4668 i2c_set_clientdata(i2c, rt5665); 4669 4670 if (pdata) 4671 rt5665->pdata = *pdata; 4672 else 4673 rt5665_parse_dt(rt5665, &i2c->dev); 4674 4675 ret = devm_regulator_bulk_get_enable(&i2c->dev, ARRAY_SIZE(rt5665_supply_names), 4676 rt5665_supply_names); 4677 if (ret != 0) { 4678 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 4679 return ret; 4680 } 4681 4682 rt5665->gpiod_ldo1_en = devm_gpiod_get_optional(&i2c->dev, 4683 "realtek,ldo1-en", 4684 GPIOD_OUT_HIGH); 4685 if (IS_ERR(rt5665->gpiod_ldo1_en)) { 4686 dev_err(&i2c->dev, "Failed gpio request ldo1_en\n"); 4687 return PTR_ERR(rt5665->gpiod_ldo1_en); 4688 } 4689 4690 /* Sleep for 300 ms minimum */ 4691 usleep_range(300000, 350000); 4692 4693 rt5665->regmap = devm_regmap_init_i2c(i2c, &rt5665_regmap); 4694 if (IS_ERR(rt5665->regmap)) { 4695 ret = PTR_ERR(rt5665->regmap); 4696 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 4697 ret); 4698 return ret; 4699 } 4700 4701 regmap_read(rt5665->regmap, RT5665_DEVICE_ID, &val); 4702 if (val != DEVICE_ID) { 4703 dev_err(&i2c->dev, 4704 "Device with ID register %x is not rt5665\n", val); 4705 return -ENODEV; 4706 } 4707 4708 regmap_read(rt5665->regmap, RT5665_RESET, &val); 4709 switch (val) { 4710 case 0x0: 4711 rt5665->id = CODEC_5666; 4712 break; 4713 case 0x3: 4714 default: 4715 rt5665->id = CODEC_5665; 4716 break; 4717 } 4718 4719 regmap_write(rt5665->regmap, RT5665_RESET, 0); 4720 4721 /* line in diff mode*/ 4722 if (rt5665->pdata.in1_diff) 4723 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2, 4724 RT5665_IN1_DF_MASK, RT5665_IN1_DF_MASK); 4725 if (rt5665->pdata.in2_diff) 4726 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2, 4727 RT5665_IN2_DF_MASK, RT5665_IN2_DF_MASK); 4728 if (rt5665->pdata.in3_diff) 4729 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4, 4730 RT5665_IN3_DF_MASK, RT5665_IN3_DF_MASK); 4731 if (rt5665->pdata.in4_diff) 4732 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4, 4733 RT5665_IN4_DF_MASK, RT5665_IN4_DF_MASK); 4734 4735 /* DMIC pin*/ 4736 if (rt5665->pdata.dmic1_data_pin != RT5665_DMIC1_NULL || 4737 rt5665->pdata.dmic2_data_pin != RT5665_DMIC2_NULL) { 4738 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2, 4739 RT5665_GP9_PIN_MASK, RT5665_GP9_PIN_DMIC1_SCL); 4740 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1, 4741 RT5665_GP8_PIN_MASK, RT5665_GP8_PIN_DMIC2_SCL); 4742 switch (rt5665->pdata.dmic1_data_pin) { 4743 case RT5665_DMIC1_DATA_IN2N: 4744 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1, 4745 RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_IN2N); 4746 break; 4747 4748 case RT5665_DMIC1_DATA_GPIO4: 4749 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1, 4750 RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_GPIO4); 4751 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1, 4752 RT5665_GP4_PIN_MASK, RT5665_GP4_PIN_DMIC1_SDA); 4753 break; 4754 4755 default: 4756 dev_dbg(&i2c->dev, "no DMIC1\n"); 4757 break; 4758 } 4759 4760 switch (rt5665->pdata.dmic2_data_pin) { 4761 case RT5665_DMIC2_DATA_IN2P: 4762 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1, 4763 RT5665_DMIC_2_DP_MASK, RT5665_DMIC_2_DP_IN2P); 4764 break; 4765 4766 case RT5665_DMIC2_DATA_GPIO5: 4767 regmap_update_bits(rt5665->regmap, 4768 RT5665_DMIC_CTRL_1, 4769 RT5665_DMIC_2_DP_MASK, 4770 RT5665_DMIC_2_DP_GPIO5); 4771 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1, 4772 RT5665_GP5_PIN_MASK, RT5665_GP5_PIN_DMIC2_SDA); 4773 break; 4774 4775 default: 4776 dev_dbg(&i2c->dev, "no DMIC2\n"); 4777 break; 4778 4779 } 4780 } 4781 4782 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0002); 4783 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1, 4784 0xf000 | RT5665_VREF_POW_MASK, 0xe000 | RT5665_VREF_POW_REG); 4785 /* Work around for pow_pump */ 4786 regmap_update_bits(rt5665->regmap, RT5665_STO1_DAC_SIL_DET, 4787 RT5665_DEB_STO_DAC_MASK, RT5665_DEB_80_MS); 4788 4789 regmap_update_bits(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1, 4790 RT5665_PM_HP_MASK, RT5665_PM_HP_HV); 4791 4792 /* Set GPIO4,8 as input for combo jack */ 4793 if (rt5665->id == CODEC_5666) { 4794 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2, 4795 RT5665_GP4_PF_MASK, RT5665_GP4_PF_IN); 4796 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_3, 4797 RT5665_GP8_PF_MASK, RT5665_GP8_PF_IN); 4798 } 4799 4800 /* Enhance performance*/ 4801 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1, 4802 RT5665_HP_DRIVER_MASK | RT5665_LDO1_DVO_MASK, 4803 RT5665_HP_DRIVER_5X | RT5665_LDO1_DVO_12); 4804 4805 INIT_DELAYED_WORK(&rt5665->jack_detect_work, 4806 rt5665_jack_detect_handler); 4807 INIT_DELAYED_WORK(&rt5665->calibrate_work, 4808 rt5665_calibrate_handler); 4809 INIT_DELAYED_WORK(&rt5665->jd_check_work, 4810 rt5665_jd_check_handler); 4811 4812 mutex_init(&rt5665->calibrate_mutex); 4813 4814 if (i2c->irq) { 4815 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, 4816 rt5665_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING 4817 | IRQF_ONESHOT, "rt5665", rt5665); 4818 if (ret) 4819 dev_err(&i2c->dev, "Failed to request IRQ: %d\n", ret); 4820 4821 } 4822 4823 return devm_snd_soc_register_component(&i2c->dev, 4824 &soc_component_dev_rt5665, 4825 rt5665_dai, ARRAY_SIZE(rt5665_dai)); 4826 } 4827 4828 static void rt5665_i2c_shutdown(struct i2c_client *client) 4829 { 4830 struct rt5665_priv *rt5665 = i2c_get_clientdata(client); 4831 4832 regmap_write(rt5665->regmap, RT5665_RESET, 0); 4833 } 4834 4835 #ifdef CONFIG_OF 4836 static const struct of_device_id rt5665_of_match[] = { 4837 {.compatible = "realtek,rt5665"}, 4838 {.compatible = "realtek,rt5666"}, 4839 { } 4840 }; 4841 MODULE_DEVICE_TABLE(of, rt5665_of_match); 4842 #endif 4843 4844 #ifdef CONFIG_ACPI 4845 static const struct acpi_device_id rt5665_acpi_match[] = { 4846 { "10EC5665" }, 4847 { "10EC5666" }, 4848 { } 4849 }; 4850 MODULE_DEVICE_TABLE(acpi, rt5665_acpi_match); 4851 #endif 4852 4853 static struct i2c_driver rt5665_i2c_driver = { 4854 .driver = { 4855 .name = "rt5665", 4856 .of_match_table = of_match_ptr(rt5665_of_match), 4857 .acpi_match_table = ACPI_PTR(rt5665_acpi_match), 4858 }, 4859 .probe = rt5665_i2c_probe, 4860 .shutdown = rt5665_i2c_shutdown, 4861 .id_table = rt5665_i2c_id, 4862 }; 4863 module_i2c_driver(rt5665_i2c_driver); 4864 4865 MODULE_DESCRIPTION("ASoC RT5665 driver"); 4866 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); 4867 MODULE_LICENSE("GPL v2"); 4868