1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 #ifndef __DML2_INTERNAL_SHARED_TYPES_H__ 6 #define __DML2_INTERNAL_SHARED_TYPES_H__ 7 8 #include "dml2_external_lib_deps.h" 9 #include "dml_top_types.h" 10 #include "dml2_core_shared_types.h" 11 /* 12 * DML2 MCG Types and Interfaces 13 */ 14 15 #define DML_MCG_MAX_CLK_TABLE_SIZE 20 16 17 struct dram_bw_to_min_clk_table_entry { 18 unsigned long long pre_derate_dram_bw_kbps; 19 unsigned long min_uclk_khz; 20 unsigned long min_fclk_khz; 21 unsigned long min_dcfclk_khz; 22 }; 23 24 struct dml2_mcg_dram_bw_to_min_clk_table { 25 struct dram_bw_to_min_clk_table_entry entries[DML_MCG_MAX_CLK_TABLE_SIZE]; 26 27 unsigned int num_entries; 28 }; 29 30 struct dml2_mcg_min_clock_table { 31 struct { 32 unsigned int dispclk; 33 unsigned int dppclk; 34 unsigned int dscclk; 35 unsigned int dtbclk; 36 unsigned int phyclk; 37 unsigned int fclk; 38 unsigned int dcfclk; 39 } max_clocks_khz; 40 41 struct { 42 unsigned int dispclk; 43 unsigned int dppclk; 44 unsigned int dtbclk; 45 } max_ss_clocks_khz; 46 47 struct { 48 unsigned int dprefclk; 49 unsigned int xtalclk; 50 unsigned int pcierefclk; 51 unsigned int dchubrefclk; 52 unsigned int amclk; 53 } fixed_clocks_khz; 54 55 struct dml2_mcg_dram_bw_to_min_clk_table dram_bw_table; 56 }; 57 58 struct dml2_mcg_build_min_clock_table_params_in_out { 59 /* 60 * Input 61 */ 62 struct dml2_soc_bb *soc_bb; 63 struct { 64 bool perform_pseudo_build; 65 } clean_me_up; 66 67 /* 68 * Output 69 */ 70 struct dml2_mcg_min_clock_table *min_clk_table; 71 }; 72 struct dml2_mcg_instance { 73 bool (*build_min_clock_table)(struct dml2_mcg_build_min_clock_table_params_in_out *in_out); 74 }; 75 76 /* 77 * DML2 DPMM Types and Interfaces 78 */ 79 80 struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out { 81 /* 82 * Input 83 */ 84 struct dml2_core_ip_params *ip; 85 struct dml2_soc_bb *soc_bb; 86 struct dml2_mcg_min_clock_table *min_clk_table; 87 const struct display_configuation_with_meta *display_cfg; 88 struct { 89 bool perform_pseudo_map; 90 struct dml2_core_internal_soc_bb *soc_bb; 91 } clean_me_up; 92 93 /* 94 * Output 95 */ 96 struct dml2_display_cfg_programming *programming; 97 }; 98 99 struct dml2_dpmm_map_watermarks_params_in_out { 100 /* 101 * Input 102 */ 103 const struct display_configuation_with_meta *display_cfg; 104 const struct dml2_core_instance *core; 105 106 /* 107 * Output 108 */ 109 struct dml2_display_cfg_programming *programming; 110 }; 111 112 struct dml2_dpmm_scratch { 113 struct dml2_display_cfg_programming programming; 114 }; 115 116 struct dml2_dpmm_instance { 117 bool (*map_mode_to_soc_dpm)(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out); 118 bool (*map_watermarks)(struct dml2_dpmm_map_watermarks_params_in_out *in_out); 119 120 struct dml2_dpmm_scratch dpmm_scratch; 121 }; 122 123 /* 124 * DML2 Core Types and Interfaces 125 */ 126 127 struct dml2_core_initialize_in_out { 128 enum dml2_project_id project_id; 129 struct dml2_core_instance *instance; 130 struct dml2_soc_bb *soc_bb; 131 struct dml2_ip_capabilities *ip_caps; 132 133 struct dml2_mcg_min_clock_table *minimum_clock_table; 134 135 void *explicit_ip_bb; 136 unsigned int explicit_ip_bb_size; 137 138 // FIXME_STAGE2 can remove but dcn3 version still need this 139 struct { 140 struct soc_bounding_box_st *soc_bb; 141 struct soc_states_st *soc_states; 142 } legacy; 143 }; 144 145 struct core_bandwidth_requirements { 146 int urgent_bandwidth_kbytes_per_sec; 147 int average_bandwidth_kbytes_per_sec; 148 }; 149 150 struct core_plane_support_info { 151 int dpps_used; 152 int dram_change_latency_hiding_margin_in_active; 153 int active_latency_hiding_us; 154 int mall_svp_size_requirement_ways; 155 int nominal_vblank_pstate_latency_hiding_us; 156 int vactive_det_fill_delay_us[dml2_pstate_type_count]; 157 }; 158 159 struct core_stream_support_info { 160 unsigned int odms_used; 161 unsigned int num_odm_output_segments; // for odm split mode (e.g. a value of 2 for odm_mode_mso_1to2) 162 163 /* FAMS2 SubVP support info */ 164 unsigned int phantom_min_v_active; 165 unsigned int phantom_v_startup; 166 167 unsigned int phantom_v_active; 168 unsigned int phantom_v_total; 169 int vblank_reserved_time_us; 170 int num_dsc_slices; 171 bool dsc_enable; 172 }; 173 174 struct core_display_cfg_support_info { 175 bool is_supported; 176 177 struct core_stream_support_info stream_support_info[DML2_MAX_PLANES]; 178 struct core_plane_support_info plane_support_info[DML2_MAX_PLANES]; 179 180 struct { 181 struct dml2_core_internal_mode_support_info support_info; 182 } clean_me_up; 183 }; 184 185 struct dml2_core_mode_support_result { 186 struct { 187 struct { 188 unsigned long urgent_bw_sdp_kbps; 189 unsigned long average_bw_sdp_kbps; 190 unsigned long urgent_bw_dram_kbps; 191 unsigned long average_bw_dram_kbps; 192 unsigned long dcfclk_khz; 193 unsigned long fclk_khz; 194 } svp_prefetch; 195 196 struct { 197 unsigned long urgent_bw_sdp_kbps; 198 unsigned long average_bw_sdp_kbps; 199 unsigned long urgent_bw_dram_kbps; 200 unsigned long average_bw_dram_kbps; 201 unsigned long dcfclk_khz; 202 unsigned long fclk_khz; 203 } active; 204 205 unsigned int dispclk_khz; 206 unsigned int dpprefclk_khz; 207 unsigned int dtbrefclk_khz; 208 unsigned int dcfclk_deepsleep_khz; 209 unsigned int socclk_khz; 210 211 unsigned int uclk_pstate_supported; 212 unsigned int fclk_pstate_supported; 213 struct dml2_core_internal_watermarks watermarks; 214 } global; 215 216 struct { 217 unsigned int dscclk_khz; 218 unsigned int dtbclk_khz; 219 unsigned int phyclk_khz; 220 } per_stream[DML2_MAX_PLANES]; 221 222 struct { 223 unsigned int dppclk_khz; 224 unsigned int mall_svp_allocation_mblks; 225 unsigned int mall_full_frame_allocation_mblks; 226 } per_plane[DML2_MAX_PLANES]; 227 228 struct core_display_cfg_support_info cfg_support_info; 229 }; 230 231 struct dml2_optimization_stage1_state { 232 bool performed; 233 bool success; 234 235 int min_clk_index_for_latency; 236 }; 237 238 struct dml2_optimization_stage2_state { 239 bool performed; 240 bool success; 241 242 // Whether or not each plane supports mcache 243 // The number of valid elements == display_cfg.num_planes 244 // The indexing of pstate_switch_modes matches plane_descriptors[] 245 bool per_plane_mcache_support[DML2_MAX_PLANES]; 246 struct dml2_mcache_surface_allocation mcache_allocations[DML2_MAX_PLANES]; 247 }; 248 249 #define DML2_PMO_LEGACY_PREFETCH_MAX_TWAIT_OPTIONS 8 250 #define DML2_PMO_PSTATE_CANDIDATE_LIST_SIZE 10 251 #define DML2_PMO_STUTTER_CANDIDATE_LIST_SIZE 3 252 253 struct dml2_implicit_svp_meta { 254 bool valid; 255 unsigned long v_active; 256 unsigned long v_total; 257 unsigned long v_front_porch; 258 }; 259 260 struct dml2_pstate_per_method_common_meta { 261 /* generic params */ 262 int allow_start_otg_vline; 263 int allow_end_otg_vline; 264 /* scheduling params */ 265 double allow_time_us; 266 double disallow_time_us; 267 double period_us; 268 }; 269 270 struct dml2_pstate_meta { 271 bool valid; 272 double otg_vline_time_us; 273 int scheduling_delay_otg_vlines; 274 int vertical_interrupt_ack_delay_otg_vlines; 275 int allow_to_target_delay_otg_vlines; 276 int contention_delay_otg_vlines; 277 int min_allow_width_otg_vlines; 278 int nom_vtotal; 279 int vblank_start; 280 double nom_refresh_rate_hz; 281 double nom_frame_time_us; 282 int max_vtotal; 283 double min_refresh_rate_hz; 284 double max_frame_time_us; 285 int blackout_otg_vlines; 286 int max_allow_delay_otg_vlines; 287 double nom_vblank_time_us; 288 struct { 289 double max_vactive_det_fill_delay_us; 290 double vactive_latency_hiding_us; 291 double reserved_vblank_required_us; 292 int max_vactive_det_fill_delay_otg_vlines; 293 int reserved_blank_required_vlines; 294 struct dml2_pstate_per_method_common_meta common; 295 } method_vactive; 296 struct { 297 struct dml2_pstate_per_method_common_meta common; 298 } method_vblank; 299 struct { 300 int programming_delay_otg_vlines; 301 int df_throttle_delay_otg_vlines; 302 int prefetch_to_mall_delay_otg_vlines; 303 unsigned long phantom_vactive; 304 unsigned long phantom_vfp; 305 unsigned long phantom_vtotal; 306 struct dml2_pstate_per_method_common_meta common; 307 } method_subvp; 308 struct { 309 int programming_delay_otg_vlines; 310 int stretched_vtotal; 311 struct dml2_pstate_per_method_common_meta common; 312 } method_drr; 313 }; 314 315 /* mask of synchronized timings by stream index */ 316 struct dml2_pmo_synchronized_timing_groups { 317 unsigned int num_timing_groups; 318 unsigned int synchronized_timing_group_masks[DML2_MAX_PLANES]; 319 bool group_is_drr_enabled[DML2_MAX_PLANES]; 320 bool group_is_drr_active[DML2_MAX_PLANES]; 321 double group_line_time_us[DML2_MAX_PLANES]; 322 }; 323 324 struct dml2_optimization_stage3_state { 325 bool performed; 326 bool success; 327 328 // The pstate support mode for each plane 329 // The number of valid elements == display_cfg.num_planes 330 // The indexing of pstate_switch_modes matches plane_descriptors[] 331 enum dml2_pstate_method pstate_switch_modes[DML2_MAX_PLANES]; 332 333 // Meta-data for implicit SVP generation, indexed by stream index 334 struct dml2_implicit_svp_meta stream_svp_meta[DML2_MAX_PLANES]; 335 336 // Meta-data for FAMS2 337 bool fams2_required; 338 struct dml2_pstate_meta stream_pstate_meta[DML2_MAX_PLANES]; 339 340 int min_clk_index_for_latency; 341 }; 342 343 struct dml2_optimization_stage4_state { 344 bool performed; 345 bool success; 346 bool unoptimizable_streams[DML2_MAX_DCN_PIPES]; 347 }; 348 349 struct dml2_optimization_stage5_state { 350 bool performed; 351 bool success; 352 353 bool optimal_reserved_time_in_vblank_us; 354 bool vblank_includes_z8_optimization; 355 }; 356 357 struct display_configuation_with_meta { 358 struct dml2_display_cfg display_config; 359 360 struct dml2_core_mode_support_result mode_support_result; 361 362 // Stage 1 = Min Clocks for Latency 363 struct dml2_optimization_stage1_state stage1; 364 365 // Stage 2 = MCache 366 struct dml2_optimization_stage2_state stage2; 367 368 // Stage 3 = UCLK PState 369 struct dml2_optimization_stage3_state stage3; 370 371 // Stage 4 = Vmin 372 struct dml2_optimization_stage4_state stage4; 373 374 // Stage 5 = Stutter 375 struct dml2_optimization_stage5_state stage5; 376 }; 377 378 struct dml2_pmo_pstate_strategy { 379 enum dml2_pstate_method per_stream_pstate_method[DML2_MAX_PLANES]; 380 bool allow_state_increase; 381 }; 382 struct dml2_core_mode_support_in_out { 383 /* 384 * Inputs 385 */ 386 struct dml2_core_instance *instance; 387 const struct display_configuation_with_meta *display_cfg; 388 389 struct dml2_mcg_min_clock_table *min_clk_table; 390 int min_clk_index; 391 /* 392 * Outputs 393 */ 394 struct dml2_core_mode_support_result mode_support_result; 395 396 struct { 397 // Inputs 398 struct dml_display_cfg_st *display_cfg; 399 400 // Outputs 401 struct dml_mode_support_info_st *support_info; 402 unsigned int out_lowest_state_idx; 403 unsigned int min_fclk_khz; 404 unsigned int min_dcfclk_khz; 405 unsigned int min_dram_speed_mts; 406 unsigned int min_socclk_khz; 407 unsigned int min_dscclk_khz; 408 unsigned int min_dtbclk_khz; 409 unsigned int min_phyclk_khz; 410 } legacy; 411 }; 412 413 414 struct dml2_core_mode_programming_in_out { 415 /* 416 * Inputs 417 */ 418 struct dml2_core_instance *instance; 419 const struct display_configuation_with_meta *display_cfg; 420 const struct core_display_cfg_support_info *cfg_support_info; 421 /* 422 * Outputs (also Input the clk freq are also from programming struct) 423 */ 424 struct dml2_display_cfg_programming *programming; 425 426 }; 427 428 struct dml2_core_populate_informative_in_out { 429 /* 430 * Inputs 431 */ 432 struct dml2_core_instance *instance; 433 434 // If this is set, then the mode was supported, and mode programming 435 // was successfully run. 436 // Otherwise, mode programming was not run, because mode support failed. 437 bool mode_is_supported; 438 439 /* 440 * Outputs 441 */ 442 struct dml2_display_cfg_programming *programming; 443 }; 444 445 struct dml2_calculate_mcache_allocation_in_out { 446 /* 447 * Inputs 448 */ 449 struct dml2_core_instance *instance; 450 const struct dml2_plane_parameters *plane_descriptor; 451 unsigned int plane_index; 452 453 /* 454 * Outputs 455 */ 456 struct dml2_mcache_surface_allocation *mcache_allocation; 457 }; 458 459 struct dml2_core_internal_state_inputs { 460 unsigned int dummy; 461 }; 462 463 struct dml2_core_internal_state_intermediates { 464 unsigned int dummy; 465 }; 466 467 struct dml2_core_mode_support_locals { 468 union { 469 struct dml2_core_calcs_mode_support_ex mode_support_ex_params; 470 }; 471 struct dml2_display_cfg svp_expanded_display_cfg; 472 struct dml2_calculate_mcache_allocation_in_out calc_mcache_allocation_params; 473 }; 474 475 struct dml2_core_mode_programming_locals { 476 union { 477 struct dml2_core_calcs_mode_programming_ex mode_programming_ex_params; 478 }; 479 struct dml2_display_cfg svp_expanded_display_cfg; 480 }; 481 482 struct dml2_core_scratch { 483 struct dml2_core_mode_support_locals mode_support_locals; 484 struct dml2_core_mode_programming_locals mode_programming_locals; 485 int main_stream_index_from_svp_stream_index[DML2_MAX_PLANES]; 486 int svp_stream_index_from_main_stream_index[DML2_MAX_PLANES]; 487 int main_plane_index_to_phantom_plane_index[DML2_MAX_PLANES]; 488 int phantom_plane_index_to_main_plane_index[DML2_MAX_PLANES]; 489 }; 490 491 struct dml2_core_instance { 492 enum dml2_project_id project_id; 493 struct dml2_mcg_min_clock_table *minimum_clock_table; 494 struct dml2_core_internal_state_inputs inputs; 495 struct dml2_core_internal_state_intermediates intermediates; 496 497 struct dml2_core_scratch scratch; 498 499 bool (*initialize)(struct dml2_core_initialize_in_out *in_out); 500 bool (*mode_support)(struct dml2_core_mode_support_in_out *in_out); 501 bool (*mode_programming)(struct dml2_core_mode_programming_in_out *in_out); 502 bool (*populate_informative)(struct dml2_core_populate_informative_in_out *in_out); 503 bool (*calculate_mcache_allocation)(struct dml2_calculate_mcache_allocation_in_out *in_out); 504 505 506 struct { 507 struct dml2_core_internal_display_mode_lib mode_lib; 508 } clean_me_up; 509 }; 510 511 /* 512 * DML2 PMO Types and Interfaces 513 */ 514 515 struct dml2_pmo_initialize_in_out { 516 /* 517 * Input 518 */ 519 struct dml2_pmo_instance *instance; 520 struct dml2_soc_bb *soc_bb; 521 struct dml2_ip_capabilities *ip_caps; 522 struct dml2_pmo_options *options; 523 int mcg_clock_table_size; 524 }; 525 526 struct dml2_pmo_optimize_dcc_mcache_in_out { 527 /* 528 * Input 529 */ 530 struct dml2_pmo_instance *instance; 531 const struct dml2_display_cfg *display_config; 532 bool *dcc_mcache_supported; 533 struct core_display_cfg_support_info *cfg_support_info; 534 535 /* 536 * Output 537 */ 538 struct dml2_display_cfg *optimized_display_cfg; 539 }; 540 541 struct dml2_pmo_init_for_vmin_in_out { 542 /* 543 * Input 544 */ 545 struct dml2_pmo_instance *instance; 546 struct display_configuation_with_meta *base_display_config; 547 }; 548 549 struct dml2_pmo_test_for_vmin_in_out { 550 /* 551 * Input 552 */ 553 struct dml2_pmo_instance *instance; 554 const struct display_configuation_with_meta *display_config; 555 const struct dml2_soc_vmin_clock_limits *vmin_limits; 556 }; 557 558 struct dml2_pmo_optimize_for_vmin_in_out { 559 /* 560 * Input 561 */ 562 struct dml2_pmo_instance *instance; 563 struct display_configuation_with_meta *base_display_config; 564 565 /* 566 * Output 567 */ 568 struct display_configuation_with_meta *optimized_display_config; 569 }; 570 571 struct dml2_pmo_init_for_pstate_support_in_out { 572 /* 573 * Input 574 */ 575 struct dml2_pmo_instance *instance; 576 struct display_configuation_with_meta *base_display_config; 577 }; 578 579 struct dml2_pmo_test_for_pstate_support_in_out { 580 /* 581 * Input 582 */ 583 struct dml2_pmo_instance *instance; 584 struct display_configuation_with_meta *base_display_config; 585 }; 586 587 struct dml2_pmo_optimize_for_pstate_support_in_out { 588 /* 589 * Input 590 */ 591 struct dml2_pmo_instance *instance; 592 struct display_configuation_with_meta *base_display_config; 593 bool last_candidate_failed; 594 595 /* 596 * Output 597 */ 598 struct display_configuation_with_meta *optimized_display_config; 599 }; 600 601 struct dml2_pmo_init_for_stutter_in_out { 602 /* 603 * Input 604 */ 605 struct dml2_pmo_instance *instance; 606 struct display_configuation_with_meta *base_display_config; 607 }; 608 609 struct dml2_pmo_test_for_stutter_in_out { 610 /* 611 * Input 612 */ 613 struct dml2_pmo_instance *instance; 614 struct display_configuation_with_meta *base_display_config; 615 }; 616 617 struct dml2_pmo_optimize_for_stutter_in_out { 618 /* 619 * Input 620 */ 621 struct dml2_pmo_instance *instance; 622 struct display_configuation_with_meta *base_display_config; 623 bool last_candidate_failed; 624 625 /* 626 * Output 627 */ 628 struct display_configuation_with_meta *optimized_display_config; 629 }; 630 631 #define PMO_NO_DRR_STRATEGY_MASK (((1 << (dml2_pstate_method_reserved_fw - dml2_pstate_method_na + 1)) - 1) << dml2_pstate_method_na) 632 #define PMO_DRR_STRATEGY_MASK (((1 << (dml2_pstate_method_reserved_fw_drr_var - dml2_pstate_method_fw_vactive_drr + 1)) - 1) << dml2_pstate_method_fw_vactive_drr) 633 #define PMO_DRR_CLAMPED_STRATEGY_MASK (((1 << (dml2_pstate_method_reserved_fw_drr_clamped - dml2_pstate_method_fw_vactive_drr + 1)) - 1) << dml2_pstate_method_fw_vactive_drr) 634 #define PMO_DRR_VAR_STRATEGY_MASK (((1 << (dml2_pstate_method_reserved_fw_drr_var - dml2_pstate_method_fw_drr + 1)) - 1) << dml2_pstate_method_fw_drr) 635 #define PMO_FW_STRATEGY_MASK (((1 << (dml2_pstate_method_reserved_fw_drr_var - dml2_pstate_method_fw_svp + 1)) - 1) << dml2_pstate_method_fw_svp) 636 637 #define PMO_DCN4_MAX_DISPLAYS 4 638 #define PMO_DCN4_MAX_NUM_VARIANTS 2 639 #define PMO_DCN4_MAX_BASE_STRATEGIES 10 640 641 struct dml2_scheduling_check_locals { 642 struct dml2_pstate_per_method_common_meta group_common_pstate_meta[DML2_MAX_PLANES]; 643 unsigned int sorted_group_gtl_disallow_index[DML2_MAX_PLANES]; 644 unsigned int sorted_group_gtl_period_index[DML2_MAX_PLANES]; 645 }; 646 647 struct dml2_pmo_scratch { 648 union { 649 struct { 650 double reserved_time_candidates[DML2_MAX_PLANES][DML2_PMO_LEGACY_PREFETCH_MAX_TWAIT_OPTIONS]; 651 int reserved_time_candidates_count[DML2_MAX_PLANES]; 652 int current_candidate[DML2_MAX_PLANES]; 653 int min_latency_index; 654 int max_latency_index; 655 int cur_latency_index; 656 int stream_mask; 657 } pmo_dcn3; 658 struct { 659 struct dml2_pmo_pstate_strategy expanded_override_strategy_list[2 * 2 * 2 * 2]; 660 unsigned int num_expanded_override_strategies; 661 struct dml2_pmo_pstate_strategy pstate_strategy_candidates[DML2_PMO_PSTATE_CANDIDATE_LIST_SIZE]; 662 int num_pstate_candidates; 663 int cur_pstate_candidate; 664 665 unsigned int stream_plane_mask[DML2_MAX_PLANES]; 666 667 unsigned int stream_vactive_capability_mask; 668 669 int min_latency_index; 670 int max_latency_index; 671 int cur_latency_index; 672 673 // Stores all the implicit SVP meta information indexed by stream index of the display 674 // configuration under inspection, built at optimization stage init 675 struct dml2_implicit_svp_meta stream_svp_meta[DML2_MAX_PLANES]; 676 struct dml2_pstate_meta stream_pstate_meta[DML2_MAX_PLANES]; 677 678 unsigned int optimal_vblank_reserved_time_for_stutter_us[DML2_PMO_STUTTER_CANDIDATE_LIST_SIZE]; 679 unsigned int num_stutter_candidates; 680 unsigned int cur_stutter_candidate; 681 bool z8_vblank_optimizable; 682 683 /* mask of synchronized timings by stream index */ 684 unsigned int num_timing_groups; 685 unsigned int synchronized_timing_group_masks[DML2_MAX_PLANES]; 686 bool group_is_drr_enabled[DML2_MAX_PLANES]; 687 bool group_is_drr_active[DML2_MAX_PLANES]; 688 double group_line_time_us[DML2_MAX_PLANES]; 689 690 /* scheduling check locals */ 691 struct dml2_pstate_per_method_common_meta group_common_pstate_meta[DML2_MAX_PLANES]; 692 unsigned int sorted_group_gtl_disallow_index[DML2_MAX_PLANES]; 693 unsigned int sorted_group_gtl_period_index[DML2_MAX_PLANES]; 694 double group_phase_offset[DML2_MAX_PLANES]; 695 } pmo_dcn4; 696 }; 697 }; 698 699 struct dml2_pmo_init_data { 700 union { 701 struct { 702 /* populated once during initialization */ 703 struct dml2_pmo_pstate_strategy expanded_strategy_list_1_display[PMO_DCN4_MAX_BASE_STRATEGIES * 2]; 704 struct dml2_pmo_pstate_strategy expanded_strategy_list_2_display[PMO_DCN4_MAX_BASE_STRATEGIES * 4 * 4]; 705 struct dml2_pmo_pstate_strategy expanded_strategy_list_3_display[PMO_DCN4_MAX_BASE_STRATEGIES * 6 * 6 * 6]; 706 struct dml2_pmo_pstate_strategy expanded_strategy_list_4_display[PMO_DCN4_MAX_BASE_STRATEGIES * 8 * 8 * 8 * 8]; 707 unsigned int num_expanded_strategies_per_list[PMO_DCN4_MAX_DISPLAYS]; 708 } pmo_dcn4; 709 }; 710 }; 711 712 struct dml2_pmo_instance { 713 struct dml2_soc_bb *soc_bb; 714 struct dml2_ip_capabilities *ip_caps; 715 716 struct dml2_pmo_options *options; 717 718 int disp_clk_vmin_threshold; 719 int mpc_combine_limit; 720 int odm_combine_limit; 721 int mcg_clock_table_size; 722 union { 723 struct { 724 struct { 725 int prefetch_end_to_mall_start_us; 726 int fw_processing_delay_us; 727 int refresh_rate_limit_min; 728 int refresh_rate_limit_max; 729 } subvp; 730 } v1; 731 struct { 732 struct { 733 int refresh_rate_limit_min; 734 int refresh_rate_limit_max; 735 } subvp; 736 struct { 737 int refresh_rate_limit_min; 738 int refresh_rate_limit_max; 739 } drr; 740 } v2; 741 } fams_params; 742 743 bool (*initialize)(struct dml2_pmo_initialize_in_out *in_out); 744 bool (*optimize_dcc_mcache)(struct dml2_pmo_optimize_dcc_mcache_in_out *in_out); 745 746 bool (*init_for_vmin)(struct dml2_pmo_init_for_vmin_in_out *in_out); 747 bool (*test_for_vmin)(struct dml2_pmo_test_for_vmin_in_out *in_out); 748 bool (*optimize_for_vmin)(struct dml2_pmo_optimize_for_vmin_in_out *in_out); 749 750 bool (*init_for_uclk_pstate)(struct dml2_pmo_init_for_pstate_support_in_out *in_out); 751 bool (*test_for_uclk_pstate)(struct dml2_pmo_test_for_pstate_support_in_out *in_out); 752 bool (*optimize_for_uclk_pstate)(struct dml2_pmo_optimize_for_pstate_support_in_out *in_out); 753 754 bool (*init_for_stutter)(struct dml2_pmo_init_for_stutter_in_out *in_out); 755 bool (*test_for_stutter)(struct dml2_pmo_test_for_stutter_in_out *in_out); 756 bool (*optimize_for_stutter)(struct dml2_pmo_optimize_for_stutter_in_out *in_out); 757 758 759 struct dml2_pmo_init_data init_data; 760 struct dml2_pmo_scratch scratch; 761 }; 762 763 /* 764 * DML2 MCache Types 765 */ 766 767 struct top_mcache_validate_admissability_in_out { 768 struct dml2_instance *dml2_instance; 769 770 const struct dml2_display_cfg *display_cfg; 771 const struct core_display_cfg_support_info *cfg_support_info; 772 struct dml2_mcache_surface_allocation *mcache_allocations; 773 774 bool per_plane_status[DML2_MAX_PLANES]; 775 776 struct { 777 const struct dml_mode_support_info_st *mode_support_info; 778 } legacy; 779 }; 780 781 struct top_mcache_assign_ids_in_out { 782 /* 783 * Input 784 */ 785 const struct dml2_mcache_surface_allocation *mcache_allocations; 786 int plane_count; 787 788 int per_pipe_viewport_x_start[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES]; 789 int per_pipe_viewport_x_end[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES]; 790 int pipe_count_per_plane[DML2_MAX_PLANES]; 791 792 struct dml2_display_mcache_regs *current_mcache_regs[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES]; //One set per pipe/hubp 793 794 /* 795 * Output 796 */ 797 struct dml2_display_mcache_regs mcache_regs[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES]; //One set per pipe/hubp 798 struct dml2_build_mcache_programming_in_out *mcache_programming; 799 }; 800 801 struct top_mcache_calc_mcache_count_and_offsets_in_out { 802 /* 803 * Inputs 804 */ 805 struct dml2_instance *dml2_instance; 806 const struct dml2_display_cfg *display_config; 807 808 /* 809 * Outputs 810 */ 811 struct dml2_mcache_surface_allocation *mcache_allocations; 812 }; 813 814 struct top_mcache_assign_global_mcache_ids_in_out { 815 /* 816 * Inputs/Outputs 817 */ 818 struct dml2_mcache_surface_allocation *allocations; 819 int num_allocations; 820 }; 821 822 /* 823 * DML2 Top Types 824 */ 825 826 struct dml2_initialize_instance_locals { 827 int dummy; 828 }; 829 830 struct dml2_optimization_init_function_locals { 831 union { 832 struct { 833 struct dml2_pmo_init_for_pstate_support_in_out init_params; 834 } uclk_pstate; 835 struct { 836 struct dml2_pmo_init_for_stutter_in_out stutter_params; 837 } stutter; 838 struct { 839 struct dml2_pmo_init_for_vmin_in_out init_params; 840 } vmin; 841 }; 842 }; 843 844 struct dml2_optimization_test_function_locals { 845 union { 846 struct { 847 struct top_mcache_calc_mcache_count_and_offsets_in_out calc_mcache_count_params; 848 struct top_mcache_assign_global_mcache_ids_in_out assign_global_mcache_ids_params; 849 struct top_mcache_validate_admissability_in_out validate_admissibility_params; 850 } test_mcache; 851 struct { 852 struct dml2_pmo_test_for_vmin_in_out pmo_test_vmin_params; 853 } test_vmin; 854 struct { 855 struct dml2_pmo_test_for_pstate_support_in_out test_params; 856 } uclk_pstate; 857 struct { 858 struct dml2_pmo_test_for_stutter_in_out stutter_params; 859 } stutter; 860 }; 861 }; 862 863 struct dml2_optimization_optimize_function_locals { 864 union { 865 struct { 866 struct dml2_pmo_optimize_dcc_mcache_in_out optimize_mcache_params; 867 } optimize_mcache; 868 struct { 869 struct dml2_pmo_optimize_for_vmin_in_out pmo_optimize_vmin_params; 870 } optimize_vmin; 871 struct { 872 struct dml2_pmo_optimize_for_pstate_support_in_out optimize_params; 873 } uclk_pstate; 874 struct { 875 struct dml2_pmo_optimize_for_stutter_in_out stutter_params; 876 } stutter; 877 }; 878 }; 879 880 struct dml2_optimization_phase_locals { 881 struct display_configuation_with_meta cur_candidate_display_cfg; 882 struct display_configuation_with_meta next_candidate_display_cfg; 883 struct dml2_core_mode_support_in_out mode_support_params; 884 struct dml2_optimization_init_function_locals init_function_locals; 885 struct dml2_optimization_test_function_locals test_function_locals; 886 struct dml2_optimization_optimize_function_locals optimize_function_locals; 887 }; 888 889 struct dml2_check_mode_supported_locals { 890 struct dml2_display_cfg display_cfg_working_copy; 891 struct dml2_core_mode_support_in_out mode_support_params; 892 struct dml2_optimization_phase_locals optimization_phase_locals; 893 struct display_configuation_with_meta base_display_config_with_meta; 894 struct display_configuation_with_meta optimized_display_config_with_meta; 895 struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out dppm_map_mode_params; 896 }; 897 898 struct optimization_init_function_params { 899 struct dml2_optimization_init_function_locals *locals; 900 struct dml2_instance *dml; 901 struct display_configuation_with_meta *display_config; 902 }; 903 904 struct optimization_test_function_params { 905 struct dml2_optimization_test_function_locals *locals; 906 struct dml2_instance *dml; 907 struct display_configuation_with_meta *display_config; 908 }; 909 910 struct optimization_optimize_function_params { 911 bool last_candidate_supported; 912 struct dml2_optimization_optimize_function_locals *locals; 913 struct dml2_instance *dml; 914 struct display_configuation_with_meta *display_config; 915 struct display_configuation_with_meta *optimized_display_config; 916 }; 917 918 struct optimization_phase_params { 919 struct dml2_instance *dml; 920 const struct display_configuation_with_meta *display_config; // Initial Display Configuration 921 bool (*init_function)(const struct optimization_init_function_params *params); // Test function to determine optimization is complete 922 bool (*test_function)(const struct optimization_test_function_params *params); // Test function to determine optimization is complete 923 bool (*optimize_function)(const struct optimization_optimize_function_params *params); // Function which produces a more optimized display configuration 924 struct display_configuation_with_meta *optimized_display_config; // The optimized display configuration 925 926 bool all_or_nothing; 927 }; 928 929 struct dml2_build_mode_programming_locals { 930 struct dml2_core_mode_support_in_out mode_support_params; 931 struct dml2_core_mode_programming_in_out mode_programming_params; 932 struct dml2_core_populate_informative_in_out informative_params; 933 struct dml2_pmo_optimize_dcc_mcache_in_out optimize_mcache_params; 934 struct display_configuation_with_meta base_display_config_with_meta; 935 struct display_configuation_with_meta optimized_display_config_with_meta; 936 struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out dppm_map_mode_params; 937 struct dml2_dpmm_map_watermarks_params_in_out dppm_map_watermarks_params; 938 struct dml2_optimization_phase_locals optimization_phase_locals; 939 struct optimization_phase_params min_clock_for_latency_phase; 940 struct optimization_phase_params mcache_phase; 941 struct optimization_phase_params uclk_pstate_phase; 942 struct optimization_phase_params vmin_phase; 943 struct optimization_phase_params stutter_phase; 944 }; 945 946 struct dml2_legacy_core_build_mode_programming_wrapper_locals { 947 struct dml2_core_mode_support_in_out mode_support_params; 948 struct dml2_core_mode_programming_in_out mode_programming_params; 949 struct dml2_core_populate_informative_in_out informative_params; 950 struct top_mcache_calc_mcache_count_and_offsets_in_out calc_mcache_count_params; 951 struct top_mcache_validate_admissability_in_out validate_admissibility_params; 952 struct dml2_mcache_surface_allocation mcache_allocations[DML2_MAX_PLANES]; 953 struct top_mcache_assign_global_mcache_ids_in_out assign_global_mcache_ids_params; 954 struct dml2_pmo_optimize_dcc_mcache_in_out optimize_mcache_params; 955 struct dml2_display_cfg optimized_display_cfg; 956 struct core_display_cfg_support_info core_support_info; 957 }; 958 959 struct dml2_top_mcache_verify_mcache_size_locals { 960 struct dml2_calculate_mcache_allocation_in_out calc_mcache_params; 961 }; 962 963 struct dml2_top_mcache_validate_admissability_locals { 964 struct { 965 int pipe_vp_startx[DML2_MAX_DCN_PIPES]; 966 int pipe_vp_endx[DML2_MAX_DCN_PIPES]; 967 } plane0; 968 struct { 969 int pipe_vp_startx[DML2_MAX_DCN_PIPES]; 970 int pipe_vp_endx[DML2_MAX_DCN_PIPES]; 971 } plane1; 972 }; 973 974 struct dml2_top_display_cfg_support_info { 975 const struct dml2_display_cfg *display_config; 976 struct core_display_cfg_support_info core_info; 977 }; 978 979 struct dml2_top_funcs { 980 bool (*check_mode_supported)(struct dml2_check_mode_supported_in_out *in_out); 981 bool (*build_mode_programming)(struct dml2_build_mode_programming_in_out *in_out); 982 bool (*build_mcache_programming)(struct dml2_build_mcache_programming_in_out *in_out); 983 }; 984 985 struct dml2_instance { 986 enum dml2_project_id project_id; 987 988 struct dml2_core_instance core_instance; 989 struct dml2_mcg_instance mcg_instance; 990 struct dml2_dpmm_instance dpmm_instance; 991 struct dml2_pmo_instance pmo_instance; 992 993 struct dml2_soc_bb soc_bbox; 994 struct dml2_ip_capabilities ip_caps; 995 996 struct dml2_mcg_min_clock_table min_clk_table; 997 struct dml2_pmo_options pmo_options; 998 struct dml2_top_funcs funcs; 999 1000 struct { 1001 struct dml2_initialize_instance_locals initialize_instance_locals; 1002 struct dml2_top_mcache_verify_mcache_size_locals mcache_verify_mcache_size_locals; 1003 struct dml2_top_mcache_validate_admissability_locals mcache_validate_admissability_locals; 1004 struct dml2_check_mode_supported_locals check_mode_supported_locals; 1005 struct dml2_build_mode_programming_locals build_mode_programming_locals; 1006 } scratch; 1007 1008 struct { 1009 struct { 1010 struct dml2_legacy_core_build_mode_programming_wrapper_locals legacy_core_build_mode_programming_wrapper_locals; 1011 } scratch; 1012 } legacy; 1013 }; 1014 #endif 1015