1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2022 Schneider Electric
4 *
5 * Clément Léger <clement.leger@bootlin.com>
6 */
7
8 #include <linux/clk.h>
9 #include <linux/device.h>
10 #include <linux/mdio.h>
11 #include <linux/of.h>
12 #include <linux/of_platform.h>
13 #include <linux/pcs-rzn1-miic.h>
14 #include <linux/phylink.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <dt-bindings/net/pcs-rzn1-miic.h>
18
19 #define MIIC_PRCMD 0x0
20 #define MIIC_ESID_CODE 0x4
21
22 #define MIIC_MODCTRL 0x20
23 #define MIIC_MODCTRL_SW_MODE GENMASK(4, 0)
24
25 #define MIIC_CONVCTRL(port) (0x100 + (port) * 4)
26
27 #define MIIC_CONVCTRL_CONV_SPEED GENMASK(1, 0)
28 #define CONV_MODE_10MBPS 0
29 #define CONV_MODE_100MBPS 1
30 #define CONV_MODE_1000MBPS 2
31
32 #define MIIC_CONVCTRL_CONV_MODE GENMASK(3, 2)
33 #define CONV_MODE_MII 0
34 #define CONV_MODE_RMII 1
35 #define CONV_MODE_RGMII 2
36
37 #define MIIC_CONVCTRL_FULLD BIT(8)
38 #define MIIC_CONVCTRL_RGMII_LINK BIT(12)
39 #define MIIC_CONVCTRL_RGMII_DUPLEX BIT(13)
40 #define MIIC_CONVCTRL_RGMII_SPEED GENMASK(15, 14)
41
42 #define MIIC_CONVRST 0x114
43 #define MIIC_CONVRST_PHYIF_RST(port) BIT(port)
44 #define MIIC_CONVRST_PHYIF_RST_MASK GENMASK(4, 0)
45
46 #define MIIC_SWCTRL 0x304
47 #define MIIC_SWDUPC 0x308
48
49 #define MIIC_MAX_NR_PORTS 5
50
51 #define MIIC_MODCTRL_CONF_CONV_NUM 6
52 #define MIIC_MODCTRL_CONF_NONE -1
53
54 /**
55 * struct modctrl_match - Matching table entry for convctrl configuration
56 * See section 8.2.1 of manual.
57 * @mode_cfg: Configuration value for convctrl
58 * @conv: Configuration of ethernet port muxes. First index is SWITCH_PORTIN,
59 * then index 1 - 5 are CONV1 - CONV5.
60 */
61 struct modctrl_match {
62 u32 mode_cfg;
63 u8 conv[MIIC_MODCTRL_CONF_CONV_NUM];
64 };
65
66 static struct modctrl_match modctrl_match_table[] = {
67 {0x0, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
68 MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}},
69 {0x1, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
70 MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
71 {0x2, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
72 MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
73 {0x3, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
74 MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}},
75
76 {0x8, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
77 MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}},
78 {0x9, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
79 MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
80 {0xA, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
81 MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
82 {0xB, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
83 MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}},
84
85 {0x10, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
86 MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}},
87 {0x11, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
88 MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
89 {0x12, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
90 MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
91 {0x13, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
92 MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}}
93 };
94
95 static const char * const conf_to_string[] = {
96 [MIIC_GMAC1_PORT] = "GMAC1_PORT",
97 [MIIC_GMAC2_PORT] = "GMAC2_PORT",
98 [MIIC_RTOS_PORT] = "RTOS_PORT",
99 [MIIC_SERCOS_PORTA] = "SERCOS_PORTA",
100 [MIIC_SERCOS_PORTB] = "SERCOS_PORTB",
101 [MIIC_ETHERCAT_PORTA] = "ETHERCAT_PORTA",
102 [MIIC_ETHERCAT_PORTB] = "ETHERCAT_PORTB",
103 [MIIC_ETHERCAT_PORTC] = "ETHERCAT_PORTC",
104 [MIIC_SWITCH_PORTA] = "SWITCH_PORTA",
105 [MIIC_SWITCH_PORTB] = "SWITCH_PORTB",
106 [MIIC_SWITCH_PORTC] = "SWITCH_PORTC",
107 [MIIC_SWITCH_PORTD] = "SWITCH_PORTD",
108 [MIIC_HSR_PORTA] = "HSR_PORTA",
109 [MIIC_HSR_PORTB] = "HSR_PORTB",
110 };
111
112 static const char *index_to_string[MIIC_MODCTRL_CONF_CONV_NUM] = {
113 "SWITCH_PORTIN",
114 "CONV1",
115 "CONV2",
116 "CONV3",
117 "CONV4",
118 "CONV5",
119 };
120
121 /**
122 * struct miic - MII converter structure
123 * @base: base address of the MII converter
124 * @dev: Device associated to the MII converter
125 * @lock: Lock used for read-modify-write access
126 */
127 struct miic {
128 void __iomem *base;
129 struct device *dev;
130 spinlock_t lock;
131 };
132
133 /**
134 * struct miic_port - Per port MII converter struct
135 * @miic: backiling to MII converter structure
136 * @pcs: PCS structure associated to the port
137 * @port: port number
138 * @interface: interface mode of the port
139 */
140 struct miic_port {
141 struct miic *miic;
142 struct phylink_pcs pcs;
143 int port;
144 phy_interface_t interface;
145 };
146
phylink_pcs_to_miic_port(struct phylink_pcs * pcs)147 static struct miic_port *phylink_pcs_to_miic_port(struct phylink_pcs *pcs)
148 {
149 return container_of(pcs, struct miic_port, pcs);
150 }
151
miic_reg_writel(struct miic * miic,int offset,u32 value)152 static void miic_reg_writel(struct miic *miic, int offset, u32 value)
153 {
154 writel(value, miic->base + offset);
155 }
156
miic_reg_readl(struct miic * miic,int offset)157 static u32 miic_reg_readl(struct miic *miic, int offset)
158 {
159 return readl(miic->base + offset);
160 }
161
miic_reg_rmw(struct miic * miic,int offset,u32 mask,u32 val)162 static void miic_reg_rmw(struct miic *miic, int offset, u32 mask, u32 val)
163 {
164 u32 reg;
165
166 spin_lock(&miic->lock);
167
168 reg = miic_reg_readl(miic, offset);
169 reg &= ~mask;
170 reg |= val;
171 miic_reg_writel(miic, offset, reg);
172
173 spin_unlock(&miic->lock);
174 }
175
miic_converter_enable(struct miic * miic,int port,int enable)176 static void miic_converter_enable(struct miic *miic, int port, int enable)
177 {
178 u32 val = 0;
179
180 if (enable)
181 val = MIIC_CONVRST_PHYIF_RST(port);
182
183 miic_reg_rmw(miic, MIIC_CONVRST, MIIC_CONVRST_PHYIF_RST(port), val);
184 }
185
miic_config(struct phylink_pcs * pcs,unsigned int neg_mode,phy_interface_t interface,const unsigned long * advertising,bool permit)186 static int miic_config(struct phylink_pcs *pcs, unsigned int neg_mode,
187 phy_interface_t interface,
188 const unsigned long *advertising, bool permit)
189 {
190 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs);
191 struct miic *miic = miic_port->miic;
192 u32 speed, conv_mode, val, mask;
193 int port = miic_port->port;
194
195 switch (interface) {
196 case PHY_INTERFACE_MODE_RMII:
197 conv_mode = CONV_MODE_RMII;
198 speed = CONV_MODE_100MBPS;
199 break;
200 case PHY_INTERFACE_MODE_RGMII:
201 case PHY_INTERFACE_MODE_RGMII_ID:
202 case PHY_INTERFACE_MODE_RGMII_TXID:
203 case PHY_INTERFACE_MODE_RGMII_RXID:
204 conv_mode = CONV_MODE_RGMII;
205 speed = CONV_MODE_1000MBPS;
206 break;
207 case PHY_INTERFACE_MODE_MII:
208 conv_mode = CONV_MODE_MII;
209 /* When in MII mode, speed should be set to 0 (which is actually
210 * CONV_MODE_10MBPS)
211 */
212 speed = CONV_MODE_10MBPS;
213 break;
214 default:
215 return -EOPNOTSUPP;
216 }
217
218 val = FIELD_PREP(MIIC_CONVCTRL_CONV_MODE, conv_mode);
219 mask = MIIC_CONVCTRL_CONV_MODE;
220
221 /* Update speed only if we are going to change the interface because
222 * the link might already be up and it would break it if the speed is
223 * changed.
224 */
225 if (interface != miic_port->interface) {
226 val |= FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, speed);
227 mask |= MIIC_CONVCTRL_CONV_SPEED;
228 miic_port->interface = interface;
229 }
230
231 miic_reg_rmw(miic, MIIC_CONVCTRL(port), mask, val);
232 miic_converter_enable(miic, miic_port->port, 1);
233
234 return 0;
235 }
236
miic_link_up(struct phylink_pcs * pcs,unsigned int neg_mode,phy_interface_t interface,int speed,int duplex)237 static void miic_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
238 phy_interface_t interface, int speed, int duplex)
239 {
240 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs);
241 struct miic *miic = miic_port->miic;
242 u32 conv_speed = 0, val = 0;
243 int port = miic_port->port;
244
245 if (duplex == DUPLEX_FULL)
246 val |= MIIC_CONVCTRL_FULLD;
247
248 /* No speed in MII through-mode */
249 if (interface != PHY_INTERFACE_MODE_MII) {
250 switch (speed) {
251 case SPEED_1000:
252 conv_speed = CONV_MODE_1000MBPS;
253 break;
254 case SPEED_100:
255 conv_speed = CONV_MODE_100MBPS;
256 break;
257 case SPEED_10:
258 conv_speed = CONV_MODE_10MBPS;
259 break;
260 default:
261 return;
262 }
263 }
264
265 val |= FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, conv_speed);
266
267 miic_reg_rmw(miic, MIIC_CONVCTRL(port),
268 (MIIC_CONVCTRL_CONV_SPEED | MIIC_CONVCTRL_FULLD), val);
269 }
270
miic_pre_init(struct phylink_pcs * pcs)271 static int miic_pre_init(struct phylink_pcs *pcs)
272 {
273 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs);
274 struct miic *miic = miic_port->miic;
275 u32 val, mask;
276
277 /* Start RX clock if required */
278 if (pcs->rxc_always_on) {
279 /* In MII through mode, the clock signals will be driven by the
280 * external PHY, which might not be initialized yet. Set RMII
281 * as default mode to ensure that a reference clock signal is
282 * generated.
283 */
284 miic_port->interface = PHY_INTERFACE_MODE_RMII;
285
286 val = FIELD_PREP(MIIC_CONVCTRL_CONV_MODE, CONV_MODE_RMII) |
287 FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, CONV_MODE_100MBPS);
288 mask = MIIC_CONVCTRL_CONV_MODE | MIIC_CONVCTRL_CONV_SPEED;
289
290 miic_reg_rmw(miic, MIIC_CONVCTRL(miic_port->port), mask, val);
291
292 miic_converter_enable(miic, miic_port->port, 1);
293 }
294
295 return 0;
296 }
297
298 static const struct phylink_pcs_ops miic_phylink_ops = {
299 .pcs_config = miic_config,
300 .pcs_link_up = miic_link_up,
301 .pcs_pre_init = miic_pre_init,
302 };
303
miic_create(struct device * dev,struct device_node * np)304 struct phylink_pcs *miic_create(struct device *dev, struct device_node *np)
305 {
306 struct platform_device *pdev;
307 struct miic_port *miic_port;
308 struct device_node *pcs_np;
309 struct miic *miic;
310 u32 port;
311
312 if (!of_device_is_available(np))
313 return ERR_PTR(-ENODEV);
314
315 if (of_property_read_u32(np, "reg", &port))
316 return ERR_PTR(-EINVAL);
317
318 if (port > MIIC_MAX_NR_PORTS || port < 1)
319 return ERR_PTR(-EINVAL);
320
321 /* The PCS pdev is attached to the parent node */
322 pcs_np = of_get_parent(np);
323 if (!pcs_np)
324 return ERR_PTR(-ENODEV);
325
326 if (!of_device_is_available(pcs_np)) {
327 of_node_put(pcs_np);
328 return ERR_PTR(-ENODEV);
329 }
330
331 pdev = of_find_device_by_node(pcs_np);
332 of_node_put(pcs_np);
333 if (!pdev || !platform_get_drvdata(pdev)) {
334 if (pdev)
335 put_device(&pdev->dev);
336 return ERR_PTR(-EPROBE_DEFER);
337 }
338
339 miic_port = kzalloc(sizeof(*miic_port), GFP_KERNEL);
340 if (!miic_port) {
341 put_device(&pdev->dev);
342 return ERR_PTR(-ENOMEM);
343 }
344
345 miic = platform_get_drvdata(pdev);
346 device_link_add(dev, miic->dev, DL_FLAG_AUTOREMOVE_CONSUMER);
347 put_device(&pdev->dev);
348
349 miic_port->miic = miic;
350 miic_port->port = port - 1;
351 miic_port->pcs.ops = &miic_phylink_ops;
352
353 phy_interface_set_rgmii(miic_port->pcs.supported_interfaces);
354 __set_bit(PHY_INTERFACE_MODE_RMII, miic_port->pcs.supported_interfaces);
355 __set_bit(PHY_INTERFACE_MODE_MII, miic_port->pcs.supported_interfaces);
356
357 return &miic_port->pcs;
358 }
359 EXPORT_SYMBOL(miic_create);
360
miic_destroy(struct phylink_pcs * pcs)361 void miic_destroy(struct phylink_pcs *pcs)
362 {
363 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs);
364
365 miic_converter_enable(miic_port->miic, miic_port->port, 0);
366 kfree(miic_port);
367 }
368 EXPORT_SYMBOL(miic_destroy);
369
miic_init_hw(struct miic * miic,u32 cfg_mode)370 static int miic_init_hw(struct miic *miic, u32 cfg_mode)
371 {
372 int port;
373
374 /* Unlock write access to accessory registers (cf datasheet). If this
375 * is going to be used in conjunction with the Cortex-M3, this sequence
376 * will have to be moved in register write
377 */
378 miic_reg_writel(miic, MIIC_PRCMD, 0x00A5);
379 miic_reg_writel(miic, MIIC_PRCMD, 0x0001);
380 miic_reg_writel(miic, MIIC_PRCMD, 0xFFFE);
381 miic_reg_writel(miic, MIIC_PRCMD, 0x0001);
382
383 miic_reg_writel(miic, MIIC_MODCTRL,
384 FIELD_PREP(MIIC_MODCTRL_SW_MODE, cfg_mode));
385
386 for (port = 0; port < MIIC_MAX_NR_PORTS; port++) {
387 miic_converter_enable(miic, port, 0);
388 /* Disable speed/duplex control from these registers, datasheet
389 * says switch registers should be used to setup switch port
390 * speed and duplex.
391 */
392 miic_reg_writel(miic, MIIC_SWCTRL, 0x0);
393 miic_reg_writel(miic, MIIC_SWDUPC, 0x0);
394 }
395
396 return 0;
397 }
398
miic_modctrl_match(s8 table_val[MIIC_MODCTRL_CONF_CONV_NUM],s8 dt_val[MIIC_MODCTRL_CONF_CONV_NUM])399 static bool miic_modctrl_match(s8 table_val[MIIC_MODCTRL_CONF_CONV_NUM],
400 s8 dt_val[MIIC_MODCTRL_CONF_CONV_NUM])
401 {
402 int i;
403
404 for (i = 0; i < MIIC_MODCTRL_CONF_CONV_NUM; i++) {
405 if (dt_val[i] == MIIC_MODCTRL_CONF_NONE)
406 continue;
407
408 if (dt_val[i] != table_val[i])
409 return false;
410 }
411
412 return true;
413 }
414
miic_dump_conf(struct device * dev,s8 conf[MIIC_MODCTRL_CONF_CONV_NUM])415 static void miic_dump_conf(struct device *dev,
416 s8 conf[MIIC_MODCTRL_CONF_CONV_NUM])
417 {
418 const char *conf_name;
419 int i;
420
421 for (i = 0; i < MIIC_MODCTRL_CONF_CONV_NUM; i++) {
422 if (conf[i] != MIIC_MODCTRL_CONF_NONE)
423 conf_name = conf_to_string[conf[i]];
424 else
425 conf_name = "NONE";
426
427 dev_err(dev, "%s: %s\n", index_to_string[i], conf_name);
428 }
429 }
430
miic_match_dt_conf(struct device * dev,s8 dt_val[MIIC_MODCTRL_CONF_CONV_NUM],u32 * mode_cfg)431 static int miic_match_dt_conf(struct device *dev,
432 s8 dt_val[MIIC_MODCTRL_CONF_CONV_NUM],
433 u32 *mode_cfg)
434 {
435 struct modctrl_match *table_entry;
436 int i;
437
438 for (i = 0; i < ARRAY_SIZE(modctrl_match_table); i++) {
439 table_entry = &modctrl_match_table[i];
440
441 if (miic_modctrl_match(table_entry->conv, dt_val)) {
442 *mode_cfg = table_entry->mode_cfg;
443 return 0;
444 }
445 }
446
447 dev_err(dev, "Failed to apply requested configuration\n");
448 miic_dump_conf(dev, dt_val);
449
450 return -EINVAL;
451 }
452
miic_parse_dt(struct device * dev,u32 * mode_cfg)453 static int miic_parse_dt(struct device *dev, u32 *mode_cfg)
454 {
455 s8 dt_val[MIIC_MODCTRL_CONF_CONV_NUM];
456 struct device_node *np = dev->of_node;
457 struct device_node *conv;
458 u32 conf;
459 int port;
460
461 memset(dt_val, MIIC_MODCTRL_CONF_NONE, sizeof(dt_val));
462
463 if (of_property_read_u32(np, "renesas,miic-switch-portin", &conf) == 0)
464 dt_val[0] = conf;
465
466 for_each_available_child_of_node(np, conv) {
467 if (of_property_read_u32(conv, "reg", &port))
468 continue;
469
470 if (of_property_read_u32(conv, "renesas,miic-input", &conf) == 0)
471 dt_val[port] = conf;
472 }
473
474 return miic_match_dt_conf(dev, dt_val, mode_cfg);
475 }
476
miic_probe(struct platform_device * pdev)477 static int miic_probe(struct platform_device *pdev)
478 {
479 struct device *dev = &pdev->dev;
480 struct miic *miic;
481 u32 mode_cfg;
482 int ret;
483
484 ret = miic_parse_dt(dev, &mode_cfg);
485 if (ret < 0)
486 return ret;
487
488 miic = devm_kzalloc(dev, sizeof(*miic), GFP_KERNEL);
489 if (!miic)
490 return -ENOMEM;
491
492 spin_lock_init(&miic->lock);
493 miic->dev = dev;
494 miic->base = devm_platform_ioremap_resource(pdev, 0);
495 if (IS_ERR(miic->base))
496 return PTR_ERR(miic->base);
497
498 ret = devm_pm_runtime_enable(dev);
499 if (ret < 0)
500 return ret;
501
502 ret = pm_runtime_resume_and_get(dev);
503 if (ret < 0)
504 return ret;
505
506 ret = miic_init_hw(miic, mode_cfg);
507 if (ret)
508 goto disable_runtime_pm;
509
510 /* miic_create() relies on that fact that data are attached to the
511 * platform device to determine if the driver is ready so this needs to
512 * be the last thing to be done after everything is initialized
513 * properly.
514 */
515 platform_set_drvdata(pdev, miic);
516
517 return 0;
518
519 disable_runtime_pm:
520 pm_runtime_put(dev);
521
522 return ret;
523 }
524
miic_remove(struct platform_device * pdev)525 static void miic_remove(struct platform_device *pdev)
526 {
527 pm_runtime_put(&pdev->dev);
528 }
529
530 static const struct of_device_id miic_of_mtable[] = {
531 { .compatible = "renesas,rzn1-miic" },
532 { /* sentinel */ },
533 };
534 MODULE_DEVICE_TABLE(of, miic_of_mtable);
535
536 static struct platform_driver miic_driver = {
537 .driver = {
538 .name = "rzn1_miic",
539 .suppress_bind_attrs = true,
540 .of_match_table = miic_of_mtable,
541 },
542 .probe = miic_probe,
543 .remove = miic_remove,
544 };
545 module_platform_driver(miic_driver);
546
547 MODULE_LICENSE("GPL");
548 MODULE_DESCRIPTION("Renesas MII converter PCS driver");
549 MODULE_AUTHOR("Clément Léger <clement.leger@bootlin.com>");
550