1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * stv0900_core.c
4 *
5 * Driver for ST STV0900 satellite demodulator IC.
6 *
7 * Copyright (C) ST Microelectronics.
8 * Copyright (C) 2009 NetUP Inc.
9 * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/string.h>
15 #include <linux/slab.h>
16 #include <linux/i2c.h>
17
18 #include "stv0900.h"
19 #include "stv0900_reg.h"
20 #include "stv0900_priv.h"
21 #include "stv0900_init.h"
22
23 int stvdebug = 1;
24 module_param_named(debug, stvdebug, int, 0644);
25
26 /* internal params node */
27 struct stv0900_inode {
28 /* pointer for internal params, one for each pair of demods */
29 struct stv0900_internal *internal;
30 struct stv0900_inode *next_inode;
31 };
32
33 /* first internal params */
34 static struct stv0900_inode *stv0900_first_inode;
35
36 /* find chip by i2c adapter and i2c address */
find_inode(struct i2c_adapter * i2c_adap,u8 i2c_addr)37 static struct stv0900_inode *find_inode(struct i2c_adapter *i2c_adap,
38 u8 i2c_addr)
39 {
40 struct stv0900_inode *temp_chip = stv0900_first_inode;
41
42 if (temp_chip != NULL) {
43 /*
44 Search of the last stv0900 chip or
45 find it by i2c adapter and i2c address */
46 while ((temp_chip != NULL) &&
47 ((temp_chip->internal->i2c_adap != i2c_adap) ||
48 (temp_chip->internal->i2c_addr != i2c_addr)))
49
50 temp_chip = temp_chip->next_inode;
51
52 }
53
54 return temp_chip;
55 }
56
57 /* deallocating chip */
remove_inode(struct stv0900_internal * internal)58 static void remove_inode(struct stv0900_internal *internal)
59 {
60 struct stv0900_inode *prev_node = stv0900_first_inode;
61 struct stv0900_inode *del_node = find_inode(internal->i2c_adap,
62 internal->i2c_addr);
63
64 if (del_node != NULL) {
65 if (del_node == stv0900_first_inode) {
66 stv0900_first_inode = del_node->next_inode;
67 } else {
68 while (prev_node->next_inode != del_node)
69 prev_node = prev_node->next_inode;
70
71 if (del_node->next_inode == NULL)
72 prev_node->next_inode = NULL;
73 else
74 prev_node->next_inode =
75 prev_node->next_inode->next_inode;
76 }
77
78 kfree(del_node);
79 }
80 }
81
82 /* allocating new chip */
append_internal(struct stv0900_internal * internal)83 static struct stv0900_inode *append_internal(struct stv0900_internal *internal)
84 {
85 struct stv0900_inode *new_node = stv0900_first_inode;
86
87 if (new_node == NULL) {
88 new_node = kmalloc_obj(struct stv0900_inode);
89 stv0900_first_inode = new_node;
90 } else {
91 while (new_node->next_inode != NULL)
92 new_node = new_node->next_inode;
93
94 new_node->next_inode = kmalloc_obj(struct stv0900_inode);
95 if (new_node->next_inode != NULL)
96 new_node = new_node->next_inode;
97 else
98 new_node = NULL;
99 }
100
101 if (new_node != NULL) {
102 new_node->internal = internal;
103 new_node->next_inode = NULL;
104 }
105
106 return new_node;
107 }
108
ge2comp(s32 a,s32 width)109 s32 ge2comp(s32 a, s32 width)
110 {
111 if (width == 32)
112 return a;
113 else
114 return (a >= (1 << (width - 1))) ? (a - (1 << width)) : a;
115 }
116
stv0900_write_reg(struct stv0900_internal * intp,u16 reg_addr,u8 reg_data)117 void stv0900_write_reg(struct stv0900_internal *intp, u16 reg_addr,
118 u8 reg_data)
119 {
120 u8 data[3];
121 int ret;
122 struct i2c_msg i2cmsg = {
123 .addr = intp->i2c_addr,
124 .flags = 0,
125 .len = 3,
126 .buf = data,
127 };
128
129 data[0] = MSB(reg_addr);
130 data[1] = LSB(reg_addr);
131 data[2] = reg_data;
132
133 ret = i2c_transfer(intp->i2c_adap, &i2cmsg, 1);
134 if (ret != 1)
135 dprintk("%s: i2c error %d\n", __func__, ret);
136 }
137
stv0900_read_reg(struct stv0900_internal * intp,u16 reg)138 u8 stv0900_read_reg(struct stv0900_internal *intp, u16 reg)
139 {
140 int ret;
141 u8 b0[] = { MSB(reg), LSB(reg) };
142 u8 buf = 0;
143 struct i2c_msg msg[] = {
144 {
145 .addr = intp->i2c_addr,
146 .flags = 0,
147 .buf = b0,
148 .len = 2,
149 }, {
150 .addr = intp->i2c_addr,
151 .flags = I2C_M_RD,
152 .buf = &buf,
153 .len = 1,
154 },
155 };
156
157 ret = i2c_transfer(intp->i2c_adap, msg, 2);
158 if (ret != 2)
159 dprintk("%s: i2c error %d, reg[0x%02x]\n",
160 __func__, ret, reg);
161
162 return buf;
163 }
164
extract_mask_pos(u32 label,u8 * mask,u8 * pos)165 static void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
166 {
167 u8 position = 0, i = 0;
168
169 (*mask) = label & 0xff;
170
171 while ((position == 0) && (i < 8)) {
172 position = ((*mask) >> i) & 0x01;
173 i++;
174 }
175
176 (*pos) = (i - 1);
177 }
178
stv0900_write_bits(struct stv0900_internal * intp,u32 label,u8 val)179 void stv0900_write_bits(struct stv0900_internal *intp, u32 label, u8 val)
180 {
181 u8 reg, mask, pos;
182
183 reg = stv0900_read_reg(intp, (label >> 16) & 0xffff);
184 extract_mask_pos(label, &mask, &pos);
185
186 val = mask & (val << pos);
187
188 reg = (reg & (~mask)) | val;
189 stv0900_write_reg(intp, (label >> 16) & 0xffff, reg);
190
191 }
192
stv0900_get_bits(struct stv0900_internal * intp,u32 label)193 u8 stv0900_get_bits(struct stv0900_internal *intp, u32 label)
194 {
195 u8 val;
196 u8 mask, pos;
197
198 extract_mask_pos(label, &mask, &pos);
199
200 val = stv0900_read_reg(intp, label >> 16);
201 val = (val & mask) >> pos;
202
203 return val;
204 }
205
stv0900_initialize(struct stv0900_internal * intp)206 static enum fe_stv0900_error stv0900_initialize(struct stv0900_internal *intp)
207 {
208 s32 i;
209
210 if (intp == NULL)
211 return STV0900_INVALID_HANDLE;
212
213 intp->chip_id = stv0900_read_reg(intp, R0900_MID);
214
215 if (intp->errs != STV0900_NO_ERROR)
216 return intp->errs;
217
218 /*Startup sequence*/
219 stv0900_write_reg(intp, R0900_P1_DMDISTATE, 0x5c);
220 stv0900_write_reg(intp, R0900_P2_DMDISTATE, 0x5c);
221 msleep(3);
222 stv0900_write_reg(intp, R0900_P1_TNRCFG, 0x6c);
223 stv0900_write_reg(intp, R0900_P2_TNRCFG, 0x6f);
224 stv0900_write_reg(intp, R0900_P1_I2CRPT, 0x20);
225 stv0900_write_reg(intp, R0900_P2_I2CRPT, 0x20);
226 stv0900_write_reg(intp, R0900_NCOARSE, 0x13);
227 msleep(3);
228 stv0900_write_reg(intp, R0900_I2CCFG, 0x08);
229
230 switch (intp->clkmode) {
231 case 0:
232 case 2:
233 stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20
234 | intp->clkmode);
235 break;
236 default:
237 /* preserve SELOSCI bit */
238 i = 0x02 & stv0900_read_reg(intp, R0900_SYNTCTRL);
239 stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | i);
240 break;
241 }
242
243 msleep(3);
244 for (i = 0; i < 181; i++)
245 stv0900_write_reg(intp, STV0900_InitVal[i][0],
246 STV0900_InitVal[i][1]);
247
248 if (stv0900_read_reg(intp, R0900_MID) >= 0x20) {
249 stv0900_write_reg(intp, R0900_TSGENERAL, 0x0c);
250 for (i = 0; i < 32; i++)
251 stv0900_write_reg(intp, STV0900_Cut20_AddOnVal[i][0],
252 STV0900_Cut20_AddOnVal[i][1]);
253 }
254
255 stv0900_write_reg(intp, R0900_P1_FSPYCFG, 0x6c);
256 stv0900_write_reg(intp, R0900_P2_FSPYCFG, 0x6c);
257
258 stv0900_write_reg(intp, R0900_P1_PDELCTRL2, 0x01);
259 stv0900_write_reg(intp, R0900_P2_PDELCTRL2, 0x21);
260
261 stv0900_write_reg(intp, R0900_P1_PDELCTRL3, 0x20);
262 stv0900_write_reg(intp, R0900_P2_PDELCTRL3, 0x20);
263
264 stv0900_write_reg(intp, R0900_TSTRES0, 0x80);
265 stv0900_write_reg(intp, R0900_TSTRES0, 0x00);
266
267 return STV0900_NO_ERROR;
268 }
269
stv0900_get_mclk_freq(struct stv0900_internal * intp,u32 ext_clk)270 static u32 stv0900_get_mclk_freq(struct stv0900_internal *intp, u32 ext_clk)
271 {
272 u32 mclk, div, ad_div;
273
274 div = stv0900_get_bits(intp, F0900_M_DIV);
275 ad_div = ((stv0900_get_bits(intp, F0900_SELX1RATIO) == 1) ? 4 : 6);
276
277 mclk = (div + 1) * ext_clk / ad_div;
278
279 dprintk("%s: Calculated Mclk = %d\n", __func__, mclk);
280
281 return mclk;
282 }
283
stv0900_set_mclk(struct stv0900_internal * intp,u32 mclk)284 static enum fe_stv0900_error stv0900_set_mclk(struct stv0900_internal *intp, u32 mclk)
285 {
286 u32 m_div, clk_sel;
287
288 if (intp == NULL)
289 return STV0900_INVALID_HANDLE;
290
291 if (intp->errs)
292 return STV0900_I2C_ERROR;
293
294 dprintk("%s: Mclk set to %d, Quartz = %d\n", __func__, mclk,
295 intp->quartz);
296
297 clk_sel = ((stv0900_get_bits(intp, F0900_SELX1RATIO) == 1) ? 4 : 6);
298 m_div = ((clk_sel * mclk) / intp->quartz) - 1;
299 stv0900_write_bits(intp, F0900_M_DIV, m_div);
300 intp->mclk = stv0900_get_mclk_freq(intp,
301 intp->quartz);
302
303 /*Set the DiseqC frequency to 22KHz */
304 /*
305 Formula:
306 DiseqC_TX_Freq= MasterClock/(32*F22TX_Reg)
307 DiseqC_RX_Freq= MasterClock/(32*F22RX_Reg)
308 */
309 m_div = intp->mclk / 704000;
310 stv0900_write_reg(intp, R0900_P1_F22TX, m_div);
311 stv0900_write_reg(intp, R0900_P1_F22RX, m_div);
312
313 stv0900_write_reg(intp, R0900_P2_F22TX, m_div);
314 stv0900_write_reg(intp, R0900_P2_F22RX, m_div);
315
316 if ((intp->errs))
317 return STV0900_I2C_ERROR;
318
319 return STV0900_NO_ERROR;
320 }
321
stv0900_get_err_count(struct stv0900_internal * intp,int cntr,enum fe_stv0900_demod_num demod)322 static u32 stv0900_get_err_count(struct stv0900_internal *intp, int cntr,
323 enum fe_stv0900_demod_num demod)
324 {
325 u32 lsb, msb, hsb, err_val;
326
327 switch (cntr) {
328 case 0:
329 default:
330 hsb = stv0900_get_bits(intp, ERR_CNT12);
331 msb = stv0900_get_bits(intp, ERR_CNT11);
332 lsb = stv0900_get_bits(intp, ERR_CNT10);
333 break;
334 case 1:
335 hsb = stv0900_get_bits(intp, ERR_CNT22);
336 msb = stv0900_get_bits(intp, ERR_CNT21);
337 lsb = stv0900_get_bits(intp, ERR_CNT20);
338 break;
339 }
340
341 err_val = (hsb << 16) + (msb << 8) + (lsb);
342
343 return err_val;
344 }
345
stv0900_i2c_gate_ctrl(struct dvb_frontend * fe,int enable)346 static int stv0900_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
347 {
348 struct stv0900_state *state = fe->demodulator_priv;
349 struct stv0900_internal *intp = state->internal;
350 enum fe_stv0900_demod_num demod = state->demod;
351
352 stv0900_write_bits(intp, I2CT_ON, enable);
353
354 return 0;
355 }
356
stv0900_set_ts_parallel_serial(struct stv0900_internal * intp,enum fe_stv0900_clock_type path1_ts,enum fe_stv0900_clock_type path2_ts)357 static void stv0900_set_ts_parallel_serial(struct stv0900_internal *intp,
358 enum fe_stv0900_clock_type path1_ts,
359 enum fe_stv0900_clock_type path2_ts)
360 {
361
362 dprintk("%s\n", __func__);
363
364 if (intp->chip_id >= 0x20) {
365 switch (path1_ts) {
366 case STV0900_PARALLEL_PUNCT_CLOCK:
367 case STV0900_DVBCI_CLOCK:
368 switch (path2_ts) {
369 case STV0900_SERIAL_PUNCT_CLOCK:
370 case STV0900_SERIAL_CONT_CLOCK:
371 default:
372 stv0900_write_reg(intp, R0900_TSGENERAL,
373 0x00);
374 break;
375 case STV0900_PARALLEL_PUNCT_CLOCK:
376 case STV0900_DVBCI_CLOCK:
377 stv0900_write_reg(intp, R0900_TSGENERAL,
378 0x06);
379 stv0900_write_bits(intp,
380 F0900_P1_TSFIFO_MANSPEED, 3);
381 stv0900_write_bits(intp,
382 F0900_P2_TSFIFO_MANSPEED, 0);
383 stv0900_write_reg(intp,
384 R0900_P1_TSSPEED, 0x14);
385 stv0900_write_reg(intp,
386 R0900_P2_TSSPEED, 0x28);
387 break;
388 }
389 break;
390 case STV0900_SERIAL_PUNCT_CLOCK:
391 case STV0900_SERIAL_CONT_CLOCK:
392 default:
393 switch (path2_ts) {
394 case STV0900_SERIAL_PUNCT_CLOCK:
395 case STV0900_SERIAL_CONT_CLOCK:
396 default:
397 stv0900_write_reg(intp,
398 R0900_TSGENERAL, 0x0C);
399 break;
400 case STV0900_PARALLEL_PUNCT_CLOCK:
401 case STV0900_DVBCI_CLOCK:
402 stv0900_write_reg(intp,
403 R0900_TSGENERAL, 0x0A);
404 dprintk("%s: 0x0a\n", __func__);
405 break;
406 }
407 break;
408 }
409 } else {
410 switch (path1_ts) {
411 case STV0900_PARALLEL_PUNCT_CLOCK:
412 case STV0900_DVBCI_CLOCK:
413 switch (path2_ts) {
414 case STV0900_SERIAL_PUNCT_CLOCK:
415 case STV0900_SERIAL_CONT_CLOCK:
416 default:
417 stv0900_write_reg(intp, R0900_TSGENERAL1X,
418 0x10);
419 break;
420 case STV0900_PARALLEL_PUNCT_CLOCK:
421 case STV0900_DVBCI_CLOCK:
422 stv0900_write_reg(intp, R0900_TSGENERAL1X,
423 0x16);
424 stv0900_write_bits(intp,
425 F0900_P1_TSFIFO_MANSPEED, 3);
426 stv0900_write_bits(intp,
427 F0900_P2_TSFIFO_MANSPEED, 0);
428 stv0900_write_reg(intp, R0900_P1_TSSPEED,
429 0x14);
430 stv0900_write_reg(intp, R0900_P2_TSSPEED,
431 0x28);
432 break;
433 }
434
435 break;
436 case STV0900_SERIAL_PUNCT_CLOCK:
437 case STV0900_SERIAL_CONT_CLOCK:
438 default:
439 switch (path2_ts) {
440 case STV0900_SERIAL_PUNCT_CLOCK:
441 case STV0900_SERIAL_CONT_CLOCK:
442 default:
443 stv0900_write_reg(intp, R0900_TSGENERAL1X,
444 0x14);
445 break;
446 case STV0900_PARALLEL_PUNCT_CLOCK:
447 case STV0900_DVBCI_CLOCK:
448 stv0900_write_reg(intp, R0900_TSGENERAL1X,
449 0x12);
450 dprintk("%s: 0x12\n", __func__);
451 break;
452 }
453
454 break;
455 }
456 }
457
458 switch (path1_ts) {
459 case STV0900_PARALLEL_PUNCT_CLOCK:
460 stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x00);
461 stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x00);
462 break;
463 case STV0900_DVBCI_CLOCK:
464 stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x00);
465 stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x01);
466 break;
467 case STV0900_SERIAL_PUNCT_CLOCK:
468 stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x01);
469 stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x00);
470 break;
471 case STV0900_SERIAL_CONT_CLOCK:
472 stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x01);
473 stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x01);
474 break;
475 default:
476 break;
477 }
478
479 switch (path2_ts) {
480 case STV0900_PARALLEL_PUNCT_CLOCK:
481 stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x00);
482 stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x00);
483 break;
484 case STV0900_DVBCI_CLOCK:
485 stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x00);
486 stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x01);
487 break;
488 case STV0900_SERIAL_PUNCT_CLOCK:
489 stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x01);
490 stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x00);
491 break;
492 case STV0900_SERIAL_CONT_CLOCK:
493 stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x01);
494 stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x01);
495 break;
496 default:
497 break;
498 }
499
500 stv0900_write_bits(intp, F0900_P2_RST_HWARE, 1);
501 stv0900_write_bits(intp, F0900_P2_RST_HWARE, 0);
502 stv0900_write_bits(intp, F0900_P1_RST_HWARE, 1);
503 stv0900_write_bits(intp, F0900_P1_RST_HWARE, 0);
504 }
505
stv0900_set_tuner(struct dvb_frontend * fe,u32 frequency,u32 bandwidth)506 void stv0900_set_tuner(struct dvb_frontend *fe, u32 frequency,
507 u32 bandwidth)
508 {
509 struct dvb_frontend_ops *frontend_ops = NULL;
510 struct dvb_tuner_ops *tuner_ops = NULL;
511
512 frontend_ops = &fe->ops;
513 tuner_ops = &frontend_ops->tuner_ops;
514
515 if (tuner_ops->set_frequency) {
516 if ((tuner_ops->set_frequency(fe, frequency)) < 0)
517 dprintk("%s: Invalid parameter\n", __func__);
518 else
519 dprintk("%s: Frequency=%d\n", __func__, frequency);
520
521 }
522
523 if (tuner_ops->set_bandwidth) {
524 if ((tuner_ops->set_bandwidth(fe, bandwidth)) < 0)
525 dprintk("%s: Invalid parameter\n", __func__);
526 else
527 dprintk("%s: Bandwidth=%d\n", __func__, bandwidth);
528
529 }
530 }
531
stv0900_set_bandwidth(struct dvb_frontend * fe,u32 bandwidth)532 void stv0900_set_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
533 {
534 struct dvb_frontend_ops *frontend_ops = NULL;
535 struct dvb_tuner_ops *tuner_ops = NULL;
536
537 frontend_ops = &fe->ops;
538 tuner_ops = &frontend_ops->tuner_ops;
539
540 if (tuner_ops->set_bandwidth) {
541 if ((tuner_ops->set_bandwidth(fe, bandwidth)) < 0)
542 dprintk("%s: Invalid parameter\n", __func__);
543 else
544 dprintk("%s: Bandwidth=%d\n", __func__, bandwidth);
545
546 }
547 }
548
stv0900_get_freq_auto(struct stv0900_internal * intp,int demod)549 u32 stv0900_get_freq_auto(struct stv0900_internal *intp, int demod)
550 {
551 u32 freq, round;
552 /* Formulat :
553 Tuner_Frequency(MHz) = Regs / 64
554 Tuner_granularity(MHz) = Regs / 2048
555 real_Tuner_Frequency = Tuner_Frequency(MHz) - Tuner_granularity(MHz)
556 */
557 freq = (stv0900_get_bits(intp, TUN_RFFREQ2) << 10) +
558 (stv0900_get_bits(intp, TUN_RFFREQ1) << 2) +
559 stv0900_get_bits(intp, TUN_RFFREQ0);
560
561 freq = (freq * 1000) / 64;
562
563 round = (stv0900_get_bits(intp, TUN_RFRESTE1) >> 2) +
564 stv0900_get_bits(intp, TUN_RFRESTE0);
565
566 round = (round * 1000) / 2048;
567
568 return freq + round;
569 }
570
stv0900_set_tuner_auto(struct stv0900_internal * intp,u32 Frequency,u32 Bandwidth,int demod)571 void stv0900_set_tuner_auto(struct stv0900_internal *intp, u32 Frequency,
572 u32 Bandwidth, int demod)
573 {
574 u32 tunerFrequency;
575 /* Formulat:
576 Tuner_frequency_reg= Frequency(MHz)*64
577 */
578 tunerFrequency = (Frequency * 64) / 1000;
579
580 stv0900_write_bits(intp, TUN_RFFREQ2, (tunerFrequency >> 10));
581 stv0900_write_bits(intp, TUN_RFFREQ1, (tunerFrequency >> 2) & 0xff);
582 stv0900_write_bits(intp, TUN_RFFREQ0, (tunerFrequency & 0x03));
583 /* Low Pass Filter = BW /2 (MHz)*/
584 stv0900_write_bits(intp, TUN_BW, Bandwidth / 2000000);
585 /* Tuner Write trig */
586 stv0900_write_reg(intp, TNRLD, 1);
587 }
588
stv0900_get_rf_level(struct stv0900_internal * intp,const struct stv0900_table * lookup,enum fe_stv0900_demod_num demod)589 static s32 stv0900_get_rf_level(struct stv0900_internal *intp,
590 const struct stv0900_table *lookup,
591 enum fe_stv0900_demod_num demod)
592 {
593 s32 agc_gain = 0,
594 imin,
595 imax,
596 i,
597 rf_lvl = 0;
598
599 dprintk("%s\n", __func__);
600
601 if ((lookup == NULL) || (lookup->size <= 0))
602 return 0;
603
604 agc_gain = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1),
605 stv0900_get_bits(intp, AGCIQ_VALUE0));
606
607 imin = 0;
608 imax = lookup->size - 1;
609 if (INRANGE(lookup->table[imin].regval, agc_gain,
610 lookup->table[imax].regval)) {
611 while ((imax - imin) > 1) {
612 i = (imax + imin) >> 1;
613
614 if (INRANGE(lookup->table[imin].regval,
615 agc_gain,
616 lookup->table[i].regval))
617 imax = i;
618 else
619 imin = i;
620 }
621
622 rf_lvl = (s32)agc_gain - lookup->table[imin].regval;
623 rf_lvl *= (lookup->table[imax].realval -
624 lookup->table[imin].realval);
625 rf_lvl /= (lookup->table[imax].regval -
626 lookup->table[imin].regval);
627 rf_lvl += lookup->table[imin].realval;
628 } else if (agc_gain > lookup->table[0].regval)
629 rf_lvl = 5;
630 else if (agc_gain < lookup->table[lookup->size-1].regval)
631 rf_lvl = -100;
632
633 dprintk("%s: RFLevel = %d\n", __func__, rf_lvl);
634
635 return rf_lvl;
636 }
637
stv0900_read_signal_strength(struct dvb_frontend * fe,u16 * strength)638 static int stv0900_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
639 {
640 struct stv0900_state *state = fe->demodulator_priv;
641 struct stv0900_internal *internal = state->internal;
642 s32 rflevel = stv0900_get_rf_level(internal, &stv0900_rf,
643 state->demod);
644
645 rflevel = (rflevel + 100) * (65535 / 70);
646 if (rflevel < 0)
647 rflevel = 0;
648
649 if (rflevel > 65535)
650 rflevel = 65535;
651
652 *strength = rflevel;
653
654 return 0;
655 }
656
stv0900_carr_get_quality(struct dvb_frontend * fe,const struct stv0900_table * lookup)657 static s32 stv0900_carr_get_quality(struct dvb_frontend *fe,
658 const struct stv0900_table *lookup)
659 {
660 struct stv0900_state *state = fe->demodulator_priv;
661 struct stv0900_internal *intp = state->internal;
662 enum fe_stv0900_demod_num demod = state->demod;
663
664 s32 c_n = -100,
665 regval,
666 imin,
667 imax,
668 i,
669 noise_field1,
670 noise_field0;
671
672 dprintk("%s\n", __func__);
673
674 if (stv0900_get_standard(fe, demod) == STV0900_DVBS2_STANDARD) {
675 noise_field1 = NOSPLHT_NORMED1;
676 noise_field0 = NOSPLHT_NORMED0;
677 } else {
678 noise_field1 = NOSDATAT_NORMED1;
679 noise_field0 = NOSDATAT_NORMED0;
680 }
681
682 if (stv0900_get_bits(intp, LOCK_DEFINITIF)) {
683 if ((lookup != NULL) && lookup->size) {
684 regval = 0;
685 msleep(5);
686 for (i = 0; i < 16; i++) {
687 regval += MAKEWORD(stv0900_get_bits(intp,
688 noise_field1),
689 stv0900_get_bits(intp,
690 noise_field0));
691 msleep(1);
692 }
693
694 regval /= 16;
695 imin = 0;
696 imax = lookup->size - 1;
697 if (INRANGE(lookup->table[imin].regval,
698 regval,
699 lookup->table[imax].regval)) {
700 while ((imax - imin) > 1) {
701 i = (imax + imin) >> 1;
702 if (INRANGE(lookup->table[imin].regval,
703 regval,
704 lookup->table[i].regval))
705 imax = i;
706 else
707 imin = i;
708 }
709
710 c_n = ((regval - lookup->table[imin].regval)
711 * (lookup->table[imax].realval
712 - lookup->table[imin].realval)
713 / (lookup->table[imax].regval
714 - lookup->table[imin].regval))
715 + lookup->table[imin].realval;
716 } else if (regval < lookup->table[imin].regval)
717 c_n = 1000;
718 }
719 }
720
721 return c_n;
722 }
723
stv0900_read_ucblocks(struct dvb_frontend * fe,u32 * ucblocks)724 static int stv0900_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
725 {
726 struct stv0900_state *state = fe->demodulator_priv;
727 struct stv0900_internal *intp = state->internal;
728 enum fe_stv0900_demod_num demod = state->demod;
729 u8 err_val1, err_val0;
730 u32 header_err_val = 0;
731
732 *ucblocks = 0x0;
733 if (stv0900_get_standard(fe, demod) == STV0900_DVBS2_STANDARD) {
734 /* DVB-S2 delineator errors count */
735
736 /* retrieving number for errnous headers */
737 err_val1 = stv0900_read_reg(intp, BBFCRCKO1);
738 err_val0 = stv0900_read_reg(intp, BBFCRCKO0);
739 header_err_val = (err_val1 << 8) | err_val0;
740
741 /* retrieving number for errnous packets */
742 err_val1 = stv0900_read_reg(intp, UPCRCKO1);
743 err_val0 = stv0900_read_reg(intp, UPCRCKO0);
744 *ucblocks = (err_val1 << 8) | err_val0;
745 *ucblocks += header_err_val;
746 }
747
748 return 0;
749 }
750
stv0900_read_snr(struct dvb_frontend * fe,u16 * snr)751 static int stv0900_read_snr(struct dvb_frontend *fe, u16 *snr)
752 {
753 s32 snrlcl = stv0900_carr_get_quality(fe,
754 (const struct stv0900_table *)&stv0900_s2_cn);
755 snrlcl = (snrlcl + 30) * 384;
756 if (snrlcl < 0)
757 snrlcl = 0;
758
759 if (snrlcl > 65535)
760 snrlcl = 65535;
761
762 *snr = snrlcl;
763
764 return 0;
765 }
766
stv0900_get_ber(struct stv0900_internal * intp,enum fe_stv0900_demod_num demod)767 static u32 stv0900_get_ber(struct stv0900_internal *intp,
768 enum fe_stv0900_demod_num demod)
769 {
770 u32 ber = 10000000, i;
771 s32 demod_state;
772
773 demod_state = stv0900_get_bits(intp, HEADER_MODE);
774
775 switch (demod_state) {
776 case STV0900_SEARCH:
777 case STV0900_PLH_DETECTED:
778 default:
779 ber = 10000000;
780 break;
781 case STV0900_DVBS_FOUND:
782 ber = 0;
783 for (i = 0; i < 5; i++) {
784 msleep(5);
785 ber += stv0900_get_err_count(intp, 0, demod);
786 }
787
788 ber /= 5;
789 if (stv0900_get_bits(intp, PRFVIT)) {
790 ber *= 9766;
791 ber = ber >> 13;
792 }
793
794 break;
795 case STV0900_DVBS2_FOUND:
796 ber = 0;
797 for (i = 0; i < 5; i++) {
798 msleep(5);
799 ber += stv0900_get_err_count(intp, 0, demod);
800 }
801
802 ber /= 5;
803 if (stv0900_get_bits(intp, PKTDELIN_LOCK)) {
804 ber *= 9766;
805 ber = ber >> 13;
806 }
807
808 break;
809 }
810
811 return ber;
812 }
813
stv0900_read_ber(struct dvb_frontend * fe,u32 * ber)814 static int stv0900_read_ber(struct dvb_frontend *fe, u32 *ber)
815 {
816 struct stv0900_state *state = fe->demodulator_priv;
817 struct stv0900_internal *internal = state->internal;
818
819 *ber = stv0900_get_ber(internal, state->demod);
820
821 return 0;
822 }
823
stv0900_get_demod_lock(struct stv0900_internal * intp,enum fe_stv0900_demod_num demod,s32 time_out)824 int stv0900_get_demod_lock(struct stv0900_internal *intp,
825 enum fe_stv0900_demod_num demod, s32 time_out)
826 {
827 s32 timer = 0,
828 lock = 0;
829
830 enum fe_stv0900_search_state dmd_state;
831
832 while ((timer < time_out) && (lock == 0)) {
833 dmd_state = stv0900_get_bits(intp, HEADER_MODE);
834 dprintk("Demod State = %d\n", dmd_state);
835 switch (dmd_state) {
836 case STV0900_SEARCH:
837 case STV0900_PLH_DETECTED:
838 default:
839 lock = 0;
840 break;
841 case STV0900_DVBS2_FOUND:
842 case STV0900_DVBS_FOUND:
843 lock = stv0900_get_bits(intp, LOCK_DEFINITIF);
844 break;
845 }
846
847 if (lock == 0)
848 msleep(10);
849
850 timer += 10;
851 }
852
853 if (lock)
854 dprintk("DEMOD LOCK OK\n");
855 else
856 dprintk("DEMOD LOCK FAIL\n");
857
858 return lock;
859 }
860
stv0900_stop_all_s2_modcod(struct stv0900_internal * intp,enum fe_stv0900_demod_num demod)861 void stv0900_stop_all_s2_modcod(struct stv0900_internal *intp,
862 enum fe_stv0900_demod_num demod)
863 {
864 s32 regflist,
865 i;
866
867 dprintk("%s\n", __func__);
868
869 regflist = MODCODLST0;
870
871 for (i = 0; i < 16; i++)
872 stv0900_write_reg(intp, regflist + i, 0xff);
873 }
874
stv0900_activate_s2_modcod(struct stv0900_internal * intp,enum fe_stv0900_demod_num demod)875 void stv0900_activate_s2_modcod(struct stv0900_internal *intp,
876 enum fe_stv0900_demod_num demod)
877 {
878 u32 matype,
879 mod_code,
880 fmod,
881 reg_index,
882 field_index;
883
884 dprintk("%s\n", __func__);
885
886 if (intp->chip_id <= 0x11) {
887 msleep(5);
888
889 mod_code = stv0900_read_reg(intp, PLHMODCOD);
890 matype = mod_code & 0x3;
891 mod_code = (mod_code & 0x7f) >> 2;
892
893 reg_index = MODCODLSTF - mod_code / 2;
894 field_index = mod_code % 2;
895
896 switch (matype) {
897 case 0:
898 default:
899 fmod = 14;
900 break;
901 case 1:
902 fmod = 13;
903 break;
904 case 2:
905 fmod = 11;
906 break;
907 case 3:
908 fmod = 7;
909 break;
910 }
911
912 if ((INRANGE(STV0900_QPSK_12, mod_code, STV0900_8PSK_910))
913 && (matype <= 1)) {
914 if (field_index == 0)
915 stv0900_write_reg(intp, reg_index,
916 0xf0 | fmod);
917 else
918 stv0900_write_reg(intp, reg_index,
919 (fmod << 4) | 0xf);
920 }
921
922 } else if (intp->chip_id >= 0x12) {
923 for (reg_index = 0; reg_index < 7; reg_index++)
924 stv0900_write_reg(intp, MODCODLST0 + reg_index, 0xff);
925
926 stv0900_write_reg(intp, MODCODLSTE, 0xff);
927 stv0900_write_reg(intp, MODCODLSTF, 0xcf);
928 for (reg_index = 0; reg_index < 8; reg_index++)
929 stv0900_write_reg(intp, MODCODLST7 + reg_index, 0xcc);
930
931
932 }
933 }
934
stv0900_activate_s2_modcod_single(struct stv0900_internal * intp,enum fe_stv0900_demod_num demod)935 void stv0900_activate_s2_modcod_single(struct stv0900_internal *intp,
936 enum fe_stv0900_demod_num demod)
937 {
938 u32 reg_index;
939
940 dprintk("%s\n", __func__);
941
942 stv0900_write_reg(intp, MODCODLST0, 0xff);
943 stv0900_write_reg(intp, MODCODLST1, 0xf0);
944 stv0900_write_reg(intp, MODCODLSTF, 0x0f);
945 for (reg_index = 0; reg_index < 13; reg_index++)
946 stv0900_write_reg(intp, MODCODLST2 + reg_index, 0);
947
948 }
949
stv0900_frontend_algo(struct dvb_frontend * fe)950 static enum dvbfe_algo stv0900_frontend_algo(struct dvb_frontend *fe)
951 {
952 return DVBFE_ALGO_CUSTOM;
953 }
954
stv0900_start_search(struct stv0900_internal * intp,enum fe_stv0900_demod_num demod)955 void stv0900_start_search(struct stv0900_internal *intp,
956 enum fe_stv0900_demod_num demod)
957 {
958 u32 freq;
959 s16 freq_s16 ;
960
961 stv0900_write_bits(intp, DEMOD_MODE, 0x1f);
962 if (intp->chip_id == 0x10)
963 stv0900_write_reg(intp, CORRELEXP, 0xaa);
964
965 if (intp->chip_id < 0x20)
966 stv0900_write_reg(intp, CARHDR, 0x55);
967
968 if (intp->chip_id <= 0x20) {
969 if (intp->symbol_rate[0] <= 5000000) {
970 stv0900_write_reg(intp, CARCFG, 0x44);
971 stv0900_write_reg(intp, CFRUP1, 0x0f);
972 stv0900_write_reg(intp, CFRUP0, 0xff);
973 stv0900_write_reg(intp, CFRLOW1, 0xf0);
974 stv0900_write_reg(intp, CFRLOW0, 0x00);
975 stv0900_write_reg(intp, RTCS2, 0x68);
976 } else {
977 stv0900_write_reg(intp, CARCFG, 0xc4);
978 stv0900_write_reg(intp, RTCS2, 0x44);
979 }
980
981 } else { /*cut 3.0 above*/
982 if (intp->symbol_rate[demod] <= 5000000)
983 stv0900_write_reg(intp, RTCS2, 0x68);
984 else
985 stv0900_write_reg(intp, RTCS2, 0x44);
986
987 stv0900_write_reg(intp, CARCFG, 0x46);
988 if (intp->srch_algo[demod] == STV0900_WARM_START) {
989 freq = 1000 << 16;
990 freq /= (intp->mclk / 1000);
991 freq_s16 = (s16)freq;
992 } else {
993 freq = (intp->srch_range[demod] / 2000);
994 if (intp->symbol_rate[demod] <= 5000000)
995 freq += 80;
996 else
997 freq += 600;
998
999 freq = freq << 16;
1000 freq /= (intp->mclk / 1000);
1001 freq_s16 = (s16)freq;
1002 }
1003
1004 stv0900_write_bits(intp, CFR_UP1, MSB(freq_s16));
1005 stv0900_write_bits(intp, CFR_UP0, LSB(freq_s16));
1006 freq_s16 *= (-1);
1007 stv0900_write_bits(intp, CFR_LOW1, MSB(freq_s16));
1008 stv0900_write_bits(intp, CFR_LOW0, LSB(freq_s16));
1009 }
1010
1011 stv0900_write_reg(intp, CFRINIT1, 0);
1012 stv0900_write_reg(intp, CFRINIT0, 0);
1013
1014 if (intp->chip_id >= 0x20) {
1015 stv0900_write_reg(intp, EQUALCFG, 0x41);
1016 stv0900_write_reg(intp, FFECFG, 0x41);
1017
1018 if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) ||
1019 (intp->srch_standard[demod] == STV0900_SEARCH_DSS) ||
1020 (intp->srch_standard[demod] == STV0900_AUTO_SEARCH)) {
1021 stv0900_write_reg(intp, VITSCALE,
1022 0x82);
1023 stv0900_write_reg(intp, VAVSRVIT, 0x0);
1024 }
1025 }
1026
1027 stv0900_write_reg(intp, SFRSTEP, 0x00);
1028 stv0900_write_reg(intp, TMGTHRISE, 0xe0);
1029 stv0900_write_reg(intp, TMGTHFALL, 0xc0);
1030 stv0900_write_bits(intp, SCAN_ENABLE, 0);
1031 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1032 stv0900_write_bits(intp, S1S2_SEQUENTIAL, 0);
1033 stv0900_write_reg(intp, RTC, 0x88);
1034 if (intp->chip_id >= 0x20) {
1035 if (intp->symbol_rate[demod] < 2000000) {
1036 if (intp->chip_id <= 0x20)
1037 stv0900_write_reg(intp, CARFREQ, 0x39);
1038 else /*cut 3.0*/
1039 stv0900_write_reg(intp, CARFREQ, 0x89);
1040
1041 stv0900_write_reg(intp, CARHDR, 0x40);
1042 } else if (intp->symbol_rate[demod] < 10000000) {
1043 stv0900_write_reg(intp, CARFREQ, 0x4c);
1044 stv0900_write_reg(intp, CARHDR, 0x20);
1045 } else {
1046 stv0900_write_reg(intp, CARFREQ, 0x4b);
1047 stv0900_write_reg(intp, CARHDR, 0x20);
1048 }
1049
1050 } else {
1051 if (intp->symbol_rate[demod] < 10000000)
1052 stv0900_write_reg(intp, CARFREQ, 0xef);
1053 else
1054 stv0900_write_reg(intp, CARFREQ, 0xed);
1055 }
1056
1057 switch (intp->srch_algo[demod]) {
1058 case STV0900_WARM_START:
1059 stv0900_write_reg(intp, DMDISTATE, 0x1f);
1060 stv0900_write_reg(intp, DMDISTATE, 0x18);
1061 break;
1062 case STV0900_COLD_START:
1063 stv0900_write_reg(intp, DMDISTATE, 0x1f);
1064 stv0900_write_reg(intp, DMDISTATE, 0x15);
1065 break;
1066 default:
1067 break;
1068 }
1069 }
1070
stv0900_get_optim_carr_loop(s32 srate,enum fe_stv0900_modcode modcode,s32 pilot,u8 chip_id)1071 u8 stv0900_get_optim_carr_loop(s32 srate, enum fe_stv0900_modcode modcode,
1072 s32 pilot, u8 chip_id)
1073 {
1074 u8 aclc_value = 0x29;
1075 s32 i, cllas2_size;
1076 const struct stv0900_car_loop_optim *cls2, *cllqs2, *cllas2;
1077
1078 dprintk("%s\n", __func__);
1079
1080 if (chip_id <= 0x12) {
1081 cls2 = FE_STV0900_S2CarLoop;
1082 cllqs2 = FE_STV0900_S2LowQPCarLoopCut30;
1083 cllas2 = FE_STV0900_S2APSKCarLoopCut30;
1084 cllas2_size = ARRAY_SIZE(FE_STV0900_S2APSKCarLoopCut30);
1085 } else if (chip_id == 0x20) {
1086 cls2 = FE_STV0900_S2CarLoopCut20;
1087 cllqs2 = FE_STV0900_S2LowQPCarLoopCut20;
1088 cllas2 = FE_STV0900_S2APSKCarLoopCut20;
1089 cllas2_size = ARRAY_SIZE(FE_STV0900_S2APSKCarLoopCut20);
1090 } else {
1091 cls2 = FE_STV0900_S2CarLoopCut30;
1092 cllqs2 = FE_STV0900_S2LowQPCarLoopCut30;
1093 cllas2 = FE_STV0900_S2APSKCarLoopCut30;
1094 cllas2_size = ARRAY_SIZE(FE_STV0900_S2APSKCarLoopCut30);
1095 }
1096
1097 if (modcode < STV0900_QPSK_12) {
1098 i = 0;
1099 while ((i < 3) && (modcode != cllqs2[i].modcode))
1100 i++;
1101
1102 if (i >= 3)
1103 i = 2;
1104 } else {
1105 i = 0;
1106 while ((i < 14) && (modcode != cls2[i].modcode))
1107 i++;
1108
1109 if (i >= 14) {
1110 i = 0;
1111 while ((i < 11) && (modcode != cllas2[i].modcode))
1112 i++;
1113
1114 if (i >= 11)
1115 i = 10;
1116 }
1117 }
1118
1119 if (modcode <= STV0900_QPSK_25) {
1120 if (pilot) {
1121 if (srate <= 3000000)
1122 aclc_value = cllqs2[i].car_loop_pilots_on_2;
1123 else if (srate <= 7000000)
1124 aclc_value = cllqs2[i].car_loop_pilots_on_5;
1125 else if (srate <= 15000000)
1126 aclc_value = cllqs2[i].car_loop_pilots_on_10;
1127 else if (srate <= 25000000)
1128 aclc_value = cllqs2[i].car_loop_pilots_on_20;
1129 else
1130 aclc_value = cllqs2[i].car_loop_pilots_on_30;
1131 } else {
1132 if (srate <= 3000000)
1133 aclc_value = cllqs2[i].car_loop_pilots_off_2;
1134 else if (srate <= 7000000)
1135 aclc_value = cllqs2[i].car_loop_pilots_off_5;
1136 else if (srate <= 15000000)
1137 aclc_value = cllqs2[i].car_loop_pilots_off_10;
1138 else if (srate <= 25000000)
1139 aclc_value = cllqs2[i].car_loop_pilots_off_20;
1140 else
1141 aclc_value = cllqs2[i].car_loop_pilots_off_30;
1142 }
1143
1144 } else if (modcode <= STV0900_8PSK_910) {
1145 if (pilot) {
1146 if (srate <= 3000000)
1147 aclc_value = cls2[i].car_loop_pilots_on_2;
1148 else if (srate <= 7000000)
1149 aclc_value = cls2[i].car_loop_pilots_on_5;
1150 else if (srate <= 15000000)
1151 aclc_value = cls2[i].car_loop_pilots_on_10;
1152 else if (srate <= 25000000)
1153 aclc_value = cls2[i].car_loop_pilots_on_20;
1154 else
1155 aclc_value = cls2[i].car_loop_pilots_on_30;
1156 } else {
1157 if (srate <= 3000000)
1158 aclc_value = cls2[i].car_loop_pilots_off_2;
1159 else if (srate <= 7000000)
1160 aclc_value = cls2[i].car_loop_pilots_off_5;
1161 else if (srate <= 15000000)
1162 aclc_value = cls2[i].car_loop_pilots_off_10;
1163 else if (srate <= 25000000)
1164 aclc_value = cls2[i].car_loop_pilots_off_20;
1165 else
1166 aclc_value = cls2[i].car_loop_pilots_off_30;
1167 }
1168
1169 } else if (i < cllas2_size) {
1170 if (srate <= 3000000)
1171 aclc_value = cllas2[i].car_loop_pilots_on_2;
1172 else if (srate <= 7000000)
1173 aclc_value = cllas2[i].car_loop_pilots_on_5;
1174 else if (srate <= 15000000)
1175 aclc_value = cllas2[i].car_loop_pilots_on_10;
1176 else if (srate <= 25000000)
1177 aclc_value = cllas2[i].car_loop_pilots_on_20;
1178 else
1179 aclc_value = cllas2[i].car_loop_pilots_on_30;
1180 }
1181
1182 return aclc_value;
1183 }
1184
stv0900_get_optim_short_carr_loop(s32 srate,enum fe_stv0900_modulation modulation,u8 chip_id)1185 u8 stv0900_get_optim_short_carr_loop(s32 srate,
1186 enum fe_stv0900_modulation modulation,
1187 u8 chip_id)
1188 {
1189 const struct stv0900_short_frames_car_loop_optim *s2scl;
1190 const struct stv0900_short_frames_car_loop_optim_vs_mod *s2sclc30;
1191 s32 mod_index = 0;
1192 u8 aclc_value = 0x0b;
1193
1194 dprintk("%s\n", __func__);
1195
1196 s2scl = FE_STV0900_S2ShortCarLoop;
1197 s2sclc30 = FE_STV0900_S2ShortCarLoopCut30;
1198
1199 switch (modulation) {
1200 case STV0900_QPSK:
1201 default:
1202 mod_index = 0;
1203 break;
1204 case STV0900_8PSK:
1205 mod_index = 1;
1206 break;
1207 case STV0900_16APSK:
1208 mod_index = 2;
1209 break;
1210 case STV0900_32APSK:
1211 mod_index = 3;
1212 break;
1213 }
1214
1215 if (chip_id >= 0x30) {
1216 if (srate <= 3000000)
1217 aclc_value = s2sclc30[mod_index].car_loop_2;
1218 else if (srate <= 7000000)
1219 aclc_value = s2sclc30[mod_index].car_loop_5;
1220 else if (srate <= 15000000)
1221 aclc_value = s2sclc30[mod_index].car_loop_10;
1222 else if (srate <= 25000000)
1223 aclc_value = s2sclc30[mod_index].car_loop_20;
1224 else
1225 aclc_value = s2sclc30[mod_index].car_loop_30;
1226
1227 } else if (chip_id >= 0x20) {
1228 if (srate <= 3000000)
1229 aclc_value = s2scl[mod_index].car_loop_cut20_2;
1230 else if (srate <= 7000000)
1231 aclc_value = s2scl[mod_index].car_loop_cut20_5;
1232 else if (srate <= 15000000)
1233 aclc_value = s2scl[mod_index].car_loop_cut20_10;
1234 else if (srate <= 25000000)
1235 aclc_value = s2scl[mod_index].car_loop_cut20_20;
1236 else
1237 aclc_value = s2scl[mod_index].car_loop_cut20_30;
1238
1239 } else {
1240 if (srate <= 3000000)
1241 aclc_value = s2scl[mod_index].car_loop_cut12_2;
1242 else if (srate <= 7000000)
1243 aclc_value = s2scl[mod_index].car_loop_cut12_5;
1244 else if (srate <= 15000000)
1245 aclc_value = s2scl[mod_index].car_loop_cut12_10;
1246 else if (srate <= 25000000)
1247 aclc_value = s2scl[mod_index].car_loop_cut12_20;
1248 else
1249 aclc_value = s2scl[mod_index].car_loop_cut12_30;
1250
1251 }
1252
1253 return aclc_value;
1254 }
1255
1256 static
stv0900_st_dvbs2_single(struct stv0900_internal * intp,enum fe_stv0900_demod_mode LDPC_Mode,enum fe_stv0900_demod_num demod)1257 enum fe_stv0900_error stv0900_st_dvbs2_single(struct stv0900_internal *intp,
1258 enum fe_stv0900_demod_mode LDPC_Mode,
1259 enum fe_stv0900_demod_num demod)
1260 {
1261 s32 reg_ind;
1262
1263 dprintk("%s\n", __func__);
1264
1265 switch (LDPC_Mode) {
1266 case STV0900_DUAL:
1267 default:
1268 if ((intp->demod_mode != STV0900_DUAL)
1269 || (stv0900_get_bits(intp, F0900_DDEMOD) != 1)) {
1270 stv0900_write_reg(intp, R0900_GENCFG, 0x1d);
1271
1272 intp->demod_mode = STV0900_DUAL;
1273
1274 stv0900_write_bits(intp, F0900_FRESFEC, 1);
1275 stv0900_write_bits(intp, F0900_FRESFEC, 0);
1276
1277 for (reg_ind = 0; reg_ind < 7; reg_ind++)
1278 stv0900_write_reg(intp,
1279 R0900_P1_MODCODLST0 + reg_ind,
1280 0xff);
1281 for (reg_ind = 0; reg_ind < 8; reg_ind++)
1282 stv0900_write_reg(intp,
1283 R0900_P1_MODCODLST7 + reg_ind,
1284 0xcc);
1285
1286 stv0900_write_reg(intp, R0900_P1_MODCODLSTE, 0xff);
1287 stv0900_write_reg(intp, R0900_P1_MODCODLSTF, 0xcf);
1288
1289 for (reg_ind = 0; reg_ind < 7; reg_ind++)
1290 stv0900_write_reg(intp,
1291 R0900_P2_MODCODLST0 + reg_ind,
1292 0xff);
1293 for (reg_ind = 0; reg_ind < 8; reg_ind++)
1294 stv0900_write_reg(intp,
1295 R0900_P2_MODCODLST7 + reg_ind,
1296 0xcc);
1297
1298 stv0900_write_reg(intp, R0900_P2_MODCODLSTE, 0xff);
1299 stv0900_write_reg(intp, R0900_P2_MODCODLSTF, 0xcf);
1300 }
1301
1302 break;
1303 case STV0900_SINGLE:
1304 if (demod == STV0900_DEMOD_2) {
1305 stv0900_stop_all_s2_modcod(intp, STV0900_DEMOD_1);
1306 stv0900_activate_s2_modcod_single(intp,
1307 STV0900_DEMOD_2);
1308 stv0900_write_reg(intp, R0900_GENCFG, 0x06);
1309 } else {
1310 stv0900_stop_all_s2_modcod(intp, STV0900_DEMOD_2);
1311 stv0900_activate_s2_modcod_single(intp,
1312 STV0900_DEMOD_1);
1313 stv0900_write_reg(intp, R0900_GENCFG, 0x04);
1314 }
1315
1316 intp->demod_mode = STV0900_SINGLE;
1317
1318 stv0900_write_bits(intp, F0900_FRESFEC, 1);
1319 stv0900_write_bits(intp, F0900_FRESFEC, 0);
1320 stv0900_write_bits(intp, F0900_P1_ALGOSWRST, 1);
1321 stv0900_write_bits(intp, F0900_P1_ALGOSWRST, 0);
1322 stv0900_write_bits(intp, F0900_P2_ALGOSWRST, 1);
1323 stv0900_write_bits(intp, F0900_P2_ALGOSWRST, 0);
1324 break;
1325 }
1326
1327 return STV0900_NO_ERROR;
1328 }
1329
stv0900_init_internal(struct dvb_frontend * fe,struct stv0900_init_params * p_init)1330 static enum fe_stv0900_error stv0900_init_internal(struct dvb_frontend *fe,
1331 struct stv0900_init_params *p_init)
1332 {
1333 struct stv0900_state *state = fe->demodulator_priv;
1334 enum fe_stv0900_error error = STV0900_NO_ERROR;
1335 enum fe_stv0900_error demodError = STV0900_NO_ERROR;
1336 struct stv0900_internal *intp = NULL;
1337 int selosci, i;
1338
1339 struct stv0900_inode *temp_int = find_inode(state->i2c_adap,
1340 state->config->demod_address);
1341
1342 dprintk("%s\n", __func__);
1343
1344 if ((temp_int != NULL) && (p_init->demod_mode == STV0900_DUAL)) {
1345 state->internal = temp_int->internal;
1346 (state->internal->dmds_used)++;
1347 dprintk("%s: Find Internal Structure!\n", __func__);
1348 return STV0900_NO_ERROR;
1349 } else {
1350 state->internal = kmalloc_obj(struct stv0900_internal);
1351 if (state->internal == NULL)
1352 return STV0900_INVALID_HANDLE;
1353 temp_int = append_internal(state->internal);
1354 if (temp_int == NULL) {
1355 kfree(state->internal);
1356 state->internal = NULL;
1357 return STV0900_INVALID_HANDLE;
1358 }
1359 state->internal->dmds_used = 1;
1360 state->internal->i2c_adap = state->i2c_adap;
1361 state->internal->i2c_addr = state->config->demod_address;
1362 state->internal->clkmode = state->config->clkmode;
1363 state->internal->errs = STV0900_NO_ERROR;
1364 dprintk("%s: Create New Internal Structure!\n", __func__);
1365 }
1366
1367 if (state->internal == NULL) {
1368 error = STV0900_INVALID_HANDLE;
1369 return error;
1370 }
1371
1372 demodError = stv0900_initialize(state->internal);
1373 if (demodError == STV0900_NO_ERROR) {
1374 error = STV0900_NO_ERROR;
1375 } else {
1376 if (demodError == STV0900_INVALID_HANDLE)
1377 error = STV0900_INVALID_HANDLE;
1378 else
1379 error = STV0900_I2C_ERROR;
1380
1381 return error;
1382 }
1383
1384 intp = state->internal;
1385
1386 intp->demod_mode = p_init->demod_mode;
1387 stv0900_st_dvbs2_single(intp, intp->demod_mode, STV0900_DEMOD_1);
1388 intp->chip_id = stv0900_read_reg(intp, R0900_MID);
1389 intp->rolloff = p_init->rolloff;
1390 intp->quartz = p_init->dmd_ref_clk;
1391
1392 stv0900_write_bits(intp, F0900_P1_ROLLOFF_CONTROL, p_init->rolloff);
1393 stv0900_write_bits(intp, F0900_P2_ROLLOFF_CONTROL, p_init->rolloff);
1394
1395 intp->ts_config = p_init->ts_config;
1396 if (intp->ts_config == NULL)
1397 stv0900_set_ts_parallel_serial(intp,
1398 p_init->path1_ts_clock,
1399 p_init->path2_ts_clock);
1400 else {
1401 for (i = 0; intp->ts_config[i].addr != 0xffff; i++)
1402 stv0900_write_reg(intp,
1403 intp->ts_config[i].addr,
1404 intp->ts_config[i].val);
1405
1406 stv0900_write_bits(intp, F0900_P2_RST_HWARE, 1);
1407 stv0900_write_bits(intp, F0900_P2_RST_HWARE, 0);
1408 stv0900_write_bits(intp, F0900_P1_RST_HWARE, 1);
1409 stv0900_write_bits(intp, F0900_P1_RST_HWARE, 0);
1410 }
1411
1412 intp->tuner_type[0] = p_init->tuner1_type;
1413 intp->tuner_type[1] = p_init->tuner2_type;
1414 /* tuner init */
1415 switch (p_init->tuner1_type) {
1416 case 3: /*FE_AUTO_STB6100:*/
1417 stv0900_write_reg(intp, R0900_P1_TNRCFG, 0x3c);
1418 stv0900_write_reg(intp, R0900_P1_TNRCFG2, 0x86);
1419 stv0900_write_reg(intp, R0900_P1_TNRCFG3, 0x18);
1420 stv0900_write_reg(intp, R0900_P1_TNRXTAL, 27); /* 27MHz */
1421 stv0900_write_reg(intp, R0900_P1_TNRSTEPS, 0x05);
1422 stv0900_write_reg(intp, R0900_P1_TNRGAIN, 0x17);
1423 stv0900_write_reg(intp, R0900_P1_TNRADJ, 0x1f);
1424 stv0900_write_reg(intp, R0900_P1_TNRCTL2, 0x0);
1425 stv0900_write_bits(intp, F0900_P1_TUN_TYPE, 3);
1426 break;
1427 /* case FE_SW_TUNER: */
1428 default:
1429 stv0900_write_bits(intp, F0900_P1_TUN_TYPE, 6);
1430 break;
1431 }
1432
1433 stv0900_write_bits(intp, F0900_P1_TUN_MADDRESS, p_init->tun1_maddress);
1434 switch (p_init->tuner1_adc) {
1435 case 1:
1436 stv0900_write_reg(intp, R0900_TSTTNR1, 0x26);
1437 break;
1438 default:
1439 break;
1440 }
1441
1442 stv0900_write_reg(intp, R0900_P1_TNRLD, 1); /* hw tuner */
1443
1444 /* tuner init */
1445 switch (p_init->tuner2_type) {
1446 case 3: /*FE_AUTO_STB6100:*/
1447 stv0900_write_reg(intp, R0900_P2_TNRCFG, 0x3c);
1448 stv0900_write_reg(intp, R0900_P2_TNRCFG2, 0x86);
1449 stv0900_write_reg(intp, R0900_P2_TNRCFG3, 0x18);
1450 stv0900_write_reg(intp, R0900_P2_TNRXTAL, 27); /* 27MHz */
1451 stv0900_write_reg(intp, R0900_P2_TNRSTEPS, 0x05);
1452 stv0900_write_reg(intp, R0900_P2_TNRGAIN, 0x17);
1453 stv0900_write_reg(intp, R0900_P2_TNRADJ, 0x1f);
1454 stv0900_write_reg(intp, R0900_P2_TNRCTL2, 0x0);
1455 stv0900_write_bits(intp, F0900_P2_TUN_TYPE, 3);
1456 break;
1457 /* case FE_SW_TUNER: */
1458 default:
1459 stv0900_write_bits(intp, F0900_P2_TUN_TYPE, 6);
1460 break;
1461 }
1462
1463 stv0900_write_bits(intp, F0900_P2_TUN_MADDRESS, p_init->tun2_maddress);
1464 switch (p_init->tuner2_adc) {
1465 case 1:
1466 stv0900_write_reg(intp, R0900_TSTTNR3, 0x26);
1467 break;
1468 default:
1469 break;
1470 }
1471
1472 stv0900_write_reg(intp, R0900_P2_TNRLD, 1); /* hw tuner */
1473
1474 stv0900_write_bits(intp, F0900_P1_TUN_IQSWAP, p_init->tun1_iq_inv);
1475 stv0900_write_bits(intp, F0900_P2_TUN_IQSWAP, p_init->tun2_iq_inv);
1476 stv0900_set_mclk(intp, 135000000);
1477 msleep(3);
1478
1479 switch (intp->clkmode) {
1480 case 0:
1481 case 2:
1482 stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | intp->clkmode);
1483 break;
1484 default:
1485 selosci = 0x02 & stv0900_read_reg(intp, R0900_SYNTCTRL);
1486 stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | selosci);
1487 break;
1488 }
1489 msleep(3);
1490
1491 intp->mclk = stv0900_get_mclk_freq(intp, intp->quartz);
1492 if (intp->errs)
1493 error = STV0900_I2C_ERROR;
1494
1495 return error;
1496 }
1497
stv0900_status(struct stv0900_internal * intp,enum fe_stv0900_demod_num demod)1498 static int stv0900_status(struct stv0900_internal *intp,
1499 enum fe_stv0900_demod_num demod)
1500 {
1501 enum fe_stv0900_search_state demod_state;
1502 int locked = FALSE;
1503 u8 tsbitrate0_val, tsbitrate1_val;
1504 s32 bitrate;
1505
1506 demod_state = stv0900_get_bits(intp, HEADER_MODE);
1507 switch (demod_state) {
1508 case STV0900_SEARCH:
1509 case STV0900_PLH_DETECTED:
1510 default:
1511 locked = FALSE;
1512 break;
1513 case STV0900_DVBS2_FOUND:
1514 locked = stv0900_get_bits(intp, LOCK_DEFINITIF) &&
1515 stv0900_get_bits(intp, PKTDELIN_LOCK) &&
1516 stv0900_get_bits(intp, TSFIFO_LINEOK);
1517 break;
1518 case STV0900_DVBS_FOUND:
1519 locked = stv0900_get_bits(intp, LOCK_DEFINITIF) &&
1520 stv0900_get_bits(intp, LOCKEDVIT) &&
1521 stv0900_get_bits(intp, TSFIFO_LINEOK);
1522 break;
1523 }
1524
1525 dprintk("%s: locked = %d\n", __func__, locked);
1526
1527 if (stvdebug) {
1528 /* Print TS bitrate */
1529 tsbitrate0_val = stv0900_read_reg(intp, TSBITRATE0);
1530 tsbitrate1_val = stv0900_read_reg(intp, TSBITRATE1);
1531 /* Formula Bit rate = Mclk * px_tsfifo_bitrate / 16384 */
1532 bitrate = (stv0900_get_mclk_freq(intp, intp->quartz)/1000000)
1533 * (tsbitrate1_val << 8 | tsbitrate0_val);
1534 bitrate /= 16384;
1535 dprintk("TS bitrate = %d Mbit/sec\n", bitrate);
1536 }
1537
1538 return locked;
1539 }
1540
stv0900_set_mis(struct stv0900_internal * intp,enum fe_stv0900_demod_num demod,int mis)1541 static int stv0900_set_mis(struct stv0900_internal *intp,
1542 enum fe_stv0900_demod_num demod, int mis)
1543 {
1544 dprintk("%s\n", __func__);
1545
1546 if (mis < 0 || mis > 255) {
1547 dprintk("Disable MIS filtering\n");
1548 stv0900_write_bits(intp, FILTER_EN, 0);
1549 } else {
1550 dprintk("Enable MIS filtering - %d\n", mis);
1551 stv0900_write_bits(intp, FILTER_EN, 1);
1552 stv0900_write_reg(intp, ISIENTRY, mis);
1553 stv0900_write_reg(intp, ISIBITENA, 0xff);
1554 }
1555
1556 return STV0900_NO_ERROR;
1557 }
1558
1559
stv0900_search(struct dvb_frontend * fe)1560 static enum dvbfe_search stv0900_search(struct dvb_frontend *fe)
1561 {
1562 struct stv0900_state *state = fe->demodulator_priv;
1563 struct stv0900_internal *intp = state->internal;
1564 enum fe_stv0900_demod_num demod = state->demod;
1565 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1566
1567 struct stv0900_search_params p_search;
1568 struct stv0900_signal_info p_result = intp->result[demod];
1569
1570 enum fe_stv0900_error error = STV0900_NO_ERROR;
1571
1572 dprintk("%s: ", __func__);
1573
1574 if (!(INRANGE(100000, c->symbol_rate, 70000000)))
1575 return DVBFE_ALGO_SEARCH_FAILED;
1576
1577 if (state->config->set_ts_params)
1578 state->config->set_ts_params(fe, 0);
1579
1580 stv0900_set_mis(intp, demod, c->stream_id);
1581
1582 p_result.locked = FALSE;
1583 p_search.path = demod;
1584 p_search.frequency = c->frequency;
1585 p_search.symbol_rate = c->symbol_rate;
1586 p_search.search_range = 10000000;
1587 p_search.fec = STV0900_FEC_UNKNOWN;
1588 p_search.standard = STV0900_AUTO_SEARCH;
1589 p_search.iq_inversion = STV0900_IQ_AUTO;
1590 p_search.search_algo = STV0900_BLIND_SEARCH;
1591 /* Speeds up DVB-S searching */
1592 if (c->delivery_system == SYS_DVBS)
1593 p_search.standard = STV0900_SEARCH_DVBS1;
1594
1595 intp->srch_standard[demod] = p_search.standard;
1596 intp->symbol_rate[demod] = p_search.symbol_rate;
1597 intp->srch_range[demod] = p_search.search_range;
1598 intp->freq[demod] = p_search.frequency;
1599 intp->srch_algo[demod] = p_search.search_algo;
1600 intp->srch_iq_inv[demod] = p_search.iq_inversion;
1601 intp->fec[demod] = p_search.fec;
1602 if ((stv0900_algo(fe) == STV0900_RANGEOK) &&
1603 (intp->errs == STV0900_NO_ERROR)) {
1604 p_result.locked = intp->result[demod].locked;
1605 p_result.standard = intp->result[demod].standard;
1606 p_result.frequency = intp->result[demod].frequency;
1607 p_result.symbol_rate = intp->result[demod].symbol_rate;
1608 p_result.fec = intp->result[demod].fec;
1609 p_result.modcode = intp->result[demod].modcode;
1610 p_result.pilot = intp->result[demod].pilot;
1611 p_result.frame_len = intp->result[demod].frame_len;
1612 p_result.spectrum = intp->result[demod].spectrum;
1613 p_result.rolloff = intp->result[demod].rolloff;
1614 p_result.modulation = intp->result[demod].modulation;
1615 } else {
1616 p_result.locked = FALSE;
1617 switch (intp->err[demod]) {
1618 case STV0900_I2C_ERROR:
1619 error = STV0900_I2C_ERROR;
1620 break;
1621 case STV0900_NO_ERROR:
1622 default:
1623 error = STV0900_SEARCH_FAILED;
1624 break;
1625 }
1626 }
1627
1628 if ((p_result.locked == TRUE) && (error == STV0900_NO_ERROR)) {
1629 dprintk("Search Success\n");
1630 return DVBFE_ALGO_SEARCH_SUCCESS;
1631 } else {
1632 dprintk("Search Fail\n");
1633 return DVBFE_ALGO_SEARCH_FAILED;
1634 }
1635
1636 }
1637
stv0900_read_status(struct dvb_frontend * fe,enum fe_status * status)1638 static int stv0900_read_status(struct dvb_frontend *fe, enum fe_status *status)
1639 {
1640 struct stv0900_state *state = fe->demodulator_priv;
1641
1642 dprintk("%s: ", __func__);
1643
1644 if ((stv0900_status(state->internal, state->demod)) == TRUE) {
1645 dprintk("DEMOD LOCK OK\n");
1646 *status = FE_HAS_CARRIER
1647 | FE_HAS_VITERBI
1648 | FE_HAS_SYNC
1649 | FE_HAS_LOCK;
1650 if (state->config->set_lock_led)
1651 state->config->set_lock_led(fe, 1);
1652 } else {
1653 *status = 0;
1654 if (state->config->set_lock_led)
1655 state->config->set_lock_led(fe, 0);
1656 dprintk("DEMOD LOCK FAIL\n");
1657 }
1658
1659 return 0;
1660 }
1661
stv0900_stop_ts(struct dvb_frontend * fe,int stop_ts)1662 static int stv0900_stop_ts(struct dvb_frontend *fe, int stop_ts)
1663 {
1664
1665 struct stv0900_state *state = fe->demodulator_priv;
1666 struct stv0900_internal *intp = state->internal;
1667 enum fe_stv0900_demod_num demod = state->demod;
1668
1669 if (stop_ts == TRUE)
1670 stv0900_write_bits(intp, RST_HWARE, 1);
1671 else
1672 stv0900_write_bits(intp, RST_HWARE, 0);
1673
1674 return 0;
1675 }
1676
stv0900_diseqc_init(struct dvb_frontend * fe)1677 static int stv0900_diseqc_init(struct dvb_frontend *fe)
1678 {
1679 struct stv0900_state *state = fe->demodulator_priv;
1680 struct stv0900_internal *intp = state->internal;
1681 enum fe_stv0900_demod_num demod = state->demod;
1682
1683 stv0900_write_bits(intp, DISTX_MODE, state->config->diseqc_mode);
1684 stv0900_write_bits(intp, DISEQC_RESET, 1);
1685 stv0900_write_bits(intp, DISEQC_RESET, 0);
1686
1687 return 0;
1688 }
1689
stv0900_init(struct dvb_frontend * fe)1690 static int stv0900_init(struct dvb_frontend *fe)
1691 {
1692 dprintk("%s\n", __func__);
1693
1694 stv0900_stop_ts(fe, 1);
1695 stv0900_diseqc_init(fe);
1696
1697 return 0;
1698 }
1699
stv0900_diseqc_send(struct stv0900_internal * intp,u8 * data,u32 NbData,enum fe_stv0900_demod_num demod)1700 static int stv0900_diseqc_send(struct stv0900_internal *intp , u8 *data,
1701 u32 NbData, enum fe_stv0900_demod_num demod)
1702 {
1703 s32 i = 0;
1704
1705 stv0900_write_bits(intp, DIS_PRECHARGE, 1);
1706 while (i < NbData) {
1707 while (stv0900_get_bits(intp, FIFO_FULL))
1708 ;/* checkpatch complains */
1709 stv0900_write_reg(intp, DISTXDATA, data[i]);
1710 i++;
1711 }
1712
1713 stv0900_write_bits(intp, DIS_PRECHARGE, 0);
1714 i = 0;
1715 while ((stv0900_get_bits(intp, TX_IDLE) != 1) && (i < 10)) {
1716 msleep(10);
1717 i++;
1718 }
1719
1720 return 0;
1721 }
1722
stv0900_send_master_cmd(struct dvb_frontend * fe,struct dvb_diseqc_master_cmd * cmd)1723 static int stv0900_send_master_cmd(struct dvb_frontend *fe,
1724 struct dvb_diseqc_master_cmd *cmd)
1725 {
1726 struct stv0900_state *state = fe->demodulator_priv;
1727
1728 return stv0900_diseqc_send(state->internal,
1729 cmd->msg,
1730 cmd->msg_len,
1731 state->demod);
1732 }
1733
stv0900_send_burst(struct dvb_frontend * fe,enum fe_sec_mini_cmd burst)1734 static int stv0900_send_burst(struct dvb_frontend *fe,
1735 enum fe_sec_mini_cmd burst)
1736 {
1737 struct stv0900_state *state = fe->demodulator_priv;
1738 struct stv0900_internal *intp = state->internal;
1739 enum fe_stv0900_demod_num demod = state->demod;
1740 u8 data;
1741
1742
1743 switch (burst) {
1744 case SEC_MINI_A:
1745 stv0900_write_bits(intp, DISTX_MODE, 3);/* Unmodulated */
1746 data = 0x00;
1747 stv0900_diseqc_send(intp, &data, 1, state->demod);
1748 break;
1749 case SEC_MINI_B:
1750 stv0900_write_bits(intp, DISTX_MODE, 2);/* Modulated */
1751 data = 0xff;
1752 stv0900_diseqc_send(intp, &data, 1, state->demod);
1753 break;
1754 }
1755
1756 return 0;
1757 }
1758
stv0900_recv_slave_reply(struct dvb_frontend * fe,struct dvb_diseqc_slave_reply * reply)1759 static int stv0900_recv_slave_reply(struct dvb_frontend *fe,
1760 struct dvb_diseqc_slave_reply *reply)
1761 {
1762 struct stv0900_state *state = fe->demodulator_priv;
1763 struct stv0900_internal *intp = state->internal;
1764 enum fe_stv0900_demod_num demod = state->demod;
1765 s32 i = 0;
1766
1767 reply->msg_len = 0;
1768
1769 while ((stv0900_get_bits(intp, RX_END) != 1) && (i < 10)) {
1770 msleep(10);
1771 i++;
1772 }
1773
1774 if (stv0900_get_bits(intp, RX_END)) {
1775 reply->msg_len = stv0900_get_bits(intp, FIFO_BYTENBR);
1776
1777 for (i = 0; i < reply->msg_len; i++)
1778 reply->msg[i] = stv0900_read_reg(intp, DISRXDATA);
1779 }
1780
1781 return 0;
1782 }
1783
stv0900_set_tone(struct dvb_frontend * fe,enum fe_sec_tone_mode toneoff)1784 static int stv0900_set_tone(struct dvb_frontend *fe,
1785 enum fe_sec_tone_mode toneoff)
1786 {
1787 struct stv0900_state *state = fe->demodulator_priv;
1788 struct stv0900_internal *intp = state->internal;
1789 enum fe_stv0900_demod_num demod = state->demod;
1790
1791 dprintk("%s: %s\n", __func__, ((toneoff == 0) ? "On" : "Off"));
1792
1793 switch (toneoff) {
1794 case SEC_TONE_ON:
1795 /*Set the DiseqC mode to 22Khz _continues_ tone*/
1796 stv0900_write_bits(intp, DISTX_MODE, 0);
1797 stv0900_write_bits(intp, DISEQC_RESET, 1);
1798 /*release DiseqC reset to enable the 22KHz tone*/
1799 stv0900_write_bits(intp, DISEQC_RESET, 0);
1800 break;
1801 case SEC_TONE_OFF:
1802 /*return diseqc mode to config->diseqc_mode.
1803 Usually it's without _continues_ tone */
1804 stv0900_write_bits(intp, DISTX_MODE,
1805 state->config->diseqc_mode);
1806 /*maintain the DiseqC reset to disable the 22KHz tone*/
1807 stv0900_write_bits(intp, DISEQC_RESET, 1);
1808 stv0900_write_bits(intp, DISEQC_RESET, 0);
1809 break;
1810 default:
1811 return -EINVAL;
1812 }
1813
1814 return 0;
1815 }
1816
stv0900_release(struct dvb_frontend * fe)1817 static void stv0900_release(struct dvb_frontend *fe)
1818 {
1819 struct stv0900_state *state = fe->demodulator_priv;
1820
1821 dprintk("%s\n", __func__);
1822
1823 if (state->config->set_lock_led)
1824 state->config->set_lock_led(fe, 0);
1825
1826 if ((--(state->internal->dmds_used)) <= 0) {
1827
1828 dprintk("%s: Actually removing\n", __func__);
1829
1830 remove_inode(state->internal);
1831 kfree(state->internal);
1832 }
1833
1834 kfree(state);
1835 }
1836
stv0900_sleep(struct dvb_frontend * fe)1837 static int stv0900_sleep(struct dvb_frontend *fe)
1838 {
1839 struct stv0900_state *state = fe->demodulator_priv;
1840
1841 dprintk("%s\n", __func__);
1842
1843 if (state->config->set_lock_led)
1844 state->config->set_lock_led(fe, 0);
1845
1846 return 0;
1847 }
1848
stv0900_get_frontend(struct dvb_frontend * fe,struct dtv_frontend_properties * p)1849 static int stv0900_get_frontend(struct dvb_frontend *fe,
1850 struct dtv_frontend_properties *p)
1851 {
1852 struct stv0900_state *state = fe->demodulator_priv;
1853 struct stv0900_internal *intp = state->internal;
1854 enum fe_stv0900_demod_num demod = state->demod;
1855 struct stv0900_signal_info p_result = intp->result[demod];
1856
1857 p->frequency = p_result.locked ? p_result.frequency : 0;
1858 p->symbol_rate = p_result.locked ? p_result.symbol_rate : 0;
1859 return 0;
1860 }
1861
1862 static const struct dvb_frontend_ops stv0900_ops = {
1863 .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS },
1864 .info = {
1865 .name = "STV0900 frontend",
1866 .frequency_min_hz = 950 * MHz,
1867 .frequency_max_hz = 2150 * MHz,
1868 .frequency_stepsize_hz = 125 * kHz,
1869 .symbol_rate_min = 1000000,
1870 .symbol_rate_max = 45000000,
1871 .symbol_rate_tolerance = 500,
1872 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
1873 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 |
1874 FE_CAN_FEC_7_8 | FE_CAN_QPSK |
1875 FE_CAN_2G_MODULATION |
1876 FE_CAN_FEC_AUTO
1877 },
1878 .release = stv0900_release,
1879 .init = stv0900_init,
1880 .get_frontend = stv0900_get_frontend,
1881 .sleep = stv0900_sleep,
1882 .get_frontend_algo = stv0900_frontend_algo,
1883 .i2c_gate_ctrl = stv0900_i2c_gate_ctrl,
1884 .diseqc_send_master_cmd = stv0900_send_master_cmd,
1885 .diseqc_send_burst = stv0900_send_burst,
1886 .diseqc_recv_slave_reply = stv0900_recv_slave_reply,
1887 .set_tone = stv0900_set_tone,
1888 .search = stv0900_search,
1889 .read_status = stv0900_read_status,
1890 .read_ber = stv0900_read_ber,
1891 .read_signal_strength = stv0900_read_signal_strength,
1892 .read_snr = stv0900_read_snr,
1893 .read_ucblocks = stv0900_read_ucblocks,
1894 };
1895
stv0900_attach(const struct stv0900_config * config,struct i2c_adapter * i2c,int demod)1896 struct dvb_frontend *stv0900_attach(const struct stv0900_config *config,
1897 struct i2c_adapter *i2c,
1898 int demod)
1899 {
1900 struct stv0900_state *state = NULL;
1901 struct stv0900_init_params init_params;
1902 enum fe_stv0900_error err_stv0900;
1903
1904 state = kzalloc_obj(struct stv0900_state);
1905 if (state == NULL)
1906 goto error;
1907
1908 state->demod = demod;
1909 state->config = config;
1910 state->i2c_adap = i2c;
1911
1912 memcpy(&state->frontend.ops, &stv0900_ops,
1913 sizeof(struct dvb_frontend_ops));
1914 state->frontend.demodulator_priv = state;
1915
1916 switch (demod) {
1917 case 0:
1918 case 1:
1919 init_params.dmd_ref_clk = config->xtal;
1920 init_params.demod_mode = config->demod_mode;
1921 init_params.rolloff = STV0900_35;
1922 init_params.path1_ts_clock = config->path1_mode;
1923 init_params.tun1_maddress = config->tun1_maddress;
1924 init_params.tun1_iq_inv = STV0900_IQ_NORMAL;
1925 init_params.tuner1_adc = config->tun1_adc;
1926 init_params.tuner1_type = config->tun1_type;
1927 init_params.path2_ts_clock = config->path2_mode;
1928 init_params.ts_config = config->ts_config_regs;
1929 init_params.tun2_maddress = config->tun2_maddress;
1930 init_params.tuner2_adc = config->tun2_adc;
1931 init_params.tuner2_type = config->tun2_type;
1932 init_params.tun2_iq_inv = STV0900_IQ_SWAPPED;
1933
1934 err_stv0900 = stv0900_init_internal(&state->frontend,
1935 &init_params);
1936
1937 if (err_stv0900)
1938 goto error;
1939
1940 if (state->internal->chip_id >= 0x30)
1941 state->frontend.ops.info.caps |= FE_CAN_MULTISTREAM;
1942
1943 break;
1944 default:
1945 goto error;
1946 break;
1947 }
1948
1949 dprintk("%s: Attaching STV0900 demodulator(%d) \n", __func__, demod);
1950 return &state->frontend;
1951
1952 error:
1953 dprintk("%s: Failed to attach STV0900 demodulator(%d) \n",
1954 __func__, demod);
1955 kfree(state);
1956 return NULL;
1957 }
1958 EXPORT_SYMBOL_GPL(stv0900_attach);
1959
1960 MODULE_PARM_DESC(debug, "Set debug");
1961
1962 MODULE_AUTHOR("Igor M. Liplianin");
1963 MODULE_DESCRIPTION("ST STV0900 frontend");
1964 MODULE_LICENSE("GPL");
1965