1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright(c) 2021 Intel Corporation. All rights reserved. 3 4 #include <linux/platform_device.h> 5 #include <linux/mod_devicetable.h> 6 #include <linux/vmalloc.h> 7 #include <linux/module.h> 8 #include <linux/delay.h> 9 #include <linux/sizes.h> 10 #include <linux/bits.h> 11 #include <cxl/mailbox.h> 12 #include <linux/unaligned.h> 13 #include <crypto/sha2.h> 14 #include <cxlmem.h> 15 16 #include "trace.h" 17 18 #define LSA_SIZE SZ_128K 19 #define FW_SIZE SZ_64M 20 #define FW_SLOTS 3 21 #define DEV_SIZE SZ_2G 22 #define EFFECT(x) (1U << x) 23 24 #define MOCK_INJECT_DEV_MAX 8 25 #define MOCK_INJECT_TEST_MAX 128 26 27 static unsigned int poison_inject_dev_max = MOCK_INJECT_DEV_MAX; 28 29 enum cxl_command_effects { 30 CONF_CHANGE_COLD_RESET = 0, 31 CONF_CHANGE_IMMEDIATE, 32 DATA_CHANGE_IMMEDIATE, 33 POLICY_CHANGE_IMMEDIATE, 34 LOG_CHANGE_IMMEDIATE, 35 SECURITY_CHANGE_IMMEDIATE, 36 BACKGROUND_OP, 37 SECONDARY_MBOX_SUPPORTED, 38 }; 39 40 #define CXL_CMD_EFFECT_NONE cpu_to_le16(0) 41 42 static struct cxl_cel_entry mock_cel[] = { 43 { 44 .opcode = cpu_to_le16(CXL_MBOX_OP_GET_SUPPORTED_LOGS), 45 .effect = CXL_CMD_EFFECT_NONE, 46 }, 47 { 48 .opcode = cpu_to_le16(CXL_MBOX_OP_GET_SUPPORTED_FEATURES), 49 .effect = CXL_CMD_EFFECT_NONE, 50 }, 51 { 52 .opcode = cpu_to_le16(CXL_MBOX_OP_GET_FEATURE), 53 .effect = CXL_CMD_EFFECT_NONE, 54 }, 55 { 56 .opcode = cpu_to_le16(CXL_MBOX_OP_SET_FEATURE), 57 .effect = cpu_to_le16(EFFECT(CONF_CHANGE_IMMEDIATE)), 58 }, 59 { 60 .opcode = cpu_to_le16(CXL_MBOX_OP_IDENTIFY), 61 .effect = CXL_CMD_EFFECT_NONE, 62 }, 63 { 64 .opcode = cpu_to_le16(CXL_MBOX_OP_GET_LSA), 65 .effect = CXL_CMD_EFFECT_NONE, 66 }, 67 { 68 .opcode = cpu_to_le16(CXL_MBOX_OP_GET_PARTITION_INFO), 69 .effect = CXL_CMD_EFFECT_NONE, 70 }, 71 { 72 .opcode = cpu_to_le16(CXL_MBOX_OP_SET_LSA), 73 .effect = cpu_to_le16(EFFECT(CONF_CHANGE_IMMEDIATE) | 74 EFFECT(DATA_CHANGE_IMMEDIATE)), 75 }, 76 { 77 .opcode = cpu_to_le16(CXL_MBOX_OP_GET_HEALTH_INFO), 78 .effect = CXL_CMD_EFFECT_NONE, 79 }, 80 { 81 .opcode = cpu_to_le16(CXL_MBOX_OP_SET_SHUTDOWN_STATE), 82 .effect = POLICY_CHANGE_IMMEDIATE, 83 }, 84 { 85 .opcode = cpu_to_le16(CXL_MBOX_OP_GET_POISON), 86 .effect = CXL_CMD_EFFECT_NONE, 87 }, 88 { 89 .opcode = cpu_to_le16(CXL_MBOX_OP_INJECT_POISON), 90 .effect = cpu_to_le16(EFFECT(DATA_CHANGE_IMMEDIATE)), 91 }, 92 { 93 .opcode = cpu_to_le16(CXL_MBOX_OP_CLEAR_POISON), 94 .effect = cpu_to_le16(EFFECT(DATA_CHANGE_IMMEDIATE)), 95 }, 96 { 97 .opcode = cpu_to_le16(CXL_MBOX_OP_GET_FW_INFO), 98 .effect = CXL_CMD_EFFECT_NONE, 99 }, 100 { 101 .opcode = cpu_to_le16(CXL_MBOX_OP_TRANSFER_FW), 102 .effect = cpu_to_le16(EFFECT(CONF_CHANGE_COLD_RESET) | 103 EFFECT(BACKGROUND_OP)), 104 }, 105 { 106 .opcode = cpu_to_le16(CXL_MBOX_OP_ACTIVATE_FW), 107 .effect = cpu_to_le16(EFFECT(CONF_CHANGE_COLD_RESET) | 108 EFFECT(CONF_CHANGE_IMMEDIATE)), 109 }, 110 { 111 .opcode = cpu_to_le16(CXL_MBOX_OP_SANITIZE), 112 .effect = cpu_to_le16(EFFECT(DATA_CHANGE_IMMEDIATE) | 113 EFFECT(SECURITY_CHANGE_IMMEDIATE) | 114 EFFECT(BACKGROUND_OP)), 115 }, 116 }; 117 118 /* See CXL 2.0 Table 181 Get Health Info Output Payload */ 119 struct cxl_mbox_health_info { 120 u8 health_status; 121 u8 media_status; 122 u8 ext_status; 123 u8 life_used; 124 __le16 temperature; 125 __le32 dirty_shutdowns; 126 __le32 volatile_errors; 127 __le32 pmem_errors; 128 } __packed; 129 130 static struct { 131 struct cxl_mbox_get_supported_logs gsl; 132 struct cxl_gsl_entry entry; 133 } mock_gsl_payload = { 134 .gsl = { 135 .entries = cpu_to_le16(1), 136 }, 137 .entry = { 138 .uuid = DEFINE_CXL_CEL_UUID, 139 .size = cpu_to_le32(sizeof(mock_cel)), 140 }, 141 }; 142 143 #define PASS_TRY_LIMIT 3 144 145 #define CXL_TEST_EVENT_CNT_MAX 15 146 147 /* Set a number of events to return at a time for simulation. */ 148 #define CXL_TEST_EVENT_RET_MAX 4 149 150 struct mock_event_log { 151 u16 clear_idx; 152 u16 cur_idx; 153 u16 nr_events; 154 u16 nr_overflow; 155 u16 overflow_reset; 156 struct cxl_event_record_raw *events[CXL_TEST_EVENT_CNT_MAX]; 157 }; 158 159 struct mock_event_store { 160 struct mock_event_log mock_logs[CXL_EVENT_TYPE_MAX]; 161 u32 ev_status; 162 }; 163 164 struct vendor_test_feat { 165 __le32 data; 166 } __packed; 167 168 struct cxl_mockmem_data { 169 void *lsa; 170 void *fw; 171 int fw_slot; 172 int fw_staged; 173 size_t fw_size; 174 u32 security_state; 175 u8 user_pass[NVDIMM_PASSPHRASE_LEN]; 176 u8 master_pass[NVDIMM_PASSPHRASE_LEN]; 177 int user_limit; 178 int master_limit; 179 struct mock_event_store mes; 180 struct cxl_memdev_state *mds; 181 u8 event_buf[SZ_4K]; 182 u64 timestamp; 183 unsigned long sanitize_timeout; 184 struct vendor_test_feat test_feat; 185 u8 shutdown_state; 186 }; 187 188 static struct mock_event_log *event_find_log(struct device *dev, int log_type) 189 { 190 struct cxl_mockmem_data *mdata = dev_get_drvdata(dev); 191 192 if (log_type >= CXL_EVENT_TYPE_MAX) 193 return NULL; 194 return &mdata->mes.mock_logs[log_type]; 195 } 196 197 static struct cxl_event_record_raw *event_get_current(struct mock_event_log *log) 198 { 199 return log->events[log->cur_idx]; 200 } 201 202 static void event_reset_log(struct mock_event_log *log) 203 { 204 log->cur_idx = 0; 205 log->clear_idx = 0; 206 log->nr_overflow = log->overflow_reset; 207 } 208 209 /* Handle can never be 0 use 1 based indexing for handle */ 210 static u16 event_get_clear_handle(struct mock_event_log *log) 211 { 212 return log->clear_idx + 1; 213 } 214 215 /* Handle can never be 0 use 1 based indexing for handle */ 216 static __le16 event_get_cur_event_handle(struct mock_event_log *log) 217 { 218 u16 cur_handle = log->cur_idx + 1; 219 220 return cpu_to_le16(cur_handle); 221 } 222 223 static bool event_log_empty(struct mock_event_log *log) 224 { 225 return log->cur_idx == log->nr_events; 226 } 227 228 static void mes_add_event(struct mock_event_store *mes, 229 enum cxl_event_log_type log_type, 230 struct cxl_event_record_raw *event) 231 { 232 struct mock_event_log *log; 233 234 if (WARN_ON(log_type >= CXL_EVENT_TYPE_MAX)) 235 return; 236 237 log = &mes->mock_logs[log_type]; 238 239 if ((log->nr_events + 1) > CXL_TEST_EVENT_CNT_MAX) { 240 log->nr_overflow++; 241 log->overflow_reset = log->nr_overflow; 242 return; 243 } 244 245 log->events[log->nr_events] = event; 246 log->nr_events++; 247 } 248 249 /* 250 * Vary the number of events returned to simulate events occuring while the 251 * logs are being read. 252 */ 253 static atomic_t event_counter = ATOMIC_INIT(0); 254 255 static int mock_get_event(struct device *dev, struct cxl_mbox_cmd *cmd) 256 { 257 struct cxl_get_event_payload *pl; 258 struct mock_event_log *log; 259 int ret_limit; 260 u8 log_type; 261 int i; 262 263 if (cmd->size_in != sizeof(log_type)) 264 return -EINVAL; 265 266 /* Vary return limit from 1 to CXL_TEST_EVENT_RET_MAX */ 267 ret_limit = (atomic_inc_return(&event_counter) % CXL_TEST_EVENT_RET_MAX) + 1; 268 269 if (cmd->size_out < struct_size(pl, records, ret_limit)) 270 return -EINVAL; 271 272 log_type = *((u8 *)cmd->payload_in); 273 if (log_type >= CXL_EVENT_TYPE_MAX) 274 return -EINVAL; 275 276 memset(cmd->payload_out, 0, struct_size(pl, records, 0)); 277 278 log = event_find_log(dev, log_type); 279 if (!log || event_log_empty(log)) 280 return 0; 281 282 pl = cmd->payload_out; 283 284 for (i = 0; i < ret_limit && !event_log_empty(log); i++) { 285 memcpy(&pl->records[i], event_get_current(log), 286 sizeof(pl->records[i])); 287 pl->records[i].event.generic.hdr.handle = 288 event_get_cur_event_handle(log); 289 log->cur_idx++; 290 } 291 292 cmd->size_out = struct_size(pl, records, i); 293 pl->record_count = cpu_to_le16(i); 294 if (!event_log_empty(log)) 295 pl->flags |= CXL_GET_EVENT_FLAG_MORE_RECORDS; 296 297 if (log->nr_overflow) { 298 u64 ns; 299 300 pl->flags |= CXL_GET_EVENT_FLAG_OVERFLOW; 301 pl->overflow_err_count = cpu_to_le16(log->nr_overflow); 302 ns = ktime_get_real_ns(); 303 ns -= 5000000000; /* 5s ago */ 304 pl->first_overflow_timestamp = cpu_to_le64(ns); 305 ns = ktime_get_real_ns(); 306 ns -= 1000000000; /* 1s ago */ 307 pl->last_overflow_timestamp = cpu_to_le64(ns); 308 } 309 310 return 0; 311 } 312 313 static int mock_clear_event(struct device *dev, struct cxl_mbox_cmd *cmd) 314 { 315 struct cxl_mbox_clear_event_payload *pl; 316 struct mock_event_log *log; 317 u8 log_type; 318 u16 handle; 319 int nr; 320 321 if (cmd->size_in < sizeof(*pl)) 322 return -EINVAL; 323 324 pl = cmd->payload_in; 325 log_type = pl->event_log; 326 if (log_type >= CXL_EVENT_TYPE_MAX) 327 return -EINVAL; 328 329 log = event_find_log(dev, log_type); 330 if (!log) 331 return 0; /* No mock data in this log */ 332 333 /* 334 * This check is technically not invalid per the specification AFAICS. 335 * (The host could 'guess' handles and clear them in order). 336 * However, this is not good behavior for the host so test it. 337 */ 338 if (log->clear_idx + pl->nr_recs > log->cur_idx) { 339 dev_err(dev, 340 "Attempting to clear more events than returned!\n"); 341 return -EINVAL; 342 } 343 344 /* Check handle order prior to clearing events */ 345 for (nr = 0, handle = event_get_clear_handle(log); 346 nr < pl->nr_recs; 347 nr++, handle++) { 348 if (handle != le16_to_cpu(pl->handles[nr])) { 349 dev_err(dev, "Clearing events out of order\n"); 350 return -EINVAL; 351 } 352 } 353 354 if (log->nr_overflow) 355 log->nr_overflow = 0; 356 357 /* Clear events */ 358 log->clear_idx += pl->nr_recs; 359 return 0; 360 } 361 362 static void cxl_mock_event_trigger(struct device *dev) 363 { 364 struct cxl_mockmem_data *mdata = dev_get_drvdata(dev); 365 struct mock_event_store *mes = &mdata->mes; 366 int i; 367 368 for (i = CXL_EVENT_TYPE_INFO; i < CXL_EVENT_TYPE_MAX; i++) { 369 struct mock_event_log *log; 370 371 log = event_find_log(dev, i); 372 if (log) 373 event_reset_log(log); 374 } 375 376 cxl_mem_get_event_records(mdata->mds, mes->ev_status); 377 } 378 379 struct cxl_event_record_raw maint_needed = { 380 .id = UUID_INIT(0xBA5EBA11, 0xABCD, 0xEFEB, 381 0xa5, 0x5a, 0xa5, 0x5a, 0xa5, 0xa5, 0x5a, 0xa5), 382 .event.generic = { 383 .hdr = { 384 .length = sizeof(struct cxl_event_record_raw), 385 .flags[0] = CXL_EVENT_RECORD_FLAG_MAINT_NEEDED, 386 /* .handle = Set dynamically */ 387 .related_handle = cpu_to_le16(0xa5b6), 388 }, 389 .data = { 0xDE, 0xAD, 0xBE, 0xEF }, 390 }, 391 }; 392 393 struct cxl_event_record_raw hardware_replace = { 394 .id = UUID_INIT(0xABCDEFEB, 0xBA11, 0xBA5E, 395 0xa5, 0x5a, 0xa5, 0x5a, 0xa5, 0xa5, 0x5a, 0xa5), 396 .event.generic = { 397 .hdr = { 398 .length = sizeof(struct cxl_event_record_raw), 399 .flags[0] = CXL_EVENT_RECORD_FLAG_HW_REPLACE, 400 /* .handle = Set dynamically */ 401 .related_handle = cpu_to_le16(0xb6a5), 402 }, 403 .data = { 0xDE, 0xAD, 0xBE, 0xEF }, 404 }, 405 }; 406 407 struct cxl_test_gen_media { 408 uuid_t id; 409 struct cxl_event_gen_media rec; 410 } __packed; 411 412 struct cxl_test_gen_media gen_media = { 413 .id = CXL_EVENT_GEN_MEDIA_UUID, 414 .rec = { 415 .media_hdr = { 416 .hdr = { 417 .length = sizeof(struct cxl_test_gen_media), 418 .flags[0] = CXL_EVENT_RECORD_FLAG_PERMANENT, 419 /* .handle = Set dynamically */ 420 .related_handle = cpu_to_le16(0), 421 }, 422 .phys_addr = cpu_to_le64(0x2000), 423 .descriptor = CXL_GMER_EVT_DESC_UNCORECTABLE_EVENT, 424 .type = CXL_GMER_MEM_EVT_TYPE_DATA_PATH_ERROR, 425 .transaction_type = CXL_GMER_TRANS_HOST_WRITE, 426 /* .validity_flags = <set below> */ 427 .channel = 1, 428 .rank = 30, 429 }, 430 .component_id = { 0x3, 0x74, 0xc5, 0x8, 0x9a, 0x1a, 0xb, 0xfc, 0xd2, 0x7e, 0x2f, 0x31, 0x9b, 0x3c, 0x81, 0x4d }, 431 .cme_threshold_ev_flags = 3, 432 .cme_count = { 33, 0, 0 }, 433 .sub_type = 0x2, 434 }, 435 }; 436 437 struct cxl_test_dram { 438 uuid_t id; 439 struct cxl_event_dram rec; 440 } __packed; 441 442 struct cxl_test_dram dram = { 443 .id = CXL_EVENT_DRAM_UUID, 444 .rec = { 445 .media_hdr = { 446 .hdr = { 447 .length = sizeof(struct cxl_test_dram), 448 .flags[0] = CXL_EVENT_RECORD_FLAG_PERF_DEGRADED, 449 /* .handle = Set dynamically */ 450 .related_handle = cpu_to_le16(0), 451 }, 452 .phys_addr = cpu_to_le64(0x8000), 453 .descriptor = CXL_GMER_EVT_DESC_THRESHOLD_EVENT, 454 .type = CXL_GMER_MEM_EVT_TYPE_INV_ADDR, 455 .transaction_type = CXL_GMER_TRANS_INTERNAL_MEDIA_SCRUB, 456 /* .validity_flags = <set below> */ 457 .channel = 1, 458 }, 459 .bank_group = 5, 460 .bank = 2, 461 .column = {0xDE, 0xAD}, 462 .component_id = { 0x1, 0x74, 0xc5, 0x8, 0x9a, 0x1a, 0xb, 0xfc, 0xd2, 0x7e, 0x2f, 0x31, 0x9b, 0x3c, 0x81, 0x4d }, 463 .sub_channel = 8, 464 .cme_threshold_ev_flags = 2, 465 .cvme_count = { 14, 0, 0 }, 466 .sub_type = 0x5, 467 }, 468 }; 469 470 struct cxl_test_mem_module { 471 uuid_t id; 472 struct cxl_event_mem_module rec; 473 } __packed; 474 475 struct cxl_test_mem_module mem_module = { 476 .id = CXL_EVENT_MEM_MODULE_UUID, 477 .rec = { 478 .hdr = { 479 .length = sizeof(struct cxl_test_mem_module), 480 /* .handle = Set dynamically */ 481 .related_handle = cpu_to_le16(0), 482 }, 483 .event_type = CXL_MMER_TEMP_CHANGE, 484 .info = { 485 .health_status = CXL_DHI_HS_PERFORMANCE_DEGRADED, 486 .media_status = CXL_DHI_MS_ALL_DATA_LOST, 487 .add_status = (CXL_DHI_AS_CRITICAL << 2) | 488 (CXL_DHI_AS_WARNING << 4) | 489 (CXL_DHI_AS_WARNING << 5), 490 .device_temp = { 0xDE, 0xAD}, 491 .dirty_shutdown_cnt = { 0xde, 0xad, 0xbe, 0xef }, 492 .cor_vol_err_cnt = { 0xde, 0xad, 0xbe, 0xef }, 493 .cor_per_err_cnt = { 0xde, 0xad, 0xbe, 0xef }, 494 }, 495 /* .validity_flags = <set below> */ 496 .component_id = { 0x2, 0x74, 0xc5, 0x8, 0x9a, 0x1a, 0xb, 0xfc, 0xd2, 0x7e, 0x2f, 0x31, 0x9b, 0x3c, 0x81, 0x4d }, 497 .event_sub_type = 0x3, 498 }, 499 }; 500 501 static int mock_set_timestamp(struct cxl_dev_state *cxlds, 502 struct cxl_mbox_cmd *cmd) 503 { 504 struct cxl_mockmem_data *mdata = dev_get_drvdata(cxlds->dev); 505 struct cxl_mbox_set_timestamp_in *ts = cmd->payload_in; 506 507 if (cmd->size_in != sizeof(*ts)) 508 return -EINVAL; 509 510 if (cmd->size_out != 0) 511 return -EINVAL; 512 513 mdata->timestamp = le64_to_cpu(ts->timestamp); 514 return 0; 515 } 516 517 static void cxl_mock_add_event_logs(struct mock_event_store *mes) 518 { 519 put_unaligned_le16(CXL_GMER_VALID_CHANNEL | CXL_GMER_VALID_RANK | 520 CXL_GMER_VALID_COMPONENT | CXL_GMER_VALID_COMPONENT_ID_FORMAT, 521 &gen_media.rec.media_hdr.validity_flags); 522 523 put_unaligned_le16(CXL_DER_VALID_CHANNEL | CXL_DER_VALID_BANK_GROUP | 524 CXL_DER_VALID_BANK | CXL_DER_VALID_COLUMN | CXL_DER_VALID_SUB_CHANNEL | 525 CXL_DER_VALID_COMPONENT | CXL_DER_VALID_COMPONENT_ID_FORMAT, 526 &dram.rec.media_hdr.validity_flags); 527 528 put_unaligned_le16(CXL_MMER_VALID_COMPONENT | CXL_MMER_VALID_COMPONENT_ID_FORMAT, 529 &mem_module.rec.validity_flags); 530 531 mes_add_event(mes, CXL_EVENT_TYPE_INFO, &maint_needed); 532 mes_add_event(mes, CXL_EVENT_TYPE_INFO, 533 (struct cxl_event_record_raw *)&gen_media); 534 mes_add_event(mes, CXL_EVENT_TYPE_INFO, 535 (struct cxl_event_record_raw *)&mem_module); 536 mes->ev_status |= CXLDEV_EVENT_STATUS_INFO; 537 538 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &maint_needed); 539 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace); 540 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, 541 (struct cxl_event_record_raw *)&dram); 542 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, 543 (struct cxl_event_record_raw *)&gen_media); 544 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, 545 (struct cxl_event_record_raw *)&mem_module); 546 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace); 547 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, 548 (struct cxl_event_record_raw *)&dram); 549 /* Overflow this log */ 550 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace); 551 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace); 552 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace); 553 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace); 554 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace); 555 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace); 556 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace); 557 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace); 558 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace); 559 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace); 560 mes->ev_status |= CXLDEV_EVENT_STATUS_FAIL; 561 562 mes_add_event(mes, CXL_EVENT_TYPE_FATAL, &hardware_replace); 563 mes_add_event(mes, CXL_EVENT_TYPE_FATAL, 564 (struct cxl_event_record_raw *)&dram); 565 mes->ev_status |= CXLDEV_EVENT_STATUS_FATAL; 566 } 567 568 static int mock_gsl(struct cxl_mbox_cmd *cmd) 569 { 570 if (cmd->size_out < sizeof(mock_gsl_payload)) 571 return -EINVAL; 572 573 memcpy(cmd->payload_out, &mock_gsl_payload, sizeof(mock_gsl_payload)); 574 cmd->size_out = sizeof(mock_gsl_payload); 575 576 return 0; 577 } 578 579 static int mock_get_log(struct cxl_memdev_state *mds, struct cxl_mbox_cmd *cmd) 580 { 581 struct cxl_mailbox *cxl_mbox = &mds->cxlds.cxl_mbox; 582 uuid_t uuid = DEFINE_CXL_CEL_UUID; 583 struct cxl_mbox_get_log *gl; 584 void *data = &mock_cel; 585 u32 offset; 586 u32 length; 587 588 if (cmd->size_in < sizeof(*gl)) 589 return -EINVAL; 590 591 gl = cmd->payload_in; 592 offset = le32_to_cpu(gl->offset); 593 length = le32_to_cpu(gl->length); 594 595 if (length > cxl_mbox->payload_size) 596 return -EINVAL; 597 if (offset + length > sizeof(mock_cel)) 598 return -EINVAL; 599 if (!uuid_equal(&gl->uuid, &uuid)) 600 return -EINVAL; 601 if (length > cmd->size_out) 602 return -EINVAL; 603 604 memcpy(cmd->payload_out, data + offset, length); 605 606 return 0; 607 } 608 609 static int mock_rcd_id(struct cxl_mbox_cmd *cmd) 610 { 611 struct cxl_mbox_identify id = { 612 .fw_revision = { "mock fw v1 " }, 613 .total_capacity = 614 cpu_to_le64(DEV_SIZE / CXL_CAPACITY_MULTIPLIER), 615 .volatile_capacity = 616 cpu_to_le64(DEV_SIZE / CXL_CAPACITY_MULTIPLIER), 617 }; 618 619 if (cmd->size_out < sizeof(id)) 620 return -EINVAL; 621 622 memcpy(cmd->payload_out, &id, sizeof(id)); 623 624 return 0; 625 } 626 627 static int mock_id(struct cxl_mbox_cmd *cmd) 628 { 629 struct cxl_mbox_identify id = { 630 .fw_revision = { "mock fw v1 " }, 631 .lsa_size = cpu_to_le32(LSA_SIZE), 632 .partition_align = 633 cpu_to_le64(SZ_256M / CXL_CAPACITY_MULTIPLIER), 634 .total_capacity = 635 cpu_to_le64(DEV_SIZE / CXL_CAPACITY_MULTIPLIER), 636 .inject_poison_limit = cpu_to_le16(MOCK_INJECT_TEST_MAX), 637 }; 638 639 put_unaligned_le24(CXL_POISON_LIST_MAX, id.poison_list_max_mer); 640 641 if (cmd->size_out < sizeof(id)) 642 return -EINVAL; 643 644 memcpy(cmd->payload_out, &id, sizeof(id)); 645 646 return 0; 647 } 648 649 static int mock_partition_info(struct cxl_mbox_cmd *cmd) 650 { 651 struct cxl_mbox_get_partition_info pi = { 652 .active_volatile_cap = 653 cpu_to_le64(DEV_SIZE / 2 / CXL_CAPACITY_MULTIPLIER), 654 .active_persistent_cap = 655 cpu_to_le64(DEV_SIZE / 2 / CXL_CAPACITY_MULTIPLIER), 656 }; 657 658 if (cmd->size_out < sizeof(pi)) 659 return -EINVAL; 660 661 memcpy(cmd->payload_out, &pi, sizeof(pi)); 662 663 return 0; 664 } 665 666 void cxl_mockmem_sanitize_work(struct work_struct *work) 667 { 668 struct cxl_memdev_state *mds = 669 container_of(work, typeof(*mds), security.poll_dwork.work); 670 struct cxl_mailbox *cxl_mbox = &mds->cxlds.cxl_mbox; 671 672 mutex_lock(&cxl_mbox->mbox_mutex); 673 if (mds->security.sanitize_node) 674 sysfs_notify_dirent(mds->security.sanitize_node); 675 mds->security.sanitize_active = false; 676 mutex_unlock(&cxl_mbox->mbox_mutex); 677 678 dev_dbg(mds->cxlds.dev, "sanitize complete\n"); 679 } 680 681 static int mock_sanitize(struct cxl_mockmem_data *mdata, 682 struct cxl_mbox_cmd *cmd) 683 { 684 struct cxl_memdev_state *mds = mdata->mds; 685 struct cxl_mailbox *cxl_mbox = &mds->cxlds.cxl_mbox; 686 int rc = 0; 687 688 if (cmd->size_in != 0) 689 return -EINVAL; 690 691 if (cmd->size_out != 0) 692 return -EINVAL; 693 694 if (mdata->security_state & CXL_PMEM_SEC_STATE_USER_PASS_SET) { 695 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 696 return -ENXIO; 697 } 698 if (mdata->security_state & CXL_PMEM_SEC_STATE_LOCKED) { 699 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 700 return -ENXIO; 701 } 702 703 mutex_lock(&cxl_mbox->mbox_mutex); 704 if (schedule_delayed_work(&mds->security.poll_dwork, 705 msecs_to_jiffies(mdata->sanitize_timeout))) { 706 mds->security.sanitize_active = true; 707 dev_dbg(mds->cxlds.dev, "sanitize issued\n"); 708 } else 709 rc = -EBUSY; 710 mutex_unlock(&cxl_mbox->mbox_mutex); 711 712 return rc; 713 } 714 715 static int mock_secure_erase(struct cxl_mockmem_data *mdata, 716 struct cxl_mbox_cmd *cmd) 717 { 718 if (cmd->size_in != 0) 719 return -EINVAL; 720 721 if (cmd->size_out != 0) 722 return -EINVAL; 723 724 if (mdata->security_state & CXL_PMEM_SEC_STATE_USER_PASS_SET) { 725 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 726 return -ENXIO; 727 } 728 729 if (mdata->security_state & CXL_PMEM_SEC_STATE_LOCKED) { 730 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 731 return -ENXIO; 732 } 733 734 return 0; 735 } 736 737 static int mock_get_security_state(struct cxl_mockmem_data *mdata, 738 struct cxl_mbox_cmd *cmd) 739 { 740 if (cmd->size_in) 741 return -EINVAL; 742 743 if (cmd->size_out != sizeof(u32)) 744 return -EINVAL; 745 746 memcpy(cmd->payload_out, &mdata->security_state, sizeof(u32)); 747 748 return 0; 749 } 750 751 static void master_plimit_check(struct cxl_mockmem_data *mdata) 752 { 753 if (mdata->master_limit == PASS_TRY_LIMIT) 754 return; 755 mdata->master_limit++; 756 if (mdata->master_limit == PASS_TRY_LIMIT) 757 mdata->security_state |= CXL_PMEM_SEC_STATE_MASTER_PLIMIT; 758 } 759 760 static void user_plimit_check(struct cxl_mockmem_data *mdata) 761 { 762 if (mdata->user_limit == PASS_TRY_LIMIT) 763 return; 764 mdata->user_limit++; 765 if (mdata->user_limit == PASS_TRY_LIMIT) 766 mdata->security_state |= CXL_PMEM_SEC_STATE_USER_PLIMIT; 767 } 768 769 static int mock_set_passphrase(struct cxl_mockmem_data *mdata, 770 struct cxl_mbox_cmd *cmd) 771 { 772 struct cxl_set_pass *set_pass; 773 774 if (cmd->size_in != sizeof(*set_pass)) 775 return -EINVAL; 776 777 if (cmd->size_out != 0) 778 return -EINVAL; 779 780 if (mdata->security_state & CXL_PMEM_SEC_STATE_FROZEN) { 781 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 782 return -ENXIO; 783 } 784 785 set_pass = cmd->payload_in; 786 switch (set_pass->type) { 787 case CXL_PMEM_SEC_PASS_MASTER: 788 if (mdata->security_state & CXL_PMEM_SEC_STATE_MASTER_PLIMIT) { 789 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 790 return -ENXIO; 791 } 792 /* 793 * CXL spec rev3.0 8.2.9.8.6.2, The master pasphrase shall only be set in 794 * the security disabled state when the user passphrase is not set. 795 */ 796 if (mdata->security_state & CXL_PMEM_SEC_STATE_USER_PASS_SET) { 797 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 798 return -ENXIO; 799 } 800 if (memcmp(mdata->master_pass, set_pass->old_pass, NVDIMM_PASSPHRASE_LEN)) { 801 master_plimit_check(mdata); 802 cmd->return_code = CXL_MBOX_CMD_RC_PASSPHRASE; 803 return -ENXIO; 804 } 805 memcpy(mdata->master_pass, set_pass->new_pass, NVDIMM_PASSPHRASE_LEN); 806 mdata->security_state |= CXL_PMEM_SEC_STATE_MASTER_PASS_SET; 807 return 0; 808 809 case CXL_PMEM_SEC_PASS_USER: 810 if (mdata->security_state & CXL_PMEM_SEC_STATE_USER_PLIMIT) { 811 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 812 return -ENXIO; 813 } 814 if (memcmp(mdata->user_pass, set_pass->old_pass, NVDIMM_PASSPHRASE_LEN)) { 815 user_plimit_check(mdata); 816 cmd->return_code = CXL_MBOX_CMD_RC_PASSPHRASE; 817 return -ENXIO; 818 } 819 memcpy(mdata->user_pass, set_pass->new_pass, NVDIMM_PASSPHRASE_LEN); 820 mdata->security_state |= CXL_PMEM_SEC_STATE_USER_PASS_SET; 821 return 0; 822 823 default: 824 cmd->return_code = CXL_MBOX_CMD_RC_INPUT; 825 } 826 return -EINVAL; 827 } 828 829 static int mock_disable_passphrase(struct cxl_mockmem_data *mdata, 830 struct cxl_mbox_cmd *cmd) 831 { 832 struct cxl_disable_pass *dis_pass; 833 834 if (cmd->size_in != sizeof(*dis_pass)) 835 return -EINVAL; 836 837 if (cmd->size_out != 0) 838 return -EINVAL; 839 840 if (mdata->security_state & CXL_PMEM_SEC_STATE_FROZEN) { 841 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 842 return -ENXIO; 843 } 844 845 dis_pass = cmd->payload_in; 846 switch (dis_pass->type) { 847 case CXL_PMEM_SEC_PASS_MASTER: 848 if (mdata->security_state & CXL_PMEM_SEC_STATE_MASTER_PLIMIT) { 849 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 850 return -ENXIO; 851 } 852 853 if (!(mdata->security_state & CXL_PMEM_SEC_STATE_MASTER_PASS_SET)) { 854 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 855 return -ENXIO; 856 } 857 858 if (memcmp(dis_pass->pass, mdata->master_pass, NVDIMM_PASSPHRASE_LEN)) { 859 master_plimit_check(mdata); 860 cmd->return_code = CXL_MBOX_CMD_RC_PASSPHRASE; 861 return -ENXIO; 862 } 863 864 mdata->master_limit = 0; 865 memset(mdata->master_pass, 0, NVDIMM_PASSPHRASE_LEN); 866 mdata->security_state &= ~CXL_PMEM_SEC_STATE_MASTER_PASS_SET; 867 return 0; 868 869 case CXL_PMEM_SEC_PASS_USER: 870 if (mdata->security_state & CXL_PMEM_SEC_STATE_USER_PLIMIT) { 871 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 872 return -ENXIO; 873 } 874 875 if (!(mdata->security_state & CXL_PMEM_SEC_STATE_USER_PASS_SET)) { 876 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 877 return -ENXIO; 878 } 879 880 if (memcmp(dis_pass->pass, mdata->user_pass, NVDIMM_PASSPHRASE_LEN)) { 881 user_plimit_check(mdata); 882 cmd->return_code = CXL_MBOX_CMD_RC_PASSPHRASE; 883 return -ENXIO; 884 } 885 886 mdata->user_limit = 0; 887 memset(mdata->user_pass, 0, NVDIMM_PASSPHRASE_LEN); 888 mdata->security_state &= ~(CXL_PMEM_SEC_STATE_USER_PASS_SET | 889 CXL_PMEM_SEC_STATE_LOCKED); 890 return 0; 891 892 default: 893 cmd->return_code = CXL_MBOX_CMD_RC_INPUT; 894 return -EINVAL; 895 } 896 897 return 0; 898 } 899 900 static int mock_freeze_security(struct cxl_mockmem_data *mdata, 901 struct cxl_mbox_cmd *cmd) 902 { 903 if (cmd->size_in != 0) 904 return -EINVAL; 905 906 if (cmd->size_out != 0) 907 return -EINVAL; 908 909 if (mdata->security_state & CXL_PMEM_SEC_STATE_FROZEN) 910 return 0; 911 912 mdata->security_state |= CXL_PMEM_SEC_STATE_FROZEN; 913 return 0; 914 } 915 916 static int mock_unlock_security(struct cxl_mockmem_data *mdata, 917 struct cxl_mbox_cmd *cmd) 918 { 919 if (cmd->size_in != NVDIMM_PASSPHRASE_LEN) 920 return -EINVAL; 921 922 if (cmd->size_out != 0) 923 return -EINVAL; 924 925 if (mdata->security_state & CXL_PMEM_SEC_STATE_FROZEN) { 926 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 927 return -ENXIO; 928 } 929 930 if (!(mdata->security_state & CXL_PMEM_SEC_STATE_USER_PASS_SET)) { 931 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 932 return -ENXIO; 933 } 934 935 if (mdata->security_state & CXL_PMEM_SEC_STATE_USER_PLIMIT) { 936 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 937 return -ENXIO; 938 } 939 940 if (!(mdata->security_state & CXL_PMEM_SEC_STATE_LOCKED)) { 941 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 942 return -ENXIO; 943 } 944 945 if (memcmp(cmd->payload_in, mdata->user_pass, NVDIMM_PASSPHRASE_LEN)) { 946 if (++mdata->user_limit == PASS_TRY_LIMIT) 947 mdata->security_state |= CXL_PMEM_SEC_STATE_USER_PLIMIT; 948 cmd->return_code = CXL_MBOX_CMD_RC_PASSPHRASE; 949 return -ENXIO; 950 } 951 952 mdata->user_limit = 0; 953 mdata->security_state &= ~CXL_PMEM_SEC_STATE_LOCKED; 954 return 0; 955 } 956 957 static int mock_passphrase_secure_erase(struct cxl_mockmem_data *mdata, 958 struct cxl_mbox_cmd *cmd) 959 { 960 struct cxl_pass_erase *erase; 961 962 if (cmd->size_in != sizeof(*erase)) 963 return -EINVAL; 964 965 if (cmd->size_out != 0) 966 return -EINVAL; 967 968 erase = cmd->payload_in; 969 if (mdata->security_state & CXL_PMEM_SEC_STATE_FROZEN) { 970 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 971 return -ENXIO; 972 } 973 974 if (mdata->security_state & CXL_PMEM_SEC_STATE_USER_PLIMIT && 975 erase->type == CXL_PMEM_SEC_PASS_USER) { 976 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 977 return -ENXIO; 978 } 979 980 if (mdata->security_state & CXL_PMEM_SEC_STATE_MASTER_PLIMIT && 981 erase->type == CXL_PMEM_SEC_PASS_MASTER) { 982 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 983 return -ENXIO; 984 } 985 986 switch (erase->type) { 987 case CXL_PMEM_SEC_PASS_MASTER: 988 /* 989 * The spec does not clearly define the behavior of the scenario 990 * where a master passphrase is passed in while the master 991 * passphrase is not set and user passphrase is not set. The 992 * code will take the assumption that it will behave the same 993 * as a CXL secure erase command without passphrase (0x4401). 994 */ 995 if (mdata->security_state & CXL_PMEM_SEC_STATE_MASTER_PASS_SET) { 996 if (memcmp(mdata->master_pass, erase->pass, 997 NVDIMM_PASSPHRASE_LEN)) { 998 master_plimit_check(mdata); 999 cmd->return_code = CXL_MBOX_CMD_RC_PASSPHRASE; 1000 return -ENXIO; 1001 } 1002 mdata->master_limit = 0; 1003 mdata->user_limit = 0; 1004 mdata->security_state &= ~CXL_PMEM_SEC_STATE_USER_PASS_SET; 1005 memset(mdata->user_pass, 0, NVDIMM_PASSPHRASE_LEN); 1006 mdata->security_state &= ~CXL_PMEM_SEC_STATE_LOCKED; 1007 } else { 1008 /* 1009 * CXL rev3 8.2.9.8.6.3 Disable Passphrase 1010 * When master passphrase is disabled, the device shall 1011 * return Invalid Input for the Passphrase Secure Erase 1012 * command with master passphrase. 1013 */ 1014 return -EINVAL; 1015 } 1016 /* Scramble encryption keys so that data is effectively erased */ 1017 break; 1018 case CXL_PMEM_SEC_PASS_USER: 1019 /* 1020 * The spec does not clearly define the behavior of the scenario 1021 * where a user passphrase is passed in while the user 1022 * passphrase is not set. The code will take the assumption that 1023 * it will behave the same as a CXL secure erase command without 1024 * passphrase (0x4401). 1025 */ 1026 if (mdata->security_state & CXL_PMEM_SEC_STATE_USER_PASS_SET) { 1027 if (memcmp(mdata->user_pass, erase->pass, 1028 NVDIMM_PASSPHRASE_LEN)) { 1029 user_plimit_check(mdata); 1030 cmd->return_code = CXL_MBOX_CMD_RC_PASSPHRASE; 1031 return -ENXIO; 1032 } 1033 mdata->user_limit = 0; 1034 mdata->security_state &= ~CXL_PMEM_SEC_STATE_USER_PASS_SET; 1035 memset(mdata->user_pass, 0, NVDIMM_PASSPHRASE_LEN); 1036 } 1037 1038 /* 1039 * CXL rev3 Table 8-118 1040 * If user passphrase is not set or supported by device, current 1041 * passphrase value is ignored. Will make the assumption that 1042 * the operation will proceed as secure erase w/o passphrase 1043 * since spec is not explicit. 1044 */ 1045 1046 /* Scramble encryption keys so that data is effectively erased */ 1047 break; 1048 default: 1049 return -EINVAL; 1050 } 1051 1052 return 0; 1053 } 1054 1055 static int mock_get_lsa(struct cxl_mockmem_data *mdata, 1056 struct cxl_mbox_cmd *cmd) 1057 { 1058 struct cxl_mbox_get_lsa *get_lsa = cmd->payload_in; 1059 void *lsa = mdata->lsa; 1060 u32 offset, length; 1061 1062 if (sizeof(*get_lsa) > cmd->size_in) 1063 return -EINVAL; 1064 offset = le32_to_cpu(get_lsa->offset); 1065 length = le32_to_cpu(get_lsa->length); 1066 if (offset > LSA_SIZE || length > LSA_SIZE - offset) 1067 return -EINVAL; 1068 if (length > cmd->size_out) 1069 return -EINVAL; 1070 1071 memcpy(cmd->payload_out, lsa + offset, length); 1072 return 0; 1073 } 1074 1075 static int mock_set_lsa(struct cxl_mockmem_data *mdata, 1076 struct cxl_mbox_cmd *cmd) 1077 { 1078 struct cxl_mbox_set_lsa *set_lsa = cmd->payload_in; 1079 void *lsa = mdata->lsa; 1080 u32 offset, length; 1081 1082 if (sizeof(*set_lsa) > cmd->size_in) 1083 return -EINVAL; 1084 offset = le32_to_cpu(set_lsa->offset); 1085 length = cmd->size_in - sizeof(*set_lsa); 1086 if (offset > LSA_SIZE || length > LSA_SIZE - offset) 1087 return -EINVAL; 1088 1089 memcpy(lsa + offset, &set_lsa->data[0], length); 1090 return 0; 1091 } 1092 1093 static int mock_health_info(struct cxl_mbox_cmd *cmd) 1094 { 1095 struct cxl_mbox_health_info health_info = { 1096 /* set flags for maint needed, perf degraded, hw replacement */ 1097 .health_status = 0x7, 1098 /* set media status to "All Data Lost" */ 1099 .media_status = 0x3, 1100 /* 1101 * set ext_status flags for: 1102 * ext_life_used: normal, 1103 * ext_temperature: critical, 1104 * ext_corrected_volatile: warning, 1105 * ext_corrected_persistent: normal, 1106 */ 1107 .ext_status = 0x18, 1108 .life_used = 15, 1109 .temperature = cpu_to_le16(25), 1110 .dirty_shutdowns = cpu_to_le32(10), 1111 .volatile_errors = cpu_to_le32(20), 1112 .pmem_errors = cpu_to_le32(30), 1113 }; 1114 1115 if (cmd->size_out < sizeof(health_info)) 1116 return -EINVAL; 1117 1118 memcpy(cmd->payload_out, &health_info, sizeof(health_info)); 1119 return 0; 1120 } 1121 1122 static int mock_set_shutdown_state(struct cxl_mockmem_data *mdata, 1123 struct cxl_mbox_cmd *cmd) 1124 { 1125 struct cxl_mbox_set_shutdown_state_in *ss = cmd->payload_in; 1126 1127 if (cmd->size_in != sizeof(*ss)) 1128 return -EINVAL; 1129 1130 if (cmd->size_out != 0) 1131 return -EINVAL; 1132 1133 mdata->shutdown_state = ss->state; 1134 return 0; 1135 } 1136 1137 static struct mock_poison { 1138 struct cxl_dev_state *cxlds; 1139 u64 dpa; 1140 } mock_poison_list[MOCK_INJECT_TEST_MAX]; 1141 1142 static struct cxl_mbox_poison_out * 1143 cxl_get_injected_po(struct cxl_dev_state *cxlds, u64 offset, u64 length) 1144 { 1145 struct cxl_mbox_poison_out *po; 1146 int nr_records = 0; 1147 u64 dpa; 1148 1149 po = kzalloc(struct_size(po, record, poison_inject_dev_max), GFP_KERNEL); 1150 if (!po) 1151 return NULL; 1152 1153 for (int i = 0; i < MOCK_INJECT_TEST_MAX; i++) { 1154 if (mock_poison_list[i].cxlds != cxlds) 1155 continue; 1156 if (mock_poison_list[i].dpa < offset || 1157 mock_poison_list[i].dpa > offset + length - 1) 1158 continue; 1159 1160 dpa = mock_poison_list[i].dpa + CXL_POISON_SOURCE_INJECTED; 1161 po->record[nr_records].address = cpu_to_le64(dpa); 1162 po->record[nr_records].length = cpu_to_le32(1); 1163 nr_records++; 1164 if (nr_records == poison_inject_dev_max) 1165 break; 1166 } 1167 1168 /* Always return count, even when zero */ 1169 po->count = cpu_to_le16(nr_records); 1170 1171 return po; 1172 } 1173 1174 static int mock_get_poison(struct cxl_dev_state *cxlds, 1175 struct cxl_mbox_cmd *cmd) 1176 { 1177 struct cxl_mbox_poison_in *pi = cmd->payload_in; 1178 struct cxl_mbox_poison_out *po; 1179 u64 offset = le64_to_cpu(pi->offset); 1180 u64 length = le64_to_cpu(pi->length); 1181 int nr_records; 1182 1183 po = cxl_get_injected_po(cxlds, offset, length); 1184 if (!po) 1185 return -ENOMEM; 1186 nr_records = le16_to_cpu(po->count); 1187 memcpy(cmd->payload_out, po, struct_size(po, record, nr_records)); 1188 cmd->size_out = struct_size(po, record, nr_records); 1189 kfree(po); 1190 1191 return 0; 1192 } 1193 1194 static bool mock_poison_dev_max_injected(struct cxl_dev_state *cxlds) 1195 { 1196 int count = 0; 1197 1198 for (int i = 0; i < MOCK_INJECT_TEST_MAX; i++) { 1199 if (mock_poison_list[i].cxlds == cxlds) 1200 count++; 1201 } 1202 return (count >= poison_inject_dev_max); 1203 } 1204 1205 static int mock_poison_add(struct cxl_dev_state *cxlds, u64 dpa) 1206 { 1207 /* Return EBUSY to match the CXL driver handling */ 1208 if (mock_poison_dev_max_injected(cxlds)) { 1209 dev_dbg(cxlds->dev, 1210 "Device poison injection limit has been reached: %d\n", 1211 poison_inject_dev_max); 1212 return -EBUSY; 1213 } 1214 1215 for (int i = 0; i < MOCK_INJECT_TEST_MAX; i++) { 1216 if (!mock_poison_list[i].cxlds) { 1217 mock_poison_list[i].cxlds = cxlds; 1218 mock_poison_list[i].dpa = dpa; 1219 return 0; 1220 } 1221 } 1222 dev_dbg(cxlds->dev, 1223 "Mock test poison injection limit has been reached: %d\n", 1224 MOCK_INJECT_TEST_MAX); 1225 1226 return -ENXIO; 1227 } 1228 1229 static bool mock_poison_found(struct cxl_dev_state *cxlds, u64 dpa) 1230 { 1231 for (int i = 0; i < MOCK_INJECT_TEST_MAX; i++) { 1232 if (mock_poison_list[i].cxlds == cxlds && 1233 mock_poison_list[i].dpa == dpa) 1234 return true; 1235 } 1236 return false; 1237 } 1238 1239 static int mock_inject_poison(struct cxl_dev_state *cxlds, 1240 struct cxl_mbox_cmd *cmd) 1241 { 1242 struct cxl_mbox_inject_poison *pi = cmd->payload_in; 1243 u64 dpa = le64_to_cpu(pi->address); 1244 1245 if (mock_poison_found(cxlds, dpa)) { 1246 /* Not an error to inject poison if already poisoned */ 1247 dev_dbg(cxlds->dev, "DPA: 0x%llx already poisoned\n", dpa); 1248 return 0; 1249 } 1250 1251 return mock_poison_add(cxlds, dpa); 1252 } 1253 1254 static bool mock_poison_del(struct cxl_dev_state *cxlds, u64 dpa) 1255 { 1256 for (int i = 0; i < MOCK_INJECT_TEST_MAX; i++) { 1257 if (mock_poison_list[i].cxlds == cxlds && 1258 mock_poison_list[i].dpa == dpa) { 1259 mock_poison_list[i].cxlds = NULL; 1260 return true; 1261 } 1262 } 1263 return false; 1264 } 1265 1266 static int mock_clear_poison(struct cxl_dev_state *cxlds, 1267 struct cxl_mbox_cmd *cmd) 1268 { 1269 struct cxl_mbox_clear_poison *pi = cmd->payload_in; 1270 u64 dpa = le64_to_cpu(pi->address); 1271 1272 /* 1273 * A real CXL device will write pi->write_data to the address 1274 * being cleared. In this mock, just delete this address from 1275 * the mock poison list. 1276 */ 1277 if (!mock_poison_del(cxlds, dpa)) 1278 dev_dbg(cxlds->dev, "DPA: 0x%llx not in poison list\n", dpa); 1279 1280 return 0; 1281 } 1282 1283 static bool mock_poison_list_empty(void) 1284 { 1285 for (int i = 0; i < MOCK_INJECT_TEST_MAX; i++) { 1286 if (mock_poison_list[i].cxlds) 1287 return false; 1288 } 1289 return true; 1290 } 1291 1292 static ssize_t poison_inject_max_show(struct device_driver *drv, char *buf) 1293 { 1294 return sysfs_emit(buf, "%u\n", poison_inject_dev_max); 1295 } 1296 1297 static ssize_t poison_inject_max_store(struct device_driver *drv, 1298 const char *buf, size_t len) 1299 { 1300 int val; 1301 1302 if (kstrtoint(buf, 0, &val) < 0) 1303 return -EINVAL; 1304 1305 if (!mock_poison_list_empty()) 1306 return -EBUSY; 1307 1308 if (val <= MOCK_INJECT_TEST_MAX) 1309 poison_inject_dev_max = val; 1310 else 1311 return -EINVAL; 1312 1313 return len; 1314 } 1315 1316 static DRIVER_ATTR_RW(poison_inject_max); 1317 1318 static struct attribute *cxl_mock_mem_core_attrs[] = { 1319 &driver_attr_poison_inject_max.attr, 1320 NULL 1321 }; 1322 ATTRIBUTE_GROUPS(cxl_mock_mem_core); 1323 1324 static int mock_fw_info(struct cxl_mockmem_data *mdata, 1325 struct cxl_mbox_cmd *cmd) 1326 { 1327 struct cxl_mbox_get_fw_info fw_info = { 1328 .num_slots = FW_SLOTS, 1329 .slot_info = (mdata->fw_slot & 0x7) | 1330 ((mdata->fw_staged & 0x7) << 3), 1331 .activation_cap = 0, 1332 }; 1333 1334 strcpy(fw_info.slot_1_revision, "cxl_test_fw_001"); 1335 strcpy(fw_info.slot_2_revision, "cxl_test_fw_002"); 1336 strcpy(fw_info.slot_3_revision, "cxl_test_fw_003"); 1337 strcpy(fw_info.slot_4_revision, ""); 1338 1339 if (cmd->size_out < sizeof(fw_info)) 1340 return -EINVAL; 1341 1342 memcpy(cmd->payload_out, &fw_info, sizeof(fw_info)); 1343 return 0; 1344 } 1345 1346 static int mock_transfer_fw(struct cxl_mockmem_data *mdata, 1347 struct cxl_mbox_cmd *cmd) 1348 { 1349 struct cxl_mbox_transfer_fw *transfer; 1350 void *fw = mdata->fw; 1351 size_t offset, length; 1352 1353 if (cmd->size_in < sizeof(*transfer)) 1354 return -EINVAL; 1355 1356 transfer = cmd->payload_in; 1357 offset = le32_to_cpu(transfer->offset) * CXL_FW_TRANSFER_ALIGNMENT; 1358 length = cmd->size_in - sizeof(*transfer); 1359 if (offset + length > FW_SIZE) 1360 return -EINVAL; 1361 1362 switch (transfer->action) { 1363 case CXL_FW_TRANSFER_ACTION_FULL: 1364 if (offset != 0) 1365 return -EINVAL; 1366 fallthrough; 1367 case CXL_FW_TRANSFER_ACTION_END: 1368 if (transfer->slot == 0 || transfer->slot > FW_SLOTS) 1369 return -EINVAL; 1370 mdata->fw_size = offset + length; 1371 break; 1372 case CXL_FW_TRANSFER_ACTION_INITIATE: 1373 case CXL_FW_TRANSFER_ACTION_CONTINUE: 1374 break; 1375 case CXL_FW_TRANSFER_ACTION_ABORT: 1376 return 0; 1377 default: 1378 return -EINVAL; 1379 } 1380 1381 memcpy(fw + offset, transfer->data, length); 1382 usleep_range(1500, 2000); 1383 return 0; 1384 } 1385 1386 static int mock_activate_fw(struct cxl_mockmem_data *mdata, 1387 struct cxl_mbox_cmd *cmd) 1388 { 1389 struct cxl_mbox_activate_fw *activate = cmd->payload_in; 1390 1391 if (activate->slot == 0 || activate->slot > FW_SLOTS) 1392 return -EINVAL; 1393 1394 switch (activate->action) { 1395 case CXL_FW_ACTIVATE_ONLINE: 1396 mdata->fw_slot = activate->slot; 1397 mdata->fw_staged = 0; 1398 return 0; 1399 case CXL_FW_ACTIVATE_OFFLINE: 1400 mdata->fw_staged = activate->slot; 1401 return 0; 1402 } 1403 1404 return -EINVAL; 1405 } 1406 1407 #define CXL_VENDOR_FEATURE_TEST \ 1408 UUID_INIT(0xffffffff, 0xffff, 0xffff, 0xff, 0xff, 0xff, 0xff, 0xff, \ 1409 0xff, 0xff, 0xff) 1410 1411 static void fill_feature_vendor_test(struct cxl_feat_entry *feat) 1412 { 1413 feat->uuid = CXL_VENDOR_FEATURE_TEST; 1414 feat->id = 0; 1415 feat->get_feat_size = cpu_to_le16(0x4); 1416 feat->set_feat_size = cpu_to_le16(0x4); 1417 feat->flags = cpu_to_le32(CXL_FEATURE_F_CHANGEABLE | 1418 CXL_FEATURE_F_DEFAULT_SEL | 1419 CXL_FEATURE_F_SAVED_SEL); 1420 feat->get_feat_ver = 1; 1421 feat->set_feat_ver = 1; 1422 feat->effects = cpu_to_le16(CXL_CMD_CONFIG_CHANGE_COLD_RESET | 1423 CXL_CMD_EFFECTS_VALID); 1424 } 1425 1426 #define MAX_CXL_TEST_FEATS 1 1427 1428 static int mock_get_test_feature(struct cxl_mockmem_data *mdata, 1429 struct cxl_mbox_cmd *cmd) 1430 { 1431 struct vendor_test_feat *output = cmd->payload_out; 1432 struct cxl_mbox_get_feat_in *input; 1433 u16 offset; 1434 u16 count; 1435 u8 *ptr; 1436 1437 if (cmd->size_in < sizeof(*input)) 1438 return -EINVAL; 1439 1440 input = cmd->payload_in; 1441 offset = le16_to_cpu(input->offset); 1442 count = le16_to_cpu(input->count); 1443 1444 if (offset > sizeof(*output)) { 1445 cmd->return_code = CXL_MBOX_CMD_RC_INPUT; 1446 return -EINVAL; 1447 } 1448 1449 if (offset + count > sizeof(*output)) { 1450 cmd->return_code = CXL_MBOX_CMD_RC_INPUT; 1451 return -EINVAL; 1452 } 1453 1454 ptr = (u8 *)&mdata->test_feat + offset; 1455 memcpy((u8 *)output + offset, ptr, count); 1456 1457 return 0; 1458 } 1459 1460 static int mock_get_feature(struct cxl_mockmem_data *mdata, 1461 struct cxl_mbox_cmd *cmd) 1462 { 1463 struct cxl_mbox_get_feat_in *input = cmd->payload_in; 1464 1465 if (uuid_equal(&input->uuid, &CXL_VENDOR_FEATURE_TEST)) 1466 return mock_get_test_feature(mdata, cmd); 1467 1468 cmd->return_code = CXL_MBOX_CMD_RC_UNSUPPORTED; 1469 1470 return -EOPNOTSUPP; 1471 } 1472 1473 static int mock_set_test_feature(struct cxl_mockmem_data *mdata, 1474 struct cxl_mbox_cmd *cmd) 1475 { 1476 struct cxl_mbox_set_feat_in *input = cmd->payload_in; 1477 struct vendor_test_feat *test = 1478 (struct vendor_test_feat *)input->feat_data; 1479 u32 action; 1480 1481 action = FIELD_GET(CXL_SET_FEAT_FLAG_DATA_TRANSFER_MASK, 1482 le32_to_cpu(input->hdr.flags)); 1483 /* 1484 * While it is spec compliant to support other set actions, it is not 1485 * necessary to add the complication in the emulation currently. Reject 1486 * anything besides full xfer. 1487 */ 1488 if (action != CXL_SET_FEAT_FLAG_FULL_DATA_TRANSFER) { 1489 cmd->return_code = CXL_MBOX_CMD_RC_INPUT; 1490 return -EINVAL; 1491 } 1492 1493 /* Offset should be reserved when doing full transfer */ 1494 if (input->hdr.offset) { 1495 cmd->return_code = CXL_MBOX_CMD_RC_INPUT; 1496 return -EINVAL; 1497 } 1498 1499 memcpy(&mdata->test_feat.data, &test->data, sizeof(u32)); 1500 1501 return 0; 1502 } 1503 1504 static int mock_set_feature(struct cxl_mockmem_data *mdata, 1505 struct cxl_mbox_cmd *cmd) 1506 { 1507 struct cxl_mbox_set_feat_in *input = cmd->payload_in; 1508 1509 if (uuid_equal(&input->hdr.uuid, &CXL_VENDOR_FEATURE_TEST)) 1510 return mock_set_test_feature(mdata, cmd); 1511 1512 cmd->return_code = CXL_MBOX_CMD_RC_UNSUPPORTED; 1513 1514 return -EOPNOTSUPP; 1515 } 1516 1517 static int mock_get_supported_features(struct cxl_mockmem_data *mdata, 1518 struct cxl_mbox_cmd *cmd) 1519 { 1520 struct cxl_mbox_get_sup_feats_in *in = cmd->payload_in; 1521 struct cxl_mbox_get_sup_feats_out *out = cmd->payload_out; 1522 struct cxl_feat_entry *feat; 1523 u16 start_idx, count; 1524 1525 if (cmd->size_out < sizeof(*out)) { 1526 cmd->return_code = CXL_MBOX_CMD_RC_PAYLOADLEN; 1527 return -EINVAL; 1528 } 1529 1530 /* 1531 * Current emulation only supports 1 feature 1532 */ 1533 start_idx = le16_to_cpu(in->start_idx); 1534 if (start_idx != 0) { 1535 cmd->return_code = CXL_MBOX_CMD_RC_INPUT; 1536 return -EINVAL; 1537 } 1538 1539 count = le16_to_cpu(in->count); 1540 if (count < struct_size(out, ents, 0)) { 1541 cmd->return_code = CXL_MBOX_CMD_RC_PAYLOADLEN; 1542 return -EINVAL; 1543 } 1544 1545 out->supported_feats = cpu_to_le16(MAX_CXL_TEST_FEATS); 1546 cmd->return_code = 0; 1547 if (count < struct_size(out, ents, MAX_CXL_TEST_FEATS)) { 1548 out->num_entries = 0; 1549 return 0; 1550 } 1551 1552 out->num_entries = cpu_to_le16(MAX_CXL_TEST_FEATS); 1553 feat = out->ents; 1554 fill_feature_vendor_test(feat); 1555 1556 return 0; 1557 } 1558 1559 static int cxl_mock_mbox_send(struct cxl_mailbox *cxl_mbox, 1560 struct cxl_mbox_cmd *cmd) 1561 { 1562 struct device *dev = cxl_mbox->host; 1563 struct cxl_mockmem_data *mdata = dev_get_drvdata(dev); 1564 struct cxl_memdev_state *mds = mdata->mds; 1565 struct cxl_dev_state *cxlds = &mds->cxlds; 1566 int rc = -EIO; 1567 1568 switch (cmd->opcode) { 1569 case CXL_MBOX_OP_SET_TIMESTAMP: 1570 rc = mock_set_timestamp(cxlds, cmd); 1571 break; 1572 case CXL_MBOX_OP_GET_SUPPORTED_LOGS: 1573 rc = mock_gsl(cmd); 1574 break; 1575 case CXL_MBOX_OP_GET_LOG: 1576 rc = mock_get_log(mds, cmd); 1577 break; 1578 case CXL_MBOX_OP_IDENTIFY: 1579 if (cxlds->rcd) 1580 rc = mock_rcd_id(cmd); 1581 else 1582 rc = mock_id(cmd); 1583 break; 1584 case CXL_MBOX_OP_GET_LSA: 1585 rc = mock_get_lsa(mdata, cmd); 1586 break; 1587 case CXL_MBOX_OP_GET_PARTITION_INFO: 1588 rc = mock_partition_info(cmd); 1589 break; 1590 case CXL_MBOX_OP_GET_EVENT_RECORD: 1591 rc = mock_get_event(dev, cmd); 1592 break; 1593 case CXL_MBOX_OP_CLEAR_EVENT_RECORD: 1594 rc = mock_clear_event(dev, cmd); 1595 break; 1596 case CXL_MBOX_OP_SET_LSA: 1597 rc = mock_set_lsa(mdata, cmd); 1598 break; 1599 case CXL_MBOX_OP_GET_HEALTH_INFO: 1600 rc = mock_health_info(cmd); 1601 break; 1602 case CXL_MBOX_OP_SANITIZE: 1603 rc = mock_sanitize(mdata, cmd); 1604 break; 1605 case CXL_MBOX_OP_SECURE_ERASE: 1606 rc = mock_secure_erase(mdata, cmd); 1607 break; 1608 case CXL_MBOX_OP_GET_SECURITY_STATE: 1609 rc = mock_get_security_state(mdata, cmd); 1610 break; 1611 case CXL_MBOX_OP_SET_PASSPHRASE: 1612 rc = mock_set_passphrase(mdata, cmd); 1613 break; 1614 case CXL_MBOX_OP_DISABLE_PASSPHRASE: 1615 rc = mock_disable_passphrase(mdata, cmd); 1616 break; 1617 case CXL_MBOX_OP_FREEZE_SECURITY: 1618 rc = mock_freeze_security(mdata, cmd); 1619 break; 1620 case CXL_MBOX_OP_UNLOCK: 1621 rc = mock_unlock_security(mdata, cmd); 1622 break; 1623 case CXL_MBOX_OP_PASSPHRASE_SECURE_ERASE: 1624 rc = mock_passphrase_secure_erase(mdata, cmd); 1625 break; 1626 case CXL_MBOX_OP_SET_SHUTDOWN_STATE: 1627 rc = mock_set_shutdown_state(mdata, cmd); 1628 break; 1629 case CXL_MBOX_OP_GET_POISON: 1630 rc = mock_get_poison(cxlds, cmd); 1631 break; 1632 case CXL_MBOX_OP_INJECT_POISON: 1633 rc = mock_inject_poison(cxlds, cmd); 1634 break; 1635 case CXL_MBOX_OP_CLEAR_POISON: 1636 rc = mock_clear_poison(cxlds, cmd); 1637 break; 1638 case CXL_MBOX_OP_GET_FW_INFO: 1639 rc = mock_fw_info(mdata, cmd); 1640 break; 1641 case CXL_MBOX_OP_TRANSFER_FW: 1642 rc = mock_transfer_fw(mdata, cmd); 1643 break; 1644 case CXL_MBOX_OP_ACTIVATE_FW: 1645 rc = mock_activate_fw(mdata, cmd); 1646 break; 1647 case CXL_MBOX_OP_GET_SUPPORTED_FEATURES: 1648 rc = mock_get_supported_features(mdata, cmd); 1649 break; 1650 case CXL_MBOX_OP_GET_FEATURE: 1651 rc = mock_get_feature(mdata, cmd); 1652 break; 1653 case CXL_MBOX_OP_SET_FEATURE: 1654 rc = mock_set_feature(mdata, cmd); 1655 break; 1656 default: 1657 break; 1658 } 1659 1660 dev_dbg(dev, "opcode: %#x sz_in: %zd sz_out: %zd rc: %d\n", cmd->opcode, 1661 cmd->size_in, cmd->size_out, rc); 1662 1663 return rc; 1664 } 1665 1666 static void label_area_release(void *lsa) 1667 { 1668 vfree(lsa); 1669 } 1670 1671 static void fw_buf_release(void *buf) 1672 { 1673 vfree(buf); 1674 } 1675 1676 static bool is_rcd(struct platform_device *pdev) 1677 { 1678 const struct platform_device_id *id = platform_get_device_id(pdev); 1679 1680 return !!id->driver_data; 1681 } 1682 1683 static ssize_t event_trigger_store(struct device *dev, 1684 struct device_attribute *attr, 1685 const char *buf, size_t count) 1686 { 1687 cxl_mock_event_trigger(dev); 1688 return count; 1689 } 1690 static DEVICE_ATTR_WO(event_trigger); 1691 1692 static int cxl_mock_mailbox_create(struct cxl_dev_state *cxlds) 1693 { 1694 int rc; 1695 1696 rc = cxl_mailbox_init(&cxlds->cxl_mbox, cxlds->dev); 1697 if (rc) 1698 return rc; 1699 1700 return 0; 1701 } 1702 1703 static void cxl_mock_test_feat_init(struct cxl_mockmem_data *mdata) 1704 { 1705 mdata->test_feat.data = cpu_to_le32(0xdeadbeef); 1706 } 1707 1708 static int cxl_mock_mem_probe(struct platform_device *pdev) 1709 { 1710 struct device *dev = &pdev->dev; 1711 struct cxl_memdev *cxlmd; 1712 struct cxl_memdev_state *mds; 1713 struct cxl_dev_state *cxlds; 1714 struct cxl_mockmem_data *mdata; 1715 struct cxl_mailbox *cxl_mbox; 1716 struct cxl_dpa_info range_info = { 0 }; 1717 int rc; 1718 1719 /* Increase async probe race window */ 1720 usleep_range(500*1000, 1000*1000); 1721 1722 mdata = devm_kzalloc(dev, sizeof(*mdata), GFP_KERNEL); 1723 if (!mdata) 1724 return -ENOMEM; 1725 dev_set_drvdata(dev, mdata); 1726 1727 mdata->lsa = vzalloc(LSA_SIZE); 1728 if (!mdata->lsa) 1729 return -ENOMEM; 1730 mdata->fw = vmalloc(FW_SIZE); 1731 if (!mdata->fw) 1732 return -ENOMEM; 1733 mdata->fw_slot = 2; 1734 1735 rc = devm_add_action_or_reset(dev, label_area_release, mdata->lsa); 1736 if (rc) 1737 return rc; 1738 1739 rc = devm_add_action_or_reset(dev, fw_buf_release, mdata->fw); 1740 if (rc) 1741 return rc; 1742 1743 mds = cxl_memdev_state_create(dev, pdev->id + 1, 0); 1744 if (IS_ERR(mds)) 1745 return PTR_ERR(mds); 1746 1747 cxlds = &mds->cxlds; 1748 rc = cxl_mock_mailbox_create(cxlds); 1749 if (rc) 1750 return rc; 1751 1752 cxl_mbox = &mds->cxlds.cxl_mbox; 1753 mdata->mds = mds; 1754 cxl_mbox->mbox_send = cxl_mock_mbox_send; 1755 cxl_mbox->payload_size = SZ_4K; 1756 mds->event.buf = (struct cxl_get_event_payload *) mdata->event_buf; 1757 INIT_DELAYED_WORK(&mds->security.poll_dwork, cxl_mockmem_sanitize_work); 1758 1759 if (is_rcd(pdev)) 1760 cxlds->rcd = true; 1761 1762 rc = cxl_enumerate_cmds(mds); 1763 if (rc) 1764 return rc; 1765 1766 rc = cxl_poison_state_init(mds); 1767 if (rc) 1768 return rc; 1769 1770 rc = cxl_set_timestamp(mds); 1771 if (rc) 1772 return rc; 1773 1774 cxlds->media_ready = true; 1775 rc = cxl_dev_state_identify(mds); 1776 if (rc) 1777 return rc; 1778 1779 rc = cxl_mem_dpa_fetch(mds, &range_info); 1780 if (rc) 1781 return rc; 1782 1783 rc = cxl_dpa_setup(cxlds, &range_info); 1784 if (rc) 1785 return rc; 1786 1787 rc = devm_cxl_setup_features(cxlds); 1788 if (rc) 1789 dev_dbg(dev, "No CXL Features discovered\n"); 1790 1791 cxl_mock_add_event_logs(&mdata->mes); 1792 1793 cxlmd = devm_cxl_add_classdev(cxlds); 1794 if (IS_ERR(cxlmd)) 1795 return PTR_ERR(cxlmd); 1796 1797 rc = devm_cxl_setup_fw_upload(&pdev->dev, mds); 1798 if (rc) 1799 return rc; 1800 1801 rc = devm_cxl_sanitize_setup_notifier(&pdev->dev, cxlmd); 1802 if (rc) 1803 return rc; 1804 1805 rc = devm_cxl_setup_fwctl(&pdev->dev, cxlmd); 1806 if (rc) 1807 dev_dbg(dev, "No CXL FWCTL setup\n"); 1808 1809 cxl_mem_get_event_records(mds, CXLDEV_EVENT_STATUS_ALL); 1810 cxl_mock_test_feat_init(mdata); 1811 1812 return 0; 1813 } 1814 1815 static ssize_t security_lock_show(struct device *dev, 1816 struct device_attribute *attr, char *buf) 1817 { 1818 struct cxl_mockmem_data *mdata = dev_get_drvdata(dev); 1819 1820 return sysfs_emit(buf, "%u\n", 1821 !!(mdata->security_state & CXL_PMEM_SEC_STATE_LOCKED)); 1822 } 1823 1824 static ssize_t security_lock_store(struct device *dev, struct device_attribute *attr, 1825 const char *buf, size_t count) 1826 { 1827 struct cxl_mockmem_data *mdata = dev_get_drvdata(dev); 1828 u32 mask = CXL_PMEM_SEC_STATE_FROZEN | CXL_PMEM_SEC_STATE_USER_PLIMIT | 1829 CXL_PMEM_SEC_STATE_MASTER_PLIMIT; 1830 int val; 1831 1832 if (kstrtoint(buf, 0, &val) < 0) 1833 return -EINVAL; 1834 1835 if (val == 1) { 1836 if (!(mdata->security_state & CXL_PMEM_SEC_STATE_USER_PASS_SET)) 1837 return -ENXIO; 1838 mdata->security_state |= CXL_PMEM_SEC_STATE_LOCKED; 1839 mdata->security_state &= ~mask; 1840 } else { 1841 return -EINVAL; 1842 } 1843 return count; 1844 } 1845 1846 static DEVICE_ATTR_RW(security_lock); 1847 1848 static ssize_t fw_buf_checksum_show(struct device *dev, 1849 struct device_attribute *attr, char *buf) 1850 { 1851 struct cxl_mockmem_data *mdata = dev_get_drvdata(dev); 1852 u8 hash[SHA256_DIGEST_SIZE]; 1853 1854 sha256(mdata->fw, mdata->fw_size, hash); 1855 1856 return sysfs_emit(buf, "%*phN\n", SHA256_DIGEST_SIZE, hash); 1857 } 1858 1859 static DEVICE_ATTR_RO(fw_buf_checksum); 1860 1861 static ssize_t sanitize_timeout_show(struct device *dev, 1862 struct device_attribute *attr, char *buf) 1863 { 1864 struct cxl_mockmem_data *mdata = dev_get_drvdata(dev); 1865 1866 return sysfs_emit(buf, "%lu\n", mdata->sanitize_timeout); 1867 } 1868 1869 static ssize_t sanitize_timeout_store(struct device *dev, 1870 struct device_attribute *attr, 1871 const char *buf, size_t count) 1872 { 1873 struct cxl_mockmem_data *mdata = dev_get_drvdata(dev); 1874 unsigned long val; 1875 int rc; 1876 1877 rc = kstrtoul(buf, 0, &val); 1878 if (rc) 1879 return rc; 1880 1881 mdata->sanitize_timeout = val; 1882 1883 return count; 1884 } 1885 1886 static DEVICE_ATTR_RW(sanitize_timeout); 1887 1888 static struct attribute *cxl_mock_mem_attrs[] = { 1889 &dev_attr_security_lock.attr, 1890 &dev_attr_event_trigger.attr, 1891 &dev_attr_fw_buf_checksum.attr, 1892 &dev_attr_sanitize_timeout.attr, 1893 NULL 1894 }; 1895 ATTRIBUTE_GROUPS(cxl_mock_mem); 1896 1897 static const struct platform_device_id cxl_mock_mem_ids[] = { 1898 { .name = "cxl_mem", 0 }, 1899 { .name = "cxl_rcd", 1 }, 1900 { }, 1901 }; 1902 MODULE_DEVICE_TABLE(platform, cxl_mock_mem_ids); 1903 1904 static struct platform_driver cxl_mock_mem_driver = { 1905 .probe = cxl_mock_mem_probe, 1906 .id_table = cxl_mock_mem_ids, 1907 .driver = { 1908 .name = KBUILD_MODNAME, 1909 .dev_groups = cxl_mock_mem_groups, 1910 .groups = cxl_mock_mem_core_groups, 1911 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1912 }, 1913 }; 1914 1915 module_platform_driver(cxl_mock_mem_driver); 1916 MODULE_LICENSE("GPL v2"); 1917 MODULE_DESCRIPTION("cxl_test: mem device mock module"); 1918 MODULE_IMPORT_NS("CXL"); 1919