1 /*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include "amdgpu.h"
25 #include "mmhub_v4_1_0.h"
26
27 #include "mmhub/mmhub_4_1_0_offset.h"
28 #include "mmhub/mmhub_4_1_0_sh_mask.h"
29
30 #include "soc15_common.h"
31 #include "soc24_enum.h"
32
33 #define regMMVM_L2_CNTL3_DEFAULT 0x80100007
34 #define regMMVM_L2_CNTL4_DEFAULT 0x000000c1
35 #define regMMVM_L2_CNTL5_DEFAULT 0x00003fe0
36
37 static const char *mmhub_client_ids_v4_1_0[][2] = {
38 [0][0] = "VMC",
39 [4][0] = "DCEDMC",
40 [6][0] = "MP0",
41 [7][0] = "MP1",
42 [8][0] = "MPIO",
43 [16][0] = "LSDMA",
44 [17][0] = "JPEG",
45 [19][0] = "VCNU",
46 [22][0] = "VSCH",
47 [23][0] = "HDP",
48 [32+23][0] = "VCNRD",
49 [3][1] = "DCEDWB",
50 [4][1] = "DCEDMC",
51 [6][1] = "MP0",
52 [7][1] = "MP1",
53 [8][1] = "MPIO",
54 [10][1] = "DBGU0",
55 [11][1] = "DBGU1",
56 [12][1] = "DBGUNBIO",
57 [14][1] = "XDP",
58 [15][1] = "OSSSYS",
59 [16][1] = "LSDMA",
60 [17][1] = "JPEG",
61 [18][1] = "VCNWR",
62 [19][1] = "VCNU",
63 [22][1] = "VSCH",
64 [23][1] = "HDP",
65 };
66
mmhub_v4_1_0_get_invalidate_req(unsigned int vmid,uint32_t flush_type)67 static uint32_t mmhub_v4_1_0_get_invalidate_req(unsigned int vmid,
68 uint32_t flush_type)
69 {
70 u32 req = 0;
71
72 /* invalidate using legacy mode on vmid*/
73 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
74 PER_VMID_INVALIDATE_REQ, 1 << vmid);
75 /* Only use legacy inv on mmhub side */
76 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
77 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
78 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
79 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
80 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
81 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
82 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
83 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
84
85 return req;
86 }
87
88 static void
mmhub_v4_1_0_print_l2_protection_fault_status(struct amdgpu_device * adev,uint32_t status)89 mmhub_v4_1_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
90 uint32_t status)
91 {
92 uint32_t cid, rw;
93 const char *mmhub_cid;
94
95 cid = REG_GET_FIELD(status,
96 MMVM_L2_PROTECTION_FAULT_STATUS_LO32, CID);
97 rw = REG_GET_FIELD(status,
98 MMVM_L2_PROTECTION_FAULT_STATUS_LO32, RW);
99
100 dev_err(adev->dev,
101 "MMVM_L2_PROTECTION_FAULT_STATUS_LO32:0x%08X\n",
102 status);
103 mmhub_cid = amdgpu_mmhub_client_name(&adev->mmhub, cid, rw);
104 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
105 mmhub_cid ? mmhub_cid : "unknown", cid);
106 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
107 REG_GET_FIELD(status,
108 MMVM_L2_PROTECTION_FAULT_STATUS_LO32, MORE_FAULTS));
109 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
110 REG_GET_FIELD(status,
111 MMVM_L2_PROTECTION_FAULT_STATUS_LO32, WALKER_ERROR));
112 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
113 REG_GET_FIELD(status,
114 MMVM_L2_PROTECTION_FAULT_STATUS_LO32, PERMISSION_FAULTS));
115 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
116 REG_GET_FIELD(status,
117 MMVM_L2_PROTECTION_FAULT_STATUS_LO32, MAPPING_ERROR));
118 dev_err(adev->dev, "\t RW: 0x%x\n", rw);
119 }
120
mmhub_v4_1_0_setup_vm_pt_regs(struct amdgpu_device * adev,uint32_t vmid,uint64_t page_table_base)121 static void mmhub_v4_1_0_setup_vm_pt_regs(struct amdgpu_device *adev,
122 uint32_t vmid, uint64_t page_table_base)
123 {
124 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
125
126 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
127 hub->ctx_addr_distance * vmid,
128 lower_32_bits(page_table_base));
129
130 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
131 hub->ctx_addr_distance * vmid,
132 upper_32_bits(page_table_base));
133 }
134
mmhub_v4_1_0_init_gart_aperture_regs(struct amdgpu_device * adev)135 static void mmhub_v4_1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
136 {
137 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
138
139 mmhub_v4_1_0_setup_vm_pt_regs(adev, 0, pt_base);
140
141 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
142 (u32)(adev->gmc.gart_start >> 12));
143 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
144 (u32)(adev->gmc.gart_start >> 44));
145
146 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
147 (u32)(adev->gmc.gart_end >> 12));
148 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
149 (u32)(adev->gmc.gart_end >> 44));
150 }
151
mmhub_v4_1_0_init_system_aperture_regs(struct amdgpu_device * adev)152 static void mmhub_v4_1_0_init_system_aperture_regs(struct amdgpu_device *adev)
153 {
154 uint64_t value;
155 uint32_t tmp;
156
157 /*
158 * the new L1 policy will block SRIOV guest from writing
159 * these regs, and they will be programed at host.
160 * so skip programing these regs.
161 */
162 if (amdgpu_sriov_vf(adev))
163 return;
164
165 /* Program the AGP BAR */
166 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0);
167 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
168 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
169
170 /* Program the system aperture low logical page number. */
171 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
172 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
173 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
174 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
175
176 /* Set default page address. */
177 value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start +
178 adev->vm_manager.vram_base_offset;
179 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
180 (u32)(value >> 12));
181 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
182 (u32)(value >> 44));
183
184 /* Program "protection fault". */
185 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
186 (u32)(adev->dummy_page_addr >> 12));
187 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
188 (u32)((u64)adev->dummy_page_addr >> 44));
189
190 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);
191 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
192 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
193 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
194 }
195
mmhub_v4_1_0_init_tlb_regs(struct amdgpu_device * adev)196 static void mmhub_v4_1_0_init_tlb_regs(struct amdgpu_device *adev)
197 {
198 uint32_t tmp;
199
200 /* Setup TLB control */
201 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
202
203 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
204 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
205 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
206 ENABLE_ADVANCED_DRIVER_MODEL, 1);
207 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
208 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
209 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
210 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
211 MTYPE, MTYPE_UC); /* UC, uncached */
212
213 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
214 }
215
mmhub_v4_1_0_init_cache_regs(struct amdgpu_device * adev)216 static void mmhub_v4_1_0_init_cache_regs(struct amdgpu_device *adev)
217 {
218 uint32_t tmp;
219
220 /* These registers are not accessible to VF-SRIOV.
221 * The PF will program them instead.
222 */
223 if (amdgpu_sriov_vf(adev))
224 return;
225
226 /* Setup L2 cache */
227 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
228 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
229 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
230 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
231 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
232 /* XXX for emulation, Refer to closed source code.*/
233 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
234 0);
235 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
236 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
237 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
238 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
239
240 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2);
241 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
242 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
243 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp);
244
245 tmp = regMMVM_L2_CNTL3_DEFAULT;
246 if (adev->gmc.translate_further) {
247 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
248 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
249 L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
250 } else {
251 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
252 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
253 L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
254 }
255 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp);
256
257 tmp = regMMVM_L2_CNTL4_DEFAULT;
258 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
259 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
260 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp);
261
262 tmp = regMMVM_L2_CNTL5_DEFAULT;
263 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
264 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp);
265 }
266
mmhub_v4_1_0_enable_system_domain(struct amdgpu_device * adev)267 static void mmhub_v4_1_0_enable_system_domain(struct amdgpu_device *adev)
268 {
269 uint32_t tmp;
270
271 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
272 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
273 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
274 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
275 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
276 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp);
277 }
278
mmhub_v4_1_0_disable_identity_aperture(struct amdgpu_device * adev)279 static void mmhub_v4_1_0_disable_identity_aperture(struct amdgpu_device *adev)
280 {
281 /* These registers are not accessible to VF-SRIOV.
282 * The PF will program them instead.
283 */
284 if (amdgpu_sriov_vf(adev))
285 return;
286
287 WREG32_SOC15(MMHUB, 0,
288 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
289 0xFFFFFFFF);
290 WREG32_SOC15(MMHUB, 0,
291 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
292 0x0000000F);
293
294 WREG32_SOC15(MMHUB, 0,
295 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
296 WREG32_SOC15(MMHUB, 0,
297 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
298
299 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
300 0);
301 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
302 0);
303 }
304
mmhub_v4_1_0_setup_vmid_config(struct amdgpu_device * adev)305 static void mmhub_v4_1_0_setup_vmid_config(struct amdgpu_device *adev)
306 {
307 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
308 int i;
309 uint32_t tmp;
310
311 for (i = 0; i <= 14; i++) {
312 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i);
313 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
314 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
315 adev->vm_manager.num_level);
316 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
317 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
318 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
319 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
320 1);
321 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
322 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
323 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
324 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
325 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
326 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
327 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
328 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
329 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
330 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
331 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
332 PAGE_TABLE_BLOCK_SIZE,
333 adev->vm_manager.block_size - 9);
334 /* Send no-retry XNACK on fault to suppress VM fault storm. */
335 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
336 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
337 !amdgpu_noretry);
338 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL,
339 i * hub->ctx_distance, tmp);
340 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
341 i * hub->ctx_addr_distance, 0);
342 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
343 i * hub->ctx_addr_distance, 0);
344 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
345 i * hub->ctx_addr_distance,
346 lower_32_bits(adev->vm_manager.max_pfn - 1));
347 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
348 i * hub->ctx_addr_distance,
349 upper_32_bits(adev->vm_manager.max_pfn - 1));
350 }
351
352 hub->vm_cntx_cntl = tmp;
353 }
354
mmhub_v4_1_0_program_invalidation(struct amdgpu_device * adev)355 static void mmhub_v4_1_0_program_invalidation(struct amdgpu_device *adev)
356 {
357 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
358 unsigned i;
359
360 for (i = 0; i < 18; ++i) {
361 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
362 i * hub->eng_addr_distance, 0xffffffff);
363 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
364 i * hub->eng_addr_distance, 0x1f);
365 }
366 }
367
mmhub_v4_1_0_gart_enable(struct amdgpu_device * adev)368 static int mmhub_v4_1_0_gart_enable(struct amdgpu_device *adev)
369 {
370 /* GART Enable. */
371 mmhub_v4_1_0_init_gart_aperture_regs(adev);
372 mmhub_v4_1_0_init_system_aperture_regs(adev);
373 mmhub_v4_1_0_init_tlb_regs(adev);
374 mmhub_v4_1_0_init_cache_regs(adev);
375
376 mmhub_v4_1_0_enable_system_domain(adev);
377 mmhub_v4_1_0_disable_identity_aperture(adev);
378 mmhub_v4_1_0_setup_vmid_config(adev);
379 mmhub_v4_1_0_program_invalidation(adev);
380
381 return 0;
382 }
383
mmhub_v4_1_0_gart_disable(struct amdgpu_device * adev)384 static void mmhub_v4_1_0_gart_disable(struct amdgpu_device *adev)
385 {
386 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
387 u32 tmp;
388 u32 i;
389
390 /* Disable all tables */
391 for (i = 0; i < 16; i++)
392 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL,
393 i * hub->ctx_distance, 0);
394
395 /* Setup TLB control */
396 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
397 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
398 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
399 ENABLE_ADVANCED_DRIVER_MODEL, 0);
400 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
401
402 /* Setup L2 cache */
403 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
404 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
405 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
406 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0);
407 }
408
409 /**
410 * mmhub_v4_1_0_set_fault_enable_default - update GART/VM fault handling
411 *
412 * @adev: amdgpu_device pointer
413 * @value: true redirects VM faults to the default page
414 */
415 static void
mmhub_v4_1_0_set_fault_enable_default(struct amdgpu_device * adev,bool value)416 mmhub_v4_1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
417 {
418 u32 tmp;
419
420 /* These registers are not accessible to VF-SRIOV.
421 * The PF will program them instead.
422 */
423 if (amdgpu_sriov_vf(adev))
424 return;
425
426 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
427 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
428 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
429 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
430 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
431 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
432 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
433 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
434 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
435 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
436 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
437 value);
438 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
439 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
440 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
441 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
442 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
443 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
444 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
445 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
446 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
447 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
448 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
449 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
450 if (!value) {
451 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
452 CRASH_ON_NO_RETRY_FAULT, 1);
453 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
454 CRASH_ON_RETRY_FAULT, 1);
455 }
456 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
457 }
458
459 static const struct amdgpu_vmhub_funcs mmhub_v4_1_0_vmhub_funcs = {
460 .print_l2_protection_fault_status = mmhub_v4_1_0_print_l2_protection_fault_status,
461 .get_invalidate_req = mmhub_v4_1_0_get_invalidate_req,
462 };
463
mmhub_v4_1_0_init(struct amdgpu_device * adev)464 static void mmhub_v4_1_0_init(struct amdgpu_device *adev)
465 {
466 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
467
468 hub->ctx0_ptb_addr_lo32 =
469 SOC15_REG_OFFSET(MMHUB, 0,
470 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
471 hub->ctx0_ptb_addr_hi32 =
472 SOC15_REG_OFFSET(MMHUB, 0,
473 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
474 hub->vm_inv_eng0_sem =
475 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM);
476 hub->vm_inv_eng0_req =
477 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ);
478 hub->vm_inv_eng0_ack =
479 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK);
480 hub->vm_context0_cntl =
481 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
482 hub->vm_l2_pro_fault_status =
483 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS_LO32);
484 hub->vm_l2_pro_fault_cntl =
485 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
486
487 hub->ctx_distance = regMMVM_CONTEXT1_CNTL - regMMVM_CONTEXT0_CNTL;
488 hub->ctx_addr_distance = regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
489 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
490 hub->eng_distance = regMMVM_INVALIDATE_ENG1_REQ -
491 regMMVM_INVALIDATE_ENG0_REQ;
492 hub->eng_addr_distance = regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
493 regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
494
495 hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
496 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
497 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
498 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
499 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
500 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
501 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
502
503 hub->vm_l2_bank_select_reserved_cid2 =
504 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_BANK_SELECT_RESERVED_CID2);
505
506 hub->vm_contexts_disable =
507 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXTS_DISABLE);
508
509 hub->vmhub_funcs = &mmhub_v4_1_0_vmhub_funcs;
510
511 amdgpu_mmhub_init_client_info(&adev->mmhub,
512 mmhub_client_ids_v4_1_0,
513 ARRAY_SIZE(mmhub_client_ids_v4_1_0));
514 }
515
mmhub_v4_1_0_get_fb_location(struct amdgpu_device * adev)516 static u64 mmhub_v4_1_0_get_fb_location(struct amdgpu_device *adev)
517 {
518 u64 base;
519
520 base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE);
521
522 base &= MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
523 base <<= 24;
524
525 return base;
526 }
527
mmhub_v4_1_0_get_mc_fb_offset(struct amdgpu_device * adev)528 static u64 mmhub_v4_1_0_get_mc_fb_offset(struct amdgpu_device *adev)
529 {
530 return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24;
531 }
532
533 static void
mmhub_v4_1_0_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)534 mmhub_v4_1_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
535 bool enable)
536 {
537 #if 0
538 uint32_t def, data;
539 #endif
540 uint32_t def1, data1, def2 = 0, data2 = 0;
541 #if 0
542 def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);
543 #endif
544 def1 = data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2);
545 def2 = data2 = RREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2);
546
547 if (enable) {
548 #if 0
549 data |= MM_ATC_L2_MISC_CG__ENABLE_MASK;
550 #endif
551 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK |
552 DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK);
553
554 data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK |
555 DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK);
556 } else {
557 #if 0
558 data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK;
559 #endif
560 data1 |= (DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK |
561 DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK);
562
563 data2 |= (DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK |
564 DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK);
565 }
566
567 #if 0
568 if (def != data)
569 WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data);
570 #endif
571 if (def1 != data1)
572 WREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2, data1);
573
574 if (def2 != data2)
575 WREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2, data2);
576 }
577
578 static void
mmhub_v4_1_0_update_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable)579 mmhub_v4_1_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
580 bool enable)
581 {
582 #if 0
583 uint32_t def, data;
584
585 def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);
586
587 if (enable)
588 data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
589 else
590 data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
591
592 if (def != data)
593 WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data);
594 #endif
595 }
596
mmhub_v4_1_0_set_clockgating(struct amdgpu_device * adev,enum amd_clockgating_state state)597 static int mmhub_v4_1_0_set_clockgating(struct amdgpu_device *adev,
598 enum amd_clockgating_state state)
599 {
600 if (amdgpu_sriov_vf(adev))
601 return 0;
602
603 if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)
604 mmhub_v4_1_0_update_medium_grain_clock_gating(adev,
605 state == AMD_CG_STATE_GATE);
606
607 if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)
608 mmhub_v4_1_0_update_medium_grain_light_sleep(adev,
609 state == AMD_CG_STATE_GATE);
610
611 return 0;
612 }
613
mmhub_v4_1_0_get_clockgating(struct amdgpu_device * adev,u64 * flags)614 static void mmhub_v4_1_0_get_clockgating(struct amdgpu_device *adev, u64 *flags)
615 {
616 #if 0
617 int data;
618
619 if (amdgpu_sriov_vf(adev))
620 *flags = 0;
621
622 data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);
623
624 /* AMD_CG_SUPPORT_MC_MGCG */
625 if (data & MM_ATC_L2_MISC_CG__ENABLE_MASK)
626 *flags |= AMD_CG_SUPPORT_MC_MGCG;
627
628 /* AMD_CG_SUPPORT_MC_LS */
629 if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
630 *flags |= AMD_CG_SUPPORT_MC_LS;
631 #endif
632 }
633
634 const struct amdgpu_mmhub_funcs mmhub_v4_1_0_funcs = {
635 .init = mmhub_v4_1_0_init,
636 .get_fb_location = mmhub_v4_1_0_get_fb_location,
637 .get_mc_fb_offset = mmhub_v4_1_0_get_mc_fb_offset,
638 .gart_enable = mmhub_v4_1_0_gart_enable,
639 .set_fault_enable_default = mmhub_v4_1_0_set_fault_enable_default,
640 .gart_disable = mmhub_v4_1_0_gart_disable,
641 .set_clockgating = mmhub_v4_1_0_set_clockgating,
642 .get_clockgating = mmhub_v4_1_0_get_clockgating,
643 .setup_vm_pt_regs = mmhub_v4_1_0_setup_vm_pt_regs,
644 };
645