1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include "amdgpu.h"
25 #include "mmhub_v3_0_2.h"
26
27 #include "mmhub/mmhub_3_0_2_offset.h"
28 #include "mmhub/mmhub_3_0_2_sh_mask.h"
29 #include "navi10_enum.h"
30
31 #include "soc15_common.h"
32
33 #define regMMVM_L2_CNTL3_DEFAULT 0x80100007
34 #define regMMVM_L2_CNTL4_DEFAULT 0x000000c1
35 #define regMMVM_L2_CNTL5_DEFAULT 0x00003fe0
36
37 static const char *mmhub_client_ids_v3_0_2[][2] = {
38 [0][0] = "VMC",
39 [4][0] = "DCEDMC",
40 [5][0] = "DCEVGA",
41 [6][0] = "MP0",
42 [7][0] = "MP1",
43 [8][0] = "MPIO",
44 [16][0] = "HDP",
45 [17][0] = "LSDMA",
46 [18][0] = "JPEG",
47 [19][0] = "VCNU0",
48 [21][0] = "VSCH",
49 [22][0] = "VCNU1",
50 [23][0] = "VCN1",
51 [32+20][0] = "VCN0",
52 [2][1] = "DBGUNBIO",
53 [3][1] = "DCEDWB",
54 [4][1] = "DCEDMC",
55 [5][1] = "DCEVGA",
56 [6][1] = "MP0",
57 [7][1] = "MP1",
58 [8][1] = "MPIO",
59 [10][1] = "DBGU0",
60 [11][1] = "DBGU1",
61 [12][1] = "DBGU2",
62 [13][1] = "DBGU3",
63 [14][1] = "XDP",
64 [15][1] = "OSSSYS",
65 [16][1] = "HDP",
66 [17][1] = "LSDMA",
67 [18][1] = "JPEG",
68 [19][1] = "VCNU0",
69 [20][1] = "VCN0",
70 [21][1] = "VSCH",
71 [22][1] = "VCNU1",
72 [23][1] = "VCN1",
73 };
74
mmhub_v3_0_2_get_invalidate_req(unsigned int vmid,uint32_t flush_type)75 static uint32_t mmhub_v3_0_2_get_invalidate_req(unsigned int vmid,
76 uint32_t flush_type)
77 {
78 u32 req = 0;
79
80 /* invalidate using legacy mode on vmid*/
81 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
82 PER_VMID_INVALIDATE_REQ, 1 << vmid);
83 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
84 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
85 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
86 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
87 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
88 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
89 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
90 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
91
92 return req;
93 }
94
95 static void
mmhub_v3_0_2_print_l2_protection_fault_status(struct amdgpu_device * adev,uint32_t status)96 mmhub_v3_0_2_print_l2_protection_fault_status(struct amdgpu_device *adev,
97 uint32_t status)
98 {
99 uint32_t cid, rw;
100 const char *mmhub_cid;
101
102 cid = REG_GET_FIELD(status,
103 MMVM_L2_PROTECTION_FAULT_STATUS, CID);
104 rw = REG_GET_FIELD(status,
105 MMVM_L2_PROTECTION_FAULT_STATUS, RW);
106
107 dev_err(adev->dev,
108 "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
109 status);
110 mmhub_cid = amdgpu_mmhub_client_name(&adev->mmhub, cid, rw);
111 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
112 mmhub_cid ? mmhub_cid : "unknown", cid);
113 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
114 REG_GET_FIELD(status,
115 MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
116 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
117 REG_GET_FIELD(status,
118 MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
119 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
120 REG_GET_FIELD(status,
121 MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
122 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
123 REG_GET_FIELD(status,
124 MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
125 dev_err(adev->dev, "\t RW: 0x%x\n", rw);
126 }
127
mmhub_v3_0_2_setup_vm_pt_regs(struct amdgpu_device * adev,uint32_t vmid,uint64_t page_table_base)128 static void mmhub_v3_0_2_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
129 uint64_t page_table_base)
130 {
131 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
132
133 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
134 hub->ctx_addr_distance * vmid,
135 lower_32_bits(page_table_base));
136
137 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
138 hub->ctx_addr_distance * vmid,
139 upper_32_bits(page_table_base));
140 }
141
mmhub_v3_0_2_init_gart_aperture_regs(struct amdgpu_device * adev)142 static void mmhub_v3_0_2_init_gart_aperture_regs(struct amdgpu_device *adev)
143 {
144 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
145
146 mmhub_v3_0_2_setup_vm_pt_regs(adev, 0, pt_base);
147
148 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
149 (u32)(adev->gmc.gart_start >> 12));
150 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
151 (u32)(adev->gmc.gart_start >> 44));
152
153 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
154 (u32)(adev->gmc.gart_end >> 12));
155 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
156 (u32)(adev->gmc.gart_end >> 44));
157 }
158
mmhub_v3_0_2_init_system_aperture_regs(struct amdgpu_device * adev)159 static void mmhub_v3_0_2_init_system_aperture_regs(struct amdgpu_device *adev)
160 {
161 uint64_t value;
162 uint32_t tmp;
163
164 /* Program the AGP BAR */
165 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0);
166 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
167 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
168
169 if (!amdgpu_sriov_vf(adev)) {
170 /*
171 * the new L1 policy will block SRIOV guest from writing
172 * these regs, and they will be programed at host.
173 * so skip programing these regs.
174 */
175 /* Program the system aperture low logical page number. */
176 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
177 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
178 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
179 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
180 }
181
182 /* Set default page address. */
183 value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
184 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
185 (u32)(value >> 12));
186 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
187 (u32)(value >> 44));
188
189 /* Program "protection fault". */
190 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
191 (u32)(adev->dummy_page_addr >> 12));
192 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
193 (u32)((u64)adev->dummy_page_addr >> 44));
194
195 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);
196 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
197 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
198 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
199 }
200
mmhub_v3_0_2_init_tlb_regs(struct amdgpu_device * adev)201 static void mmhub_v3_0_2_init_tlb_regs(struct amdgpu_device *adev)
202 {
203 uint32_t tmp;
204
205 /* Setup TLB control */
206 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
207
208 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
209 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
210 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
211 ENABLE_ADVANCED_DRIVER_MODEL, 1);
212 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
213 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
214 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
215 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
216 MTYPE, MTYPE_UC); /* UC, uncached */
217
218 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
219 }
220
mmhub_v3_0_2_init_cache_regs(struct amdgpu_device * adev)221 static void mmhub_v3_0_2_init_cache_regs(struct amdgpu_device *adev)
222 {
223 uint32_t tmp;
224
225 /* These registers are not accessible to VF-SRIOV.
226 * The PF will program them instead.
227 */
228 if (amdgpu_sriov_vf(adev))
229 return;
230
231 /* Setup L2 cache */
232 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
233 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
234 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
235 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
236 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
237 /* XXX for emulation, Refer to closed source code.*/
238 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
239 0);
240 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
241 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
242 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
243 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
244
245 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2);
246 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
247 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
248 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp);
249
250 tmp = regMMVM_L2_CNTL3_DEFAULT;
251 if (adev->gmc.translate_further) {
252 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
253 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
254 L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
255 } else {
256 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
257 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
258 L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
259 }
260 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp);
261
262 tmp = regMMVM_L2_CNTL4_DEFAULT;
263 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
264 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
265 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp);
266
267 tmp = regMMVM_L2_CNTL5_DEFAULT;
268 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
269 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp);
270 }
271
mmhub_v3_0_2_enable_system_domain(struct amdgpu_device * adev)272 static void mmhub_v3_0_2_enable_system_domain(struct amdgpu_device *adev)
273 {
274 uint32_t tmp;
275
276 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
277 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
278 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
279 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
280 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
281 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp);
282 }
283
mmhub_v3_0_2_disable_identity_aperture(struct amdgpu_device * adev)284 static void mmhub_v3_0_2_disable_identity_aperture(struct amdgpu_device *adev)
285 {
286 /* These registers are not accessible to VF-SRIOV.
287 * The PF will program them instead.
288 */
289 if (amdgpu_sriov_vf(adev))
290 return;
291
292 WREG32_SOC15(MMHUB, 0,
293 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
294 0xFFFFFFFF);
295 WREG32_SOC15(MMHUB, 0,
296 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
297 0x0000000F);
298
299 WREG32_SOC15(MMHUB, 0,
300 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
301 WREG32_SOC15(MMHUB, 0,
302 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
303
304 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
305 0);
306 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
307 0);
308 }
309
mmhub_v3_0_2_setup_vmid_config(struct amdgpu_device * adev)310 static void mmhub_v3_0_2_setup_vmid_config(struct amdgpu_device *adev)
311 {
312 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
313 int i;
314 uint32_t tmp;
315
316 for (i = 0; i <= 14; i++) {
317 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i * hub->ctx_distance);
318 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
319 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
320 adev->vm_manager.num_level);
321 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
322 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
323 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
324 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
325 1);
326 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
327 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
328 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
329 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
330 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
331 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
332 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
333 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
334 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
335 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
336 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
337 PAGE_TABLE_BLOCK_SIZE,
338 adev->vm_manager.block_size - 9);
339 /* Send no-retry XNACK on fault to suppress VM fault storm. */
340 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
341 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
342 !amdgpu_noretry);
343 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL,
344 i * hub->ctx_distance, tmp);
345 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
346 i * hub->ctx_addr_distance, 0);
347 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
348 i * hub->ctx_addr_distance, 0);
349 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
350 i * hub->ctx_addr_distance,
351 lower_32_bits(adev->vm_manager.max_pfn - 1));
352 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
353 i * hub->ctx_addr_distance,
354 upper_32_bits(adev->vm_manager.max_pfn - 1));
355 }
356
357 hub->vm_cntx_cntl = tmp;
358 }
359
mmhub_v3_0_2_program_invalidation(struct amdgpu_device * adev)360 static void mmhub_v3_0_2_program_invalidation(struct amdgpu_device *adev)
361 {
362 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
363 unsigned i;
364
365 for (i = 0; i < 18; ++i) {
366 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
367 i * hub->eng_addr_distance, 0xffffffff);
368 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
369 i * hub->eng_addr_distance, 0x1f);
370 }
371 }
372
mmhub_v3_0_2_gart_enable(struct amdgpu_device * adev)373 static int mmhub_v3_0_2_gart_enable(struct amdgpu_device *adev)
374 {
375 /* GART Enable. */
376 mmhub_v3_0_2_init_gart_aperture_regs(adev);
377 mmhub_v3_0_2_init_system_aperture_regs(adev);
378 mmhub_v3_0_2_init_tlb_regs(adev);
379 mmhub_v3_0_2_init_cache_regs(adev);
380
381 mmhub_v3_0_2_enable_system_domain(adev);
382 mmhub_v3_0_2_disable_identity_aperture(adev);
383 mmhub_v3_0_2_setup_vmid_config(adev);
384 mmhub_v3_0_2_program_invalidation(adev);
385
386 return 0;
387 }
388
mmhub_v3_0_2_gart_disable(struct amdgpu_device * adev)389 static void mmhub_v3_0_2_gart_disable(struct amdgpu_device *adev)
390 {
391 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
392 u32 tmp;
393 u32 i;
394
395 /* Disable all tables */
396 for (i = 0; i < 16; i++)
397 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL,
398 i * hub->ctx_distance, 0);
399
400 /* Setup TLB control */
401 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
402 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
403 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
404 ENABLE_ADVANCED_DRIVER_MODEL, 0);
405 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
406
407 /* Setup L2 cache */
408 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
409 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
410 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
411 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0);
412 }
413
414 /**
415 * mmhub_v3_0_2_set_fault_enable_default - update GART/VM fault handling
416 *
417 * @adev: amdgpu_device pointer
418 * @value: true redirects VM faults to the default page
419 */
mmhub_v3_0_2_set_fault_enable_default(struct amdgpu_device * adev,bool value)420 static void mmhub_v3_0_2_set_fault_enable_default(struct amdgpu_device *adev, bool value)
421 {
422 u32 tmp;
423
424 /* These registers are not accessible to VF-SRIOV.
425 * The PF will program them instead.
426 */
427 if (amdgpu_sriov_vf(adev))
428 return;
429
430 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
431 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
432 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
433 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
434 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
435 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
436 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
437 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
438 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
439 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
440 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
441 value);
442 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
443 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
444 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
445 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
446 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
447 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
448 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
449 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
450 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
451 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
452 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
453 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
454 if (!value) {
455 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
456 CRASH_ON_NO_RETRY_FAULT, 1);
457 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
458 CRASH_ON_RETRY_FAULT, 1);
459 }
460 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
461 }
462
463 static const struct amdgpu_vmhub_funcs mmhub_v3_0_2_vmhub_funcs = {
464 .print_l2_protection_fault_status = mmhub_v3_0_2_print_l2_protection_fault_status,
465 .get_invalidate_req = mmhub_v3_0_2_get_invalidate_req,
466 };
467
mmhub_v3_0_2_init(struct amdgpu_device * adev)468 static void mmhub_v3_0_2_init(struct amdgpu_device *adev)
469 {
470 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
471
472 hub->ctx0_ptb_addr_lo32 =
473 SOC15_REG_OFFSET(MMHUB, 0,
474 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
475 hub->ctx0_ptb_addr_hi32 =
476 SOC15_REG_OFFSET(MMHUB, 0,
477 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
478 hub->vm_inv_eng0_sem =
479 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM);
480 hub->vm_inv_eng0_req =
481 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ);
482 hub->vm_inv_eng0_ack =
483 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK);
484 hub->vm_context0_cntl =
485 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
486 hub->vm_l2_pro_fault_status =
487 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS);
488 hub->vm_l2_pro_fault_cntl =
489 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
490
491 hub->ctx_distance = regMMVM_CONTEXT1_CNTL - regMMVM_CONTEXT0_CNTL;
492 hub->ctx_addr_distance = regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
493 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
494 hub->eng_distance = regMMVM_INVALIDATE_ENG1_REQ -
495 regMMVM_INVALIDATE_ENG0_REQ;
496 hub->eng_addr_distance = regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
497 regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
498
499 hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
500 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
501 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
502 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
503 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
504 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
505 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
506
507 hub->vm_l2_bank_select_reserved_cid2 =
508 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_BANK_SELECT_RESERVED_CID2);
509
510 hub->vmhub_funcs = &mmhub_v3_0_2_vmhub_funcs;
511
512 amdgpu_mmhub_init_client_info(&adev->mmhub,
513 mmhub_client_ids_v3_0_2,
514 ARRAY_SIZE(mmhub_client_ids_v3_0_2));
515 }
516
mmhub_v3_0_2_get_fb_location(struct amdgpu_device * adev)517 static u64 mmhub_v3_0_2_get_fb_location(struct amdgpu_device *adev)
518 {
519 u64 base;
520
521 base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE);
522 base &= MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
523 base <<= 24;
524
525 return base;
526 }
527
mmhub_v3_0_2_get_mc_fb_offset(struct amdgpu_device * adev)528 static u64 mmhub_v3_0_2_get_mc_fb_offset(struct amdgpu_device *adev)
529 {
530 return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24;
531 }
532
mmhub_v3_0_2_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)533 static void mmhub_v3_0_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
534 bool enable)
535 {
536 //TODO
537 }
538
mmhub_v3_0_2_update_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable)539 static void mmhub_v3_0_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
540 bool enable)
541 {
542 //TODO
543 }
544
mmhub_v3_0_2_set_clockgating(struct amdgpu_device * adev,enum amd_clockgating_state state)545 static int mmhub_v3_0_2_set_clockgating(struct amdgpu_device *adev,
546 enum amd_clockgating_state state)
547 {
548 if (amdgpu_sriov_vf(adev))
549 return 0;
550
551 mmhub_v3_0_2_update_medium_grain_clock_gating(adev,
552 state == AMD_CG_STATE_GATE);
553 mmhub_v3_0_2_update_medium_grain_light_sleep(adev,
554 state == AMD_CG_STATE_GATE);
555 return 0;
556 }
557
mmhub_v3_0_2_get_clockgating(struct amdgpu_device * adev,u64 * flags)558 static void mmhub_v3_0_2_get_clockgating(struct amdgpu_device *adev, u64 *flags)
559 {
560 //TODO
561 }
562
563 const struct amdgpu_mmhub_funcs mmhub_v3_0_2_funcs = {
564 .init = mmhub_v3_0_2_init,
565 .get_fb_location = mmhub_v3_0_2_get_fb_location,
566 .get_mc_fb_offset = mmhub_v3_0_2_get_mc_fb_offset,
567 .gart_enable = mmhub_v3_0_2_gart_enable,
568 .set_fault_enable_default = mmhub_v3_0_2_set_fault_enable_default,
569 .gart_disable = mmhub_v3_0_2_gart_disable,
570 .set_clockgating = mmhub_v3_0_2_set_clockgating,
571 .get_clockgating = mmhub_v3_0_2_get_clockgating,
572 .setup_vm_pt_regs = mmhub_v3_0_2_setup_vm_pt_regs,
573 };
574