1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include "amdgpu.h"
25 #include "mmhub_v3_0_1.h"
26
27 #include "mmhub/mmhub_3_0_1_offset.h"
28 #include "mmhub/mmhub_3_0_1_sh_mask.h"
29 #include "navi10_enum.h"
30
31 #include "soc15_common.h"
32
33 #define regMMVM_L2_CNTL3_DEFAULT 0x80100007
34 #define regMMVM_L2_CNTL4_DEFAULT 0x000000c1
35 #define regMMVM_L2_CNTL5_DEFAULT 0x00003fe0
36
37 static const char *mmhub_client_ids_v3_0_1[][2] = {
38 [0][0] = "VMC",
39 [1][0] = "ISPXT",
40 [2][0] = "ISPIXT",
41 [4][0] = "DCEDMC",
42 [5][0] = "DCEVGA",
43 [6][0] = "MP0",
44 [7][0] = "MP1",
45 [8][0] = "MPM",
46 [12][0] = "ISPTNR",
47 [14][0] = "ISPCRD0",
48 [15][0] = "ISPCRD1",
49 [16][0] = "ISPCRD2",
50 [22][0] = "HDP",
51 [23][0] = "LSDMA",
52 [24][0] = "JPEG",
53 [27][0] = "VSCH",
54 [28][0] = "VCNU",
55 [29][0] = "VCN",
56 [1][1] = "ISPXT",
57 [2][1] = "ISPIXT",
58 [3][1] = "DCEDWB",
59 [4][1] = "DCEDMC",
60 [5][1] = "DCEVGA",
61 [6][1] = "MP0",
62 [7][1] = "MP1",
63 [8][1] = "MPM",
64 [10][1] = "ISPMWR0",
65 [11][1] = "ISPMWR1",
66 [12][1] = "ISPTNR",
67 [13][1] = "ISPSWR",
68 [14][1] = "ISPCWR0",
69 [15][1] = "ISPCWR1",
70 [16][1] = "ISPCWR2",
71 [17][1] = "ISPCWR3",
72 [18][1] = "XDP",
73 [21][1] = "OSSSYS",
74 [22][1] = "HDP",
75 [23][1] = "LSDMA",
76 [24][1] = "JPEG",
77 [27][1] = "VSCH",
78 [28][1] = "VCNU",
79 [29][1] = "VCN",
80 };
81
mmhub_v3_0_1_get_invalidate_req(unsigned int vmid,uint32_t flush_type)82 static uint32_t mmhub_v3_0_1_get_invalidate_req(unsigned int vmid,
83 uint32_t flush_type)
84 {
85 u32 req = 0;
86
87 /* invalidate using legacy mode on vmid*/
88 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
89 PER_VMID_INVALIDATE_REQ, 1 << vmid);
90 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
91 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
92 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
93 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
94 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
95 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
96 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
97 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
98
99 return req;
100 }
101
102 static void
mmhub_v3_0_1_print_l2_protection_fault_status(struct amdgpu_device * adev,uint32_t status)103 mmhub_v3_0_1_print_l2_protection_fault_status(struct amdgpu_device *adev,
104 uint32_t status)
105 {
106 uint32_t cid, rw;
107 const char *mmhub_cid;
108
109 cid = REG_GET_FIELD(status,
110 MMVM_L2_PROTECTION_FAULT_STATUS, CID);
111 rw = REG_GET_FIELD(status,
112 MMVM_L2_PROTECTION_FAULT_STATUS, RW);
113
114 dev_err(adev->dev,
115 "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
116 status);
117 mmhub_cid = amdgpu_mmhub_client_name(&adev->mmhub, cid, rw);
118 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
119 mmhub_cid ? mmhub_cid : "unknown", cid);
120 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
121 REG_GET_FIELD(status,
122 MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
123 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
124 REG_GET_FIELD(status,
125 MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
126 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
127 REG_GET_FIELD(status,
128 MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
129 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
130 REG_GET_FIELD(status,
131 MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
132 dev_err(adev->dev, "\t RW: 0x%x\n", rw);
133 }
134
mmhub_v3_0_1_setup_vm_pt_regs(struct amdgpu_device * adev,uint32_t vmid,uint64_t page_table_base)135 static void mmhub_v3_0_1_setup_vm_pt_regs(struct amdgpu_device *adev,
136 uint32_t vmid,
137 uint64_t page_table_base)
138 {
139 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
140
141 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
142 hub->ctx_addr_distance * vmid,
143 lower_32_bits(page_table_base));
144
145 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
146 hub->ctx_addr_distance * vmid,
147 upper_32_bits(page_table_base));
148 }
149
mmhub_v3_0_1_init_gart_aperture_regs(struct amdgpu_device * adev)150 static void mmhub_v3_0_1_init_gart_aperture_regs(struct amdgpu_device *adev)
151 {
152 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
153
154 mmhub_v3_0_1_setup_vm_pt_regs(adev, 0, pt_base);
155
156 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
157 (u32)(adev->gmc.gart_start >> 12));
158 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
159 (u32)(adev->gmc.gart_start >> 44));
160
161 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
162 (u32)(adev->gmc.gart_end >> 12));
163 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
164 (u32)(adev->gmc.gart_end >> 44));
165 }
166
mmhub_v3_0_1_init_system_aperture_regs(struct amdgpu_device * adev)167 static void mmhub_v3_0_1_init_system_aperture_regs(struct amdgpu_device *adev)
168 {
169 uint64_t value;
170 uint32_t tmp;
171
172 /* Program the AGP BAR */
173 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0);
174 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
175 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
176
177 /*
178 * the new L1 policy will block SRIOV guest from writing
179 * these regs, and they will be programed at host.
180 * so skip programing these regs.
181 */
182 /* Program the system aperture low logical page number. */
183 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
184 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
185 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
186 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
187
188 /* Set default page address. */
189 value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
190 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
191 (u32)(value >> 12));
192 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
193 (u32)(value >> 44));
194
195 /* Program "protection fault". */
196 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
197 (u32)(adev->dummy_page_addr >> 12));
198 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
199 (u32)((u64)adev->dummy_page_addr >> 44));
200
201 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);
202 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
203 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
204 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
205 }
206
mmhub_v3_0_1_init_tlb_regs(struct amdgpu_device * adev)207 static void mmhub_v3_0_1_init_tlb_regs(struct amdgpu_device *adev)
208 {
209 uint32_t tmp;
210
211 /* Setup TLB control */
212 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
213
214 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
215 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
216 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
217 ENABLE_ADVANCED_DRIVER_MODEL, 1);
218 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
219 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
220 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
221 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
222 MTYPE, MTYPE_UC); /* UC, uncached */
223
224 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
225 }
226
mmhub_v3_0_1_init_cache_regs(struct amdgpu_device * adev)227 static void mmhub_v3_0_1_init_cache_regs(struct amdgpu_device *adev)
228 {
229 uint32_t tmp;
230
231 /* Setup L2 cache */
232 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
233 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
234 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
235 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
236 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
237 /* XXX for emulation, Refer to closed source code.*/
238 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
239 0);
240 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
241 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
242 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
243 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
244
245 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2);
246 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
247 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
248 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp);
249
250 tmp = regMMVM_L2_CNTL3_DEFAULT;
251 if (adev->gmc.translate_further) {
252 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
253 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
254 L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
255 } else {
256 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
257 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
258 L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
259 }
260 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp);
261
262 tmp = regMMVM_L2_CNTL4_DEFAULT;
263 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
264 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
265 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp);
266
267 tmp = regMMVM_L2_CNTL5_DEFAULT;
268 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
269 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp);
270 }
271
mmhub_v3_0_1_enable_system_domain(struct amdgpu_device * adev)272 static void mmhub_v3_0_1_enable_system_domain(struct amdgpu_device *adev)
273 {
274 uint32_t tmp;
275
276 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
277 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
278 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
279 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
280 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
281 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp);
282 }
283
mmhub_v3_0_1_disable_identity_aperture(struct amdgpu_device * adev)284 static void mmhub_v3_0_1_disable_identity_aperture(struct amdgpu_device *adev)
285 {
286 WREG32_SOC15(MMHUB, 0,
287 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
288 0xFFFFFFFF);
289 WREG32_SOC15(MMHUB, 0,
290 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
291 0x0000000F);
292
293 WREG32_SOC15(MMHUB, 0,
294 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
295 WREG32_SOC15(MMHUB, 0,
296 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
297
298 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
299 0);
300 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
301 0);
302 }
303
mmhub_v3_0_1_setup_vmid_config(struct amdgpu_device * adev)304 static void mmhub_v3_0_1_setup_vmid_config(struct amdgpu_device *adev)
305 {
306 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
307 int i;
308 uint32_t tmp;
309
310 for (i = 0; i <= 14; i++) {
311 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i * hub->ctx_distance);
312 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
313 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
314 adev->vm_manager.num_level);
315 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
316 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
317 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
318 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
319 1);
320 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
321 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
322 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
323 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
324 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
325 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
326 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
327 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
328 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
329 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
330 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
331 PAGE_TABLE_BLOCK_SIZE,
332 adev->vm_manager.block_size - 9);
333 /* Send no-retry XNACK on fault to suppress VM fault storm. */
334 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
335 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
336 !amdgpu_noretry);
337 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL,
338 i * hub->ctx_distance, tmp);
339 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
340 i * hub->ctx_addr_distance, 0);
341 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
342 i * hub->ctx_addr_distance, 0);
343 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
344 i * hub->ctx_addr_distance,
345 lower_32_bits(adev->vm_manager.max_pfn - 1));
346 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
347 i * hub->ctx_addr_distance,
348 upper_32_bits(adev->vm_manager.max_pfn - 1));
349 }
350
351 hub->vm_cntx_cntl = tmp;
352 }
353
mmhub_v3_0_1_program_invalidation(struct amdgpu_device * adev)354 static void mmhub_v3_0_1_program_invalidation(struct amdgpu_device *adev)
355 {
356 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
357 unsigned i;
358
359 for (i = 0; i < 18; ++i) {
360 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
361 i * hub->eng_addr_distance, 0xffffffff);
362 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
363 i * hub->eng_addr_distance, 0x1f);
364 }
365 }
366
mmhub_v3_0_1_gart_enable(struct amdgpu_device * adev)367 static int mmhub_v3_0_1_gart_enable(struct amdgpu_device *adev)
368 {
369 /* GART Enable. */
370 mmhub_v3_0_1_init_gart_aperture_regs(adev);
371 mmhub_v3_0_1_init_system_aperture_regs(adev);
372 mmhub_v3_0_1_init_tlb_regs(adev);
373 mmhub_v3_0_1_init_cache_regs(adev);
374
375 mmhub_v3_0_1_enable_system_domain(adev);
376 mmhub_v3_0_1_disable_identity_aperture(adev);
377 mmhub_v3_0_1_setup_vmid_config(adev);
378 mmhub_v3_0_1_program_invalidation(adev);
379
380 return 0;
381 }
382
mmhub_v3_0_1_gart_disable(struct amdgpu_device * adev)383 static void mmhub_v3_0_1_gart_disable(struct amdgpu_device *adev)
384 {
385 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
386 u32 tmp;
387 u32 i;
388
389 /* Disable all tables */
390 for (i = 0; i < 16; i++)
391 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL,
392 i * hub->ctx_distance, 0);
393
394 /* Setup TLB control */
395 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
396 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
397 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
398 ENABLE_ADVANCED_DRIVER_MODEL, 0);
399 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
400
401 /* Setup L2 cache */
402 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
403 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
404 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
405 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0);
406 }
407
408 /**
409 * mmhub_v3_0_1_set_fault_enable_default - update GART/VM fault handling
410 *
411 * @adev: amdgpu_device pointer
412 * @value: true redirects VM faults to the default page
413 */
mmhub_v3_0_1_set_fault_enable_default(struct amdgpu_device * adev,bool value)414 static void mmhub_v3_0_1_set_fault_enable_default(struct amdgpu_device *adev,
415 bool value)
416 {
417 u32 tmp;
418
419 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
420 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
421 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
422 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
423 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
424 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
425 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
426 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
427 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
428 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
429 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
430 value);
431 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
432 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
433 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
434 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
435 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
436 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
437 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
438 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
439 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
440 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
441 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
442 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
443 if (!value) {
444 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
445 CRASH_ON_NO_RETRY_FAULT, 1);
446 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
447 CRASH_ON_RETRY_FAULT, 1);
448 }
449 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
450 }
451
452 static const struct amdgpu_vmhub_funcs mmhub_v3_0_1_vmhub_funcs = {
453 .print_l2_protection_fault_status = mmhub_v3_0_1_print_l2_protection_fault_status,
454 .get_invalidate_req = mmhub_v3_0_1_get_invalidate_req,
455 };
456
mmhub_v3_0_1_init(struct amdgpu_device * adev)457 static void mmhub_v3_0_1_init(struct amdgpu_device *adev)
458 {
459 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
460
461 hub->ctx0_ptb_addr_lo32 =
462 SOC15_REG_OFFSET(MMHUB, 0,
463 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
464 hub->ctx0_ptb_addr_hi32 =
465 SOC15_REG_OFFSET(MMHUB, 0,
466 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
467 hub->vm_inv_eng0_sem =
468 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM);
469 hub->vm_inv_eng0_req =
470 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ);
471 hub->vm_inv_eng0_ack =
472 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK);
473 hub->vm_context0_cntl =
474 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
475 hub->vm_l2_pro_fault_status =
476 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS);
477 hub->vm_l2_pro_fault_cntl =
478 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
479
480 hub->ctx_distance = regMMVM_CONTEXT1_CNTL - regMMVM_CONTEXT0_CNTL;
481 hub->ctx_addr_distance = regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
482 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
483 hub->eng_distance = regMMVM_INVALIDATE_ENG1_REQ -
484 regMMVM_INVALIDATE_ENG0_REQ;
485 hub->eng_addr_distance = regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
486 regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
487
488 hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
489 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
490 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
491 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
492 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
493 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
494 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
495
496 hub->vmhub_funcs = &mmhub_v3_0_1_vmhub_funcs;
497
498 amdgpu_mmhub_init_client_info(&adev->mmhub,
499 mmhub_client_ids_v3_0_1,
500 ARRAY_SIZE(mmhub_client_ids_v3_0_1));
501 }
502
mmhub_v3_0_1_get_fb_location(struct amdgpu_device * adev)503 static u64 mmhub_v3_0_1_get_fb_location(struct amdgpu_device *adev)
504 {
505 u64 base;
506
507 base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE);
508 base &= MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
509 base <<= 24;
510
511 return base;
512 }
513
mmhub_v3_0_1_get_mc_fb_offset(struct amdgpu_device * adev)514 static u64 mmhub_v3_0_1_get_mc_fb_offset(struct amdgpu_device *adev)
515 {
516 return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24;
517 }
518
mmhub_v3_0_1_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)519 static void mmhub_v3_0_1_update_medium_grain_clock_gating(struct amdgpu_device *adev,
520 bool enable)
521 {
522 uint32_t def, data;
523
524 def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);
525
526 if (enable)
527 data |= MM_ATC_L2_MISC_CG__ENABLE_MASK;
528 else
529 data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK;
530
531 if (def != data)
532 WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data);
533 }
534
mmhub_v3_0_1_update_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable)535 static void mmhub_v3_0_1_update_medium_grain_light_sleep(struct amdgpu_device *adev,
536 bool enable)
537 {
538 uint32_t def, data;
539
540 def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);
541
542 if (enable)
543 data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
544 else
545 data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
546
547 if (def != data)
548 WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data);
549 }
550
mmhub_v3_0_1_set_clockgating(struct amdgpu_device * adev,enum amd_clockgating_state state)551 static int mmhub_v3_0_1_set_clockgating(struct amdgpu_device *adev,
552 enum amd_clockgating_state state)
553 {
554 if (amdgpu_sriov_vf(adev))
555 return 0;
556
557 mmhub_v3_0_1_update_medium_grain_clock_gating(adev,
558 state == AMD_CG_STATE_GATE);
559 mmhub_v3_0_1_update_medium_grain_light_sleep(adev,
560 state == AMD_CG_STATE_GATE);
561 return 0;
562 }
563
mmhub_v3_0_1_get_clockgating(struct amdgpu_device * adev,u64 * flags)564 static void mmhub_v3_0_1_get_clockgating(struct amdgpu_device *adev, u64 *flags)
565 {
566 int data;
567
568 if (amdgpu_sriov_vf(adev))
569 *flags = 0;
570
571 data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);
572
573 /* AMD_CG_SUPPORT_MC_MGCG */
574 if (data & MM_ATC_L2_MISC_CG__ENABLE_MASK)
575 *flags |= AMD_CG_SUPPORT_MC_MGCG;
576
577 /* AMD_CG_SUPPORT_MC_LS */
578 if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
579 *flags |= AMD_CG_SUPPORT_MC_LS;
580 }
581
582 const struct amdgpu_mmhub_funcs mmhub_v3_0_1_funcs = {
583 .init = mmhub_v3_0_1_init,
584 .get_fb_location = mmhub_v3_0_1_get_fb_location,
585 .get_mc_fb_offset = mmhub_v3_0_1_get_mc_fb_offset,
586 .gart_enable = mmhub_v3_0_1_gart_enable,
587 .set_fault_enable_default = mmhub_v3_0_1_set_fault_enable_default,
588 .gart_disable = mmhub_v3_0_1_gart_disable,
589 .set_clockgating = mmhub_v3_0_1_set_clockgating,
590 .get_clockgating = mmhub_v3_0_1_get_clockgating,
591 .setup_vm_pt_regs = mmhub_v3_0_1_setup_vm_pt_regs,
592 };
593