1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include "amdgpu.h"
25 #include "mmhub_v2_0.h"
26
27 #include "mmhub/mmhub_2_0_0_offset.h"
28 #include "mmhub/mmhub_2_0_0_sh_mask.h"
29 #include "mmhub/mmhub_2_0_0_default.h"
30 #include "navi10_enum.h"
31
32 #include "gc/gc_10_1_0_offset.h"
33 #include "soc15_common.h"
34
35 #define mmDAGB0_CNTL_MISC2_Sienna_Cichlid 0x0070
36 #define mmDAGB0_CNTL_MISC2_Sienna_Cichlid_BASE_IDX 0
37
38 static const char *mmhub_client_ids_navi1x[][2] = {
39 [3][0] = "DCEDMC",
40 [4][0] = "DCEVGA",
41 [5][0] = "MP0",
42 [6][0] = "MP1",
43 [13][0] = "VMC",
44 [14][0] = "HDP",
45 [15][0] = "OSS",
46 [16][0] = "VCNU",
47 [17][0] = "JPEG",
48 [18][0] = "VCN",
49 [3][1] = "DCEDMC",
50 [4][1] = "DCEXFC",
51 [5][1] = "DCEVGA",
52 [6][1] = "DCEDWB",
53 [7][1] = "MP0",
54 [8][1] = "MP1",
55 [9][1] = "DBGU1",
56 [10][1] = "DBGU0",
57 [11][1] = "XDP",
58 [14][1] = "HDP",
59 [15][1] = "OSS",
60 [16][1] = "VCNU",
61 [17][1] = "JPEG",
62 [18][1] = "VCN",
63 };
64
65 static const char *mmhub_client_ids_sienna_cichlid[][2] = {
66 [3][0] = "DCEDMC",
67 [4][0] = "DCEVGA",
68 [5][0] = "MP0",
69 [6][0] = "MP1",
70 [8][0] = "VMC",
71 [9][0] = "VCNU0",
72 [10][0] = "JPEG",
73 [12][0] = "VCNU1",
74 [13][0] = "VCN1",
75 [14][0] = "HDP",
76 [15][0] = "OSS",
77 [32+11][0] = "VCN0",
78 [0][1] = "DBGU0",
79 [1][1] = "DBGU1",
80 [2][1] = "DCEDWB",
81 [3][1] = "DCEDMC",
82 [4][1] = "DCEVGA",
83 [5][1] = "MP0",
84 [6][1] = "MP1",
85 [7][1] = "XDP",
86 [9][1] = "VCNU0",
87 [10][1] = "JPEG",
88 [11][1] = "VCN0",
89 [12][1] = "VCNU1",
90 [13][1] = "VCN1",
91 [14][1] = "HDP",
92 [15][1] = "OSS",
93 };
94
95 static const char *mmhub_client_ids_beige_goby[][2] = {
96 [3][0] = "DCEDMC",
97 [4][0] = "DCEVGA",
98 [5][0] = "MP0",
99 [6][0] = "MP1",
100 [8][0] = "VMC",
101 [9][0] = "VCNU0",
102 [11][0] = "VCN0",
103 [14][0] = "HDP",
104 [15][0] = "OSS",
105 [0][1] = "DBGU0",
106 [1][1] = "DBGU1",
107 [2][1] = "DCEDWB",
108 [3][1] = "DCEDMC",
109 [4][1] = "DCEVGA",
110 [5][1] = "MP0",
111 [6][1] = "MP1",
112 [7][1] = "XDP",
113 [9][1] = "VCNU0",
114 [11][1] = "VCN0",
115 [14][1] = "HDP",
116 [15][1] = "OSS",
117 };
118
mmhub_v2_0_get_invalidate_req(unsigned int vmid,uint32_t flush_type)119 static uint32_t mmhub_v2_0_get_invalidate_req(unsigned int vmid,
120 uint32_t flush_type)
121 {
122 u32 req = 0;
123
124 /* invalidate using legacy mode on vmid*/
125 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
126 PER_VMID_INVALIDATE_REQ, 1 << vmid);
127 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
128 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
129 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
130 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
131 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
132 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
133 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
134 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
135
136 return req;
137 }
138
139 static void
mmhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device * adev,uint32_t status)140 mmhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
141 uint32_t status)
142 {
143 uint32_t cid, rw;
144 const char *mmhub_cid;
145
146 cid = REG_GET_FIELD(status,
147 MMVM_L2_PROTECTION_FAULT_STATUS, CID);
148 rw = REG_GET_FIELD(status,
149 MMVM_L2_PROTECTION_FAULT_STATUS, RW);
150
151 dev_err(adev->dev,
152 "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
153 status);
154 mmhub_cid = amdgpu_mmhub_client_name(&adev->mmhub, cid, rw);
155 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
156 mmhub_cid ? mmhub_cid : "unknown", cid);
157 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
158 REG_GET_FIELD(status,
159 MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
160 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
161 REG_GET_FIELD(status,
162 MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
163 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
164 REG_GET_FIELD(status,
165 MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
166 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
167 REG_GET_FIELD(status,
168 MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
169 dev_err(adev->dev, "\t RW: 0x%x\n", rw);
170 }
171
mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device * adev,uint32_t vmid,uint64_t page_table_base)172 static void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
173 uint64_t page_table_base)
174 {
175 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
176
177 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
178 hub->ctx_addr_distance * vmid,
179 lower_32_bits(page_table_base));
180
181 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
182 hub->ctx_addr_distance * vmid,
183 upper_32_bits(page_table_base));
184 }
185
mmhub_v2_0_init_gart_aperture_regs(struct amdgpu_device * adev)186 static void mmhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev)
187 {
188 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
189
190 mmhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base);
191
192 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
193 (u32)(adev->gmc.gart_start >> 12));
194 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
195 (u32)(adev->gmc.gart_start >> 44));
196
197 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
198 (u32)(adev->gmc.gart_end >> 12));
199 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
200 (u32)(adev->gmc.gart_end >> 44));
201 }
202
mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device * adev)203 static void mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev)
204 {
205 uint64_t value;
206 uint32_t tmp;
207
208 if (!amdgpu_sriov_vf(adev)) {
209 /* Program the AGP BAR */
210 WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);
211 WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
212 WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
213
214 /* Program the system aperture low logical page number. */
215 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
216 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
217 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
218 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
219 }
220
221 /* Set default page address. */
222 value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
223 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
224 (u32)(value >> 12));
225 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
226 (u32)(value >> 44));
227
228 /* Program "protection fault". */
229 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
230 (u32)(adev->dummy_page_addr >> 12));
231 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
232 (u32)((u64)adev->dummy_page_addr >> 44));
233
234 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2);
235 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
236 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
237 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
238 }
239
mmhub_v2_0_init_tlb_regs(struct amdgpu_device * adev)240 static void mmhub_v2_0_init_tlb_regs(struct amdgpu_device *adev)
241 {
242 uint32_t tmp;
243
244 /* Setup TLB control */
245 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
246
247 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
248 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
249 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
250 ENABLE_ADVANCED_DRIVER_MODEL, 1);
251 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
252 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
253 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
254 MTYPE, MTYPE_UC); /* UC, uncached */
255
256 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
257 }
258
mmhub_v2_0_init_cache_regs(struct amdgpu_device * adev)259 static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
260 {
261 uint32_t tmp;
262
263 /* These registers are not accessible to VF-SRIOV.
264 * The PF will program them instead.
265 */
266 if (amdgpu_sriov_vf(adev))
267 return;
268
269 /* Setup L2 cache */
270 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
271 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
272 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
273 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
274 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
275 /* XXX for emulation, Refer to closed source code.*/
276 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
277 0);
278 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
279 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
280 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
281 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
282
283 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2);
284 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
285 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
286 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp);
287
288 tmp = mmMMVM_L2_CNTL3_DEFAULT;
289 if (adev->gmc.translate_further) {
290 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
291 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
292 L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
293 } else {
294 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
295 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
296 L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
297 }
298 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp);
299
300 tmp = mmMMVM_L2_CNTL4_DEFAULT;
301 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
302 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
303 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL4, tmp);
304
305 tmp = mmMMVM_L2_CNTL5_DEFAULT;
306 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
307 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL5, tmp);
308 }
309
mmhub_v2_0_enable_system_domain(struct amdgpu_device * adev)310 static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev)
311 {
312 uint32_t tmp;
313
314 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
315 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
316 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
317 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
318 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
319 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp);
320 }
321
mmhub_v2_0_disable_identity_aperture(struct amdgpu_device * adev)322 static void mmhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev)
323 {
324 /* These registers are not accessible to VF-SRIOV.
325 * The PF will program them instead.
326 */
327 if (amdgpu_sriov_vf(adev))
328 return;
329
330 WREG32_SOC15(MMHUB, 0,
331 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
332 0xFFFFFFFF);
333 WREG32_SOC15(MMHUB, 0,
334 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
335 0x0000000F);
336
337 WREG32_SOC15(MMHUB, 0,
338 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
339 WREG32_SOC15(MMHUB, 0,
340 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
341
342 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
343 0);
344 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
345 0);
346 }
347
mmhub_v2_0_setup_vmid_config(struct amdgpu_device * adev)348 static void mmhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
349 {
350 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
351 int i;
352 uint32_t tmp;
353
354 for (i = 0; i <= 14; i++) {
355 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i * hub->ctx_distance);
356 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
357 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
358 adev->vm_manager.num_level);
359 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
360 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
361 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
362 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
363 1);
364 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
365 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
366 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
367 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
368 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
369 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
370 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
371 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
372 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
373 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
374 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
375 PAGE_TABLE_BLOCK_SIZE,
376 adev->vm_manager.block_size - 9);
377 /* Send no-retry XNACK on fault to suppress VM fault storm. */
378 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
379 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
380 !adev->gmc.noretry);
381 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_CNTL,
382 i * hub->ctx_distance, tmp);
383 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
384 i * hub->ctx_addr_distance, 0);
385 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
386 i * hub->ctx_addr_distance, 0);
387 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
388 i * hub->ctx_addr_distance,
389 lower_32_bits(adev->vm_manager.max_pfn - 1));
390 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
391 i * hub->ctx_addr_distance,
392 upper_32_bits(adev->vm_manager.max_pfn - 1));
393 }
394
395 hub->vm_cntx_cntl = tmp;
396 }
397
mmhub_v2_0_program_invalidation(struct amdgpu_device * adev)398 static void mmhub_v2_0_program_invalidation(struct amdgpu_device *adev)
399 {
400 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
401 unsigned i;
402
403 for (i = 0; i < 18; ++i) {
404 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
405 i * hub->eng_addr_distance, 0xffffffff);
406 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
407 i * hub->eng_addr_distance, 0x1f);
408 }
409 }
410
mmhub_v2_0_gart_enable(struct amdgpu_device * adev)411 static int mmhub_v2_0_gart_enable(struct amdgpu_device *adev)
412 {
413 /* GART Enable. */
414 mmhub_v2_0_init_gart_aperture_regs(adev);
415 mmhub_v2_0_init_system_aperture_regs(adev);
416 mmhub_v2_0_init_tlb_regs(adev);
417 mmhub_v2_0_init_cache_regs(adev);
418
419 mmhub_v2_0_enable_system_domain(adev);
420 mmhub_v2_0_disable_identity_aperture(adev);
421 mmhub_v2_0_setup_vmid_config(adev);
422 mmhub_v2_0_program_invalidation(adev);
423
424 return 0;
425 }
426
mmhub_v2_0_gart_disable(struct amdgpu_device * adev)427 static void mmhub_v2_0_gart_disable(struct amdgpu_device *adev)
428 {
429 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
430 u32 tmp;
431 u32 i;
432
433 /* Disable all tables */
434 for (i = 0; i < AMDGPU_NUM_VMID; i++)
435 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_CNTL,
436 i * hub->ctx_distance, 0);
437
438 /* Setup TLB control */
439 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
440 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
441 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
442 ENABLE_ADVANCED_DRIVER_MODEL, 0);
443 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
444
445 /* Setup L2 cache */
446 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
447 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
448 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
449 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, 0);
450 }
451
452 /**
453 * mmhub_v2_0_set_fault_enable_default - update GART/VM fault handling
454 *
455 * @adev: amdgpu_device pointer
456 * @value: true redirects VM faults to the default page
457 */
mmhub_v2_0_set_fault_enable_default(struct amdgpu_device * adev,bool value)458 static void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
459 {
460 u32 tmp;
461
462 /* These registers are not accessible to VF-SRIOV.
463 * The PF will program them instead.
464 */
465 if (amdgpu_sriov_vf(adev))
466 return;
467
468 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
469 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
470 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
471 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
472 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
473 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
474 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
475 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
476 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
477 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
478 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
479 value);
480 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
481 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
482 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
483 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
484 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
485 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
486 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
487 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
488 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
489 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
490 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
491 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
492 if (!value) {
493 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
494 CRASH_ON_NO_RETRY_FAULT, 1);
495 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
496 CRASH_ON_RETRY_FAULT, 1);
497 }
498 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
499 }
500
501 static const struct amdgpu_vmhub_funcs mmhub_v2_0_vmhub_funcs = {
502 .print_l2_protection_fault_status = mmhub_v2_0_print_l2_protection_fault_status,
503 .get_invalidate_req = mmhub_v2_0_get_invalidate_req,
504 };
505
mmhub_v2_0_init_client_info(struct amdgpu_device * adev)506 static void mmhub_v2_0_init_client_info(struct amdgpu_device *adev)
507 {
508 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
509 case IP_VERSION(2, 0, 0):
510 case IP_VERSION(2, 0, 2):
511 amdgpu_mmhub_init_client_info(&adev->mmhub,
512 mmhub_client_ids_navi1x,
513 ARRAY_SIZE(mmhub_client_ids_navi1x));
514 break;
515 case IP_VERSION(2, 1, 0):
516 case IP_VERSION(2, 1, 1):
517 amdgpu_mmhub_init_client_info(&adev->mmhub,
518 mmhub_client_ids_sienna_cichlid,
519 ARRAY_SIZE(mmhub_client_ids_sienna_cichlid));
520 break;
521 case IP_VERSION(2, 1, 2):
522 amdgpu_mmhub_init_client_info(&adev->mmhub,
523 mmhub_client_ids_beige_goby,
524 ARRAY_SIZE(mmhub_client_ids_beige_goby));
525 break;
526 default:
527 break;
528 }
529 }
530
mmhub_v2_0_init(struct amdgpu_device * adev)531 static void mmhub_v2_0_init(struct amdgpu_device *adev)
532 {
533 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
534
535 hub->ctx0_ptb_addr_lo32 =
536 SOC15_REG_OFFSET(MMHUB, 0,
537 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
538 hub->ctx0_ptb_addr_hi32 =
539 SOC15_REG_OFFSET(MMHUB, 0,
540 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
541 hub->vm_inv_eng0_sem =
542 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_SEM);
543 hub->vm_inv_eng0_req =
544 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ);
545 hub->vm_inv_eng0_ack =
546 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ACK);
547 hub->vm_context0_cntl =
548 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
549 hub->vm_l2_pro_fault_status =
550 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_STATUS);
551 hub->vm_l2_pro_fault_cntl =
552 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
553
554 hub->ctx_distance = mmMMVM_CONTEXT1_CNTL - mmMMVM_CONTEXT0_CNTL;
555 hub->ctx_addr_distance = mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
556 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
557 hub->eng_distance = mmMMVM_INVALIDATE_ENG1_REQ -
558 mmMMVM_INVALIDATE_ENG0_REQ;
559 hub->eng_addr_distance = mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
560 mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
561
562 hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
563 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
564 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
565 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
566 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
567 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
568 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
569
570 hub->vmhub_funcs = &mmhub_v2_0_vmhub_funcs;
571
572 mmhub_v2_0_init_client_info(adev);
573 }
574
mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)575 static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
576 bool enable)
577 {
578 uint32_t def, data, def1, data1;
579
580 if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
581 return;
582
583 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
584 case IP_VERSION(2, 1, 0):
585 case IP_VERSION(2, 1, 1):
586 case IP_VERSION(2, 1, 2):
587 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);
588 break;
589 default:
590 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
591 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
592 break;
593 }
594
595 if (enable) {
596 data |= MM_ATC_L2_MISC_CG__ENABLE_MASK;
597
598 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
599 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
600 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
601 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
602 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
603 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
604
605 } else {
606 data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK;
607
608 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
609 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
610 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
611 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
612 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
613 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
614 }
615
616 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
617 case IP_VERSION(2, 1, 0):
618 case IP_VERSION(2, 1, 1):
619 case IP_VERSION(2, 1, 2):
620 if (def1 != data1)
621 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid, data1);
622 break;
623 default:
624 if (def != data)
625 WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
626 if (def1 != data1)
627 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1);
628 break;
629 }
630 }
631
mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable)632 static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
633 bool enable)
634 {
635 uint32_t def, data;
636
637 if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
638 return;
639
640 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
641 case IP_VERSION(2, 1, 0):
642 case IP_VERSION(2, 1, 1):
643 case IP_VERSION(2, 1, 2):
644 /* There is no ATCL2 in MMHUB for 2.1.x */
645 return;
646 default:
647 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
648 break;
649 }
650
651 if (enable)
652 data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
653 else
654 data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
655
656 if (def != data)
657 WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
658 }
659
mmhub_v2_0_set_clockgating(struct amdgpu_device * adev,enum amd_clockgating_state state)660 static int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
661 enum amd_clockgating_state state)
662 {
663 if (amdgpu_sriov_vf(adev))
664 return 0;
665
666 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
667 case IP_VERSION(2, 0, 0):
668 case IP_VERSION(2, 0, 2):
669 case IP_VERSION(2, 1, 0):
670 case IP_VERSION(2, 1, 1):
671 case IP_VERSION(2, 1, 2):
672 mmhub_v2_0_update_medium_grain_clock_gating(adev,
673 state == AMD_CG_STATE_GATE);
674 mmhub_v2_0_update_medium_grain_light_sleep(adev,
675 state == AMD_CG_STATE_GATE);
676 break;
677 default:
678 break;
679 }
680
681 return 0;
682 }
683
mmhub_v2_0_get_clockgating(struct amdgpu_device * adev,u64 * flags)684 static void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u64 *flags)
685 {
686 u32 data, data1;
687
688 if (amdgpu_sriov_vf(adev))
689 *flags = 0;
690
691 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
692 case IP_VERSION(2, 1, 0):
693 case IP_VERSION(2, 1, 1):
694 case IP_VERSION(2, 1, 2):
695 /* There is no ATCL2 in MMHUB for 2.1.x. Keep the status
696 * based on DAGB
697 */
698 data = MM_ATC_L2_MISC_CG__ENABLE_MASK;
699 data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);
700 break;
701 default:
702 data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
703 data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
704 break;
705 }
706
707 /* AMD_CG_SUPPORT_MC_MGCG */
708 if ((data & MM_ATC_L2_MISC_CG__ENABLE_MASK) &&
709 !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
710 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
711 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
712 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
713 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
714 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
715 *flags |= AMD_CG_SUPPORT_MC_MGCG;
716
717 /* AMD_CG_SUPPORT_MC_LS */
718 if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
719 *flags |= AMD_CG_SUPPORT_MC_LS;
720 }
721
722 const struct amdgpu_mmhub_funcs mmhub_v2_0_funcs = {
723 .init = mmhub_v2_0_init,
724 .gart_enable = mmhub_v2_0_gart_enable,
725 .set_fault_enable_default = mmhub_v2_0_set_fault_enable_default,
726 .gart_disable = mmhub_v2_0_gart_disable,
727 .set_clockgating = mmhub_v2_0_set_clockgating,
728 .get_clockgating = mmhub_v2_0_get_clockgating,
729 .setup_vm_pt_regs = mmhub_v2_0_setup_vm_pt_regs,
730 };
731