1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include "amdgpu.h"
25 #include "mmhub_v2_0.h"
26
27 #include "mmhub/mmhub_2_0_0_offset.h"
28 #include "mmhub/mmhub_2_0_0_sh_mask.h"
29 #include "mmhub/mmhub_2_0_0_default.h"
30 #include "navi10_enum.h"
31
32 #include "gc/gc_10_1_0_offset.h"
33 #include "soc15_common.h"
34
35 #define mmDAGB0_CNTL_MISC2_Sienna_Cichlid 0x0070
36 #define mmDAGB0_CNTL_MISC2_Sienna_Cichlid_BASE_IDX 0
37
38 static const char *mmhub_client_ids_navi1x[][2] = {
39 [3][0] = "DCEDMC",
40 [4][0] = "DCEVGA",
41 [5][0] = "MP0",
42 [6][0] = "MP1",
43 [13][0] = "VMC",
44 [14][0] = "HDP",
45 [15][0] = "OSS",
46 [16][0] = "VCNU",
47 [17][0] = "JPEG",
48 [18][0] = "VCN",
49 [3][1] = "DCEDMC",
50 [4][1] = "DCEXFC",
51 [5][1] = "DCEVGA",
52 [6][1] = "DCEDWB",
53 [7][1] = "MP0",
54 [8][1] = "MP1",
55 [9][1] = "DBGU1",
56 [10][1] = "DBGU0",
57 [11][1] = "XDP",
58 [14][1] = "HDP",
59 [15][1] = "OSS",
60 [16][1] = "VCNU",
61 [17][1] = "JPEG",
62 [18][1] = "VCN",
63 };
64
65 static const char *mmhub_client_ids_sienna_cichlid[][2] = {
66 [3][0] = "DCEDMC",
67 [4][0] = "DCEVGA",
68 [5][0] = "MP0",
69 [6][0] = "MP1",
70 [8][0] = "VMC",
71 [9][0] = "VCNU0",
72 [10][0] = "JPEG",
73 [12][0] = "VCNU1",
74 [13][0] = "VCN1",
75 [14][0] = "HDP",
76 [15][0] = "OSS",
77 [32+11][0] = "VCN0",
78 [0][1] = "DBGU0",
79 [1][1] = "DBGU1",
80 [2][1] = "DCEDWB",
81 [3][1] = "DCEDMC",
82 [4][1] = "DCEVGA",
83 [5][1] = "MP0",
84 [6][1] = "MP1",
85 [7][1] = "XDP",
86 [9][1] = "VCNU0",
87 [10][1] = "JPEG",
88 [11][1] = "VCN0",
89 [12][1] = "VCNU1",
90 [13][1] = "VCN1",
91 [14][1] = "HDP",
92 [15][1] = "OSS",
93 };
94
95 static const char *mmhub_client_ids_beige_goby[][2] = {
96 [3][0] = "DCEDMC",
97 [4][0] = "DCEVGA",
98 [5][0] = "MP0",
99 [6][0] = "MP1",
100 [8][0] = "VMC",
101 [9][0] = "VCNU0",
102 [11][0] = "VCN0",
103 [14][0] = "HDP",
104 [15][0] = "OSS",
105 [0][1] = "DBGU0",
106 [1][1] = "DBGU1",
107 [2][1] = "DCEDWB",
108 [3][1] = "DCEDMC",
109 [4][1] = "DCEVGA",
110 [5][1] = "MP0",
111 [6][1] = "MP1",
112 [7][1] = "XDP",
113 [9][1] = "VCNU0",
114 [11][1] = "VCN0",
115 [14][1] = "HDP",
116 [15][1] = "OSS",
117 };
118
mmhub_v2_0_get_invalidate_req(unsigned int vmid,uint32_t flush_type)119 static uint32_t mmhub_v2_0_get_invalidate_req(unsigned int vmid,
120 uint32_t flush_type)
121 {
122 u32 req = 0;
123
124 /* invalidate using legacy mode on vmid*/
125 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
126 PER_VMID_INVALIDATE_REQ, 1 << vmid);
127 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
128 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
129 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
130 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
131 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
132 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
133 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
134 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
135
136 return req;
137 }
138
139 static void
mmhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device * adev,uint32_t status)140 mmhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
141 uint32_t status)
142 {
143 uint32_t cid, rw;
144 const char *mmhub_cid = NULL;
145
146 cid = REG_GET_FIELD(status,
147 MMVM_L2_PROTECTION_FAULT_STATUS, CID);
148 rw = REG_GET_FIELD(status,
149 MMVM_L2_PROTECTION_FAULT_STATUS, RW);
150
151 dev_err(adev->dev,
152 "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
153 status);
154 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
155 case IP_VERSION(2, 0, 0):
156 case IP_VERSION(2, 0, 2):
157 mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_navi1x) ?
158 mmhub_client_ids_navi1x[cid][rw] : NULL;
159 break;
160 case IP_VERSION(2, 1, 0):
161 case IP_VERSION(2, 1, 1):
162 mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_sienna_cichlid) ?
163 mmhub_client_ids_sienna_cichlid[cid][rw] : NULL;
164 break;
165 case IP_VERSION(2, 1, 2):
166 mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_beige_goby) ?
167 mmhub_client_ids_beige_goby[cid][rw] : NULL;
168 break;
169 default:
170 mmhub_cid = NULL;
171 break;
172 }
173 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
174 mmhub_cid ? mmhub_cid : "unknown", cid);
175 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
176 REG_GET_FIELD(status,
177 MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
178 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
179 REG_GET_FIELD(status,
180 MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
181 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
182 REG_GET_FIELD(status,
183 MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
184 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
185 REG_GET_FIELD(status,
186 MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
187 dev_err(adev->dev, "\t RW: 0x%x\n", rw);
188 }
189
mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device * adev,uint32_t vmid,uint64_t page_table_base)190 static void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
191 uint64_t page_table_base)
192 {
193 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
194
195 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
196 hub->ctx_addr_distance * vmid,
197 lower_32_bits(page_table_base));
198
199 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
200 hub->ctx_addr_distance * vmid,
201 upper_32_bits(page_table_base));
202 }
203
mmhub_v2_0_init_gart_aperture_regs(struct amdgpu_device * adev)204 static void mmhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev)
205 {
206 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
207
208 mmhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base);
209
210 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
211 (u32)(adev->gmc.gart_start >> 12));
212 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
213 (u32)(adev->gmc.gart_start >> 44));
214
215 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
216 (u32)(adev->gmc.gart_end >> 12));
217 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
218 (u32)(adev->gmc.gart_end >> 44));
219 }
220
mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device * adev)221 static void mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev)
222 {
223 uint64_t value;
224 uint32_t tmp;
225
226 if (!amdgpu_sriov_vf(adev)) {
227 /* Program the AGP BAR */
228 WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);
229 WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
230 WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
231
232 /* Program the system aperture low logical page number. */
233 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
234 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
235 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
236 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
237 }
238
239 /* Set default page address. */
240 value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
241 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
242 (u32)(value >> 12));
243 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
244 (u32)(value >> 44));
245
246 /* Program "protection fault". */
247 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
248 (u32)(adev->dummy_page_addr >> 12));
249 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
250 (u32)((u64)adev->dummy_page_addr >> 44));
251
252 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2);
253 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
254 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
255 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
256 }
257
mmhub_v2_0_init_tlb_regs(struct amdgpu_device * adev)258 static void mmhub_v2_0_init_tlb_regs(struct amdgpu_device *adev)
259 {
260 uint32_t tmp;
261
262 /* Setup TLB control */
263 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
264
265 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
266 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
267 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
268 ENABLE_ADVANCED_DRIVER_MODEL, 1);
269 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
270 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
271 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
272 MTYPE, MTYPE_UC); /* UC, uncached */
273
274 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
275 }
276
mmhub_v2_0_init_cache_regs(struct amdgpu_device * adev)277 static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
278 {
279 uint32_t tmp;
280
281 /* These registers are not accessible to VF-SRIOV.
282 * The PF will program them instead.
283 */
284 if (amdgpu_sriov_vf(adev))
285 return;
286
287 /* Setup L2 cache */
288 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
289 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
290 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
291 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
292 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
293 /* XXX for emulation, Refer to closed source code.*/
294 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
295 0);
296 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
297 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
298 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
299 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
300
301 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2);
302 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
303 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
304 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp);
305
306 tmp = mmMMVM_L2_CNTL3_DEFAULT;
307 if (adev->gmc.translate_further) {
308 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
309 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
310 L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
311 } else {
312 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
313 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
314 L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
315 }
316 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp);
317
318 tmp = mmMMVM_L2_CNTL4_DEFAULT;
319 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
320 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
321 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL4, tmp);
322
323 tmp = mmMMVM_L2_CNTL5_DEFAULT;
324 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
325 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL5, tmp);
326 }
327
mmhub_v2_0_enable_system_domain(struct amdgpu_device * adev)328 static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev)
329 {
330 uint32_t tmp;
331
332 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
333 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
334 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
335 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
336 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
337 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp);
338 }
339
mmhub_v2_0_disable_identity_aperture(struct amdgpu_device * adev)340 static void mmhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev)
341 {
342 /* These registers are not accessible to VF-SRIOV.
343 * The PF will program them instead.
344 */
345 if (amdgpu_sriov_vf(adev))
346 return;
347
348 WREG32_SOC15(MMHUB, 0,
349 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
350 0xFFFFFFFF);
351 WREG32_SOC15(MMHUB, 0,
352 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
353 0x0000000F);
354
355 WREG32_SOC15(MMHUB, 0,
356 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
357 WREG32_SOC15(MMHUB, 0,
358 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
359
360 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
361 0);
362 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
363 0);
364 }
365
mmhub_v2_0_setup_vmid_config(struct amdgpu_device * adev)366 static void mmhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
367 {
368 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
369 int i;
370 uint32_t tmp;
371
372 for (i = 0; i <= 14; i++) {
373 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i * hub->ctx_distance);
374 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
375 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
376 adev->vm_manager.num_level);
377 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
378 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
379 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
380 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
381 1);
382 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
383 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
384 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
385 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
386 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
387 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
388 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
389 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
390 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
391 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
392 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
393 PAGE_TABLE_BLOCK_SIZE,
394 adev->vm_manager.block_size - 9);
395 /* Send no-retry XNACK on fault to suppress VM fault storm. */
396 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
397 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
398 !adev->gmc.noretry);
399 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_CNTL,
400 i * hub->ctx_distance, tmp);
401 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
402 i * hub->ctx_addr_distance, 0);
403 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
404 i * hub->ctx_addr_distance, 0);
405 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
406 i * hub->ctx_addr_distance,
407 lower_32_bits(adev->vm_manager.max_pfn - 1));
408 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
409 i * hub->ctx_addr_distance,
410 upper_32_bits(adev->vm_manager.max_pfn - 1));
411 }
412
413 hub->vm_cntx_cntl = tmp;
414 }
415
mmhub_v2_0_program_invalidation(struct amdgpu_device * adev)416 static void mmhub_v2_0_program_invalidation(struct amdgpu_device *adev)
417 {
418 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
419 unsigned i;
420
421 for (i = 0; i < 18; ++i) {
422 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
423 i * hub->eng_addr_distance, 0xffffffff);
424 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
425 i * hub->eng_addr_distance, 0x1f);
426 }
427 }
428
mmhub_v2_0_gart_enable(struct amdgpu_device * adev)429 static int mmhub_v2_0_gart_enable(struct amdgpu_device *adev)
430 {
431 /* GART Enable. */
432 mmhub_v2_0_init_gart_aperture_regs(adev);
433 mmhub_v2_0_init_system_aperture_regs(adev);
434 mmhub_v2_0_init_tlb_regs(adev);
435 mmhub_v2_0_init_cache_regs(adev);
436
437 mmhub_v2_0_enable_system_domain(adev);
438 mmhub_v2_0_disable_identity_aperture(adev);
439 mmhub_v2_0_setup_vmid_config(adev);
440 mmhub_v2_0_program_invalidation(adev);
441
442 return 0;
443 }
444
mmhub_v2_0_gart_disable(struct amdgpu_device * adev)445 static void mmhub_v2_0_gart_disable(struct amdgpu_device *adev)
446 {
447 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
448 u32 tmp;
449 u32 i;
450
451 /* Disable all tables */
452 for (i = 0; i < AMDGPU_NUM_VMID; i++)
453 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_CNTL,
454 i * hub->ctx_distance, 0);
455
456 /* Setup TLB control */
457 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
458 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
459 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
460 ENABLE_ADVANCED_DRIVER_MODEL, 0);
461 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
462
463 /* Setup L2 cache */
464 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
465 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
466 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
467 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, 0);
468 }
469
470 /**
471 * mmhub_v2_0_set_fault_enable_default - update GART/VM fault handling
472 *
473 * @adev: amdgpu_device pointer
474 * @value: true redirects VM faults to the default page
475 */
mmhub_v2_0_set_fault_enable_default(struct amdgpu_device * adev,bool value)476 static void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
477 {
478 u32 tmp;
479
480 /* These registers are not accessible to VF-SRIOV.
481 * The PF will program them instead.
482 */
483 if (amdgpu_sriov_vf(adev))
484 return;
485
486 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
487 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
488 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
489 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
490 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
491 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
492 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
493 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
494 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
495 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
496 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
497 value);
498 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
499 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
500 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
501 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
502 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
503 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
504 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
505 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
506 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
507 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
508 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
509 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
510 if (!value) {
511 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
512 CRASH_ON_NO_RETRY_FAULT, 1);
513 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
514 CRASH_ON_RETRY_FAULT, 1);
515 }
516 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
517 }
518
519 static const struct amdgpu_vmhub_funcs mmhub_v2_0_vmhub_funcs = {
520 .print_l2_protection_fault_status = mmhub_v2_0_print_l2_protection_fault_status,
521 .get_invalidate_req = mmhub_v2_0_get_invalidate_req,
522 };
523
mmhub_v2_0_init(struct amdgpu_device * adev)524 static void mmhub_v2_0_init(struct amdgpu_device *adev)
525 {
526 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
527
528 hub->ctx0_ptb_addr_lo32 =
529 SOC15_REG_OFFSET(MMHUB, 0,
530 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
531 hub->ctx0_ptb_addr_hi32 =
532 SOC15_REG_OFFSET(MMHUB, 0,
533 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
534 hub->vm_inv_eng0_sem =
535 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_SEM);
536 hub->vm_inv_eng0_req =
537 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ);
538 hub->vm_inv_eng0_ack =
539 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ACK);
540 hub->vm_context0_cntl =
541 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
542 hub->vm_l2_pro_fault_status =
543 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_STATUS);
544 hub->vm_l2_pro_fault_cntl =
545 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
546
547 hub->ctx_distance = mmMMVM_CONTEXT1_CNTL - mmMMVM_CONTEXT0_CNTL;
548 hub->ctx_addr_distance = mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
549 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
550 hub->eng_distance = mmMMVM_INVALIDATE_ENG1_REQ -
551 mmMMVM_INVALIDATE_ENG0_REQ;
552 hub->eng_addr_distance = mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
553 mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
554
555 hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
556 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
557 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
558 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
559 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
560 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
561 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
562
563 hub->vmhub_funcs = &mmhub_v2_0_vmhub_funcs;
564 }
565
mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)566 static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
567 bool enable)
568 {
569 uint32_t def, data, def1, data1;
570
571 if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
572 return;
573
574 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
575 case IP_VERSION(2, 1, 0):
576 case IP_VERSION(2, 1, 1):
577 case IP_VERSION(2, 1, 2):
578 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);
579 break;
580 default:
581 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
582 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
583 break;
584 }
585
586 if (enable) {
587 data |= MM_ATC_L2_MISC_CG__ENABLE_MASK;
588
589 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
590 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
591 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
592 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
593 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
594 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
595
596 } else {
597 data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK;
598
599 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
600 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
601 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
602 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
603 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
604 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
605 }
606
607 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
608 case IP_VERSION(2, 1, 0):
609 case IP_VERSION(2, 1, 1):
610 case IP_VERSION(2, 1, 2):
611 if (def1 != data1)
612 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid, data1);
613 break;
614 default:
615 if (def != data)
616 WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
617 if (def1 != data1)
618 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1);
619 break;
620 }
621 }
622
mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable)623 static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
624 bool enable)
625 {
626 uint32_t def, data;
627
628 if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
629 return;
630
631 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
632 case IP_VERSION(2, 1, 0):
633 case IP_VERSION(2, 1, 1):
634 case IP_VERSION(2, 1, 2):
635 /* There is no ATCL2 in MMHUB for 2.1.x */
636 return;
637 default:
638 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
639 break;
640 }
641
642 if (enable)
643 data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
644 else
645 data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
646
647 if (def != data)
648 WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
649 }
650
mmhub_v2_0_set_clockgating(struct amdgpu_device * adev,enum amd_clockgating_state state)651 static int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
652 enum amd_clockgating_state state)
653 {
654 if (amdgpu_sriov_vf(adev))
655 return 0;
656
657 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
658 case IP_VERSION(2, 0, 0):
659 case IP_VERSION(2, 0, 2):
660 case IP_VERSION(2, 1, 0):
661 case IP_VERSION(2, 1, 1):
662 case IP_VERSION(2, 1, 2):
663 mmhub_v2_0_update_medium_grain_clock_gating(adev,
664 state == AMD_CG_STATE_GATE);
665 mmhub_v2_0_update_medium_grain_light_sleep(adev,
666 state == AMD_CG_STATE_GATE);
667 break;
668 default:
669 break;
670 }
671
672 return 0;
673 }
674
mmhub_v2_0_get_clockgating(struct amdgpu_device * adev,u64 * flags)675 static void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u64 *flags)
676 {
677 u32 data, data1;
678
679 if (amdgpu_sriov_vf(adev))
680 *flags = 0;
681
682 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
683 case IP_VERSION(2, 1, 0):
684 case IP_VERSION(2, 1, 1):
685 case IP_VERSION(2, 1, 2):
686 /* There is no ATCL2 in MMHUB for 2.1.x. Keep the status
687 * based on DAGB
688 */
689 data = MM_ATC_L2_MISC_CG__ENABLE_MASK;
690 data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);
691 break;
692 default:
693 data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
694 data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
695 break;
696 }
697
698 /* AMD_CG_SUPPORT_MC_MGCG */
699 if ((data & MM_ATC_L2_MISC_CG__ENABLE_MASK) &&
700 !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
701 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
702 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
703 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
704 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
705 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
706 *flags |= AMD_CG_SUPPORT_MC_MGCG;
707
708 /* AMD_CG_SUPPORT_MC_LS */
709 if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
710 *flags |= AMD_CG_SUPPORT_MC_LS;
711 }
712
713 const struct amdgpu_mmhub_funcs mmhub_v2_0_funcs = {
714 .init = mmhub_v2_0_init,
715 .gart_enable = mmhub_v2_0_gart_enable,
716 .set_fault_enable_default = mmhub_v2_0_set_fault_enable_default,
717 .gart_disable = mmhub_v2_0_gart_disable,
718 .set_clockgating = mmhub_v2_0_set_clockgating,
719 .get_clockgating = mmhub_v2_0_get_clockgating,
720 .setup_vm_pt_regs = mmhub_v2_0_setup_vm_pt_regs,
721 };
722