1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020, Martin Botka <martin.botka@somainline.org>
5 * Copyright (c) 2020, Konrad Dybcio <konrad.dybcio@somainline.org>
6 */
7
8 #include <linux/kernel.h>
9 #include <linux/bitops.h>
10 #include <linux/err.h>
11 #include <linux/platform_device.h>
12 #include <linux/module.h>
13 #include <linux/clk-provider.h>
14 #include <linux/regmap.h>
15
16 #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
17
18 #include "common.h"
19 #include "clk-regmap.h"
20 #include "clk-regmap-divider.h"
21 #include "clk-alpha-pll.h"
22 #include "clk-rcg.h"
23 #include "clk-branch.h"
24 #include "reset.h"
25 #include "gdsc.h"
26
27 enum {
28 P_XO,
29 P_DSI0PLL_BYTE,
30 P_DSI0PLL,
31 P_DSI1PLL_BYTE,
32 P_DSI1PLL,
33 P_GPLL0,
34 P_GPLL0_DIV,
35 P_MMPLL0,
36 P_MMPLL10,
37 P_MMPLL3,
38 P_MMPLL4,
39 P_MMPLL5,
40 P_MMPLL6,
41 P_MMPLL7,
42 P_MMPLL8,
43 P_SLEEP_CLK,
44 P_DP_PHY_PLL_LINK_CLK,
45 P_DP_PHY_PLL_VCO_DIV,
46 };
47
48 static const struct parent_map mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div_map[] = {
49 { P_XO, 0 },
50 { P_MMPLL0, 1 },
51 { P_MMPLL4, 2 },
52 { P_MMPLL7, 3 },
53 { P_MMPLL8, 4 },
54 { P_GPLL0, 5 },
55 { P_GPLL0_DIV, 6 },
56 };
57
58 /* Voteable PLL */
59 static struct clk_alpha_pll mmpll0 = {
60 .offset = 0xc000,
61 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
62 .clkr = {
63 .enable_reg = 0x1f0,
64 .enable_mask = BIT(0),
65 .hw.init = &(struct clk_init_data){
66 .name = "mmpll0",
67 .parent_data = &(const struct clk_parent_data){
68 .fw_name = "xo",
69 },
70 .num_parents = 1,
71 .ops = &clk_alpha_pll_ops,
72 },
73 },
74 };
75
76 static struct clk_alpha_pll mmpll6 = {
77 .offset = 0xf0,
78 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
79 .clkr = {
80 .enable_reg = 0x1f0,
81 .enable_mask = BIT(2),
82 .hw.init = &(struct clk_init_data){
83 .name = "mmpll6",
84 .parent_data = &(const struct clk_parent_data){
85 .fw_name = "xo",
86 },
87 .num_parents = 1,
88 .ops = &clk_alpha_pll_ops,
89 },
90 },
91 };
92
93 /* APSS controlled PLLs */
94 static const struct pll_vco vco[] = {
95 { 1000000000, 2000000000, 0 },
96 { 750000000, 1500000000, 1 },
97 { 500000000, 1000000000, 2 },
98 { 250000000, 500000000, 3 },
99 };
100
101 static const struct pll_vco mmpll3_vco[] = {
102 { 750000000, 1500000000, 1 },
103 };
104
105 static const struct alpha_pll_config mmpll10_config = {
106 .l = 0x1e,
107 .config_ctl_val = 0x00004289,
108 .main_output_mask = 0x1,
109 };
110
111 static struct clk_alpha_pll mmpll10 = {
112 .offset = 0x190,
113 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
114 .clkr = {
115 .hw.init = &(struct clk_init_data){
116 .name = "mmpll10",
117 .parent_data = &(const struct clk_parent_data){
118 .fw_name = "xo",
119 },
120 .num_parents = 1,
121 .ops = &clk_alpha_pll_ops,
122 },
123 },
124 };
125
126 static const struct alpha_pll_config mmpll3_config = {
127 .l = 0x2e,
128 .config_ctl_val = 0x4001055b,
129 .vco_val = 0x1 << 20,
130 .vco_mask = 0x3 << 20,
131 .main_output_mask = 0x1,
132 };
133
134 static struct clk_alpha_pll mmpll3 = {
135 .offset = 0x0,
136 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
137 .vco_table = mmpll3_vco,
138 .num_vco = ARRAY_SIZE(mmpll3_vco),
139 .clkr = {
140 .hw.init = &(struct clk_init_data){
141 .name = "mmpll3",
142 .parent_data = &(const struct clk_parent_data){
143 .fw_name = "xo",
144 },
145 .num_parents = 1,
146 .ops = &clk_alpha_pll_ops,
147 },
148 },
149 };
150
151 static const struct alpha_pll_config mmpll4_config = {
152 .l = 0x28,
153 .config_ctl_val = 0x4001055b,
154 .vco_val = 0x2 << 20,
155 .vco_mask = 0x3 << 20,
156 .main_output_mask = 0x1,
157 };
158
159 static struct clk_alpha_pll mmpll4 = {
160 .offset = 0x50,
161 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
162 .vco_table = vco,
163 .num_vco = ARRAY_SIZE(vco),
164 .clkr = {
165 .hw.init = &(struct clk_init_data){
166 .name = "mmpll4",
167 .parent_data = &(const struct clk_parent_data){
168 .fw_name = "xo",
169 },
170 .num_parents = 1,
171 .ops = &clk_alpha_pll_ops,
172 },
173 },
174 };
175
176 static const struct alpha_pll_config mmpll5_config = {
177 .l = 0x2a,
178 .config_ctl_val = 0x4001055b,
179 .alpha_hi = 0xf8,
180 .alpha_en_mask = BIT(24),
181 .vco_val = 0x2 << 20,
182 .vco_mask = 0x3 << 20,
183 .main_output_mask = 0x1,
184 };
185
186 static struct clk_alpha_pll mmpll5 = {
187 .offset = 0xa0,
188 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
189 .vco_table = vco,
190 .num_vco = ARRAY_SIZE(vco),
191 .clkr = {
192 .hw.init = &(struct clk_init_data){
193 .name = "mmpll5",
194 .parent_data = &(const struct clk_parent_data){
195 .fw_name = "xo",
196 },
197 .num_parents = 1,
198 .ops = &clk_alpha_pll_ops,
199 },
200 },
201 };
202
203 static const struct alpha_pll_config mmpll7_config = {
204 .l = 0x32,
205 .config_ctl_val = 0x4001055b,
206 .vco_val = 0x2 << 20,
207 .vco_mask = 0x3 << 20,
208 .main_output_mask = 0x1,
209 };
210
211 static struct clk_alpha_pll mmpll7 = {
212 .offset = 0x140,
213 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
214 .vco_table = vco,
215 .num_vco = ARRAY_SIZE(vco),
216 .clkr = {
217 .hw.init = &(struct clk_init_data){
218 .name = "mmpll7",
219 .parent_data = &(const struct clk_parent_data){
220 .fw_name = "xo",
221 },
222 .num_parents = 1,
223 .ops = &clk_alpha_pll_ops,
224 },
225 },
226 };
227
228 static const struct alpha_pll_config mmpll8_config = {
229 .l = 0x30,
230 .alpha_hi = 0x70,
231 .alpha_en_mask = BIT(24),
232 .config_ctl_val = 0x4001055b,
233 .vco_val = 0x2 << 20,
234 .vco_mask = 0x3 << 20,
235 .main_output_mask = 0x1,
236 };
237
238 static struct clk_alpha_pll mmpll8 = {
239 .offset = 0x1c0,
240 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
241 .vco_table = vco,
242 .num_vco = ARRAY_SIZE(vco),
243 .clkr = {
244 .hw.init = &(struct clk_init_data){
245 .name = "mmpll8",
246 .parent_data = &(const struct clk_parent_data){
247 .fw_name = "xo",
248 },
249 .num_parents = 1,
250 .ops = &clk_alpha_pll_ops,
251 },
252 },
253 };
254
255 static const struct clk_parent_data mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div[] = {
256 { .fw_name = "xo" },
257 { .hw = &mmpll0.clkr.hw },
258 { .hw = &mmpll4.clkr.hw },
259 { .hw = &mmpll7.clkr.hw },
260 { .hw = &mmpll8.clkr.hw },
261 { .fw_name = "gpll0" },
262 { .fw_name = "gpll0_div" },
263 };
264
265 static const struct parent_map mmcc_xo_dsibyte_map[] = {
266 { P_XO, 0 },
267 { P_DSI0PLL_BYTE, 1 },
268 { P_DSI1PLL_BYTE, 2 },
269 };
270
271 static const struct clk_parent_data mmcc_xo_dsibyte[] = {
272 { .fw_name = "xo" },
273 { .fw_name = "dsi0pllbyte" },
274 { .fw_name = "dsi1pllbyte" },
275 };
276
277 static const struct parent_map mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
278 { P_XO, 0 },
279 { P_MMPLL0, 1 },
280 { P_MMPLL4, 2 },
281 { P_MMPLL7, 3 },
282 { P_MMPLL10, 4 },
283 { P_GPLL0, 5 },
284 { P_GPLL0_DIV, 6 },
285 };
286
287 static const struct clk_parent_data mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div[] = {
288 { .fw_name = "xo" },
289 { .hw = &mmpll0.clkr.hw },
290 { .hw = &mmpll4.clkr.hw },
291 { .hw = &mmpll7.clkr.hw },
292 { .hw = &mmpll10.clkr.hw },
293 { .fw_name = "gpll0" },
294 { .fw_name = "gpll0_div" },
295 };
296
297 static const struct parent_map mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map[] = {
298 { P_XO, 0 },
299 { P_MMPLL4, 1 },
300 { P_MMPLL7, 2 },
301 { P_MMPLL10, 3 },
302 { P_SLEEP_CLK, 4 },
303 { P_GPLL0, 5 },
304 { P_GPLL0_DIV, 6 },
305 };
306
307 static const struct clk_parent_data mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div[] = {
308 { .fw_name = "xo" },
309 { .hw = &mmpll4.clkr.hw },
310 { .hw = &mmpll7.clkr.hw },
311 { .hw = &mmpll10.clkr.hw },
312 { .fw_name = "sleep_clk" },
313 { .fw_name = "gpll0" },
314 { .fw_name = "gpll0_div" },
315 };
316
317 static const struct parent_map mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map[] = {
318 { P_XO, 0 },
319 { P_MMPLL0, 1 },
320 { P_MMPLL7, 2 },
321 { P_MMPLL10, 3 },
322 { P_SLEEP_CLK, 4 },
323 { P_GPLL0, 5 },
324 { P_GPLL0_DIV, 6 },
325 };
326
327 static const struct clk_parent_data mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div[] = {
328 { .fw_name = "xo" },
329 { .hw = &mmpll0.clkr.hw },
330 { .hw = &mmpll7.clkr.hw },
331 { .hw = &mmpll10.clkr.hw },
332 { .fw_name = "sleep_clk" },
333 { .fw_name = "gpll0" },
334 { .fw_name = "gpll0_div" },
335 };
336
337 static const struct parent_map mmcc_xo_gpll0_gpll0_div_map[] = {
338 { P_XO, 0 },
339 { P_GPLL0, 5 },
340 { P_GPLL0_DIV, 6 },
341 };
342
343 static const struct clk_parent_data mmcc_xo_gpll0_gpll0_div[] = {
344 { .fw_name = "xo" },
345 { .fw_name = "gpll0" },
346 { .fw_name = "gpll0_div" },
347 };
348
349 static const struct parent_map mmcc_xo_dplink_dpvco_map[] = {
350 { P_XO, 0 },
351 { P_DP_PHY_PLL_LINK_CLK, 1 },
352 { P_DP_PHY_PLL_VCO_DIV, 2 },
353 };
354
355 static const struct clk_parent_data mmcc_xo_dplink_dpvco[] = {
356 { .fw_name = "xo" },
357 { .fw_name = "dp_link_2x_clk_divsel_five" },
358 { .fw_name = "dp_vco_divided_clk_src_mux" },
359 };
360
361 static const struct parent_map mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div_map[] = {
362 { P_XO, 0 },
363 { P_MMPLL0, 1 },
364 { P_MMPLL5, 2 },
365 { P_MMPLL7, 3 },
366 { P_GPLL0, 5 },
367 { P_GPLL0_DIV, 6 },
368 };
369
370 static const struct clk_parent_data mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div[] = {
371 { .fw_name = "xo" },
372 { .hw = &mmpll0.clkr.hw },
373 { .hw = &mmpll5.clkr.hw },
374 { .hw = &mmpll7.clkr.hw },
375 { .fw_name = "gpll0" },
376 { .fw_name = "gpll0_div" },
377 };
378
379 static const struct parent_map mmcc_xo_dsi0pll_dsi1pll_map[] = {
380 { P_XO, 0 },
381 { P_DSI0PLL, 1 },
382 { P_DSI1PLL, 2 },
383 };
384
385 static const struct clk_parent_data mmcc_xo_dsi0pll_dsi1pll[] = {
386 { .fw_name = "xo" },
387 { .fw_name = "dsi0pll" },
388 { .fw_name = "dsi1pll" },
389 };
390
391 static const struct parent_map mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0_map[] = {
392 { P_XO, 0 },
393 { P_MMPLL0, 1 },
394 { P_MMPLL4, 2 },
395 { P_MMPLL7, 3 },
396 { P_MMPLL10, 4 },
397 { P_MMPLL6, 5 },
398 { P_GPLL0, 6 },
399 };
400
401 static const struct clk_parent_data mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0[] = {
402 { .fw_name = "xo" },
403 { .hw = &mmpll0.clkr.hw },
404 { .hw = &mmpll4.clkr.hw },
405 { .hw = &mmpll7.clkr.hw },
406 { .hw = &mmpll10.clkr.hw },
407 { .hw = &mmpll6.clkr.hw },
408 { .fw_name = "gpll0" },
409 };
410
411 static const struct parent_map mmcc_xo_mmpll0_gpll0_gpll0_div_map[] = {
412 { P_XO, 0 },
413 { P_MMPLL0, 1 },
414 { P_GPLL0, 5 },
415 { P_GPLL0_DIV, 6 },
416 };
417
418 static const struct clk_parent_data mmcc_xo_mmpll0_gpll0_gpll0_div[] = {
419 { .fw_name = "xo" },
420 { .hw = &mmpll0.clkr.hw },
421 { .fw_name = "gpll0" },
422 { .fw_name = "gpll0_div" },
423 };
424
425 static const struct parent_map mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_mmpll6_map[] = {
426 { P_XO, 0 },
427 { P_MMPLL0, 1 },
428 { P_MMPLL4, 2 },
429 { P_MMPLL7, 3 },
430 { P_MMPLL10, 4 },
431 { P_GPLL0, 5 },
432 { P_MMPLL6, 6 },
433 };
434
435 static const struct clk_parent_data mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_mmpll6[] = {
436 { .fw_name = "xo" },
437 { .hw = &mmpll0.clkr.hw },
438 { .hw = &mmpll4.clkr.hw },
439 { .hw = &mmpll7.clkr.hw },
440 { .hw = &mmpll10.clkr.hw },
441 { .fw_name = "gpll0" },
442 { .hw = &mmpll6.clkr.hw },
443 };
444
445 static const struct parent_map mmcc_xo_mmpll0_mmpll8_mmpll3_mmpll6_gpll0_mmpll7_map[] = {
446 { P_XO, 0 },
447 { P_MMPLL0, 1 },
448 { P_MMPLL8, 2 },
449 { P_MMPLL3, 3 },
450 { P_MMPLL6, 4 },
451 { P_GPLL0, 5 },
452 { P_MMPLL7, 6 },
453 };
454
455 static const struct clk_parent_data mmcc_xo_mmpll0_mmpll8_mmpll3_mmpll6_gpll0_mmpll7[] = {
456 { .fw_name = "xo" },
457 { .hw = &mmpll0.clkr.hw },
458 { .hw = &mmpll8.clkr.hw },
459 { .hw = &mmpll3.clkr.hw },
460 { .hw = &mmpll6.clkr.hw },
461 { .fw_name = "gpll0" },
462 { .hw = &mmpll7.clkr.hw },
463 };
464
465 static const struct freq_tbl ftbl_ahb_clk_src[] = {
466 F(19200000, P_XO, 1, 0, 0),
467 F(40000000, P_GPLL0_DIV, 7.5, 0, 0),
468 F(80800000, P_MMPLL0, 10, 0, 0),
469 { }
470 };
471
472 static struct clk_rcg2 ahb_clk_src = {
473 .cmd_rcgr = 0x5000,
474 .mnd_width = 0,
475 .hid_width = 5,
476 .parent_map = mmcc_xo_mmpll0_gpll0_gpll0_div_map,
477 .freq_tbl = ftbl_ahb_clk_src,
478 .clkr.hw.init = &(struct clk_init_data){
479 .name = "ahb_clk_src",
480 .parent_data = mmcc_xo_mmpll0_gpll0_gpll0_div,
481 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_gpll0_gpll0_div),
482 .ops = &clk_rcg2_ops,
483 },
484 };
485
486 static struct clk_rcg2 byte0_clk_src = {
487 .cmd_rcgr = 0x2120,
488 .mnd_width = 0,
489 .hid_width = 5,
490 .parent_map = mmcc_xo_dsibyte_map,
491 .clkr.hw.init = &(struct clk_init_data){
492 .name = "byte0_clk_src",
493 .parent_data = mmcc_xo_dsibyte,
494 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
495 .ops = &clk_byte2_ops,
496 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
497 },
498 };
499
500 static struct clk_rcg2 byte1_clk_src = {
501 .cmd_rcgr = 0x2140,
502 .mnd_width = 0,
503 .hid_width = 5,
504 .parent_map = mmcc_xo_dsibyte_map,
505 .clkr.hw.init = &(struct clk_init_data){
506 .name = "byte1_clk_src",
507 .parent_data = mmcc_xo_dsibyte,
508 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
509 .ops = &clk_byte2_ops,
510 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
511 },
512 };
513
514 static const struct freq_tbl ftbl_camss_gp0_clk_src[] = {
515 F(10000, P_XO, 16, 1, 120),
516 F(24000, P_XO, 16, 1, 50),
517 F(6000000, P_GPLL0_DIV, 10, 1, 5),
518 F(12000000, P_GPLL0_DIV, 10, 2, 5),
519 F(13043478, P_GPLL0_DIV, 1, 1, 23),
520 F(24000000, P_GPLL0_DIV, 1, 2, 25),
521 F(50000000, P_GPLL0_DIV, 6, 0, 0),
522 F(100000000, P_GPLL0_DIV, 3, 0, 0),
523 F(200000000, P_GPLL0, 3, 0, 0),
524 { }
525 };
526
527 static struct clk_rcg2 camss_gp0_clk_src = {
528 .cmd_rcgr = 0x3420,
529 .mnd_width = 8,
530 .hid_width = 5,
531 .parent_map = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map,
532 .freq_tbl = ftbl_camss_gp0_clk_src,
533 .clkr.hw.init = &(struct clk_init_data){
534 .name = "camss_gp0_clk_src",
535 .parent_data = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div,
536 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div),
537 .ops = &clk_rcg2_ops,
538 },
539 };
540
541 static struct clk_rcg2 camss_gp1_clk_src = {
542 .cmd_rcgr = 0x3450,
543 .mnd_width = 8,
544 .hid_width = 5,
545 .parent_map = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map,
546 .freq_tbl = ftbl_camss_gp0_clk_src,
547 .clkr.hw.init = &(struct clk_init_data){
548 .name = "camss_gp1_clk_src",
549 .parent_data = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div,
550 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div),
551 .ops = &clk_rcg2_ops,
552 },
553 };
554
555 static const struct freq_tbl ftbl_cci_clk_src[] = {
556 F(37500000, P_GPLL0_DIV, 8, 0, 0),
557 F(50000000, P_GPLL0_DIV, 6, 0, 0),
558 F(100000000, P_GPLL0, 6, 0, 0),
559 { }
560 };
561
562 static struct clk_rcg2 cci_clk_src = {
563 .cmd_rcgr = 0x3300,
564 .mnd_width = 8,
565 .hid_width = 5,
566 .parent_map = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map,
567 .freq_tbl = ftbl_cci_clk_src,
568 .clkr.hw.init = &(struct clk_init_data){
569 .name = "cci_clk_src",
570 .parent_data = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div,
571 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div),
572 .ops = &clk_rcg2_ops,
573 },
574 };
575
576 static const struct freq_tbl ftbl_cpp_clk_src[] = {
577 F(120000000, P_GPLL0, 5, 0, 0),
578 F(256000000, P_MMPLL4, 3, 0, 0),
579 F(384000000, P_MMPLL4, 2, 0, 0),
580 F(480000000, P_MMPLL7, 2, 0, 0),
581 F(540000000, P_MMPLL6, 2, 0, 0),
582 F(576000000, P_MMPLL10, 1, 0, 0),
583 { }
584 };
585
586 static struct clk_rcg2 cpp_clk_src = {
587 .cmd_rcgr = 0x3640,
588 .mnd_width = 0,
589 .hid_width = 5,
590 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_mmpll6_map,
591 .freq_tbl = ftbl_cpp_clk_src,
592 .clkr.hw.init = &(struct clk_init_data){
593 .name = "cpp_clk_src",
594 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_mmpll6,
595 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_mmpll6),
596 .ops = &clk_rcg2_ops,
597 },
598 };
599
600 static const struct freq_tbl ftbl_csi0_clk_src[] = {
601 F(100000000, P_GPLL0_DIV, 3, 0, 0),
602 F(200000000, P_GPLL0, 3, 0, 0),
603 F(310000000, P_MMPLL8, 3, 0, 0),
604 F(404000000, P_MMPLL0, 2, 0, 0),
605 F(465000000, P_MMPLL8, 2, 0, 0),
606 { }
607 };
608
609 static struct clk_rcg2 csi0_clk_src = {
610 .cmd_rcgr = 0x3090,
611 .mnd_width = 0,
612 .hid_width = 5,
613 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div_map,
614 .freq_tbl = ftbl_csi0_clk_src,
615 .clkr.hw.init = &(struct clk_init_data){
616 .name = "csi0_clk_src",
617 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div,
618 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div),
619 .ops = &clk_rcg2_ops,
620 },
621 };
622
623 static const struct freq_tbl ftbl_csi0phytimer_clk_src[] = {
624 F(100000000, P_GPLL0_DIV, 3, 0, 0),
625 F(200000000, P_GPLL0, 3, 0, 0),
626 F(269333333, P_MMPLL0, 3, 0, 0),
627 { }
628 };
629
630 static struct clk_rcg2 csi0phytimer_clk_src = {
631 .cmd_rcgr = 0x3000,
632 .mnd_width = 0,
633 .hid_width = 5,
634 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
635 .freq_tbl = ftbl_csi0phytimer_clk_src,
636 .clkr.hw.init = &(struct clk_init_data){
637 .name = "csi0phytimer_clk_src",
638 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
639 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
640 .ops = &clk_rcg2_ops,
641 },
642 };
643
644 static struct clk_rcg2 csi1_clk_src = {
645 .cmd_rcgr = 0x3100,
646 .mnd_width = 0,
647 .hid_width = 5,
648 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div_map,
649 .freq_tbl = ftbl_csi0_clk_src,
650 .clkr.hw.init = &(struct clk_init_data){
651 .name = "csi1_clk_src",
652 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div,
653 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div),
654 .ops = &clk_rcg2_ops,
655 },
656 };
657
658 static struct clk_rcg2 csi1phytimer_clk_src = {
659 .cmd_rcgr = 0x3030,
660 .mnd_width = 0,
661 .hid_width = 5,
662 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
663 .freq_tbl = ftbl_csi0phytimer_clk_src,
664 .clkr.hw.init = &(struct clk_init_data){
665 .name = "csi1phytimer_clk_src",
666 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
667 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
668 .ops = &clk_rcg2_ops,
669 },
670 };
671
672 static struct clk_rcg2 csi2_clk_src = {
673 .cmd_rcgr = 0x3160,
674 .mnd_width = 0,
675 .hid_width = 5,
676 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div_map,
677 .freq_tbl = ftbl_csi0_clk_src,
678 .clkr.hw.init = &(struct clk_init_data){
679 .name = "csi2_clk_src",
680 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div,
681 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div),
682 .ops = &clk_rcg2_ops,
683 },
684 };
685
686 static struct clk_rcg2 csi2phytimer_clk_src = {
687 .cmd_rcgr = 0x3060,
688 .mnd_width = 0,
689 .hid_width = 5,
690 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
691 .freq_tbl = ftbl_csi0phytimer_clk_src,
692 .clkr.hw.init = &(struct clk_init_data){
693 .name = "csi2phytimer_clk_src",
694 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
695 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
696 .ops = &clk_rcg2_ops,
697 },
698 };
699
700 static struct clk_rcg2 csi3_clk_src = {
701 .cmd_rcgr = 0x31c0,
702 .mnd_width = 0,
703 .hid_width = 5,
704 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div_map,
705 .freq_tbl = ftbl_csi0_clk_src,
706 .clkr.hw.init = &(struct clk_init_data){
707 .name = "csi3_clk_src",
708 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div,
709 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div),
710 .ops = &clk_rcg2_ops,
711 },
712 };
713
714 static const struct freq_tbl ftbl_csiphy_clk_src[] = {
715 F(100000000, P_GPLL0_DIV, 3, 0, 0),
716 F(200000000, P_GPLL0, 3, 0, 0),
717 F(269333333, P_MMPLL0, 3, 0, 0),
718 F(320000000, P_MMPLL7, 3, 0, 0),
719 { }
720 };
721
722 static struct clk_rcg2 csiphy_clk_src = {
723 .cmd_rcgr = 0x3800,
724 .mnd_width = 0,
725 .hid_width = 5,
726 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div_map,
727 .freq_tbl = ftbl_csiphy_clk_src,
728 .clkr.hw.init = &(struct clk_init_data){
729 .name = "csiphy_clk_src",
730 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div,
731 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div),
732 .ops = &clk_rcg2_ops,
733 },
734 };
735
736 static const struct freq_tbl ftbl_dp_aux_clk_src[] = {
737 F(19200000, P_XO, 1, 0, 0),
738 { }
739 };
740
741 static struct clk_rcg2 dp_aux_clk_src = {
742 .cmd_rcgr = 0x2260,
743 .mnd_width = 0,
744 .hid_width = 5,
745 .parent_map = mmcc_xo_gpll0_gpll0_div_map,
746 .freq_tbl = ftbl_dp_aux_clk_src,
747 .clkr.hw.init = &(struct clk_init_data){
748 .name = "dp_aux_clk_src",
749 .parent_data = mmcc_xo_gpll0_gpll0_div,
750 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_gpll0_div),
751 .ops = &clk_rcg2_ops,
752 },
753 };
754
755 static const struct freq_tbl ftbl_dp_crypto_clk_src[] = {
756 F(101250000, P_DP_PHY_PLL_VCO_DIV, 4, 0, 0),
757 F(168750000, P_DP_PHY_PLL_VCO_DIV, 4, 0, 0),
758 F(337500000, P_DP_PHY_PLL_VCO_DIV, 4, 0, 0),
759 { }
760 };
761
762 static struct clk_rcg2 dp_crypto_clk_src = {
763 .cmd_rcgr = 0x2220,
764 .mnd_width = 8,
765 .hid_width = 5,
766 .parent_map = mmcc_xo_dplink_dpvco_map,
767 .freq_tbl = ftbl_dp_crypto_clk_src,
768 .clkr.hw.init = &(struct clk_init_data){
769 .name = "dp_crypto_clk_src",
770 .parent_data = mmcc_xo_dplink_dpvco,
771 .num_parents = ARRAY_SIZE(mmcc_xo_dplink_dpvco),
772 .ops = &clk_rcg2_ops,
773 },
774 };
775
776 static const struct freq_tbl ftbl_dp_gtc_clk_src[] = {
777 F(40000000, P_GPLL0_DIV, 7.5, 0, 0),
778 F(60000000, P_GPLL0, 10, 0, 0),
779 { }
780 };
781
782 static struct clk_rcg2 dp_gtc_clk_src = {
783 .cmd_rcgr = 0x2280,
784 .mnd_width = 0,
785 .hid_width = 5,
786 .parent_map = mmcc_xo_gpll0_gpll0_div_map,
787 .freq_tbl = ftbl_dp_gtc_clk_src,
788 .clkr.hw.init = &(struct clk_init_data){
789 .name = "dp_gtc_clk_src",
790 .parent_data = mmcc_xo_gpll0_gpll0_div,
791 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_gpll0_div),
792 .ops = &clk_rcg2_ops,
793 },
794 };
795
796 static const struct freq_tbl ftbl_dp_link_clk_src[] = {
797 F(162000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0),
798 F(270000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0),
799 F(540000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0),
800 { }
801 };
802
803 static struct clk_rcg2 dp_link_clk_src = {
804 .cmd_rcgr = 0x2200,
805 .mnd_width = 0,
806 .hid_width = 5,
807 .parent_map = mmcc_xo_dplink_dpvco_map,
808 .freq_tbl = ftbl_dp_link_clk_src,
809 .clkr.hw.init = &(struct clk_init_data){
810 .name = "dp_link_clk_src",
811 .parent_data = mmcc_xo_dplink_dpvco,
812 .num_parents = ARRAY_SIZE(mmcc_xo_dplink_dpvco),
813 .ops = &clk_rcg2_ops,
814 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
815 },
816 };
817
818 static struct clk_rcg2 dp_pixel_clk_src = {
819 .cmd_rcgr = 0x2240,
820 .mnd_width = 16,
821 .hid_width = 5,
822 .parent_map = mmcc_xo_dplink_dpvco_map,
823 .clkr.hw.init = &(struct clk_init_data){
824 .name = "dp_pixel_clk_src",
825 .parent_data = mmcc_xo_dplink_dpvco,
826 .num_parents = ARRAY_SIZE(mmcc_xo_dplink_dpvco),
827 .ops = &clk_dp_ops,
828 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
829 },
830 };
831
832 static struct clk_rcg2 esc0_clk_src = {
833 .cmd_rcgr = 0x2160,
834 .mnd_width = 0,
835 .hid_width = 5,
836 .parent_map = mmcc_xo_dsibyte_map,
837 .clkr.hw.init = &(struct clk_init_data){
838 .name = "esc0_clk_src",
839 .parent_data = mmcc_xo_dsibyte,
840 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
841 .ops = &clk_rcg2_ops,
842 },
843 };
844
845 static struct clk_rcg2 esc1_clk_src = {
846 .cmd_rcgr = 0x2180,
847 .mnd_width = 0,
848 .hid_width = 5,
849 .parent_map = mmcc_xo_dsibyte_map,
850 .clkr.hw.init = &(struct clk_init_data){
851 .name = "esc1_clk_src",
852 .parent_data = mmcc_xo_dsibyte,
853 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
854 .ops = &clk_rcg2_ops,
855 },
856 };
857
858 static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
859 F(66666667, P_GPLL0_DIV, 4.5, 0, 0),
860 F(133333333, P_GPLL0, 4.5, 0, 0),
861 F(219428571, P_MMPLL4, 3.5, 0, 0),
862 F(320000000, P_MMPLL7, 3, 0, 0),
863 F(480000000, P_MMPLL7, 2, 0, 0),
864 { }
865 };
866
867 static struct clk_rcg2 jpeg0_clk_src = {
868 .cmd_rcgr = 0x3500,
869 .mnd_width = 0,
870 .hid_width = 5,
871 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
872 .freq_tbl = ftbl_jpeg0_clk_src,
873 .clkr.hw.init = &(struct clk_init_data){
874 .name = "jpeg0_clk_src",
875 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
876 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
877 .ops = &clk_rcg2_ops,
878 },
879 };
880
881 static const struct freq_tbl ftbl_mclk0_clk_src[] = {
882 F(4800000, P_XO, 4, 0, 0),
883 F(6000000, P_GPLL0_DIV, 10, 1, 5),
884 F(8000000, P_GPLL0_DIV, 1, 2, 75),
885 F(9600000, P_XO, 2, 0, 0),
886 F(16666667, P_GPLL0_DIV, 2, 1, 9),
887 F(19200000, P_XO, 1, 0, 0),
888 F(24000000, P_MMPLL10, 1, 1, 24),
889 F(33333333, P_GPLL0_DIV, 1, 1, 9),
890 F(48000000, P_GPLL0, 1, 2, 25),
891 F(66666667, P_GPLL0, 1, 1, 9),
892 { }
893 };
894
895 static struct clk_rcg2 mclk0_clk_src = {
896 .cmd_rcgr = 0x3360,
897 .mnd_width = 8,
898 .hid_width = 5,
899 .parent_map = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map,
900 .freq_tbl = ftbl_mclk0_clk_src,
901 .clkr.hw.init = &(struct clk_init_data){
902 .name = "mclk0_clk_src",
903 .parent_data = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div,
904 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div),
905 .ops = &clk_rcg2_ops,
906 },
907 };
908
909 static struct clk_rcg2 mclk1_clk_src = {
910 .cmd_rcgr = 0x3390,
911 .mnd_width = 8,
912 .hid_width = 5,
913 .parent_map = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map,
914 .freq_tbl = ftbl_mclk0_clk_src,
915 .clkr.hw.init = &(struct clk_init_data){
916 .name = "mclk1_clk_src",
917 .parent_data = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div,
918 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div),
919 .ops = &clk_rcg2_ops,
920 },
921 };
922
923 static struct clk_rcg2 mclk2_clk_src = {
924 .cmd_rcgr = 0x33c0,
925 .mnd_width = 8,
926 .hid_width = 5,
927 .parent_map = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map,
928 .freq_tbl = ftbl_mclk0_clk_src,
929 .clkr.hw.init = &(struct clk_init_data){
930 .name = "mclk2_clk_src",
931 .parent_data = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div,
932 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div),
933 .ops = &clk_rcg2_ops,
934 },
935 };
936
937 static struct clk_rcg2 mclk3_clk_src = {
938 .cmd_rcgr = 0x33f0,
939 .mnd_width = 8,
940 .hid_width = 5,
941 .parent_map = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map,
942 .freq_tbl = ftbl_mclk0_clk_src,
943 .clkr.hw.init = &(struct clk_init_data){
944 .name = "mclk3_clk_src",
945 .parent_data = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div,
946 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div),
947 .ops = &clk_rcg2_ops,
948 },
949 };
950
951 static const struct freq_tbl ftbl_mdp_clk_src[] = {
952 F(100000000, P_GPLL0_DIV, 3, 0, 0),
953 F(150000000, P_GPLL0_DIV, 2, 0, 0),
954 F(171428571, P_GPLL0, 3.5, 0, 0),
955 F(200000000, P_GPLL0, 3, 0, 0),
956 F(275000000, P_MMPLL5, 3, 0, 0),
957 F(300000000, P_GPLL0, 2, 0, 0),
958 F(330000000, P_MMPLL5, 2.5, 0, 0),
959 F(412500000, P_MMPLL5, 2, 0, 0),
960 { }
961 };
962
963 static struct clk_rcg2 mdp_clk_src = {
964 .cmd_rcgr = 0x2040,
965 .mnd_width = 0,
966 .hid_width = 5,
967 .parent_map = mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div_map,
968 .freq_tbl = ftbl_mdp_clk_src,
969 .clkr.hw.init = &(struct clk_init_data){
970 .name = "mdp_clk_src",
971 .parent_data = mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div,
972 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div),
973 .ops = &clk_rcg2_ops,
974 },
975 };
976
977 static struct clk_rcg2 pclk0_clk_src = {
978 .cmd_rcgr = 0x2000,
979 .mnd_width = 8,
980 .hid_width = 5,
981 .parent_map = mmcc_xo_dsi0pll_dsi1pll_map,
982 .clkr.hw.init = &(struct clk_init_data){
983 .name = "pclk0_clk_src",
984 .parent_data = mmcc_xo_dsi0pll_dsi1pll,
985 .num_parents = ARRAY_SIZE(mmcc_xo_dsi0pll_dsi1pll),
986 .ops = &clk_pixel_ops,
987 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
988 },
989 };
990
991 static struct clk_rcg2 pclk1_clk_src = {
992 .cmd_rcgr = 0x2020,
993 .mnd_width = 8,
994 .hid_width = 5,
995 .parent_map = mmcc_xo_dsi0pll_dsi1pll_map,
996 .clkr.hw.init = &(struct clk_init_data){
997 .name = "pclk1_clk_src",
998 .parent_data = mmcc_xo_dsi0pll_dsi1pll,
999 .num_parents = ARRAY_SIZE(mmcc_xo_dsi0pll_dsi1pll),
1000 .ops = &clk_pixel_ops,
1001 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
1002 },
1003 };
1004
1005 static const struct freq_tbl ftbl_rot_clk_src[] = {
1006 F(171428571, P_GPLL0, 3.5, 0, 0),
1007 F(275000000, P_MMPLL5, 3, 0, 0),
1008 F(300000000, P_GPLL0, 2, 0, 0),
1009 F(330000000, P_MMPLL5, 2.5, 0, 0),
1010 F(412500000, P_MMPLL5, 2, 0, 0),
1011 { }
1012 };
1013
1014 static struct clk_rcg2 rot_clk_src = {
1015 .cmd_rcgr = 0x21a0,
1016 .mnd_width = 0,
1017 .hid_width = 5,
1018 .parent_map = mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div_map,
1019 .freq_tbl = ftbl_rot_clk_src,
1020 .clkr.hw.init = &(struct clk_init_data){
1021 .name = "rot_clk_src",
1022 .parent_data = mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div,
1023 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div),
1024 .ops = &clk_rcg2_ops,
1025 },
1026 };
1027
1028 static const struct freq_tbl ftbl_vfe0_clk_src[] = {
1029 F(120000000, P_GPLL0, 5, 0, 0),
1030 F(200000000, P_GPLL0, 3, 0, 0),
1031 F(256000000, P_MMPLL4, 3, 0, 0),
1032 F(300000000, P_GPLL0, 2, 0, 0),
1033 F(404000000, P_MMPLL0, 2, 0, 0),
1034 F(480000000, P_MMPLL7, 2, 0, 0),
1035 F(540000000, P_MMPLL6, 2, 0, 0),
1036 F(576000000, P_MMPLL10, 1, 0, 0),
1037 { }
1038 };
1039
1040 static struct clk_rcg2 vfe0_clk_src = {
1041 .cmd_rcgr = 0x3600,
1042 .mnd_width = 0,
1043 .hid_width = 5,
1044 .parent_map = mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0_map,
1045 .freq_tbl = ftbl_vfe0_clk_src,
1046 .clkr.hw.init = &(struct clk_init_data){
1047 .name = "vfe0_clk_src",
1048 .parent_data = mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0,
1049 .num_parents = ARRAY_SIZE(mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0),
1050 .ops = &clk_rcg2_ops,
1051 },
1052 };
1053
1054 static struct clk_rcg2 vfe1_clk_src = {
1055 .cmd_rcgr = 0x3620,
1056 .mnd_width = 0,
1057 .hid_width = 5,
1058 .parent_map = mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0_map,
1059 .freq_tbl = ftbl_vfe0_clk_src,
1060 .clkr.hw.init = &(struct clk_init_data){
1061 .name = "vfe1_clk_src",
1062 .parent_data = mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0,
1063 .num_parents = ARRAY_SIZE(mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0),
1064 .ops = &clk_rcg2_ops,
1065 },
1066 };
1067
1068 static const struct freq_tbl ftbl_video_core_clk_src[] = {
1069 F(133333333, P_GPLL0, 4.5, 0, 0),
1070 F(269333333, P_MMPLL0, 3, 0, 0),
1071 F(320000000, P_MMPLL7, 3, 0, 0),
1072 F(404000000, P_MMPLL0, 2, 0, 0),
1073 F(441600000, P_MMPLL3, 2, 0, 0),
1074 F(518400000, P_MMPLL3, 2, 0, 0),
1075 { }
1076 };
1077
1078 static struct clk_rcg2 video_core_clk_src = {
1079 .cmd_rcgr = 0x1000,
1080 .mnd_width = 0,
1081 .hid_width = 5,
1082 .parent_map = mmcc_xo_mmpll0_mmpll8_mmpll3_mmpll6_gpll0_mmpll7_map,
1083 .freq_tbl = ftbl_video_core_clk_src,
1084 .clkr.hw.init = &(struct clk_init_data){
1085 .name = "video_core_clk_src",
1086 .parent_data = mmcc_xo_mmpll0_mmpll8_mmpll3_mmpll6_gpll0_mmpll7,
1087 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll8_mmpll3_mmpll6_gpll0_mmpll7),
1088 .ops = &clk_rcg2_ops,
1089 .flags = CLK_IS_CRITICAL,
1090 },
1091 };
1092
1093 static struct clk_rcg2 vsync_clk_src = {
1094 .cmd_rcgr = 0x2080,
1095 .mnd_width = 0,
1096 .hid_width = 5,
1097 .parent_map = mmcc_xo_gpll0_gpll0_div_map,
1098 .freq_tbl = ftbl_dp_aux_clk_src,
1099 .clkr.hw.init = &(struct clk_init_data){
1100 .name = "vsync_clk_src",
1101 .parent_data = mmcc_xo_gpll0_gpll0_div,
1102 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_gpll0_div),
1103 .ops = &clk_rcg2_ops,
1104 },
1105 };
1106
1107 static struct clk_branch bimc_smmu_ahb_clk = {
1108 .halt_reg = 0xe004,
1109 .halt_check = BRANCH_VOTED,
1110 .hwcg_reg = 0xe004,
1111 .hwcg_bit = 1,
1112 .clkr = {
1113 .enable_reg = 0xe004,
1114 .enable_mask = BIT(0),
1115 .hw.init = &(struct clk_init_data){
1116 .name = "bimc_smmu_ahb_clk",
1117 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1118 .num_parents = 1,
1119 .ops = &clk_branch2_ops,
1120 },
1121 },
1122 };
1123
1124 static struct clk_branch bimc_smmu_axi_clk = {
1125 .halt_reg = 0xe008,
1126 .halt_check = BRANCH_VOTED,
1127 .hwcg_reg = 0xe008,
1128 .hwcg_bit = 1,
1129 .clkr = {
1130 .enable_reg = 0xe008,
1131 .enable_mask = BIT(0),
1132 .hw.init = &(struct clk_init_data){
1133 .name = "bimc_smmu_axi_clk",
1134 .ops = &clk_branch2_ops,
1135 },
1136 },
1137 };
1138
1139 static struct clk_branch camss_ahb_clk = {
1140 .halt_reg = 0x348c,
1141 .halt_check = BRANCH_HALT,
1142 .hwcg_reg = 0x348c,
1143 .hwcg_bit = 1,
1144 .clkr = {
1145 .enable_reg = 0x348c,
1146 .enable_mask = BIT(0),
1147 .hw.init = &(struct clk_init_data){
1148 .name = "camss_ahb_clk",
1149 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1150 .num_parents = 1,
1151 .ops = &clk_branch2_ops,
1152 },
1153 },
1154 };
1155
1156 static struct clk_branch camss_cci_ahb_clk = {
1157 .halt_reg = 0x3348,
1158 .halt_check = BRANCH_HALT,
1159 .clkr = {
1160 .enable_reg = 0x3348,
1161 .enable_mask = BIT(0),
1162 .hw.init = &(struct clk_init_data){
1163 .name = "camss_cci_ahb_clk",
1164 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1165 .num_parents = 1,
1166 .flags = CLK_SET_RATE_PARENT,
1167 .ops = &clk_branch2_ops,
1168 },
1169 },
1170 };
1171
1172 static struct clk_branch camss_cci_clk = {
1173 .halt_reg = 0x3344,
1174 .halt_check = BRANCH_HALT,
1175 .clkr = {
1176 .enable_reg = 0x3344,
1177 .enable_mask = BIT(0),
1178 .hw.init = &(struct clk_init_data){
1179 .name = "camss_cci_clk",
1180 .parent_hws = (const struct clk_hw *[]){ &cci_clk_src.clkr.hw },
1181 .num_parents = 1,
1182 .flags = CLK_SET_RATE_PARENT,
1183 .ops = &clk_branch2_ops,
1184 },
1185 },
1186 };
1187
1188 static struct clk_branch camss_cpp_ahb_clk = {
1189 .halt_reg = 0x36b4,
1190 .halt_check = BRANCH_HALT,
1191 .clkr = {
1192 .enable_reg = 0x36b4,
1193 .enable_mask = BIT(0),
1194 .hw.init = &(struct clk_init_data){
1195 .name = "camss_cpp_ahb_clk",
1196 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1197 .num_parents = 1,
1198 .ops = &clk_branch2_ops,
1199 },
1200 },
1201 };
1202
1203 static struct clk_branch camss_cpp_axi_clk = {
1204 .halt_reg = 0x36c4,
1205 .halt_check = BRANCH_HALT,
1206 .clkr = {
1207 .enable_reg = 0x36c4,
1208 .enable_mask = BIT(0),
1209 .hw.init = &(struct clk_init_data){
1210 .name = "camss_cpp_axi_clk",
1211 .ops = &clk_branch2_ops,
1212 },
1213 },
1214 };
1215
1216 static struct clk_branch camss_cpp_clk = {
1217 .halt_reg = 0x36b0,
1218 .halt_check = BRANCH_HALT,
1219 .clkr = {
1220 .enable_reg = 0x36b0,
1221 .enable_mask = BIT(0),
1222 .hw.init = &(struct clk_init_data){
1223 .name = "camss_cpp_clk",
1224 .parent_hws = (const struct clk_hw *[]){ &cpp_clk_src.clkr.hw },
1225 .num_parents = 1,
1226 .flags = CLK_SET_RATE_PARENT,
1227 .ops = &clk_branch2_ops,
1228 },
1229 },
1230 };
1231
1232 static struct clk_branch camss_cpp_vbif_ahb_clk = {
1233 .halt_reg = 0x36c8,
1234 .halt_check = BRANCH_HALT,
1235 .clkr = {
1236 .enable_reg = 0x36c8,
1237 .enable_mask = BIT(0),
1238 .hw.init = &(struct clk_init_data){
1239 .name = "camss_cpp_vbif_ahb_clk",
1240 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1241 .num_parents = 1,
1242 .ops = &clk_branch2_ops,
1243 },
1244 },
1245 };
1246
1247 static struct clk_branch camss_csi0_ahb_clk = {
1248 .halt_reg = 0x30bc,
1249 .halt_check = BRANCH_HALT,
1250 .clkr = {
1251 .enable_reg = 0x30bc,
1252 .enable_mask = BIT(0),
1253 .hw.init = &(struct clk_init_data){
1254 .name = "camss_csi0_ahb_clk",
1255 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1256 .num_parents = 1,
1257 .ops = &clk_branch2_ops,
1258 },
1259 },
1260 };
1261
1262 static struct clk_branch camss_csi0_clk = {
1263 .halt_reg = 0x30b4,
1264 .halt_check = BRANCH_HALT,
1265 .clkr = {
1266 .enable_reg = 0x30b4,
1267 .enable_mask = BIT(0),
1268 .hw.init = &(struct clk_init_data){
1269 .name = "camss_csi0_clk",
1270 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1271 .num_parents = 1,
1272 .flags = CLK_SET_RATE_PARENT,
1273 .ops = &clk_branch2_ops,
1274 },
1275 },
1276 };
1277
1278 static struct clk_branch camss_csi0phytimer_clk = {
1279 .halt_reg = 0x3024,
1280 .halt_check = BRANCH_HALT,
1281 .clkr = {
1282 .enable_reg = 0x3024,
1283 .enable_mask = BIT(0),
1284 .hw.init = &(struct clk_init_data){
1285 .name = "camss_csi0phytimer_clk",
1286 .parent_hws = (const struct clk_hw *[]){ &csi0phytimer_clk_src.clkr.hw },
1287 .num_parents = 1,
1288 .flags = CLK_SET_RATE_PARENT,
1289 .ops = &clk_branch2_ops,
1290 },
1291 },
1292 };
1293
1294 static struct clk_branch camss_csi0pix_clk = {
1295 .halt_reg = 0x30e4,
1296 .halt_check = BRANCH_HALT,
1297 .clkr = {
1298 .enable_reg = 0x30e4,
1299 .enable_mask = BIT(0),
1300 .hw.init = &(struct clk_init_data){
1301 .name = "camss_csi0pix_clk",
1302 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1303 .num_parents = 1,
1304 .ops = &clk_branch2_ops,
1305 },
1306 },
1307 };
1308
1309 static struct clk_branch camss_csi0rdi_clk = {
1310 .halt_reg = 0x30d4,
1311 .halt_check = BRANCH_HALT,
1312 .clkr = {
1313 .enable_reg = 0x30d4,
1314 .enable_mask = BIT(0),
1315 .hw.init = &(struct clk_init_data){
1316 .name = "camss_csi0rdi_clk",
1317 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1318 .num_parents = 1,
1319 .ops = &clk_branch2_ops,
1320 },
1321 },
1322 };
1323
1324 static struct clk_branch camss_csi1_ahb_clk = {
1325 .halt_reg = 0x3128,
1326 .halt_check = BRANCH_HALT,
1327 .clkr = {
1328 .enable_reg = 0x3128,
1329 .enable_mask = BIT(0),
1330 .hw.init = &(struct clk_init_data){
1331 .name = "camss_csi1_ahb_clk",
1332 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1333 .num_parents = 1,
1334 .ops = &clk_branch2_ops,
1335 },
1336 },
1337 };
1338
1339 static struct clk_branch camss_csi1_clk = {
1340 .halt_reg = 0x3124,
1341 .halt_check = BRANCH_HALT,
1342 .clkr = {
1343 .enable_reg = 0x3124,
1344 .enable_mask = BIT(0),
1345 .hw.init = &(struct clk_init_data){
1346 .name = "camss_csi1_clk",
1347 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1348 .num_parents = 1,
1349 .flags = CLK_SET_RATE_PARENT,
1350 .ops = &clk_branch2_ops,
1351 },
1352 },
1353 };
1354
1355 static struct clk_branch camss_csi1phytimer_clk = {
1356 .halt_reg = 0x3054,
1357 .halt_check = BRANCH_HALT,
1358 .clkr = {
1359 .enable_reg = 0x3054,
1360 .enable_mask = BIT(0),
1361 .hw.init = &(struct clk_init_data){
1362 .name = "camss_csi1phytimer_clk",
1363 .parent_hws = (const struct clk_hw *[]){ &csi1phytimer_clk_src.clkr.hw },
1364 .num_parents = 1,
1365 .flags = CLK_SET_RATE_PARENT,
1366 .ops = &clk_branch2_ops,
1367 },
1368 },
1369 };
1370
1371 static struct clk_branch camss_csi1pix_clk = {
1372 .halt_reg = 0x3154,
1373 .halt_check = BRANCH_HALT,
1374 .clkr = {
1375 .enable_reg = 0x3154,
1376 .enable_mask = BIT(0),
1377 .hw.init = &(struct clk_init_data){
1378 .name = "camss_csi1pix_clk",
1379 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1380 .num_parents = 1,
1381 .ops = &clk_branch2_ops,
1382 },
1383 },
1384 };
1385
1386 static struct clk_branch camss_csi1rdi_clk = {
1387 .halt_reg = 0x3144,
1388 .halt_check = BRANCH_HALT,
1389 .clkr = {
1390 .enable_reg = 0x3144,
1391 .enable_mask = BIT(0),
1392 .hw.init = &(struct clk_init_data){
1393 .name = "camss_csi1rdi_clk",
1394 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1395 .num_parents = 1,
1396 .ops = &clk_branch2_ops,
1397 },
1398 },
1399 };
1400
1401 static struct clk_branch camss_csi2_ahb_clk = {
1402 .halt_reg = 0x3188,
1403 .halt_check = BRANCH_HALT,
1404 .clkr = {
1405 .enable_reg = 0x3188,
1406 .enable_mask = BIT(0),
1407 .hw.init = &(struct clk_init_data){
1408 .name = "camss_csi2_ahb_clk",
1409 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1410 .num_parents = 1,
1411 .ops = &clk_branch2_ops,
1412 },
1413 },
1414 };
1415
1416 static struct clk_branch camss_csi2_clk = {
1417 .halt_reg = 0x3184,
1418 .halt_check = BRANCH_HALT,
1419 .clkr = {
1420 .enable_reg = 0x3184,
1421 .enable_mask = BIT(0),
1422 .hw.init = &(struct clk_init_data){
1423 .name = "camss_csi2_clk",
1424 .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
1425 .num_parents = 1,
1426 .flags = CLK_SET_RATE_PARENT,
1427 .ops = &clk_branch2_ops,
1428 },
1429 },
1430 };
1431
1432 static struct clk_branch camss_csi2phytimer_clk = {
1433 .halt_reg = 0x3084,
1434 .halt_check = BRANCH_HALT,
1435 .clkr = {
1436 .enable_reg = 0x3084,
1437 .enable_mask = BIT(0),
1438 .hw.init = &(struct clk_init_data){
1439 .name = "camss_csi2phytimer_clk",
1440 .parent_hws = (const struct clk_hw *[]){ &csi2phytimer_clk_src.clkr.hw },
1441 .num_parents = 1,
1442 .flags = CLK_SET_RATE_PARENT,
1443 .ops = &clk_branch2_ops,
1444 },
1445 },
1446 };
1447
1448 static struct clk_branch camss_csi2pix_clk = {
1449 .halt_reg = 0x31b4,
1450 .halt_check = BRANCH_HALT,
1451 .clkr = {
1452 .enable_reg = 0x31b4,
1453 .enable_mask = BIT(0),
1454 .hw.init = &(struct clk_init_data){
1455 .name = "camss_csi2pix_clk",
1456 .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
1457 .num_parents = 1,
1458 .ops = &clk_branch2_ops,
1459 },
1460 },
1461 };
1462
1463 static struct clk_branch camss_csi2rdi_clk = {
1464 .halt_reg = 0x31a4,
1465 .halt_check = BRANCH_HALT,
1466 .clkr = {
1467 .enable_reg = 0x31a4,
1468 .enable_mask = BIT(0),
1469 .hw.init = &(struct clk_init_data){
1470 .name = "camss_csi2rdi_clk",
1471 .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
1472 .num_parents = 1,
1473 .ops = &clk_branch2_ops,
1474 },
1475 },
1476 };
1477
1478 static struct clk_branch camss_csi3_ahb_clk = {
1479 .halt_reg = 0x31e8,
1480 .halt_check = BRANCH_HALT,
1481 .clkr = {
1482 .enable_reg = 0x31e8,
1483 .enable_mask = BIT(0),
1484 .hw.init = &(struct clk_init_data){
1485 .name = "camss_csi3_ahb_clk",
1486 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1487 .num_parents = 1,
1488 .ops = &clk_branch2_ops,
1489 },
1490 },
1491 };
1492
1493 static struct clk_branch camss_csi3_clk = {
1494 .halt_reg = 0x31e4,
1495 .halt_check = BRANCH_HALT,
1496 .clkr = {
1497 .enable_reg = 0x31e4,
1498 .enable_mask = BIT(0),
1499 .hw.init = &(struct clk_init_data){
1500 .name = "camss_csi3_clk",
1501 .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
1502 .num_parents = 1,
1503 .flags = CLK_SET_RATE_PARENT,
1504 .ops = &clk_branch2_ops,
1505 },
1506 },
1507 };
1508
1509 static struct clk_branch camss_csi3pix_clk = {
1510 .halt_reg = 0x3214,
1511 .halt_check = BRANCH_HALT,
1512 .clkr = {
1513 .enable_reg = 0x3214,
1514 .enable_mask = BIT(0),
1515 .hw.init = &(struct clk_init_data){
1516 .name = "camss_csi3pix_clk",
1517 .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
1518 .num_parents = 1,
1519 .ops = &clk_branch2_ops,
1520 },
1521 },
1522 };
1523
1524 static struct clk_branch camss_csi3rdi_clk = {
1525 .halt_reg = 0x3204,
1526 .halt_check = BRANCH_HALT,
1527 .clkr = {
1528 .enable_reg = 0x3204,
1529 .enable_mask = BIT(0),
1530 .hw.init = &(struct clk_init_data){
1531 .name = "camss_csi3rdi_clk",
1532 .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
1533 .num_parents = 1,
1534 .ops = &clk_branch2_ops,
1535 },
1536 },
1537 };
1538
1539 static struct clk_branch camss_csi_vfe0_clk = {
1540 .halt_reg = 0x3704,
1541 .halt_check = BRANCH_HALT,
1542 .clkr = {
1543 .enable_reg = 0x3704,
1544 .enable_mask = BIT(0),
1545 .hw.init = &(struct clk_init_data){
1546 .name = "camss_csi_vfe0_clk",
1547 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
1548 .num_parents = 1,
1549 .ops = &clk_branch2_ops,
1550 },
1551 },
1552 };
1553
1554 static struct clk_branch camss_csi_vfe1_clk = {
1555 .halt_reg = 0x3714,
1556 .halt_check = BRANCH_HALT,
1557 .clkr = {
1558 .enable_reg = 0x3714,
1559 .enable_mask = BIT(0),
1560 .hw.init = &(struct clk_init_data){
1561 .name = "camss_csi_vfe1_clk",
1562 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
1563 .num_parents = 1,
1564 .ops = &clk_branch2_ops,
1565 },
1566 },
1567 };
1568
1569 static struct clk_branch camss_csiphy0_clk = {
1570 .halt_reg = 0x3740,
1571 .halt_check = BRANCH_HALT,
1572 .clkr = {
1573 .enable_reg = 0x3740,
1574 .enable_mask = BIT(0),
1575 .hw.init = &(struct clk_init_data){
1576 .name = "camss_csiphy0_clk",
1577 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
1578 .num_parents = 1,
1579 .flags = CLK_SET_RATE_PARENT,
1580 .ops = &clk_branch2_ops,
1581 },
1582 },
1583 };
1584
1585 static struct clk_branch camss_csiphy1_clk = {
1586 .halt_reg = 0x3744,
1587 .halt_check = BRANCH_HALT,
1588 .clkr = {
1589 .enable_reg = 0x3744,
1590 .enable_mask = BIT(0),
1591 .hw.init = &(struct clk_init_data){
1592 .name = "camss_csiphy1_clk",
1593 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
1594 .num_parents = 1,
1595 .flags = CLK_SET_RATE_PARENT,
1596 .ops = &clk_branch2_ops,
1597 },
1598 },
1599 };
1600
1601 static struct clk_branch camss_csiphy2_clk = {
1602 .halt_reg = 0x3748,
1603 .halt_check = BRANCH_HALT,
1604 .clkr = {
1605 .enable_reg = 0x3748,
1606 .enable_mask = BIT(0),
1607 .hw.init = &(struct clk_init_data){
1608 .name = "camss_csiphy2_clk",
1609 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
1610 .num_parents = 1,
1611 .flags = CLK_SET_RATE_PARENT,
1612 .ops = &clk_branch2_ops,
1613 },
1614 },
1615 };
1616
1617
1618 static struct clk_branch camss_cphy_csid0_clk = {
1619 .halt_reg = 0x3730,
1620 .halt_check = BRANCH_HALT,
1621 .clkr = {
1622 .enable_reg = 0x3730,
1623 .enable_mask = BIT(0),
1624 .hw.init = &(struct clk_init_data){
1625 .name = "camss_cphy_csid0_clk",
1626 .parent_hws = (const struct clk_hw *[]){ &camss_csiphy0_clk.clkr.hw },
1627 .num_parents = 1,
1628 .flags = CLK_SET_RATE_PARENT,
1629 .ops = &clk_branch2_ops,
1630 },
1631 },
1632 };
1633
1634 static struct clk_branch camss_cphy_csid1_clk = {
1635 .halt_reg = 0x3734,
1636 .halt_check = BRANCH_HALT,
1637 .clkr = {
1638 .enable_reg = 0x3734,
1639 .enable_mask = BIT(0),
1640 .hw.init = &(struct clk_init_data){
1641 .name = "camss_cphy_csid1_clk",
1642 .parent_hws = (const struct clk_hw *[]){ &camss_csiphy1_clk.clkr.hw },
1643 .num_parents = 1,
1644 .flags = CLK_SET_RATE_PARENT,
1645 .ops = &clk_branch2_ops,
1646 },
1647 },
1648 };
1649
1650 static struct clk_branch camss_cphy_csid2_clk = {
1651 .halt_reg = 0x3738,
1652 .halt_check = BRANCH_HALT,
1653 .clkr = {
1654 .enable_reg = 0x3738,
1655 .enable_mask = BIT(0),
1656 .hw.init = &(struct clk_init_data){
1657 .name = "camss_cphy_csid2_clk",
1658 .parent_hws = (const struct clk_hw *[]){ &camss_csiphy2_clk.clkr.hw },
1659 .num_parents = 1,
1660 .flags = CLK_SET_RATE_PARENT,
1661 .ops = &clk_branch2_ops,
1662 },
1663 },
1664 };
1665
1666 static struct clk_branch camss_cphy_csid3_clk = {
1667 .halt_reg = 0x373c,
1668 .halt_check = BRANCH_HALT,
1669 .clkr = {
1670 .enable_reg = 0x373c,
1671 .enable_mask = BIT(0),
1672 .hw.init = &(struct clk_init_data){
1673 .name = "camss_cphy_csid3_clk",
1674 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
1675 .num_parents = 1,
1676 .flags = CLK_SET_RATE_PARENT,
1677 .ops = &clk_branch2_ops,
1678 },
1679 },
1680 };
1681
1682 static struct clk_branch camss_gp0_clk = {
1683 .halt_reg = 0x3444,
1684 .halt_check = BRANCH_HALT,
1685 .clkr = {
1686 .enable_reg = 0x3444,
1687 .enable_mask = BIT(0),
1688 .hw.init = &(struct clk_init_data){
1689 .name = "camss_gp0_clk",
1690 .parent_hws = (const struct clk_hw *[]){ &camss_gp0_clk_src.clkr.hw },
1691 .num_parents = 1,
1692 .flags = CLK_SET_RATE_PARENT,
1693 .ops = &clk_branch2_ops,
1694 },
1695 },
1696 };
1697
1698 static struct clk_branch camss_gp1_clk = {
1699 .halt_reg = 0x3474,
1700 .halt_check = BRANCH_HALT,
1701 .clkr = {
1702 .enable_reg = 0x3474,
1703 .enable_mask = BIT(0),
1704 .hw.init = &(struct clk_init_data){
1705 .name = "camss_gp1_clk",
1706 .parent_hws = (const struct clk_hw *[]){ &camss_gp1_clk_src.clkr.hw },
1707 .num_parents = 1,
1708 .flags = CLK_SET_RATE_PARENT,
1709 .ops = &clk_branch2_ops,
1710 },
1711 },
1712 };
1713
1714 static struct clk_branch camss_ispif_ahb_clk = {
1715 .halt_reg = 0x3224,
1716 .halt_check = BRANCH_HALT,
1717 .clkr = {
1718 .enable_reg = 0x3224,
1719 .enable_mask = BIT(0),
1720 .hw.init = &(struct clk_init_data){
1721 .name = "camss_ispif_ahb_clk",
1722 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1723 .num_parents = 1,
1724 .ops = &clk_branch2_ops,
1725 },
1726 },
1727 };
1728
1729 static struct clk_branch camss_jpeg0_clk = {
1730 .halt_reg = 0x35a8,
1731 .halt_check = BRANCH_HALT,
1732 .clkr = {
1733 .enable_reg = 0x35a8,
1734 .enable_mask = BIT(0),
1735 .hw.init = &(struct clk_init_data){
1736 .name = "camss_jpeg0_clk",
1737 .parent_hws = (const struct clk_hw *[]){ &jpeg0_clk_src.clkr.hw },
1738 .num_parents = 1,
1739 .flags = CLK_SET_RATE_PARENT,
1740 .ops = &clk_branch2_ops,
1741 },
1742 },
1743 };
1744
1745 static struct clk_branch camss_jpeg_ahb_clk = {
1746 .halt_reg = 0x35b4,
1747 .halt_check = BRANCH_HALT,
1748 .clkr = {
1749 .enable_reg = 0x35b4,
1750 .enable_mask = BIT(0),
1751 .hw.init = &(struct clk_init_data){
1752 .name = "camss_jpeg_ahb_clk",
1753 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1754 .num_parents = 1,
1755 .ops = &clk_branch2_ops,
1756 },
1757 },
1758 };
1759
1760 static struct clk_branch camss_jpeg_axi_clk = {
1761 .halt_reg = 0x35b8,
1762 .halt_check = BRANCH_HALT,
1763 .clkr = {
1764 .enable_reg = 0x35b8,
1765 .enable_mask = BIT(0),
1766 .hw.init = &(struct clk_init_data){
1767 .name = "camss_jpeg_axi_clk",
1768 .ops = &clk_branch2_ops,
1769 },
1770 },
1771 };
1772
1773 static struct clk_branch throttle_camss_axi_clk = {
1774 .halt_reg = 0x3c3c,
1775 .halt_check = BRANCH_HALT,
1776 .clkr = {
1777 .enable_reg = 0x3c3c,
1778 .enable_mask = BIT(0),
1779 .hw.init = &(struct clk_init_data){
1780 .name = "throttle_camss_axi_clk",
1781 .ops = &clk_branch2_ops,
1782 },
1783 },
1784 };
1785
1786 static struct clk_branch camss_mclk0_clk = {
1787 .halt_reg = 0x3384,
1788 .halt_check = BRANCH_HALT,
1789 .clkr = {
1790 .enable_reg = 0x3384,
1791 .enable_mask = BIT(0),
1792 .hw.init = &(struct clk_init_data){
1793 .name = "camss_mclk0_clk",
1794 .parent_hws = (const struct clk_hw *[]){ &mclk0_clk_src.clkr.hw },
1795 .num_parents = 1,
1796 .flags = CLK_SET_RATE_PARENT,
1797 .ops = &clk_branch2_ops,
1798 },
1799 },
1800 };
1801
1802 static struct clk_branch camss_mclk1_clk = {
1803 .halt_reg = 0x33b4,
1804 .halt_check = BRANCH_HALT,
1805 .clkr = {
1806 .enable_reg = 0x33b4,
1807 .enable_mask = BIT(0),
1808 .hw.init = &(struct clk_init_data){
1809 .name = "camss_mclk1_clk",
1810 .parent_hws = (const struct clk_hw *[]){ &mclk1_clk_src.clkr.hw },
1811 .num_parents = 1,
1812 .flags = CLK_SET_RATE_PARENT,
1813 .ops = &clk_branch2_ops,
1814 },
1815 },
1816 };
1817
1818 static struct clk_branch camss_mclk2_clk = {
1819 .halt_reg = 0x33e4,
1820 .halt_check = BRANCH_HALT,
1821 .clkr = {
1822 .enable_reg = 0x33e4,
1823 .enable_mask = BIT(0),
1824 .hw.init = &(struct clk_init_data){
1825 .name = "camss_mclk2_clk",
1826 .parent_hws = (const struct clk_hw *[]){ &mclk2_clk_src.clkr.hw },
1827 .num_parents = 1,
1828 .flags = CLK_SET_RATE_PARENT,
1829 .ops = &clk_branch2_ops,
1830 },
1831 },
1832 };
1833
1834 static struct clk_branch camss_mclk3_clk = {
1835 .halt_reg = 0x3414,
1836 .halt_check = BRANCH_HALT,
1837 .clkr = {
1838 .enable_reg = 0x3414,
1839 .enable_mask = BIT(0),
1840 .hw.init = &(struct clk_init_data){
1841 .name = "camss_mclk3_clk",
1842 .parent_hws = (const struct clk_hw *[]){ &mclk3_clk_src.clkr.hw },
1843 .num_parents = 1,
1844 .flags = CLK_SET_RATE_PARENT,
1845 .ops = &clk_branch2_ops,
1846 },
1847 },
1848 };
1849
1850 static struct clk_branch camss_micro_ahb_clk = {
1851 .halt_reg = 0x3494,
1852 .halt_check = BRANCH_HALT,
1853 .clkr = {
1854 .enable_reg = 0x3494,
1855 .enable_mask = BIT(0),
1856 .hw.init = &(struct clk_init_data){
1857 .name = "camss_micro_ahb_clk",
1858 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1859 .num_parents = 1,
1860 .ops = &clk_branch2_ops,
1861 },
1862 },
1863 };
1864
1865 static struct clk_branch camss_top_ahb_clk = {
1866 .halt_reg = 0x3484,
1867 .halt_check = BRANCH_HALT,
1868 .clkr = {
1869 .enable_reg = 0x3484,
1870 .enable_mask = BIT(0),
1871 .hw.init = &(struct clk_init_data){
1872 .name = "camss_top_ahb_clk",
1873 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1874 .num_parents = 1,
1875 .ops = &clk_branch2_ops,
1876 },
1877 },
1878 };
1879
1880 static struct clk_branch camss_vfe0_ahb_clk = {
1881 .halt_reg = 0x3668,
1882 .halt_check = BRANCH_HALT,
1883 .clkr = {
1884 .enable_reg = 0x3668,
1885 .enable_mask = BIT(0),
1886 .hw.init = &(struct clk_init_data){
1887 .name = "camss_vfe0_ahb_clk",
1888 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1889 .num_parents = 1,
1890 .ops = &clk_branch2_ops,
1891 },
1892 },
1893 };
1894
1895 static struct clk_branch camss_vfe0_clk = {
1896 .halt_reg = 0x36a8,
1897 .halt_check = BRANCH_HALT,
1898 .clkr = {
1899 .enable_reg = 0x36a8,
1900 .enable_mask = BIT(0),
1901 .hw.init = &(struct clk_init_data){
1902 .name = "camss_vfe0_clk",
1903 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
1904 .num_parents = 1,
1905 .flags = CLK_SET_RATE_PARENT,
1906 .ops = &clk_branch2_ops,
1907 },
1908 },
1909 };
1910
1911 static struct clk_branch camss_vfe0_stream_clk = {
1912 .halt_reg = 0x3720,
1913 .halt_check = BRANCH_HALT,
1914 .clkr = {
1915 .enable_reg = 0x3720,
1916 .enable_mask = BIT(0),
1917 .hw.init = &(struct clk_init_data){
1918 .name = "camss_vfe0_stream_clk",
1919 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
1920 .num_parents = 1,
1921 .ops = &clk_branch2_ops,
1922 },
1923 },
1924 };
1925
1926 static struct clk_branch camss_vfe1_ahb_clk = {
1927 .halt_reg = 0x3678,
1928 .halt_check = BRANCH_HALT,
1929 .clkr = {
1930 .enable_reg = 0x3678,
1931 .enable_mask = BIT(0),
1932 .hw.init = &(struct clk_init_data){
1933 .name = "camss_vfe1_ahb_clk",
1934 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1935 .num_parents = 1,
1936 .ops = &clk_branch2_ops,
1937 },
1938 },
1939 };
1940
1941 static struct clk_branch camss_vfe1_clk = {
1942 .halt_reg = 0x36ac,
1943 .halt_check = BRANCH_HALT,
1944 .clkr = {
1945 .enable_reg = 0x36ac,
1946 .enable_mask = BIT(0),
1947 .hw.init = &(struct clk_init_data){
1948 .name = "camss_vfe1_clk",
1949 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
1950 .num_parents = 1,
1951 .flags = CLK_SET_RATE_PARENT,
1952 .ops = &clk_branch2_ops,
1953 },
1954 },
1955 };
1956
1957 static struct clk_branch camss_vfe1_stream_clk = {
1958 .halt_reg = 0x3724,
1959 .halt_check = BRANCH_HALT,
1960 .clkr = {
1961 .enable_reg = 0x3724,
1962 .enable_mask = BIT(0),
1963 .hw.init = &(struct clk_init_data){
1964 .name = "camss_vfe1_stream_clk",
1965 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
1966 .num_parents = 1,
1967 .ops = &clk_branch2_ops,
1968 },
1969 },
1970 };
1971
1972 static struct clk_branch camss_vfe_vbif_ahb_clk = {
1973 .halt_reg = 0x36b8,
1974 .halt_check = BRANCH_HALT,
1975 .clkr = {
1976 .enable_reg = 0x36b8,
1977 .enable_mask = BIT(0),
1978 .hw.init = &(struct clk_init_data){
1979 .name = "camss_vfe_vbif_ahb_clk",
1980 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1981 .num_parents = 1,
1982 .ops = &clk_branch2_ops,
1983 },
1984 },
1985 };
1986
1987 static struct clk_branch camss_vfe_vbif_axi_clk = {
1988 .halt_reg = 0x36bc,
1989 .halt_check = BRANCH_HALT,
1990 .clkr = {
1991 .enable_reg = 0x36bc,
1992 .enable_mask = BIT(0),
1993 .hw.init = &(struct clk_init_data){
1994 .name = "camss_vfe_vbif_axi_clk",
1995 .ops = &clk_branch2_ops,
1996 },
1997 },
1998 };
1999
2000 static struct clk_branch csiphy_ahb2crif_clk = {
2001 .halt_reg = 0x374c,
2002 .halt_check = BRANCH_HALT,
2003 .hwcg_reg = 0x374c,
2004 .hwcg_bit = 1,
2005 .clkr = {
2006 .enable_reg = 0x374c,
2007 .enable_mask = BIT(0),
2008 .hw.init = &(struct clk_init_data){
2009 .name = "csiphy_ahb2crif_clk",
2010 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2011 .num_parents = 1,
2012 .ops = &clk_branch2_ops,
2013 },
2014 },
2015 };
2016
2017 static struct clk_branch mdss_ahb_clk = {
2018 .halt_reg = 0x2308,
2019 .halt_check = BRANCH_HALT,
2020 .hwcg_reg = 0x8a004,
2021 .hwcg_bit = 1,
2022 .clkr = {
2023 .enable_reg = 0x2308,
2024 .enable_mask = BIT(0),
2025 .hw.init = &(struct clk_init_data){
2026 .name = "mdss_ahb_clk",
2027 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2028 .flags = CLK_SET_RATE_PARENT,
2029 .num_parents = 1,
2030 .ops = &clk_branch2_ops,
2031 },
2032 },
2033 };
2034
2035 static const struct freq_tbl ftbl_axi_clk_src[] = {
2036 F(75000000, P_GPLL0, 8, 0, 0),
2037 F(171428571, P_GPLL0, 3.5, 0, 0),
2038 F(240000000, P_GPLL0, 2.5, 0, 0),
2039 F(323200000, P_MMPLL0, 2.5, 0, 0),
2040 F(406000000, P_MMPLL0, 2, 0, 0),
2041 { }
2042 };
2043
2044 /* RO to linux */
2045 static struct clk_rcg2 axi_clk_src = {
2046 .cmd_rcgr = 0xd000,
2047 .hid_width = 5,
2048 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
2049 .freq_tbl = ftbl_axi_clk_src,
2050 .clkr.hw.init = &(struct clk_init_data){
2051 .name = "axi_clk_src",
2052 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
2053 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
2054 .ops = &clk_rcg2_ops,
2055 },
2056 };
2057
2058 static struct clk_branch mdss_axi_clk = {
2059 .halt_reg = 0x2310,
2060 .halt_check = BRANCH_HALT,
2061 .clkr = {
2062 .enable_reg = 0x2310,
2063 .enable_mask = BIT(0),
2064 .hw.init = &(struct clk_init_data){
2065 .name = "mdss_axi_clk",
2066 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2067 .ops = &clk_branch2_ops,
2068 },
2069 },
2070 };
2071
2072 static struct clk_branch throttle_mdss_axi_clk = {
2073 .halt_reg = 0x246c,
2074 .halt_check = BRANCH_HALT,
2075 .hwcg_reg = 0x246c,
2076 .hwcg_bit = 1,
2077 .clkr = {
2078 .enable_reg = 0x246c,
2079 .enable_mask = BIT(0),
2080 .hw.init = &(struct clk_init_data){
2081 .name = "throttle_mdss_axi_clk",
2082 .ops = &clk_branch2_ops,
2083 },
2084 },
2085 };
2086
2087 static struct clk_branch mdss_byte0_clk = {
2088 .halt_reg = 0x233c,
2089 .halt_check = BRANCH_HALT,
2090 .clkr = {
2091 .enable_reg = 0x233c,
2092 .enable_mask = BIT(0),
2093 .hw.init = &(struct clk_init_data){
2094 .name = "mdss_byte0_clk",
2095 .parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
2096 .num_parents = 1,
2097 .flags = CLK_SET_RATE_PARENT,
2098 .ops = &clk_branch2_ops,
2099 },
2100 },
2101 };
2102
2103 static struct clk_regmap_div mdss_byte0_intf_div_clk = {
2104 .reg = 0x237c,
2105 .shift = 0,
2106 .width = 2,
2107 /*
2108 * NOTE: Op does not work for div-3. Current assumption is that div-3
2109 * is not a recommended setting for this divider.
2110 */
2111 .clkr = {
2112 .hw.init = &(struct clk_init_data){
2113 .name = "mdss_byte0_intf_div_clk",
2114 .parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
2115 .num_parents = 1,
2116 .ops = &clk_regmap_div_ops,
2117 .flags = CLK_GET_RATE_NOCACHE,
2118 },
2119 },
2120 };
2121
2122 static struct clk_branch mdss_byte0_intf_clk = {
2123 .halt_reg = 0x2374,
2124 .halt_check = BRANCH_HALT,
2125 .clkr = {
2126 .enable_reg = 0x2374,
2127 .enable_mask = BIT(0),
2128 .hw.init = &(struct clk_init_data){
2129 .name = "mdss_byte0_intf_clk",
2130 .parent_hws = (const struct clk_hw *[]){ &mdss_byte0_intf_div_clk.clkr.hw },
2131 .num_parents = 1,
2132 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2133 .ops = &clk_branch2_ops,
2134 },
2135 },
2136 };
2137
2138 static struct clk_branch mdss_byte1_clk = {
2139 .halt_reg = 0x2340,
2140 .halt_check = BRANCH_HALT,
2141 .clkr = {
2142 .enable_reg = 0x2340,
2143 .enable_mask = BIT(0),
2144 .hw.init = &(struct clk_init_data){
2145 .name = "mdss_byte1_clk",
2146 .parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
2147 .num_parents = 1,
2148 .flags = CLK_SET_RATE_PARENT,
2149 .ops = &clk_branch2_ops,
2150 },
2151 },
2152 };
2153
2154 static struct clk_regmap_div mdss_byte1_intf_div_clk = {
2155 .reg = 0x2380,
2156 .shift = 0,
2157 .width = 2,
2158 /*
2159 * NOTE: Op does not work for div-3. Current assumption is that div-3
2160 * is not a recommended setting for this divider.
2161 */
2162 .clkr = {
2163 .hw.init = &(struct clk_init_data){
2164 .name = "mdss_byte1_intf_div_clk",
2165 .parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
2166 .num_parents = 1,
2167 .ops = &clk_regmap_div_ops,
2168 .flags = CLK_GET_RATE_NOCACHE,
2169 },
2170 },
2171 };
2172
2173 static struct clk_branch mdss_byte1_intf_clk = {
2174 .halt_reg = 0x2378,
2175 .halt_check = BRANCH_HALT,
2176 .clkr = {
2177 .enable_reg = 0x2378,
2178 .enable_mask = BIT(0),
2179 .hw.init = &(struct clk_init_data){
2180 .name = "mdss_byte1_intf_clk",
2181 .parent_hws = (const struct clk_hw *[]){ &mdss_byte1_intf_div_clk.clkr.hw },
2182 .num_parents = 1,
2183 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2184 .ops = &clk_branch2_ops,
2185 },
2186 },
2187 };
2188
2189 static struct clk_branch mdss_dp_aux_clk = {
2190 .halt_reg = 0x2364,
2191 .halt_check = BRANCH_HALT,
2192 .clkr = {
2193 .enable_reg = 0x2364,
2194 .enable_mask = BIT(0),
2195 .hw.init = &(struct clk_init_data){
2196 .name = "mdss_dp_aux_clk",
2197 .parent_hws = (const struct clk_hw *[]){ &dp_aux_clk_src.clkr.hw },
2198 .num_parents = 1,
2199 .flags = CLK_SET_RATE_PARENT,
2200 .ops = &clk_branch2_ops,
2201 },
2202 },
2203 };
2204
2205 static struct clk_branch mdss_dp_crypto_clk = {
2206 .halt_reg = 0x235c,
2207 .halt_check = BRANCH_HALT,
2208 .clkr = {
2209 .enable_reg = 0x235c,
2210 .enable_mask = BIT(0),
2211 .hw.init = &(struct clk_init_data){
2212 .name = "mdss_dp_crypto_clk",
2213 .parent_hws = (const struct clk_hw *[]){ &dp_crypto_clk_src.clkr.hw },
2214 .num_parents = 1,
2215 .flags = CLK_SET_RATE_PARENT,
2216 .ops = &clk_branch2_ops,
2217 },
2218 },
2219 };
2220
2221 static struct clk_branch mdss_dp_gtc_clk = {
2222 .halt_reg = 0x2368,
2223 .halt_check = BRANCH_HALT,
2224 .clkr = {
2225 .enable_reg = 0x2368,
2226 .enable_mask = BIT(0),
2227 .hw.init = &(struct clk_init_data){
2228 .name = "mdss_dp_gtc_clk",
2229 .parent_hws = (const struct clk_hw *[]){ &dp_gtc_clk_src.clkr.hw },
2230 .num_parents = 1,
2231 .flags = CLK_SET_RATE_PARENT,
2232 .ops = &clk_branch2_ops,
2233 },
2234 },
2235 };
2236
2237 static struct clk_branch mdss_dp_link_clk = {
2238 .halt_reg = 0x2354,
2239 .halt_check = BRANCH_HALT,
2240 .clkr = {
2241 .enable_reg = 0x2354,
2242 .enable_mask = BIT(0),
2243 .hw.init = &(struct clk_init_data){
2244 .name = "mdss_dp_link_clk",
2245 .parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw },
2246 .num_parents = 1,
2247 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
2248 .ops = &clk_branch2_ops,
2249 },
2250 },
2251 };
2252
2253 /* Reset state of MDSS_DP_LINK_INTF_DIV is 0x3 (div-4) */
2254 static struct clk_branch mdss_dp_link_intf_clk = {
2255 .halt_reg = 0x2358,
2256 .halt_check = BRANCH_HALT,
2257 .clkr = {
2258 .enable_reg = 0x2358,
2259 .enable_mask = BIT(0),
2260 .hw.init = &(struct clk_init_data){
2261 .name = "mdss_dp_link_intf_clk",
2262 .parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw },
2263 .num_parents = 1,
2264 .ops = &clk_branch2_ops,
2265 },
2266 },
2267 };
2268
2269 static struct clk_branch mdss_dp_pixel_clk = {
2270 .halt_reg = 0x2360,
2271 .halt_check = BRANCH_HALT,
2272 .clkr = {
2273 .enable_reg = 0x2360,
2274 .enable_mask = BIT(0),
2275 .hw.init = &(struct clk_init_data){
2276 .name = "mdss_dp_pixel_clk",
2277 .parent_hws = (const struct clk_hw *[]){ &dp_pixel_clk_src.clkr.hw },
2278 .num_parents = 1,
2279 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
2280 .ops = &clk_branch2_ops,
2281 },
2282 },
2283 };
2284
2285 static struct clk_branch mdss_esc0_clk = {
2286 .halt_reg = 0x2344,
2287 .halt_check = BRANCH_HALT,
2288 .clkr = {
2289 .enable_reg = 0x2344,
2290 .enable_mask = BIT(0),
2291 .hw.init = &(struct clk_init_data){
2292 .name = "mdss_esc0_clk",
2293 .parent_hws = (const struct clk_hw *[]){ &esc0_clk_src.clkr.hw },
2294 .num_parents = 1,
2295 .flags = CLK_SET_RATE_PARENT,
2296 .ops = &clk_branch2_ops,
2297 },
2298 },
2299 };
2300
2301 static struct clk_branch mdss_esc1_clk = {
2302 .halt_reg = 0x2348,
2303 .halt_check = BRANCH_HALT,
2304 .clkr = {
2305 .enable_reg = 0x2348,
2306 .enable_mask = BIT(0),
2307 .hw.init = &(struct clk_init_data){
2308 .name = "mdss_esc1_clk",
2309 .parent_hws = (const struct clk_hw *[]){ &esc1_clk_src.clkr.hw },
2310 .num_parents = 1,
2311 .flags = CLK_SET_RATE_PARENT,
2312 .ops = &clk_branch2_ops,
2313 },
2314 },
2315 };
2316
2317 static struct clk_branch mdss_hdmi_dp_ahb_clk = {
2318 .halt_reg = 0x230c,
2319 .halt_check = BRANCH_HALT,
2320 .clkr = {
2321 .enable_reg = 0x230c,
2322 .enable_mask = BIT(0),
2323 .hw.init = &(struct clk_init_data){
2324 .name = "mdss_hdmi_dp_ahb_clk",
2325 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2326 .num_parents = 1,
2327 .ops = &clk_branch2_ops,
2328 },
2329 },
2330 };
2331
2332 static struct clk_branch mdss_mdp_clk = {
2333 .halt_reg = 0x231c,
2334 .halt_check = BRANCH_HALT,
2335 .clkr = {
2336 .enable_reg = 0x231c,
2337 .enable_mask = BIT(0),
2338 .hw.init = &(struct clk_init_data){
2339 .name = "mdss_mdp_clk",
2340 .parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw },
2341 .num_parents = 1,
2342 .flags = CLK_SET_RATE_PARENT,
2343 .ops = &clk_branch2_ops,
2344 },
2345 },
2346 };
2347
2348 static struct clk_branch mdss_pclk0_clk = {
2349 .halt_reg = 0x2314,
2350 .halt_check = BRANCH_HALT,
2351 .clkr = {
2352 .enable_reg = 0x2314,
2353 .enable_mask = BIT(0),
2354 .hw.init = &(struct clk_init_data){
2355 .name = "mdss_pclk0_clk",
2356 .parent_hws = (const struct clk_hw *[]){ &pclk0_clk_src.clkr.hw },
2357 .num_parents = 1,
2358 .flags = CLK_SET_RATE_PARENT,
2359 .ops = &clk_branch2_ops,
2360 },
2361 },
2362 };
2363
2364 static struct clk_branch mdss_pclk1_clk = {
2365 .halt_reg = 0x2318,
2366 .halt_check = BRANCH_HALT,
2367 .clkr = {
2368 .enable_reg = 0x2318,
2369 .enable_mask = BIT(0),
2370 .hw.init = &(struct clk_init_data){
2371 .name = "mdss_pclk1_clk",
2372 .parent_hws = (const struct clk_hw *[]){ &pclk1_clk_src.clkr.hw },
2373 .num_parents = 1,
2374 .flags = CLK_SET_RATE_PARENT,
2375 .ops = &clk_branch2_ops,
2376 },
2377 },
2378 };
2379
2380 static struct clk_branch mdss_rot_clk = {
2381 .halt_reg = 0x2350,
2382 .halt_check = BRANCH_HALT,
2383 .clkr = {
2384 .enable_reg = 0x2350,
2385 .enable_mask = BIT(0),
2386 .hw.init = &(struct clk_init_data){
2387 .name = "mdss_rot_clk",
2388 .parent_hws = (const struct clk_hw *[]){ &rot_clk_src.clkr.hw },
2389 .num_parents = 1,
2390 .flags = CLK_SET_RATE_PARENT,
2391 .ops = &clk_branch2_ops,
2392 },
2393 },
2394 };
2395
2396 static struct clk_branch mdss_vsync_clk = {
2397 .halt_reg = 0x2328,
2398 .halt_check = BRANCH_HALT,
2399 .clkr = {
2400 .enable_reg = 0x2328,
2401 .enable_mask = BIT(0),
2402 .hw.init = &(struct clk_init_data){
2403 .name = "mdss_vsync_clk",
2404 .parent_hws = (const struct clk_hw *[]){ &vsync_clk_src.clkr.hw },
2405 .num_parents = 1,
2406 .flags = CLK_SET_RATE_PARENT,
2407 .ops = &clk_branch2_ops,
2408 },
2409 },
2410 };
2411
2412 static struct clk_branch mnoc_ahb_clk = {
2413 .halt_reg = 0x5024,
2414 .halt_check = BRANCH_VOTED,
2415 .clkr = {
2416 .enable_reg = 0x5024,
2417 .enable_mask = BIT(0),
2418 .hw.init = &(struct clk_init_data){
2419 .name = "mnoc_ahb_clk",
2420 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2421 .num_parents = 1,
2422 .flags = CLK_SET_RATE_PARENT,
2423 .ops = &clk_branch2_ops,
2424 },
2425 },
2426 };
2427
2428 static struct clk_branch misc_ahb_clk = {
2429 .halt_reg = 0x328,
2430 .halt_check = BRANCH_HALT,
2431 .hwcg_reg = 0x328,
2432 .hwcg_bit = 1,
2433 .clkr = {
2434 .enable_reg = 0x328,
2435 .enable_mask = BIT(0),
2436 .hw.init = &(struct clk_init_data){
2437 .name = "misc_ahb_clk",
2438 /*
2439 * Dependency to be enabled before the branch is
2440 * enabled.
2441 */
2442 .parent_hws = (const struct clk_hw *[]){ &mnoc_ahb_clk.clkr.hw },
2443 .num_parents = 1,
2444 .ops = &clk_branch2_ops,
2445 },
2446 },
2447 };
2448
2449 static struct clk_branch misc_cxo_clk = {
2450 .halt_reg = 0x324,
2451 .halt_check = BRANCH_HALT,
2452 .clkr = {
2453 .enable_reg = 0x324,
2454 .enable_mask = BIT(0),
2455 .hw.init = &(struct clk_init_data){
2456 .name = "misc_cxo_clk",
2457 .parent_data = &(const struct clk_parent_data){
2458 .fw_name = "xo",
2459 },
2460 .num_parents = 1,
2461 .ops = &clk_branch2_ops,
2462 },
2463 },
2464 };
2465
2466 static struct clk_branch snoc_dvm_axi_clk = {
2467 .halt_reg = 0xe040,
2468 .halt_check = BRANCH_HALT,
2469 .clkr = {
2470 .enable_reg = 0xe040,
2471 .enable_mask = BIT(0),
2472 .hw.init = &(struct clk_init_data){
2473 .name = "snoc_dvm_axi_clk",
2474 .ops = &clk_branch2_ops,
2475 },
2476 },
2477 };
2478
2479 static struct clk_branch video_ahb_clk = {
2480 .halt_reg = 0x1030,
2481 .halt_check = BRANCH_HALT,
2482 .hwcg_reg = 0x1030,
2483 .hwcg_bit = 1,
2484 .clkr = {
2485 .enable_reg = 0x1030,
2486 .enable_mask = BIT(0),
2487 .hw.init = &(struct clk_init_data){
2488 .name = "video_ahb_clk",
2489 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2490 .num_parents = 1,
2491 .ops = &clk_branch2_ops,
2492 },
2493 },
2494 };
2495
2496 static struct clk_branch video_axi_clk = {
2497 .halt_reg = 0x1034,
2498 .halt_check = BRANCH_HALT,
2499 .clkr = {
2500 .enable_reg = 0x1034,
2501 .enable_mask = BIT(0),
2502 .hw.init = &(struct clk_init_data){
2503 .name = "video_axi_clk",
2504 .ops = &clk_branch2_ops,
2505 },
2506 },
2507 };
2508
2509 static struct clk_branch throttle_video_axi_clk = {
2510 .halt_reg = 0x118c,
2511 .halt_check = BRANCH_HALT,
2512 .hwcg_reg = 0x118c,
2513 .hwcg_bit = 1,
2514 .clkr = {
2515 .enable_reg = 0x118c,
2516 .enable_mask = BIT(0),
2517 .hw.init = &(struct clk_init_data){
2518 .name = "throttle_video_axi_clk",
2519 .ops = &clk_branch2_ops,
2520 },
2521 },
2522 };
2523
2524 static struct clk_branch video_core_clk = {
2525 .halt_reg = 0x1028,
2526 .halt_check = BRANCH_HALT,
2527 .clkr = {
2528 .enable_reg = 0x1028,
2529 .enable_mask = BIT(0),
2530 .hw.init = &(struct clk_init_data){
2531 .name = "video_core_clk",
2532 .parent_hws = (const struct clk_hw *[]){ &video_core_clk_src.clkr.hw },
2533 .num_parents = 1,
2534 .flags = CLK_SET_RATE_PARENT,
2535 .ops = &clk_branch2_ops,
2536 },
2537 },
2538 };
2539
2540 static struct clk_branch video_subcore0_clk = {
2541 .halt_reg = 0x1048,
2542 .halt_check = BRANCH_HALT_SKIP,
2543 .clkr = {
2544 .enable_reg = 0x1048,
2545 .enable_mask = BIT(0),
2546 .hw.init = &(struct clk_init_data){
2547 .name = "video_subcore0_clk",
2548 .parent_hws = (const struct clk_hw *[]){ &video_core_clk_src.clkr.hw },
2549 .num_parents = 1,
2550 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2551 .ops = &clk_branch2_ops,
2552 },
2553 },
2554 };
2555
2556 static struct gdsc venus_gdsc = {
2557 .gdscr = 0x1024,
2558 .cxcs = (unsigned int[]){ 0x1028, 0x1034, 0x1048 },
2559 .cxc_count = 3,
2560 .pd = {
2561 .name = "venus",
2562 },
2563 .pwrsts = PWRSTS_OFF_ON,
2564 };
2565
2566 static struct gdsc venus_core0_gdsc = {
2567 .gdscr = 0x1040,
2568 .pd = {
2569 .name = "venus_core0",
2570 },
2571 .parent = &venus_gdsc.pd,
2572 .pwrsts = PWRSTS_OFF_ON,
2573 .flags = HW_CTRL,
2574 };
2575
2576 static struct gdsc mdss_gdsc = {
2577 .gdscr = 0x2304,
2578 .pd = {
2579 .name = "mdss",
2580 },
2581 .cxcs = (unsigned int []){ 0x2040 },
2582 .cxc_count = 1,
2583 .pwrsts = PWRSTS_OFF_ON,
2584 };
2585
2586 static struct gdsc camss_top_gdsc = {
2587 .gdscr = 0x34a0,
2588 .pd = {
2589 .name = "camss_top",
2590 },
2591 .pwrsts = PWRSTS_OFF_ON,
2592 };
2593
2594 static struct gdsc camss_vfe0_gdsc = {
2595 .gdscr = 0x3664,
2596 .pd = {
2597 .name = "camss_vfe0",
2598 },
2599 .parent = &camss_top_gdsc.pd,
2600 .pwrsts = PWRSTS_OFF_ON,
2601 };
2602
2603 static struct gdsc camss_vfe1_gdsc = {
2604 .gdscr = 0x3674,
2605 .pd = {
2606 .name = "camss_vfe1_gdsc",
2607 },
2608 .parent = &camss_top_gdsc.pd,
2609 .pwrsts = PWRSTS_OFF_ON,
2610 };
2611
2612 static struct gdsc camss_cpp_gdsc = {
2613 .gdscr = 0x36d4,
2614 .pd = {
2615 .name = "camss_cpp",
2616 },
2617 .parent = &camss_top_gdsc.pd,
2618 .pwrsts = PWRSTS_OFF_ON,
2619 };
2620
2621 /* This GDSC seems to hang the whole multimedia subsystem.
2622 static struct gdsc bimc_smmu_gdsc = {
2623 .gdscr = 0xe020,
2624 .gds_hw_ctrl = 0xe024,
2625 .pd = {
2626 .name = "bimc_smmu",
2627 },
2628 .pwrsts = PWRSTS_OFF_ON,
2629 .parent = &bimc_smmu_gdsc.pd,
2630 .flags = HW_CTRL,
2631 };
2632 */
2633
2634 static struct clk_regmap *mmcc_660_clocks[] = {
2635 [AHB_CLK_SRC] = &ahb_clk_src.clkr,
2636 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2637 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2638 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
2639 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
2640 [CCI_CLK_SRC] = &cci_clk_src.clkr,
2641 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2642 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2643 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2644 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2645 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2646 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2647 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2648 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2649 [CSIPHY_CLK_SRC] = &csiphy_clk_src.clkr,
2650 [DP_AUX_CLK_SRC] = &dp_aux_clk_src.clkr,
2651 [DP_CRYPTO_CLK_SRC] = &dp_crypto_clk_src.clkr,
2652 [DP_GTC_CLK_SRC] = &dp_gtc_clk_src.clkr,
2653 [DP_LINK_CLK_SRC] = &dp_link_clk_src.clkr,
2654 [DP_PIXEL_CLK_SRC] = &dp_pixel_clk_src.clkr,
2655 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2656 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2657 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2658 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2659 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2660 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2661 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2662 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2663 [MMPLL0_PLL] = &mmpll0.clkr,
2664 [MMPLL10_PLL] = &mmpll10.clkr,
2665 [MMPLL3_PLL] = &mmpll3.clkr,
2666 [MMPLL4_PLL] = &mmpll4.clkr,
2667 [MMPLL5_PLL] = &mmpll5.clkr,
2668 [MMPLL6_PLL] = &mmpll6.clkr,
2669 [MMPLL7_PLL] = &mmpll7.clkr,
2670 [MMPLL8_PLL] = &mmpll8.clkr,
2671 [BIMC_SMMU_AHB_CLK] = &bimc_smmu_ahb_clk.clkr,
2672 [BIMC_SMMU_AXI_CLK] = &bimc_smmu_axi_clk.clkr,
2673 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
2674 [CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr,
2675 [CAMSS_CCI_CLK] = &camss_cci_clk.clkr,
2676 [CAMSS_CPHY_CSID0_CLK] = &camss_cphy_csid0_clk.clkr,
2677 [CAMSS_CPHY_CSID1_CLK] = &camss_cphy_csid1_clk.clkr,
2678 [CAMSS_CPHY_CSID2_CLK] = &camss_cphy_csid2_clk.clkr,
2679 [CAMSS_CPHY_CSID3_CLK] = &camss_cphy_csid3_clk.clkr,
2680 [CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr,
2681 [CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr,
2682 [CAMSS_CPP_CLK] = &camss_cpp_clk.clkr,
2683 [CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr,
2684 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2685 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2686 [CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr,
2687 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2688 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2689 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2690 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2691 [CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr,
2692 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2693 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2694 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
2695 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
2696 [CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr,
2697 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
2698 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
2699 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
2700 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
2701 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
2702 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
2703 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2704 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
2705 [CAMSS_CSIPHY0_CLK] = &camss_csiphy0_clk.clkr,
2706 [CAMSS_CSIPHY1_CLK] = &camss_csiphy1_clk.clkr,
2707 [CAMSS_CSIPHY2_CLK] = &camss_csiphy2_clk.clkr,
2708 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
2709 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
2710 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2711 [CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr,
2712 [CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr,
2713 [CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr,
2714 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2715 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2716 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
2717 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
2718 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2719 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2720 [CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr,
2721 [CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr,
2722 [CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr,
2723 [CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr,
2724 [CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr,
2725 [CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr,
2726 [CAMSS_VFE_VBIF_AHB_CLK] = &camss_vfe_vbif_ahb_clk.clkr,
2727 [CAMSS_VFE_VBIF_AXI_CLK] = &camss_vfe_vbif_axi_clk.clkr,
2728 [CSIPHY_AHB2CRIF_CLK] = &csiphy_ahb2crif_clk.clkr,
2729 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2730 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2731 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2732 [MDSS_BYTE0_INTF_CLK] = &mdss_byte0_intf_clk.clkr,
2733 [MDSS_BYTE0_INTF_DIV_CLK] = &mdss_byte0_intf_div_clk.clkr,
2734 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
2735 [MDSS_BYTE1_INTF_CLK] = &mdss_byte1_intf_clk.clkr,
2736 [MDSS_DP_AUX_CLK] = &mdss_dp_aux_clk.clkr,
2737 [MDSS_DP_CRYPTO_CLK] = &mdss_dp_crypto_clk.clkr,
2738 [MDSS_DP_GTC_CLK] = &mdss_dp_gtc_clk.clkr,
2739 [MDSS_DP_LINK_CLK] = &mdss_dp_link_clk.clkr,
2740 [MDSS_DP_LINK_INTF_CLK] = &mdss_dp_link_intf_clk.clkr,
2741 [MDSS_DP_PIXEL_CLK] = &mdss_dp_pixel_clk.clkr,
2742 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2743 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
2744 [MDSS_HDMI_DP_AHB_CLK] = &mdss_hdmi_dp_ahb_clk.clkr,
2745 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2746 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2747 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
2748 [MDSS_ROT_CLK] = &mdss_rot_clk.clkr,
2749 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2750 [MISC_AHB_CLK] = &misc_ahb_clk.clkr,
2751 [MISC_CXO_CLK] = &misc_cxo_clk.clkr,
2752 [MNOC_AHB_CLK] = &mnoc_ahb_clk.clkr,
2753 [SNOC_DVM_AXI_CLK] = &snoc_dvm_axi_clk.clkr,
2754 [THROTTLE_CAMSS_AXI_CLK] = &throttle_camss_axi_clk.clkr,
2755 [THROTTLE_MDSS_AXI_CLK] = &throttle_mdss_axi_clk.clkr,
2756 [THROTTLE_VIDEO_AXI_CLK] = &throttle_video_axi_clk.clkr,
2757 [VIDEO_AHB_CLK] = &video_ahb_clk.clkr,
2758 [VIDEO_AXI_CLK] = &video_axi_clk.clkr,
2759 [VIDEO_CORE_CLK] = &video_core_clk.clkr,
2760 [VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr,
2761 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2762 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2763 [ROT_CLK_SRC] = &rot_clk_src.clkr,
2764 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2765 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2766 [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr,
2767 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2768 [MDSS_BYTE1_INTF_DIV_CLK] = &mdss_byte1_intf_div_clk.clkr,
2769 [AXI_CLK_SRC] = &axi_clk_src.clkr,
2770 };
2771
2772 static struct gdsc *mmcc_sdm660_gdscs[] = {
2773 [VENUS_GDSC] = &venus_gdsc,
2774 [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
2775 [MDSS_GDSC] = &mdss_gdsc,
2776 [CAMSS_TOP_GDSC] = &camss_top_gdsc,
2777 [CAMSS_VFE0_GDSC] = &camss_vfe0_gdsc,
2778 [CAMSS_VFE1_GDSC] = &camss_vfe1_gdsc,
2779 [CAMSS_CPP_GDSC] = &camss_cpp_gdsc,
2780 };
2781
2782 static const struct qcom_reset_map mmcc_660_resets[] = {
2783 [MDSS_BCR] = { 0x2300 },
2784 [CAMSS_MICRO_BCR] = { 0x3490 },
2785 };
2786
2787 static const struct regmap_config mmcc_660_regmap_config = {
2788 .reg_bits = 32,
2789 .reg_stride = 4,
2790 .val_bits = 32,
2791 .max_register = 0x40000,
2792 .fast_io = true,
2793 };
2794
2795 static const struct qcom_cc_desc mmcc_660_desc = {
2796 .config = &mmcc_660_regmap_config,
2797 .clks = mmcc_660_clocks,
2798 .num_clks = ARRAY_SIZE(mmcc_660_clocks),
2799 .resets = mmcc_660_resets,
2800 .num_resets = ARRAY_SIZE(mmcc_660_resets),
2801 .gdscs = mmcc_sdm660_gdscs,
2802 .num_gdscs = ARRAY_SIZE(mmcc_sdm660_gdscs),
2803 };
2804
2805 static const struct of_device_id mmcc_660_match_table[] = {
2806 { .compatible = "qcom,mmcc-sdm660" },
2807 { .compatible = "qcom,mmcc-sdm630", .data = (void *)1UL },
2808 { }
2809 };
2810 MODULE_DEVICE_TABLE(of, mmcc_660_match_table);
2811
sdm630_clock_override(void)2812 static void sdm630_clock_override(void)
2813 {
2814 /* SDM630 has only one DSI */
2815 mmcc_660_desc.clks[BYTE1_CLK_SRC] = NULL;
2816 mmcc_660_desc.clks[MDSS_BYTE1_CLK] = NULL;
2817 mmcc_660_desc.clks[MDSS_BYTE1_INTF_DIV_CLK] = NULL;
2818 mmcc_660_desc.clks[MDSS_BYTE1_INTF_CLK] = NULL;
2819 mmcc_660_desc.clks[ESC1_CLK_SRC] = NULL;
2820 mmcc_660_desc.clks[MDSS_ESC1_CLK] = NULL;
2821 mmcc_660_desc.clks[PCLK1_CLK_SRC] = NULL;
2822 mmcc_660_desc.clks[MDSS_PCLK1_CLK] = NULL;
2823 }
2824
mmcc_660_probe(struct platform_device * pdev)2825 static int mmcc_660_probe(struct platform_device *pdev)
2826 {
2827 struct regmap *regmap;
2828 bool is_sdm630;
2829
2830 is_sdm630 = !!device_get_match_data(&pdev->dev);
2831
2832 regmap = qcom_cc_map(pdev, &mmcc_660_desc);
2833 if (IS_ERR(regmap))
2834 return PTR_ERR(regmap);
2835
2836 if (is_sdm630)
2837 sdm630_clock_override();
2838
2839 clk_alpha_pll_configure(&mmpll3, regmap, &mmpll3_config);
2840 clk_alpha_pll_configure(&mmpll4, regmap, &mmpll4_config);
2841 clk_alpha_pll_configure(&mmpll5, regmap, &mmpll5_config);
2842 clk_alpha_pll_configure(&mmpll7, regmap, &mmpll7_config);
2843 clk_alpha_pll_configure(&mmpll8, regmap, &mmpll8_config);
2844 clk_alpha_pll_configure(&mmpll10, regmap, &mmpll10_config);
2845
2846 return qcom_cc_really_probe(&pdev->dev, &mmcc_660_desc, regmap);
2847 }
2848
2849 static struct platform_driver mmcc_660_driver = {
2850 .probe = mmcc_660_probe,
2851 .driver = {
2852 .name = "mmcc-sdm660",
2853 .of_match_table = mmcc_660_match_table,
2854 },
2855 };
2856 module_platform_driver(mmcc_660_driver);
2857
2858 MODULE_DESCRIPTION("Qualcomm SDM630/SDM660 MMCC driver");
2859 MODULE_LICENSE("GPL v2");
2860