1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * IIO accel core driver for Freescale MMA7455L 3-axis 10-bit accelerometer
4 * Copyright 2015 Joachim Eastwood <manabian@gmail.com>
5 *
6 * UNSUPPORTED hardware features:
7 * - 8-bit mode with different scales
8 * - INT1/INT2 interrupts
9 * - Offset calibration
10 * - Events
11 */
12
13 #include <linux/delay.h>
14 #include <linux/iio/iio.h>
15 #include <linux/iio/sysfs.h>
16 #include <linux/iio/buffer.h>
17 #include <linux/iio/trigger.h>
18 #include <linux/iio/trigger_consumer.h>
19 #include <linux/iio/triggered_buffer.h>
20 #include <linux/module.h>
21 #include <linux/regmap.h>
22 #include <linux/types.h>
23
24 #include "mma7455.h"
25
26 #define MMA7455_REG_XOUTL 0x00
27 #define MMA7455_REG_XOUTH 0x01
28 #define MMA7455_REG_YOUTL 0x02
29 #define MMA7455_REG_YOUTH 0x03
30 #define MMA7455_REG_ZOUTL 0x04
31 #define MMA7455_REG_ZOUTH 0x05
32 #define MMA7455_REG_STATUS 0x09
33 #define MMA7455_STATUS_DRDY BIT(0)
34 #define MMA7455_REG_WHOAMI 0x0f
35 #define MMA7455_WHOAMI_ID 0x55
36 #define MMA7455_REG_MCTL 0x16
37 #define MMA7455_MCTL_MODE_STANDBY 0x00
38 #define MMA7455_MCTL_MODE_MEASURE 0x01
39 #define MMA7455_REG_CTL1 0x18
40 #define MMA7455_CTL1_DFBW_MASK BIT(7)
41 #define MMA7455_CTL1_DFBW_125HZ BIT(7)
42 #define MMA7455_CTL1_DFBW_62_5HZ 0
43 #define MMA7455_REG_TW 0x1e
44
45 /*
46 * When MMA7455 is used in 10-bit it has a fullscale of -8g
47 * corresponding to raw value -512. The userspace interface
48 * uses m/s^2 and we declare micro units.
49 * So scale factor is given by:
50 * g * 8 * 1e6 / 512 = 153228.90625, with g = 9.80665
51 */
52 #define MMA7455_10BIT_SCALE 153229
53
54 struct mma7455_data {
55 struct regmap *regmap;
56 /*
57 * Used to reorganize data. Will ensure correct alignment of
58 * the timestamp if present
59 */
60 struct {
61 __le16 channels[3];
62 aligned_s64 ts;
63 } scan;
64 };
65
mma7455_drdy(struct mma7455_data * mma7455)66 static int mma7455_drdy(struct mma7455_data *mma7455)
67 {
68 struct device *dev = regmap_get_device(mma7455->regmap);
69 unsigned int reg;
70 int tries = 3;
71 int ret;
72
73 while (tries-- > 0) {
74 ret = regmap_read(mma7455->regmap, MMA7455_REG_STATUS, ®);
75 if (ret)
76 return ret;
77
78 if (reg & MMA7455_STATUS_DRDY)
79 return 0;
80
81 msleep(20);
82 }
83
84 dev_warn(dev, "data not ready\n");
85
86 return -EIO;
87 }
88
mma7455_trigger_handler(int irq,void * p)89 static irqreturn_t mma7455_trigger_handler(int irq, void *p)
90 {
91 struct iio_poll_func *pf = p;
92 struct iio_dev *indio_dev = pf->indio_dev;
93 struct mma7455_data *mma7455 = iio_priv(indio_dev);
94 int ret;
95
96 ret = mma7455_drdy(mma7455);
97 if (ret)
98 goto done;
99
100 ret = regmap_bulk_read(mma7455->regmap, MMA7455_REG_XOUTL,
101 mma7455->scan.channels,
102 sizeof(mma7455->scan.channels));
103 if (ret)
104 goto done;
105
106 iio_push_to_buffers_with_ts(indio_dev, &mma7455->scan,
107 sizeof(mma7455->scan),
108 iio_get_time_ns(indio_dev));
109
110 done:
111 iio_trigger_notify_done(indio_dev->trig);
112
113 return IRQ_HANDLED;
114 }
115
mma7455_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)116 static int mma7455_read_raw(struct iio_dev *indio_dev,
117 struct iio_chan_spec const *chan,
118 int *val, int *val2, long mask)
119 {
120 struct mma7455_data *mma7455 = iio_priv(indio_dev);
121 unsigned int reg;
122 __le16 data;
123 int ret;
124
125 switch (mask) {
126 case IIO_CHAN_INFO_RAW:
127 if (iio_buffer_enabled(indio_dev))
128 return -EBUSY;
129
130 ret = mma7455_drdy(mma7455);
131 if (ret)
132 return ret;
133
134 ret = regmap_bulk_read(mma7455->regmap, chan->address, &data,
135 sizeof(data));
136 if (ret)
137 return ret;
138
139 *val = sign_extend32(le16_to_cpu(data),
140 chan->scan_type.realbits - 1);
141
142 return IIO_VAL_INT;
143
144 case IIO_CHAN_INFO_SCALE:
145 *val = 0;
146 *val2 = MMA7455_10BIT_SCALE;
147
148 return IIO_VAL_INT_PLUS_MICRO;
149
150 case IIO_CHAN_INFO_SAMP_FREQ:
151 ret = regmap_read(mma7455->regmap, MMA7455_REG_CTL1, ®);
152 if (ret)
153 return ret;
154
155 if (reg & MMA7455_CTL1_DFBW_MASK)
156 *val = 250;
157 else
158 *val = 125;
159
160 return IIO_VAL_INT;
161 }
162
163 return -EINVAL;
164 }
165
mma7455_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)166 static int mma7455_write_raw(struct iio_dev *indio_dev,
167 struct iio_chan_spec const *chan,
168 int val, int val2, long mask)
169 {
170 struct mma7455_data *mma7455 = iio_priv(indio_dev);
171 int i;
172
173 switch (mask) {
174 case IIO_CHAN_INFO_SAMP_FREQ:
175 if (val == 250 && val2 == 0)
176 i = MMA7455_CTL1_DFBW_125HZ;
177 else if (val == 125 && val2 == 0)
178 i = MMA7455_CTL1_DFBW_62_5HZ;
179 else
180 return -EINVAL;
181
182 return regmap_update_bits(mma7455->regmap, MMA7455_REG_CTL1,
183 MMA7455_CTL1_DFBW_MASK, i);
184
185 case IIO_CHAN_INFO_SCALE:
186 /* In 10-bit mode there is only one scale available */
187 if (val == 0 && val2 == MMA7455_10BIT_SCALE)
188 return 0;
189 break;
190 }
191
192 return -EINVAL;
193 }
194
195 static IIO_CONST_ATTR(sampling_frequency_available, "125 250");
196
197 static struct attribute *mma7455_attributes[] = {
198 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
199 NULL
200 };
201
202 static const struct attribute_group mma7455_group = {
203 .attrs = mma7455_attributes,
204 };
205
206 static const struct iio_info mma7455_info = {
207 .attrs = &mma7455_group,
208 .read_raw = mma7455_read_raw,
209 .write_raw = mma7455_write_raw,
210 };
211
212 #define MMA7455_CHANNEL(axis, idx) { \
213 .type = IIO_ACCEL, \
214 .modified = 1, \
215 .address = MMA7455_REG_##axis##OUTL,\
216 .channel2 = IIO_MOD_##axis, \
217 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
218 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
219 BIT(IIO_CHAN_INFO_SCALE), \
220 .scan_index = idx, \
221 .scan_type = { \
222 .sign = 's', \
223 .realbits = 10, \
224 .storagebits = 16, \
225 .endianness = IIO_LE, \
226 }, \
227 }
228
229 static const struct iio_chan_spec mma7455_channels[] = {
230 MMA7455_CHANNEL(X, 0),
231 MMA7455_CHANNEL(Y, 1),
232 MMA7455_CHANNEL(Z, 2),
233 IIO_CHAN_SOFT_TIMESTAMP(3),
234 };
235
236 static const unsigned long mma7455_scan_masks[] = {0x7, 0};
237
238 const struct regmap_config mma7455_core_regmap = {
239 .reg_bits = 8,
240 .val_bits = 8,
241 .max_register = MMA7455_REG_TW,
242 };
243 EXPORT_SYMBOL_NS_GPL(mma7455_core_regmap, "IIO_MMA7455");
244
mma7455_core_probe(struct device * dev,struct regmap * regmap,const char * name)245 int mma7455_core_probe(struct device *dev, struct regmap *regmap,
246 const char *name)
247 {
248 struct mma7455_data *mma7455;
249 struct iio_dev *indio_dev;
250 unsigned int reg;
251 int ret;
252
253 ret = regmap_read(regmap, MMA7455_REG_WHOAMI, ®);
254 if (ret) {
255 dev_err(dev, "unable to read reg\n");
256 return ret;
257 }
258
259 if (reg != MMA7455_WHOAMI_ID) {
260 dev_err(dev, "device id mismatch\n");
261 return -ENODEV;
262 }
263
264 indio_dev = devm_iio_device_alloc(dev, sizeof(*mma7455));
265 if (!indio_dev)
266 return -ENOMEM;
267
268 dev_set_drvdata(dev, indio_dev);
269 mma7455 = iio_priv(indio_dev);
270 mma7455->regmap = regmap;
271
272 indio_dev->info = &mma7455_info;
273 indio_dev->name = name;
274 indio_dev->modes = INDIO_DIRECT_MODE;
275 indio_dev->channels = mma7455_channels;
276 indio_dev->num_channels = ARRAY_SIZE(mma7455_channels);
277 indio_dev->available_scan_masks = mma7455_scan_masks;
278
279 regmap_write(mma7455->regmap, MMA7455_REG_MCTL,
280 MMA7455_MCTL_MODE_MEASURE);
281
282 ret = iio_triggered_buffer_setup(indio_dev, NULL,
283 mma7455_trigger_handler, NULL);
284 if (ret) {
285 dev_err(dev, "unable to setup triggered buffer\n");
286 return ret;
287 }
288
289 ret = iio_device_register(indio_dev);
290 if (ret) {
291 dev_err(dev, "unable to register device\n");
292 iio_triggered_buffer_cleanup(indio_dev);
293 return ret;
294 }
295
296 return 0;
297 }
298 EXPORT_SYMBOL_NS_GPL(mma7455_core_probe, "IIO_MMA7455");
299
mma7455_core_remove(struct device * dev)300 void mma7455_core_remove(struct device *dev)
301 {
302 struct iio_dev *indio_dev = dev_get_drvdata(dev);
303 struct mma7455_data *mma7455 = iio_priv(indio_dev);
304
305 iio_device_unregister(indio_dev);
306 iio_triggered_buffer_cleanup(indio_dev);
307
308 regmap_write(mma7455->regmap, MMA7455_REG_MCTL,
309 MMA7455_MCTL_MODE_STANDBY);
310 }
311 EXPORT_SYMBOL_NS_GPL(mma7455_core_remove, "IIO_MMA7455");
312
313 MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
314 MODULE_DESCRIPTION("Freescale MMA7455L core accelerometer driver");
315 MODULE_LICENSE("GPL v2");
316