1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_XBAR_MID_0_REGS_H_ 14 #define ASIC_REG_XBAR_MID_0_REGS_H_ 15 16 /* 17 ***************************************** 18 * XBAR_MID_0 19 * (Prototype: XBAR) 20 ***************************************** 21 */ 22 23 #define mmXBAR_MID_0_LBW_HIF0_BASE_ADDR 0x4D40000 24 25 #define mmXBAR_MID_0_LBW_HIF0_ADDR_MASK 0x4D40004 26 27 #define mmXBAR_MID_0_LBW_HIF1_BASE_ADDR 0x4D40008 28 29 #define mmXBAR_MID_0_LBW_HIF1_ADDR_MASK 0x4D4000C 30 31 #define mmXBAR_MID_0_LBW_HMMU0_BASE_ADDR 0x4D40010 32 33 #define mmXBAR_MID_0_LBW_HMMU0_ADDR_MASK 0x4D40014 34 35 #define mmXBAR_MID_0_LBW_HMMU1_BASE_ADDR 0x4D40018 36 37 #define mmXBAR_MID_0_LBW_HMMU1_ADDR_MASK 0x4D4001C 38 39 #define mmXBAR_MID_0_LBW_EDMA_BASE_ADDR0 0x4D40020 40 41 #define mmXBAR_MID_0_LBW_EDMA_ADDR_MASK0 0x4D40024 42 43 #define mmXBAR_MID_0_LBW_EDMA_BASE_ADDR1 0x4D40028 44 45 #define mmXBAR_MID_0_LBW_EDMA_ADDR_MASK1 0x4D4002C 46 47 #define mmXBAR_MID_0_LBW_HBM_BASE_ADDR0 0x4D40030 48 49 #define mmXBAR_MID_0_LBW_HBM_ADDR_MASK0 0x4D40034 50 51 #define mmXBAR_MID_0_LBW_HBM_BASE_ADDR1 0x4D40038 52 53 #define mmXBAR_MID_0_LBW_HBM_ADDR_MASK1 0x4D4003C 54 55 #define mmXBAR_MID_0_LBW_XBAR_BASE_ADDR0 0x4D40040 56 57 #define mmXBAR_MID_0_LBW_XBAR_ADDR_MASK0 0x4D40044 58 59 #define mmXBAR_MID_0_LBW_XBAR_BASE_ADDR1 0x4D40048 60 61 #define mmXBAR_MID_0_LBW_XBAR_ADDR_MASK1 0x4D4004C 62 63 #define mmXBAR_MID_0_DBG_HIF0_BASE_ADDR 0x4D40080 64 65 #define mmXBAR_MID_0_DBG_HIF0_ADDR_MASK 0x4D40084 66 67 #define mmXBAR_MID_0_DBG_HIF1_BASE_ADDR 0x4D40088 68 69 #define mmXBAR_MID_0_DBG_HIF1_ADDR_MASK 0x4D4008C 70 71 #define mmXBAR_MID_0_DBG_HMMU0_BASE_ADDR 0x4D40090 72 73 #define mmXBAR_MID_0_DBG_HMMU0_ADDR_MASK 0x4D40094 74 75 #define mmXBAR_MID_0_DBG_HMMU1_BASE_ADDR 0x4D40098 76 77 #define mmXBAR_MID_0_DBG_HMMU1_ADDR_MASK 0x4D4009C 78 79 #define mmXBAR_MID_0_DBG_EDMA_BASE_ADDR0 0x4D400A0 80 81 #define mmXBAR_MID_0_DBG_EDMA_ADDR_MASK0 0x4D400A4 82 83 #define mmXBAR_MID_0_DBG_EDMA_BASE_ADDR1 0x4D400A8 84 85 #define mmXBAR_MID_0_DBG_EDMA_ADDR_MASK1 0x4D400AC 86 87 #define mmXBAR_MID_0_DBG_HBM_BASE_ADDR0 0x4D400B0 88 89 #define mmXBAR_MID_0_DBG_HBM_ADDR_MASK0 0x4D400B4 90 91 #define mmXBAR_MID_0_DBG_HBM_BASE_ADDR1 0x4D400B8 92 93 #define mmXBAR_MID_0_DBG_HBM_ADDR_MASK1 0x4D400BC 94 95 #define mmXBAR_MID_0_DBG_XBAR_BASE_ADDR0 0x4D400C0 96 97 #define mmXBAR_MID_0_DBG_XBAR_ADDR_MASK0 0x4D400C4 98 99 #define mmXBAR_MID_0_DBG_XBAR_BASE_ADDR1 0x4D400C8 100 101 #define mmXBAR_MID_0_DBG_XBAR_ADDR_MASK1 0x4D400CC 102 103 #define mmXBAR_MID_0_LBW_INTERNAL_ADDR_RGF 0x4D400D0 104 105 #define mmXBAR_MID_0_DBG_INTERNAL_ADDR_FUN 0x4D400D4 106 107 #define mmXBAR_MID_0_EMEM_HBM_BIT_LOCATION 0x4D40100 108 109 #define mmXBAR_MID_0_EMEM_PC_BIT_LOCATION 0x4D40104 110 111 #define mmXBAR_MID_0_HIF_WR_RS_CH_LOCATION 0x4D40108 112 113 #define mmXBAR_MID_0_HBW_MST_ARB_WEIGHT 0x4D4010C 114 115 #define mmXBAR_MID_0_MMU_PC_IDX_MAP_0 0x4D40110 116 117 #define mmXBAR_MID_0_MMU_PC_IDX_MAP_1 0x4D40114 118 119 #define mmXBAR_MID_0_MMU_RD_LL_ARB_0 0x4D40120 120 121 #define mmXBAR_MID_0_MMU_RD_LL_ARB_1 0x4D40124 122 123 #define mmXBAR_MID_0_MMU_WR_LL_ARB_0 0x4D40128 124 125 #define mmXBAR_MID_0_MMU_WR_LL_ARB_1 0x4D4012C 126 127 #define mmXBAR_MID_0_HBM_USER_RESP_OVR_0 0x4D40130 128 129 #define mmXBAR_MID_0_HBM_USER_RESP_OVR_1 0x4D40134 130 131 #define mmXBAR_MID_0_RL_RD_0 0x4D40140 132 133 #define mmXBAR_MID_0_RL_RD_1 0x4D40144 134 135 #define mmXBAR_MID_0_RL_RD_2 0x4D40148 136 137 #define mmXBAR_MID_0_RL_RD_3 0x4D4014C 138 139 #define mmXBAR_MID_0_RL_RD_4 0x4D40150 140 141 #define mmXBAR_MID_0_RL_RD_5 0x4D40154 142 143 #define mmXBAR_MID_0_RL_RD_6 0x4D40158 144 145 #define mmXBAR_MID_0_RL_RD_7 0x4D4015C 146 147 #define mmXBAR_MID_0_RL_RD_8 0x4D40160 148 149 #define mmXBAR_MID_0_RL_RD_9 0x4D40164 150 151 #define mmXBAR_MID_0_RL_RD_10 0x4D40168 152 153 #define mmXBAR_MID_0_RL_RD_11 0x4D4016C 154 155 #define mmXBAR_MID_0_RL_WR_0 0x4D40180 156 157 #define mmXBAR_MID_0_RL_WR_1 0x4D40184 158 159 #define mmXBAR_MID_0_RL_WR_2 0x4D40188 160 161 #define mmXBAR_MID_0_RL_WR_3 0x4D4018C 162 163 #define mmXBAR_MID_0_RL_WR_4 0x4D40190 164 165 #define mmXBAR_MID_0_RL_WR_5 0x4D40194 166 167 #define mmXBAR_MID_0_RL_WR_6 0x4D40198 168 169 #define mmXBAR_MID_0_RL_WR_7 0x4D4019C 170 171 #define mmXBAR_MID_0_RL_WR_8 0x4D401A0 172 173 #define mmXBAR_MID_0_RL_WR_9 0x4D401A4 174 175 #define mmXBAR_MID_0_RL_WR_10 0x4D401A8 176 177 #define mmXBAR_MID_0_RL_WR_11 0x4D401AC 178 179 #define mmXBAR_MID_0_E2E_CRDT_SLV_0 0x4D401B0 180 181 #define mmXBAR_MID_0_E2E_CRDT_SLV_1 0x4D401B4 182 183 #define mmXBAR_MID_0_E2E_CRDT_SLV_2 0x4D401B8 184 185 #define mmXBAR_MID_0_E2E_CRDT_DEBUG 0x4D401BC 186 187 #define mmXBAR_MID_0_UPSCALE 0x4D401C0 188 189 #define mmXBAR_MID_0_DOWN_CONV 0x4D401C4 190 191 #define mmXBAR_MID_0_DOWN_CONV_LFSR_EN 0x4D401D0 192 193 #define mmXBAR_MID_0_DOWN_CONV_LFSR_SET_VLD 0x4D401D4 194 195 #define mmXBAR_MID_0_DOWN_CONV_LFSR_SET_VALUE 0x4D401D8 196 197 #define mmXBAR_MID_0_DOWN_CONV_LFSR_CFG_POLY 0x4D401DC 198 199 #endif /* ASIC_REG_XBAR_MID_0_REGS_H_ */ 200