1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_PDMA0_CORE_REGS_H_ 14 #define ASIC_REG_PDMA0_CORE_REGS_H_ 15 16 /* 17 ***************************************** 18 * PDMA0_CORE 19 * (Prototype: DMA_CORE) 20 ***************************************** 21 */ 22 23 #define mmPDMA0_CORE_CFG_0 0x4C8B000 24 25 #define mmPDMA0_CORE_CFG_1 0x4C8B004 26 27 #define mmPDMA0_CORE_PROT 0x4C8B008 28 29 #define mmPDMA0_CORE_CKG 0x4C8B00C 30 31 #define mmPDMA0_CORE_RD_GLBL 0x4C8B07C 32 33 #define mmPDMA0_CORE_RD_HBW_MAX_OUTSTAND 0x4C8B080 34 35 #define mmPDMA0_CORE_RD_HBW_MAX_SIZE 0x4C8B084 36 37 #define mmPDMA0_CORE_RD_HBW_ARCACHE 0x4C8B088 38 39 #define mmPDMA0_CORE_RD_HBW_INFLIGHTS 0x4C8B090 40 41 #define mmPDMA0_CORE_RD_HBW_RATE_LIM_CFG 0x4C8B094 42 43 #define mmPDMA0_CORE_RD_LBW_MAX_OUTSTAND 0x4C8B0C0 44 45 #define mmPDMA0_CORE_RD_LBW_MAX_SIZE 0x4C8B0C4 46 47 #define mmPDMA0_CORE_RD_LBW_ARCACHE 0x4C8B0C8 48 49 #define mmPDMA0_CORE_RD_LBW_INFLIGHTS 0x4C8B0D0 50 51 #define mmPDMA0_CORE_RD_LBW_RATE_LIM_CFG 0x4C8B0D4 52 53 #define mmPDMA0_CORE_WR_HBW_MAX_OUTSTAND 0x4C8B100 54 55 #define mmPDMA0_CORE_WR_HBW_MAX_AWID 0x4C8B104 56 57 #define mmPDMA0_CORE_WR_HBW_AWCACHE 0x4C8B108 58 59 #define mmPDMA0_CORE_WR_HBW_INFLIGHTS 0x4C8B10C 60 61 #define mmPDMA0_CORE_WR_HBW_RATE_LIM_CFG 0x4C8B110 62 63 #define mmPDMA0_CORE_WR_LBW_MAX_OUTSTAND 0x4C8B140 64 65 #define mmPDMA0_CORE_WR_LBW_MAX_AWID 0x4C8B144 66 67 #define mmPDMA0_CORE_WR_LBW_AWCACHE 0x4C8B148 68 69 #define mmPDMA0_CORE_WR_LBW_INFLIGHTS 0x4C8B14C 70 71 #define mmPDMA0_CORE_WR_LBW_RATE_LIM_CFG 0x4C8B150 72 73 #define mmPDMA0_CORE_WR_COMP_MAX_OUTSTAND 0x4C8B180 74 75 #define mmPDMA0_CORE_WR_COMP_AWUSER 0x4C8B184 76 77 #define mmPDMA0_CORE_ERR_CFG 0x4C8B300 78 79 #define mmPDMA0_CORE_ERR_CAUSE 0x4C8B304 80 81 #define mmPDMA0_CORE_ERRMSG_ADDR_LO 0x4C8B308 82 83 #define mmPDMA0_CORE_ERRMSG_ADDR_HI 0x4C8B30C 84 85 #define mmPDMA0_CORE_ERRMSG_WDATA 0x4C8B310 86 87 #define mmPDMA0_CORE_STS0 0x4C8B380 88 89 #define mmPDMA0_CORE_STS1 0x4C8B384 90 91 #define mmPDMA0_CORE_STS_RD_CTX_SEL 0x4C8B400 92 93 #define mmPDMA0_CORE_STS_RD_CTX_SIZE 0x4C8B404 94 95 #define mmPDMA0_CORE_STS_RD_CTX_BASE_LO 0x4C8B408 96 97 #define mmPDMA0_CORE_STS_RD_CTX_BASE_HI 0x4C8B40C 98 99 #define mmPDMA0_CORE_STS_RD_CTX_ID 0x4C8B410 100 101 #define mmPDMA0_CORE_STS_RD_HB_AXI_ADDR_LO 0x4C8B414 102 103 #define mmPDMA0_CORE_STS_RD_HB_AXI_ADDR_HI 0x4C8B418 104 105 #define mmPDMA0_CORE_STS_RD_LB_AXI_ADDR 0x4C8B41C 106 107 #define mmPDMA0_CORE_STS_WR_CTX_SEL 0x4C8B420 108 109 #define mmPDMA0_CORE_STS_WR_CTX_SIZE 0x4C8B424 110 111 #define mmPDMA0_CORE_STS_WR_CTX_BASE_LO 0x4C8B428 112 113 #define mmPDMA0_CORE_STS_WR_CTX_BASE_HI 0x4C8B42C 114 115 #define mmPDMA0_CORE_STS_WR_CTX_ID 0x4C8B430 116 117 #define mmPDMA0_CORE_STS_WR_HB_AXI_ADDR_LO 0x4C8B434 118 119 #define mmPDMA0_CORE_STS_WR_HB_AXI_ADDR_HI 0x4C8B438 120 121 #define mmPDMA0_CORE_STS_WR_LB_AXI_ADDR 0x4C8B43C 122 123 #define mmPDMA0_CORE_PWRLP_CFG 0x4C8B700 124 125 #define mmPDMA0_CORE_PWRLP_STS 0x4C8B704 126 127 #define mmPDMA0_CORE_DBG_DESC_CNT 0x4C8B710 128 129 #define mmPDMA0_CORE_DBG_STS 0x4C8B714 130 131 #define mmPDMA0_CORE_DBG_BUF_STS 0x4C8B718 132 133 #define mmPDMA0_CORE_DBG_RD_DESC_ID 0x4C8B720 134 135 #define mmPDMA0_CORE_DBG_WR_DESC_ID 0x4C8B724 136 137 #define mmPDMA0_CORE_APB_DMA_LBW_BASE 0x4C8B728 138 139 #define mmPDMA0_CORE_APB_MSTR_IF_LBW_BASE 0x4C8B72C 140 141 #define mmPDMA0_CORE_E2E_CRED_ASYNC_CFG 0x4C8B730 142 143 #define mmPDMA0_CORE_DBG_APB_ENABLER 0x4C8BE1C 144 145 #define mmPDMA0_CORE_L2H_CMPR_LO 0x4C8BE20 146 147 #define mmPDMA0_CORE_L2H_CMPR_HI 0x4C8BE24 148 149 #define mmPDMA0_CORE_L2H_MASK_LO 0x4C8BE28 150 151 #define mmPDMA0_CORE_L2H_MASK_HI 0x4C8BE2C 152 153 #define mmPDMA0_CORE_IDLE_IND_MASK 0x4C8BE30 154 155 #define mmPDMA0_CORE_APB_ENABLER 0x4C8BE34 156 157 #endif /* ASIC_REG_PDMA0_CORE_REGS_H_ */ 158