1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/delay.h>
25 #include <linux/kernel.h>
26 #include <linux/firmware.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include "amdgpu.h"
30 #include "amdgpu_gfx.h"
31 #include "amdgpu_psp.h"
32 #include "nv.h"
33 #include "nvd.h"
34
35 #include "gc/gc_10_1_0_offset.h"
36 #include "gc/gc_10_1_0_sh_mask.h"
37 #include "smuio/smuio_11_0_0_offset.h"
38 #include "smuio/smuio_11_0_0_sh_mask.h"
39 #include "navi10_enum.h"
40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
41
42 #include "soc15.h"
43 #include "soc15_common.h"
44 #include "clearstate_gfx10.h"
45 #include "v10_structs.h"
46 #include "gfx_v10_0.h"
47 #include "gfx_v10_0_cleaner_shader.h"
48 #include "nbio_v2_3.h"
49
50 /*
51 * Navi10 has two graphic rings to share each graphic pipe.
52 * 1. Primary ring
53 * 2. Async ring
54 */
55 #define GFX10_NUM_GFX_RINGS_NV1X 1
56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 2
57 #define GFX10_MEC_HPD_SIZE 2048
58
59 #define F32_CE_PROGRAM_RAM_SIZE 65536
60 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
61
62 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087
63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
68
69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8
70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L
71
72 #define mmCGTS_TCC_DISABLE_gc_10_3 0x5006
73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX 1
74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007
75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX 1
76
77 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55
78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0
79 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0
80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1
81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1
82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1
83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec
84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0
85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1
86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0
87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2
88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0
89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3
90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0
91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4
92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0
93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5
94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0
95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6
96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a
98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L
99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL
100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2
101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL
102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580
103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0
104
105 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish 0x0105
106 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish_BASE_IDX 1
107 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish 0x0106
108 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish_BASE_IDX 1
109
110 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025
111 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1
112 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026
113 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1
114
115 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6 0x002d
116 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX 1
117 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6 0x002e
118 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX 1
119
120 #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441
121 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1
122 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261
123 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
124 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f
125 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1
126 #define mmVGT_TF_RING_SIZE_Vangogh 0x224e
127 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1
128 #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241
129 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1
130 #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250
131 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1
132 #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240
133 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1
134 #define mmSPI_CONFIG_CNTL_Vangogh 0x2440
135 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1
136 #define mmGCR_GENERAL_CNTL_Vangogh 0x1580
137 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0
138 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL
139
140 #define mmCP_HYP_PFP_UCODE_ADDR 0x5814
141 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1
142 #define mmCP_HYP_PFP_UCODE_DATA 0x5815
143 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1
144 #define mmCP_HYP_CE_UCODE_ADDR 0x5818
145 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1
146 #define mmCP_HYP_CE_UCODE_DATA 0x5819
147 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1
148 #define mmCP_HYP_ME_UCODE_ADDR 0x5816
149 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1
150 #define mmCP_HYP_ME_UCODE_DATA 0x5817
151 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1
152
153 #define mmCPG_PSP_DEBUG 0x5c10
154 #define mmCPG_PSP_DEBUG_BASE_IDX 1
155 #define mmCPC_PSP_DEBUG 0x5c11
156 #define mmCPC_PSP_DEBUG_BASE_IDX 1
157 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L
158 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L
159
160 //CC_GC_SA_UNIT_DISABLE
161 #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9
162 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0
163 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8
164 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L
165 //GC_USER_SA_UNIT_DISABLE
166 #define mmGC_USER_SA_UNIT_DISABLE 0x0fea
167 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0
168 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8
169 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L
170 //PA_SC_ENHANCE_3
171 #define mmPA_SC_ENHANCE_3 0x1085
172 #define mmPA_SC_ENHANCE_3_BASE_IDX 0
173 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
174 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L
175
176 #define mmCGTT_SPI_CS_CLK_CTRL 0x507c
177 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1
178
179 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3
180 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
181 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db
182 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
183
184 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030
185 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0
186
187 #define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5
188 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1
189
190 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
191 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
192 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
193 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
194 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
195 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
196
197 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
198 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
199 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
200 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
201 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
202 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
203 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
204 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
205 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
206 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
207 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
208
209 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
210 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
211 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
212 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
213 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
214 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
215
216 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
217 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
218 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
219 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
220 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
221 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
222
223 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
224 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
225 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
226 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
227 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
228 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
229
230 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
231 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
232 MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
233 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
234 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
235 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
236
237 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
238 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
239 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
240 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
241 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
242 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
243
244 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin");
245 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin");
246 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin");
247 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin");
248 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin");
249 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin");
250
251 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin");
252 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin");
253 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin");
254 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin");
255 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin");
256 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin");
257
258 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin");
259 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin");
260 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin");
261 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin");
262 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin");
263 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin");
264
265 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin");
266 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin");
267 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin");
268 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin");
269 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin");
270 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin");
271
272 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin");
273 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin");
274 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin");
275 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
276 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
277 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
278
279 static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = {
280 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),
281 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2),
282 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3),
283 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1),
284 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2),
285 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1),
286 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1),
287 SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT),
288 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT),
289 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT),
290 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2),
291 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2),
292 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS),
293 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR),
294 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0),
295 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE),
296 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR),
297 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR),
298 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE),
299 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR),
300 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR),
301 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE),
302 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR),
303 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR),
304 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE),
305 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
306 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
307 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ),
308 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ),
309 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ),
310 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ),
311 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO),
312 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI),
313 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ),
314 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO),
315 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI),
316 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ),
317 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO),
318 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI),
319 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ),
320 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO),
321 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI),
322 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ),
323 SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS),
324 SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS),
325 SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS),
326 SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT),
327 SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT),
328 SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS),
329 SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS_2),
330 SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS),
331 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS),
332 SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS),
333 SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL0_STATUS),
334 SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL0_STATUS),
335 SOC15_REG_ENTRY_STR(GC, 0, mmSQG_UTCL0_STATUS),
336 SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL0_STATUS),
337 SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS),
338 SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL),
339 SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS),
340 SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG),
341 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL),
342 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_CNTL),
343 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR),
344 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR),
345 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR),
346 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR),
347 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_INSTR_PNTR),
348 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR),
349 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR),
350 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS),
351 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT),
352 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND),
353 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE),
354 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1),
355 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2),
356 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_3),
357 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_4),
358 SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE),
359 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE),
360 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),
361 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_GPM_STAT_2),
362 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SPP_STATUS),
363 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS),
364 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),
365 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),
366 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_A),
367 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_B),
368 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR),
369 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST),
370 /* cp header registers */
371 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
372 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
373 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME2_HEADER_DUMP),
374 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
375 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
376 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_HEADER_DUMP),
377 /* SE status registers */
378 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0),
379 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1),
380 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2),
381 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3)
382 };
383
384 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_10[] = {
385 /* compute registers */
386 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_VMID),
387 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PERSISTENT_STATE),
388 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PIPE_PRIORITY),
389 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUEUE_PRIORITY),
390 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUANTUM),
391 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE),
392 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE_HI),
393 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_RPTR),
394 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
395 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
396 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL),
397 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_CONTROL),
398 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR),
399 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR_HI),
400 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_RPTR),
401 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_CONTROL),
402 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_REQUEST),
403 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR),
404 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI),
405 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_CONTROL),
406 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_RPTR),
407 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR),
408 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_EVENTS),
409 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_LO),
410 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_HI),
411 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_CONTROL),
412 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_OFFSET),
413 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_SIZE),
414 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_WG_STATE_OFFSET),
415 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_SIZE),
416 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GDS_RESOURCE_STATE),
417 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ERROR),
418 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR_MEM),
419 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO),
420 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),
421 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
422 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
423 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_WG_STATE_OFFSET),
424 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_STATUS)
425 };
426
427 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_10[] = {
428 /* gfx queue registers */
429 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_ACTIVE),
430 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY),
431 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE),
432 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE_HI),
433 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_OFFSET),
434 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CSMD_RPTR),
435 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR),
436 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR_HI),
437 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_DEQUEUE_REQUEST),
438 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_MAPPED),
439 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUE_MGR_CONTROL),
440 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_CONTROL0),
441 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_STATUS0),
442 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO),
443 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI),
444 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_OFFSET),
445 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_CSMD_RPTR),
446 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR),
447 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_HI),
448 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR),
449 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR_HI),
450 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO),
451 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI)
452 };
453
454 static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
495 };
496
497 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = {
498 /* Pending on emulation bring up */
499 };
500
501 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = {
502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1554 };
1555
1556 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = {
1557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1595 };
1596
1597 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = {
1598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)
1640 };
1641
1642 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = {
1643 /* Pending on emulation bring up */
1644 };
1645
1646 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = {
1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
2186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
2190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2267 };
2268
2269 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = {
2270 /* Pending on emulation bring up */
2271 };
2272
2273 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = {
2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
3141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
3145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
3157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3326 };
3327
3328 static const struct soc15_reg_golden golden_settings_gc_10_3[] = {
3329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020),
3348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3372 };
3373
3374 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = {
3375 /* Pending on emulation bring up */
3376 };
3377
3378 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = {
3379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
3389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
3390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
3420
3421 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020),
3423 };
3424
3425 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = {
3426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3450
3451 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
3452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020),
3453 };
3454
3455 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = {
3456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242),
3462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3476 };
3477
3478 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = {
3479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
3481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
3482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
3486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
3490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
3491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
3494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
3513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
3514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020)
3515 };
3516
3517 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = {
3518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100),
3520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100),
3521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3550 };
3551
3552 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = {
3553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000),
3554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e),
3555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
3556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100),
3557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000),
3558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014),
3559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8),
3561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003),
3562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
3563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
3564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
3566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210),
3567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
3568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500),
3569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff),
3570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8),
3572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130),
3573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130),
3574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
3577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f),
3578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188),
3579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009),
3580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02),
3581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000),
3582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101),
3583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
3584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
3585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000),
3586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)
3587 };
3588
3589 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = {
3590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044),
3592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042),
3596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044),
3598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3612 };
3613
3614 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = {
3615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041),
3621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007),
3631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3637 };
3638
3639 #define DEFAULT_SH_MEM_CONFIG \
3640 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3641 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3642 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3643 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3644
3645 /* TODO: pending on golden setting value of gb address config */
3646 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044
3647
3648 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3649 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3650 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3651 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3652 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev);
3653 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3654 struct amdgpu_cu_info *cu_info);
3655 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3656 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3657 u32 sh_num, u32 instance, int xcc_id);
3658 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3659
3660 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3661 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3662 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3663 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3664 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3665 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3666 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3667 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3668 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3669 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3670 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
3671 uint16_t pasid, uint32_t flush_type,
3672 bool all_hub, uint8_t dst_sel);
3673 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
3674 unsigned int vmid);
3675
3676 static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
3677 enum amd_powergating_state state);
gfx10_kiq_set_resources(struct amdgpu_ring * kiq_ring,uint64_t queue_mask)3678 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3679 {
3680 struct amdgpu_device *adev = kiq_ring->adev;
3681 u64 shader_mc_addr;
3682
3683 /* Cleaner shader MC address */
3684 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8;
3685
3686 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3687 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3688 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3689 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3690 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3691 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */
3692 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */
3693 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3694 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3695 }
3696
gfx10_kiq_map_queues(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring)3697 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3698 struct amdgpu_ring *ring)
3699 {
3700 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3701 uint64_t wptr_addr = ring->wptr_gpu_addr;
3702 uint32_t eng_sel = 0;
3703
3704 switch (ring->funcs->type) {
3705 case AMDGPU_RING_TYPE_COMPUTE:
3706 eng_sel = 0;
3707 break;
3708 case AMDGPU_RING_TYPE_GFX:
3709 eng_sel = 4;
3710 break;
3711 case AMDGPU_RING_TYPE_MES:
3712 eng_sel = 5;
3713 break;
3714 default:
3715 WARN_ON(1);
3716 }
3717
3718 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3719 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3720 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3721 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3722 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3723 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3724 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3725 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3726 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3727 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3728 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3729 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3730 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3731 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3732 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3733 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3734 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3735 }
3736
gfx10_kiq_unmap_queues(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring,enum amdgpu_unmap_queues_action action,u64 gpu_addr,u64 seq)3737 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3738 struct amdgpu_ring *ring,
3739 enum amdgpu_unmap_queues_action action,
3740 u64 gpu_addr, u64 seq)
3741 {
3742 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3743
3744 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3745 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3746 PACKET3_UNMAP_QUEUES_ACTION(action) |
3747 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3748 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3749 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3750 amdgpu_ring_write(kiq_ring,
3751 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3752
3753 if (action == PREEMPT_QUEUES_NO_UNMAP) {
3754 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3755 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3756 amdgpu_ring_write(kiq_ring, seq);
3757 } else {
3758 amdgpu_ring_write(kiq_ring, 0);
3759 amdgpu_ring_write(kiq_ring, 0);
3760 amdgpu_ring_write(kiq_ring, 0);
3761 }
3762 }
3763
gfx10_kiq_query_status(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring,u64 addr,u64 seq)3764 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3765 struct amdgpu_ring *ring,
3766 u64 addr,
3767 u64 seq)
3768 {
3769 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3770
3771 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3772 amdgpu_ring_write(kiq_ring,
3773 PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3774 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3775 PACKET3_QUERY_STATUS_COMMAND(2));
3776 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3777 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3778 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3779 amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3780 amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3781 amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3782 amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3783 }
3784
gfx10_kiq_invalidate_tlbs(struct amdgpu_ring * kiq_ring,uint16_t pasid,uint32_t flush_type,bool all_hub)3785 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3786 uint16_t pasid, uint32_t flush_type,
3787 bool all_hub)
3788 {
3789 gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);
3790 }
3791
gfx_v10_0_kiq_reset_hw_queue(struct amdgpu_ring * kiq_ring,uint32_t queue_type,uint32_t me_id,uint32_t pipe_id,uint32_t queue_id,uint32_t xcc_id,uint32_t vmid)3792 static void gfx_v10_0_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t queue_type,
3793 uint32_t me_id, uint32_t pipe_id, uint32_t queue_id,
3794 uint32_t xcc_id, uint32_t vmid)
3795 {
3796 struct amdgpu_device *adev = kiq_ring->adev;
3797 unsigned i;
3798 uint32_t tmp;
3799
3800 /* enter save mode */
3801 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id);
3802 mutex_lock(&adev->srbm_mutex);
3803 nv_grbm_select(adev, me_id, pipe_id, queue_id, 0);
3804
3805 if (queue_type == AMDGPU_RING_TYPE_COMPUTE) {
3806 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 0x2);
3807 WREG32_SOC15(GC, 0, mmSPI_COMPUTE_QUEUE_RESET, 0x1);
3808 /* wait till dequeue take effects */
3809 for (i = 0; i < adev->usec_timeout; i++) {
3810 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
3811 break;
3812 udelay(1);
3813 }
3814 if (i >= adev->usec_timeout)
3815 dev_err(adev->dev, "fail to wait on hqd deactive\n");
3816 } else if (queue_type == AMDGPU_RING_TYPE_GFX) {
3817 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
3818 (uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
3819 tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);
3820 if (pipe_id == 0)
3821 tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id);
3822 else
3823 tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id);
3824 WREG32_SOC15(GC, 0, mmCP_VMID_RESET, tmp);
3825
3826 /* wait till dequeue take effects */
3827 for (i = 0; i < adev->usec_timeout; i++) {
3828 if (!(RREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE) & 1))
3829 break;
3830 udelay(1);
3831 }
3832 if (i >= adev->usec_timeout)
3833 dev_err(adev->dev, "failed to wait on gfx hqd deactivate\n");
3834 } else {
3835 dev_err(adev->dev, "reset queue_type(%d) not supported\n", queue_type);
3836 }
3837
3838 nv_grbm_select(adev, 0, 0, 0, 0);
3839 mutex_unlock(&adev->srbm_mutex);
3840 /* exit safe mode */
3841 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
3842 }
3843
3844 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3845 .kiq_set_resources = gfx10_kiq_set_resources,
3846 .kiq_map_queues = gfx10_kiq_map_queues,
3847 .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3848 .kiq_query_status = gfx10_kiq_query_status,
3849 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3850 .kiq_reset_hw_queue = gfx_v10_0_kiq_reset_hw_queue,
3851 .set_resources_size = 8,
3852 .map_queues_size = 7,
3853 .unmap_queues_size = 6,
3854 .query_status_size = 7,
3855 .invalidate_tlbs_size = 2,
3856 };
3857
gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device * adev)3858 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3859 {
3860 adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs;
3861 }
3862
gfx_v10_0_init_spm_golden_registers(struct amdgpu_device * adev)3863 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3864 {
3865 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3866 case IP_VERSION(10, 1, 10):
3867 soc15_program_register_sequence(adev,
3868 golden_settings_gc_rlc_spm_10_0_nv10,
3869 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3870 break;
3871 case IP_VERSION(10, 1, 1):
3872 soc15_program_register_sequence(adev,
3873 golden_settings_gc_rlc_spm_10_1_nv14,
3874 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3875 break;
3876 case IP_VERSION(10, 1, 2):
3877 soc15_program_register_sequence(adev,
3878 golden_settings_gc_rlc_spm_10_1_2_nv12,
3879 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3880 break;
3881 default:
3882 break;
3883 }
3884 }
3885
gfx_v10_0_init_golden_registers(struct amdgpu_device * adev)3886 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3887 {
3888 if (amdgpu_sriov_vf(adev))
3889 return;
3890
3891 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3892 case IP_VERSION(10, 1, 10):
3893 soc15_program_register_sequence(adev,
3894 golden_settings_gc_10_1,
3895 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3896 soc15_program_register_sequence(adev,
3897 golden_settings_gc_10_0_nv10,
3898 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3899 break;
3900 case IP_VERSION(10, 1, 1):
3901 soc15_program_register_sequence(adev,
3902 golden_settings_gc_10_1_1,
3903 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3904 soc15_program_register_sequence(adev,
3905 golden_settings_gc_10_1_nv14,
3906 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3907 break;
3908 case IP_VERSION(10, 1, 2):
3909 soc15_program_register_sequence(adev,
3910 golden_settings_gc_10_1_2,
3911 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3912 soc15_program_register_sequence(adev,
3913 golden_settings_gc_10_1_2_nv12,
3914 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3915 break;
3916 case IP_VERSION(10, 3, 0):
3917 soc15_program_register_sequence(adev,
3918 golden_settings_gc_10_3,
3919 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3920 soc15_program_register_sequence(adev,
3921 golden_settings_gc_10_3_sienna_cichlid,
3922 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3923 break;
3924 case IP_VERSION(10, 3, 2):
3925 soc15_program_register_sequence(adev,
3926 golden_settings_gc_10_3_2,
3927 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3928 break;
3929 case IP_VERSION(10, 3, 1):
3930 soc15_program_register_sequence(adev,
3931 golden_settings_gc_10_3_vangogh,
3932 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3933 break;
3934 case IP_VERSION(10, 3, 3):
3935 soc15_program_register_sequence(adev,
3936 golden_settings_gc_10_3_3,
3937 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3));
3938 break;
3939 case IP_VERSION(10, 3, 4):
3940 soc15_program_register_sequence(adev,
3941 golden_settings_gc_10_3_4,
3942 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
3943 break;
3944 case IP_VERSION(10, 3, 5):
3945 soc15_program_register_sequence(adev,
3946 golden_settings_gc_10_3_5,
3947 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));
3948 break;
3949 case IP_VERSION(10, 1, 3):
3950 case IP_VERSION(10, 1, 4):
3951 soc15_program_register_sequence(adev,
3952 golden_settings_gc_10_0_cyan_skillfish,
3953 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish));
3954 break;
3955 case IP_VERSION(10, 3, 6):
3956 soc15_program_register_sequence(adev,
3957 golden_settings_gc_10_3_6,
3958 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6));
3959 break;
3960 case IP_VERSION(10, 3, 7):
3961 soc15_program_register_sequence(adev,
3962 golden_settings_gc_10_3_7,
3963 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7));
3964 break;
3965 default:
3966 break;
3967 }
3968 gfx_v10_0_init_spm_golden_registers(adev);
3969 }
3970
gfx_v10_0_write_data_to_reg(struct amdgpu_ring * ring,int eng_sel,bool wc,uint32_t reg,uint32_t val)3971 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3972 bool wc, uint32_t reg, uint32_t val)
3973 {
3974 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3975 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3976 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3977 amdgpu_ring_write(ring, reg);
3978 amdgpu_ring_write(ring, 0);
3979 amdgpu_ring_write(ring, val);
3980 }
3981
gfx_v10_0_wait_reg_mem(struct amdgpu_ring * ring,int eng_sel,int mem_space,int opt,uint32_t addr0,uint32_t addr1,uint32_t ref,uint32_t mask,uint32_t inv)3982 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3983 int mem_space, int opt, uint32_t addr0,
3984 uint32_t addr1, uint32_t ref, uint32_t mask,
3985 uint32_t inv)
3986 {
3987 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3988 amdgpu_ring_write(ring,
3989 /* memory (1) or register (0) */
3990 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3991 WAIT_REG_MEM_OPERATION(opt) | /* wait */
3992 WAIT_REG_MEM_FUNCTION(3) | /* equal */
3993 WAIT_REG_MEM_ENGINE(eng_sel)));
3994
3995 if (mem_space)
3996 BUG_ON(addr0 & 0x3); /* Dword align */
3997 amdgpu_ring_write(ring, addr0);
3998 amdgpu_ring_write(ring, addr1);
3999 amdgpu_ring_write(ring, ref);
4000 amdgpu_ring_write(ring, mask);
4001 amdgpu_ring_write(ring, inv); /* poll interval */
4002 }
4003
gfx_v10_0_ring_test_ring(struct amdgpu_ring * ring)4004 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
4005 {
4006 struct amdgpu_device *adev = ring->adev;
4007 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
4008 uint32_t tmp = 0;
4009 unsigned int i;
4010 int r;
4011
4012 WREG32(scratch, 0xCAFEDEAD);
4013 r = amdgpu_ring_alloc(ring, 3);
4014 if (r) {
4015 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
4016 ring->idx, r);
4017 return r;
4018 }
4019
4020 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
4021 amdgpu_ring_write(ring, scratch -
4022 PACKET3_SET_UCONFIG_REG_START);
4023 amdgpu_ring_write(ring, 0xDEADBEEF);
4024 amdgpu_ring_commit(ring);
4025
4026 for (i = 0; i < adev->usec_timeout; i++) {
4027 tmp = RREG32(scratch);
4028 if (tmp == 0xDEADBEEF)
4029 break;
4030 if (amdgpu_emu_mode == 1)
4031 msleep(1);
4032 else
4033 udelay(1);
4034 }
4035
4036 if (i >= adev->usec_timeout)
4037 r = -ETIMEDOUT;
4038
4039 return r;
4040 }
4041
gfx_v10_0_ring_test_ib(struct amdgpu_ring * ring,long timeout)4042 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
4043 {
4044 struct amdgpu_device *adev = ring->adev;
4045 struct amdgpu_ib ib;
4046 struct dma_fence *f = NULL;
4047 unsigned int index;
4048 uint64_t gpu_addr;
4049 volatile uint32_t *cpu_ptr;
4050 long r;
4051
4052 memset(&ib, 0, sizeof(ib));
4053
4054 r = amdgpu_device_wb_get(adev, &index);
4055 if (r)
4056 return r;
4057
4058 gpu_addr = adev->wb.gpu_addr + (index * 4);
4059 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
4060 cpu_ptr = &adev->wb.wb[index];
4061
4062 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
4063 if (r) {
4064 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
4065 goto err1;
4066 }
4067
4068 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
4069 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
4070 ib.ptr[2] = lower_32_bits(gpu_addr);
4071 ib.ptr[3] = upper_32_bits(gpu_addr);
4072 ib.ptr[4] = 0xDEADBEEF;
4073 ib.length_dw = 5;
4074
4075 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
4076 if (r)
4077 goto err2;
4078
4079 r = dma_fence_wait_timeout(f, false, timeout);
4080 if (r == 0) {
4081 r = -ETIMEDOUT;
4082 goto err2;
4083 } else if (r < 0) {
4084 goto err2;
4085 }
4086
4087 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)
4088 r = 0;
4089 else
4090 r = -EINVAL;
4091 err2:
4092 amdgpu_ib_free(&ib, NULL);
4093 dma_fence_put(f);
4094 err1:
4095 amdgpu_device_wb_free(adev, index);
4096 return r;
4097 }
4098
gfx_v10_0_free_microcode(struct amdgpu_device * adev)4099 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
4100 {
4101 amdgpu_ucode_release(&adev->gfx.pfp_fw);
4102 amdgpu_ucode_release(&adev->gfx.me_fw);
4103 amdgpu_ucode_release(&adev->gfx.ce_fw);
4104 amdgpu_ucode_release(&adev->gfx.rlc_fw);
4105 amdgpu_ucode_release(&adev->gfx.mec_fw);
4106 amdgpu_ucode_release(&adev->gfx.mec2_fw);
4107
4108 kfree(adev->gfx.rlc.register_list_format);
4109 }
4110
gfx_v10_0_check_fw_write_wait(struct amdgpu_device * adev)4111 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
4112 {
4113 adev->gfx.cp_fw_write_wait = false;
4114
4115 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4116 case IP_VERSION(10, 1, 10):
4117 case IP_VERSION(10, 1, 2):
4118 case IP_VERSION(10, 1, 1):
4119 case IP_VERSION(10, 1, 3):
4120 case IP_VERSION(10, 1, 4):
4121 if ((adev->gfx.me_fw_version >= 0x00000046) &&
4122 (adev->gfx.me_feature_version >= 27) &&
4123 (adev->gfx.pfp_fw_version >= 0x00000068) &&
4124 (adev->gfx.pfp_feature_version >= 27) &&
4125 (adev->gfx.mec_fw_version >= 0x0000005b) &&
4126 (adev->gfx.mec_feature_version >= 27))
4127 adev->gfx.cp_fw_write_wait = true;
4128 break;
4129 case IP_VERSION(10, 3, 0):
4130 case IP_VERSION(10, 3, 2):
4131 case IP_VERSION(10, 3, 1):
4132 case IP_VERSION(10, 3, 4):
4133 case IP_VERSION(10, 3, 5):
4134 case IP_VERSION(10, 3, 6):
4135 case IP_VERSION(10, 3, 3):
4136 case IP_VERSION(10, 3, 7):
4137 adev->gfx.cp_fw_write_wait = true;
4138 break;
4139 default:
4140 break;
4141 }
4142
4143 if (!adev->gfx.cp_fw_write_wait)
4144 DRM_WARN_ONCE("CP firmware version too old, please update!");
4145 }
4146
gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device * adev)4147 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
4148 {
4149 bool ret = false;
4150
4151 switch (adev->pdev->revision) {
4152 case 0xc2:
4153 case 0xc3:
4154 ret = true;
4155 break;
4156 default:
4157 ret = false;
4158 break;
4159 }
4160
4161 return ret;
4162 }
4163
gfx_v10_0_check_gfxoff_flag(struct amdgpu_device * adev)4164 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
4165 {
4166 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4167 case IP_VERSION(10, 1, 10):
4168 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
4169 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
4170 break;
4171 default:
4172 break;
4173 }
4174 }
4175
gfx_v10_0_init_microcode(struct amdgpu_device * adev)4176 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
4177 {
4178 char fw_name[53];
4179 char ucode_prefix[30];
4180 const char *wks = "";
4181 int err;
4182 const struct rlc_firmware_header_v2_0 *rlc_hdr;
4183 uint16_t version_major;
4184 uint16_t version_minor;
4185
4186 DRM_DEBUG("\n");
4187
4188 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) &&
4189 (!(adev->pdev->device == 0x7340 && adev->pdev->revision != 0x00)))
4190 wks = "_wks";
4191 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
4192
4193 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,
4194 AMDGPU_UCODE_REQUIRED,
4195 "amdgpu/%s_pfp%s.bin", ucode_prefix, wks);
4196 if (err)
4197 goto out;
4198 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP);
4199
4200 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,
4201 AMDGPU_UCODE_REQUIRED,
4202 "amdgpu/%s_me%s.bin", ucode_prefix, wks);
4203 if (err)
4204 goto out;
4205 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME);
4206
4207 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw,
4208 AMDGPU_UCODE_REQUIRED,
4209 "amdgpu/%s_ce%s.bin", ucode_prefix, wks);
4210 if (err)
4211 goto out;
4212 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE);
4213
4214 if (!amdgpu_sriov_vf(adev)) {
4215 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix);
4216 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
4217 if (err)
4218 goto out;
4219
4220 /* don't validate this firmware. There are apparently firmwares
4221 * in the wild with incorrect size in the header
4222 */
4223 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4224 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
4225 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
4226 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
4227 if (err)
4228 goto out;
4229 }
4230
4231 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,
4232 AMDGPU_UCODE_REQUIRED,
4233 "amdgpu/%s_mec%s.bin", ucode_prefix, wks);
4234 if (err)
4235 goto out;
4236 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
4237 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
4238
4239 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw,
4240 AMDGPU_UCODE_REQUIRED,
4241 "amdgpu/%s_mec2%s.bin", ucode_prefix, wks);
4242 if (!err) {
4243 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2);
4244 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT);
4245 } else {
4246 err = 0;
4247 adev->gfx.mec2_fw = NULL;
4248 }
4249
4250 gfx_v10_0_check_fw_write_wait(adev);
4251 out:
4252 if (err) {
4253 amdgpu_ucode_release(&adev->gfx.pfp_fw);
4254 amdgpu_ucode_release(&adev->gfx.me_fw);
4255 amdgpu_ucode_release(&adev->gfx.ce_fw);
4256 amdgpu_ucode_release(&adev->gfx.rlc_fw);
4257 amdgpu_ucode_release(&adev->gfx.mec_fw);
4258 amdgpu_ucode_release(&adev->gfx.mec2_fw);
4259 }
4260
4261 gfx_v10_0_check_gfxoff_flag(adev);
4262
4263 return err;
4264 }
4265
gfx_v10_0_get_csb_size(struct amdgpu_device * adev)4266 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4267 {
4268 u32 count = 0;
4269 const struct cs_section_def *sect = NULL;
4270 const struct cs_extent_def *ext = NULL;
4271
4272 /* begin clear state */
4273 count += 2;
4274 /* context control state */
4275 count += 3;
4276
4277 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4278 for (ext = sect->section; ext->extent != NULL; ++ext) {
4279 if (sect->id == SECT_CONTEXT)
4280 count += 2 + ext->reg_count;
4281 else
4282 return 0;
4283 }
4284 }
4285
4286 /* set PA_SC_TILE_STEERING_OVERRIDE */
4287 count += 3;
4288 /* end clear state */
4289 count += 2;
4290 /* clear state */
4291 count += 2;
4292
4293 return count;
4294 }
4295
gfx_v10_0_get_csb_buffer(struct amdgpu_device * adev,volatile u32 * buffer)4296 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4297 volatile u32 *buffer)
4298 {
4299 u32 count = 0, i;
4300 const struct cs_section_def *sect = NULL;
4301 const struct cs_extent_def *ext = NULL;
4302 int ctx_reg_offset;
4303
4304 if (adev->gfx.rlc.cs_data == NULL)
4305 return;
4306 if (buffer == NULL)
4307 return;
4308
4309 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4310 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4311
4312 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4313 buffer[count++] = cpu_to_le32(0x80000000);
4314 buffer[count++] = cpu_to_le32(0x80000000);
4315
4316 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4317 for (ext = sect->section; ext->extent != NULL; ++ext) {
4318 if (sect->id == SECT_CONTEXT) {
4319 buffer[count++] =
4320 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4321 buffer[count++] = cpu_to_le32(ext->reg_index -
4322 PACKET3_SET_CONTEXT_REG_START);
4323 for (i = 0; i < ext->reg_count; i++)
4324 buffer[count++] = cpu_to_le32(ext->extent[i]);
4325 } else {
4326 return;
4327 }
4328 }
4329 }
4330
4331 ctx_reg_offset =
4332 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4333 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4334 buffer[count++] = cpu_to_le32(ctx_reg_offset);
4335 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4336
4337 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4338 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4339
4340 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4341 buffer[count++] = cpu_to_le32(0);
4342 }
4343
gfx_v10_0_rlc_fini(struct amdgpu_device * adev)4344 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4345 {
4346 /* clear state block */
4347 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4348 &adev->gfx.rlc.clear_state_gpu_addr,
4349 (void **)&adev->gfx.rlc.cs_ptr);
4350
4351 /* jump table block */
4352 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4353 &adev->gfx.rlc.cp_table_gpu_addr,
4354 (void **)&adev->gfx.rlc.cp_table_ptr);
4355 }
4356
gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device * adev)4357 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
4358 {
4359 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
4360
4361 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0];
4362 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
4363 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1);
4364 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2);
4365 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3);
4366 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL);
4367 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX);
4368 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4369 case IP_VERSION(10, 3, 0):
4370 reg_access_ctrl->spare_int =
4371 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid);
4372 break;
4373 default:
4374 reg_access_ctrl->spare_int =
4375 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT);
4376 break;
4377 }
4378 adev->gfx.rlc.rlcg_reg_access_supported = true;
4379 }
4380
gfx_v10_0_rlc_init(struct amdgpu_device * adev)4381 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4382 {
4383 const struct cs_section_def *cs_data;
4384 int r;
4385
4386 adev->gfx.rlc.cs_data = gfx10_cs_data;
4387
4388 cs_data = adev->gfx.rlc.cs_data;
4389
4390 if (cs_data) {
4391 /* init clear state block */
4392 r = amdgpu_gfx_rlc_init_csb(adev);
4393 if (r)
4394 return r;
4395 }
4396
4397 return 0;
4398 }
4399
gfx_v10_0_mec_fini(struct amdgpu_device * adev)4400 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4401 {
4402 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4403 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4404 }
4405
gfx_v10_0_me_init(struct amdgpu_device * adev)4406 static void gfx_v10_0_me_init(struct amdgpu_device *adev)
4407 {
4408 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4409
4410 amdgpu_gfx_graphics_queue_acquire(adev);
4411 }
4412
gfx_v10_0_mec_init(struct amdgpu_device * adev)4413 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4414 {
4415 int r;
4416 u32 *hpd;
4417 const __le32 *fw_data = NULL;
4418 unsigned int fw_size;
4419 u32 *fw = NULL;
4420 size_t mec_hpd_size;
4421
4422 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4423
4424 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4425
4426 /* take ownership of the relevant compute queues */
4427 amdgpu_gfx_compute_queue_acquire(adev);
4428 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4429
4430 if (mec_hpd_size) {
4431 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4432 AMDGPU_GEM_DOMAIN_GTT,
4433 &adev->gfx.mec.hpd_eop_obj,
4434 &adev->gfx.mec.hpd_eop_gpu_addr,
4435 (void **)&hpd);
4436 if (r) {
4437 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4438 gfx_v10_0_mec_fini(adev);
4439 return r;
4440 }
4441
4442 memset(hpd, 0, mec_hpd_size);
4443
4444 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4445 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4446 }
4447
4448 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4449 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4450
4451 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4452 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4453 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4454
4455 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4456 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4457 &adev->gfx.mec.mec_fw_obj,
4458 &adev->gfx.mec.mec_fw_gpu_addr,
4459 (void **)&fw);
4460 if (r) {
4461 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4462 gfx_v10_0_mec_fini(adev);
4463 return r;
4464 }
4465
4466 memcpy(fw, fw_data, fw_size);
4467
4468 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4469 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4470 }
4471
4472 return 0;
4473 }
4474
wave_read_ind(struct amdgpu_device * adev,uint32_t wave,uint32_t address)4475 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4476 {
4477 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4478 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4479 (address << SQ_IND_INDEX__INDEX__SHIFT));
4480 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4481 }
4482
wave_read_regs(struct amdgpu_device * adev,uint32_t wave,uint32_t thread,uint32_t regno,uint32_t num,uint32_t * out)4483 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4484 uint32_t thread, uint32_t regno,
4485 uint32_t num, uint32_t *out)
4486 {
4487 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4488 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4489 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4490 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4491 (SQ_IND_INDEX__AUTO_INCR_MASK));
4492 while (num--)
4493 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4494 }
4495
gfx_v10_0_read_wave_data(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t * dst,int * no_fields)4496 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4497 {
4498 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4499 * field when performing a select_se_sh so it should be
4500 * zero here
4501 */
4502 WARN_ON(simd != 0);
4503
4504 /* type 2 wave data */
4505 dst[(*no_fields)++] = 2;
4506 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4507 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4508 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4509 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4510 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4511 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4512 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4513 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4514 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4515 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4516 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4517 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4518 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4519 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4520 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4521 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
4522 }
4523
gfx_v10_0_read_wave_sgprs(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t start,uint32_t size,uint32_t * dst)4524 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
4525 uint32_t wave, uint32_t start,
4526 uint32_t size, uint32_t *dst)
4527 {
4528 WARN_ON(simd != 0);
4529
4530 wave_read_regs(
4531 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4532 dst);
4533 }
4534
gfx_v10_0_read_wave_vgprs(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t thread,uint32_t start,uint32_t size,uint32_t * dst)4535 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
4536 uint32_t wave, uint32_t thread,
4537 uint32_t start, uint32_t size,
4538 uint32_t *dst)
4539 {
4540 wave_read_regs(
4541 adev, wave, thread,
4542 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4543 }
4544
gfx_v10_0_select_me_pipe_q(struct amdgpu_device * adev,u32 me,u32 pipe,u32 q,u32 vm,u32 xcc_id)4545 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4546 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
4547 {
4548 nv_grbm_select(adev, me, pipe, q, vm);
4549 }
4550
gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device * adev,bool enable)4551 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4552 bool enable)
4553 {
4554 uint32_t data, def;
4555
4556 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
4557
4558 if (enable)
4559 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4560 else
4561 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4562
4563 if (data != def)
4564 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
4565 }
4566
4567 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4568 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4569 .select_se_sh = &gfx_v10_0_select_se_sh,
4570 .read_wave_data = &gfx_v10_0_read_wave_data,
4571 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4572 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4573 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4574 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4575 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4576 };
4577
gfx_v10_0_gpu_early_init(struct amdgpu_device * adev)4578 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4579 {
4580 u32 gb_addr_config;
4581
4582 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4583 case IP_VERSION(10, 1, 10):
4584 case IP_VERSION(10, 1, 1):
4585 case IP_VERSION(10, 1, 2):
4586 adev->gfx.config.max_hw_contexts = 8;
4587 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4588 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4589 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4590 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4591 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4592 break;
4593 case IP_VERSION(10, 3, 0):
4594 case IP_VERSION(10, 3, 2):
4595 case IP_VERSION(10, 3, 1):
4596 case IP_VERSION(10, 3, 4):
4597 case IP_VERSION(10, 3, 5):
4598 case IP_VERSION(10, 3, 6):
4599 case IP_VERSION(10, 3, 3):
4600 case IP_VERSION(10, 3, 7):
4601 adev->gfx.config.max_hw_contexts = 8;
4602 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4603 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4604 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4605 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4606 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4607 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4608 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4609 break;
4610 case IP_VERSION(10, 1, 3):
4611 case IP_VERSION(10, 1, 4):
4612 adev->gfx.config.max_hw_contexts = 8;
4613 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4614 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4615 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4616 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4617 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN;
4618 break;
4619 default:
4620 BUG();
4621 break;
4622 }
4623
4624 adev->gfx.config.gb_addr_config = gb_addr_config;
4625
4626 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4627 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4628 GB_ADDR_CONFIG, NUM_PIPES);
4629
4630 adev->gfx.config.max_tile_pipes =
4631 adev->gfx.config.gb_addr_config_fields.num_pipes;
4632
4633 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4634 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4635 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4636 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4637 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4638 GB_ADDR_CONFIG, NUM_RB_PER_SE);
4639 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4640 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4641 GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4642 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4643 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4644 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4645 }
4646
gfx_v10_0_gfx_ring_init(struct amdgpu_device * adev,int ring_id,int me,int pipe,int queue)4647 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4648 int me, int pipe, int queue)
4649 {
4650 struct amdgpu_ring *ring;
4651 unsigned int irq_type;
4652 unsigned int hw_prio;
4653
4654 ring = &adev->gfx.gfx_ring[ring_id];
4655
4656 ring->me = me;
4657 ring->pipe = pipe;
4658 ring->queue = queue;
4659
4660 ring->ring_obj = NULL;
4661 ring->use_doorbell = true;
4662
4663 if (!ring_id)
4664 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4665 else
4666 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4667 ring->vm_hub = AMDGPU_GFXHUB(0);
4668 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4669
4670 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4671 hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ?
4672 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4673 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4674 hw_prio, NULL);
4675 }
4676
gfx_v10_0_compute_ring_init(struct amdgpu_device * adev,int ring_id,int mec,int pipe,int queue)4677 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4678 int mec, int pipe, int queue)
4679 {
4680 unsigned int irq_type;
4681 struct amdgpu_ring *ring;
4682 unsigned int hw_prio;
4683
4684 ring = &adev->gfx.compute_ring[ring_id];
4685
4686 /* mec0 is me1 */
4687 ring->me = mec + 1;
4688 ring->pipe = pipe;
4689 ring->queue = queue;
4690
4691 ring->ring_obj = NULL;
4692 ring->use_doorbell = true;
4693 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4694 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4695 + (ring_id * GFX10_MEC_HPD_SIZE);
4696 ring->vm_hub = AMDGPU_GFXHUB(0);
4697 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4698
4699 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4700 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4701 + ring->pipe;
4702 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
4703 AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;
4704 /* type-2 packets are deprecated on MEC, use type-3 instead */
4705 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4706 hw_prio, NULL);
4707 }
4708
gfx_v10_0_alloc_ip_dump(struct amdgpu_device * adev)4709 static void gfx_v10_0_alloc_ip_dump(struct amdgpu_device *adev)
4710 {
4711 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
4712 uint32_t *ptr;
4713 uint32_t inst;
4714
4715 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
4716 if (!ptr) {
4717 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n");
4718 adev->gfx.ip_dump_core = NULL;
4719 } else {
4720 adev->gfx.ip_dump_core = ptr;
4721 }
4722
4723 /* Allocate memory for compute queue registers for all the instances */
4724 reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
4725 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *
4726 adev->gfx.mec.num_queue_per_pipe;
4727
4728 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
4729 if (!ptr) {
4730 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n");
4731 adev->gfx.ip_dump_compute_queues = NULL;
4732 } else {
4733 adev->gfx.ip_dump_compute_queues = ptr;
4734 }
4735
4736 /* Allocate memory for gfx queue registers for all the instances */
4737 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
4738 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me *
4739 adev->gfx.me.num_queue_per_pipe;
4740
4741 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
4742 if (!ptr) {
4743 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n");
4744 adev->gfx.ip_dump_gfx_queues = NULL;
4745 } else {
4746 adev->gfx.ip_dump_gfx_queues = ptr;
4747 }
4748 }
4749
gfx_v10_0_sw_init(struct amdgpu_ip_block * ip_block)4750 static int gfx_v10_0_sw_init(struct amdgpu_ip_block *ip_block)
4751 {
4752 int i, j, k, r, ring_id = 0;
4753 int xcc_id = 0;
4754 struct amdgpu_device *adev = ip_block->adev;
4755
4756 INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler);
4757
4758 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4759 case IP_VERSION(10, 1, 10):
4760 case IP_VERSION(10, 1, 1):
4761 case IP_VERSION(10, 1, 2):
4762 case IP_VERSION(10, 1, 3):
4763 case IP_VERSION(10, 1, 4):
4764 adev->gfx.me.num_me = 1;
4765 adev->gfx.me.num_pipe_per_me = 1;
4766 adev->gfx.me.num_queue_per_pipe = 1;
4767 adev->gfx.mec.num_mec = 2;
4768 adev->gfx.mec.num_pipe_per_mec = 4;
4769 adev->gfx.mec.num_queue_per_pipe = 8;
4770 break;
4771 case IP_VERSION(10, 3, 0):
4772 case IP_VERSION(10, 3, 2):
4773 case IP_VERSION(10, 3, 1):
4774 case IP_VERSION(10, 3, 4):
4775 case IP_VERSION(10, 3, 5):
4776 case IP_VERSION(10, 3, 6):
4777 case IP_VERSION(10, 3, 3):
4778 case IP_VERSION(10, 3, 7):
4779 adev->gfx.me.num_me = 1;
4780 adev->gfx.me.num_pipe_per_me = 2;
4781 adev->gfx.me.num_queue_per_pipe = 1;
4782 adev->gfx.mec.num_mec = 2;
4783 adev->gfx.mec.num_pipe_per_mec = 4;
4784 adev->gfx.mec.num_queue_per_pipe = 4;
4785 break;
4786 default:
4787 adev->gfx.me.num_me = 1;
4788 adev->gfx.me.num_pipe_per_me = 1;
4789 adev->gfx.me.num_queue_per_pipe = 1;
4790 adev->gfx.mec.num_mec = 1;
4791 adev->gfx.mec.num_pipe_per_mec = 4;
4792 adev->gfx.mec.num_queue_per_pipe = 8;
4793 break;
4794 }
4795 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4796 case IP_VERSION(10, 1, 10):
4797 case IP_VERSION(10, 1, 1):
4798 case IP_VERSION(10, 1, 2):
4799 adev->gfx.cleaner_shader_ptr = gfx_10_1_10_cleaner_shader_hex;
4800 adev->gfx.cleaner_shader_size = sizeof(gfx_10_1_10_cleaner_shader_hex);
4801 if (adev->gfx.me_fw_version >= 101 &&
4802 adev->gfx.pfp_fw_version >= 158 &&
4803 adev->gfx.mec_fw_version >= 152) {
4804 adev->gfx.enable_cleaner_shader = true;
4805 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size);
4806 if (r) {
4807 adev->gfx.enable_cleaner_shader = false;
4808 dev_err(adev->dev, "Failed to initialize cleaner shader\n");
4809 }
4810 }
4811 break;
4812 case IP_VERSION(10, 3, 0):
4813 case IP_VERSION(10, 3, 2):
4814 case IP_VERSION(10, 3, 4):
4815 case IP_VERSION(10, 3, 5):
4816 adev->gfx.cleaner_shader_ptr = gfx_10_3_0_cleaner_shader_hex;
4817 adev->gfx.cleaner_shader_size = sizeof(gfx_10_3_0_cleaner_shader_hex);
4818 if (adev->gfx.me_fw_version >= 64 &&
4819 adev->gfx.pfp_fw_version >= 100 &&
4820 adev->gfx.mec_fw_version >= 122) {
4821 adev->gfx.enable_cleaner_shader = true;
4822 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size);
4823 if (r) {
4824 adev->gfx.enable_cleaner_shader = false;
4825 dev_err(adev->dev, "Failed to initialize cleaner shader\n");
4826 }
4827 }
4828 break;
4829 default:
4830 adev->gfx.enable_cleaner_shader = false;
4831 break;
4832 }
4833
4834 /* KIQ event */
4835 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4836 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4837 &adev->gfx.kiq[0].irq);
4838 if (r)
4839 return r;
4840
4841 /* EOP Event */
4842 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4843 GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4844 &adev->gfx.eop_irq);
4845 if (r)
4846 return r;
4847
4848 /* Bad opcode Event */
4849 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4850 GFX_10_1__SRCID__CP_BAD_OPCODE_ERROR,
4851 &adev->gfx.bad_op_irq);
4852 if (r)
4853 return r;
4854
4855 /* Privileged reg */
4856 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4857 &adev->gfx.priv_reg_irq);
4858 if (r)
4859 return r;
4860
4861 /* Privileged inst */
4862 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4863 &adev->gfx.priv_inst_irq);
4864 if (r)
4865 return r;
4866
4867 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4868
4869 gfx_v10_0_me_init(adev);
4870
4871 if (adev->gfx.rlc.funcs) {
4872 if (adev->gfx.rlc.funcs->init) {
4873 r = adev->gfx.rlc.funcs->init(adev);
4874 if (r) {
4875 dev_err(adev->dev, "Failed to init rlc BOs!\n");
4876 return r;
4877 }
4878 }
4879 }
4880
4881 r = gfx_v10_0_mec_init(adev);
4882 if (r) {
4883 DRM_ERROR("Failed to init MEC BOs!\n");
4884 return r;
4885 }
4886
4887 /* set up the gfx ring */
4888 for (i = 0; i < adev->gfx.me.num_me; i++) {
4889 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4890 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4891 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4892 continue;
4893
4894 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4895 i, k, j);
4896 if (r)
4897 return r;
4898 ring_id++;
4899 }
4900 }
4901 }
4902
4903 ring_id = 0;
4904 /* set up the compute queues - allocate horizontally across pipes */
4905 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4906 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4907 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4908 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,
4909 k, j))
4910 continue;
4911
4912 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4913 i, k, j);
4914 if (r)
4915 return r;
4916
4917 ring_id++;
4918 }
4919 }
4920 }
4921 /* TODO: Add queue reset mask when FW fully supports it */
4922 adev->gfx.gfx_supported_reset =
4923 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]);
4924 adev->gfx.compute_supported_reset =
4925 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]);
4926
4927 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0);
4928 if (r) {
4929 DRM_ERROR("Failed to init KIQ BOs!\n");
4930 return r;
4931 }
4932
4933 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id);
4934 if (r)
4935 return r;
4936
4937 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd), 0);
4938 if (r)
4939 return r;
4940
4941 /* allocate visible FB for rlc auto-loading fw */
4942 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4943 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4944 if (r)
4945 return r;
4946 }
4947
4948 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4949
4950 gfx_v10_0_gpu_early_init(adev);
4951
4952 gfx_v10_0_alloc_ip_dump(adev);
4953
4954 r = amdgpu_gfx_sysfs_init(adev);
4955 if (r)
4956 return r;
4957
4958 return 0;
4959 }
4960
gfx_v10_0_pfp_fini(struct amdgpu_device * adev)4961 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4962 {
4963 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4964 &adev->gfx.pfp.pfp_fw_gpu_addr,
4965 (void **)&adev->gfx.pfp.pfp_fw_ptr);
4966 }
4967
gfx_v10_0_ce_fini(struct amdgpu_device * adev)4968 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4969 {
4970 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4971 &adev->gfx.ce.ce_fw_gpu_addr,
4972 (void **)&adev->gfx.ce.ce_fw_ptr);
4973 }
4974
gfx_v10_0_me_fini(struct amdgpu_device * adev)4975 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4976 {
4977 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4978 &adev->gfx.me.me_fw_gpu_addr,
4979 (void **)&adev->gfx.me.me_fw_ptr);
4980 }
4981
gfx_v10_0_sw_fini(struct amdgpu_ip_block * ip_block)4982 static int gfx_v10_0_sw_fini(struct amdgpu_ip_block *ip_block)
4983 {
4984 int i;
4985 struct amdgpu_device *adev = ip_block->adev;
4986
4987 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4988 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4989 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4990 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4991
4992 amdgpu_gfx_mqd_sw_fini(adev, 0);
4993
4994 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);
4995 amdgpu_gfx_kiq_fini(adev, 0);
4996
4997 amdgpu_gfx_cleaner_shader_sw_fini(adev);
4998
4999 gfx_v10_0_pfp_fini(adev);
5000 gfx_v10_0_ce_fini(adev);
5001 gfx_v10_0_me_fini(adev);
5002 gfx_v10_0_rlc_fini(adev);
5003 gfx_v10_0_mec_fini(adev);
5004
5005 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
5006 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
5007
5008 gfx_v10_0_free_microcode(adev);
5009 amdgpu_gfx_sysfs_fini(adev);
5010
5011 kfree(adev->gfx.ip_dump_core);
5012 kfree(adev->gfx.ip_dump_compute_queues);
5013 kfree(adev->gfx.ip_dump_gfx_queues);
5014
5015 return 0;
5016 }
5017
gfx_v10_0_select_se_sh(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 instance,int xcc_id)5018 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
5019 u32 sh_num, u32 instance, int xcc_id)
5020 {
5021 u32 data;
5022
5023 if (instance == 0xffffffff)
5024 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
5025 INSTANCE_BROADCAST_WRITES, 1);
5026 else
5027 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
5028 instance);
5029
5030 if (se_num == 0xffffffff)
5031 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
5032 1);
5033 else
5034 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
5035
5036 if (sh_num == 0xffffffff)
5037 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
5038 1);
5039 else
5040 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
5041
5042 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
5043 }
5044
gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device * adev)5045 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
5046 {
5047 u32 data, mask;
5048
5049 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
5050 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
5051
5052 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
5053 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
5054
5055 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
5056 adev->gfx.config.max_sh_per_se);
5057
5058 return (~data) & mask;
5059 }
5060
gfx_v10_0_setup_rb(struct amdgpu_device * adev)5061 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
5062 {
5063 int i, j;
5064 u32 data;
5065 u32 active_rbs = 0;
5066 u32 bitmap;
5067 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
5068 adev->gfx.config.max_sh_per_se;
5069
5070 mutex_lock(&adev->grbm_idx_mutex);
5071 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5072 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5073 bitmap = i * adev->gfx.config.max_sh_per_se + j;
5074 if (((amdgpu_ip_version(adev, GC_HWIP, 0) ==
5075 IP_VERSION(10, 3, 0)) ||
5076 (amdgpu_ip_version(adev, GC_HWIP, 0) ==
5077 IP_VERSION(10, 3, 3)) ||
5078 (amdgpu_ip_version(adev, GC_HWIP, 0) ==
5079 IP_VERSION(10, 3, 6))) &&
5080 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
5081 continue;
5082 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
5083 data = gfx_v10_0_get_rb_active_bitmap(adev);
5084 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
5085 rb_bitmap_width_per_sh);
5086 }
5087 }
5088 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
5089 mutex_unlock(&adev->grbm_idx_mutex);
5090
5091 adev->gfx.config.backend_enable_mask = active_rbs;
5092 adev->gfx.config.num_rbs = hweight32(active_rbs);
5093 }
5094
gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device * adev)5095 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
5096 {
5097 uint32_t num_sc;
5098 uint32_t enabled_rb_per_sh;
5099 uint32_t active_rb_bitmap;
5100 uint32_t num_rb_per_sc;
5101 uint32_t num_packer_per_sc;
5102 uint32_t pa_sc_tile_steering_override;
5103
5104 /* for ASICs that integrates GFX v10.3
5105 * pa_sc_tile_steering_override should be set to 0
5106 */
5107 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0))
5108 return 0;
5109
5110 /* init num_sc */
5111 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
5112 adev->gfx.config.num_sc_per_sh;
5113 /* init num_rb_per_sc */
5114 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
5115 enabled_rb_per_sh = hweight32(active_rb_bitmap);
5116 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
5117 /* init num_packer_per_sc */
5118 num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
5119
5120 pa_sc_tile_steering_override = 0;
5121 pa_sc_tile_steering_override |=
5122 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
5123 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
5124 pa_sc_tile_steering_override |=
5125 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
5126 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
5127 pa_sc_tile_steering_override |=
5128 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
5129 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
5130
5131 return pa_sc_tile_steering_override;
5132 }
5133
5134 #define DEFAULT_SH_MEM_BASES (0x6000)
5135
gfx_v10_0_debug_trap_config_init(struct amdgpu_device * adev,uint32_t first_vmid,uint32_t last_vmid)5136 static void gfx_v10_0_debug_trap_config_init(struct amdgpu_device *adev,
5137 uint32_t first_vmid,
5138 uint32_t last_vmid)
5139 {
5140 uint32_t data;
5141 uint32_t trap_config_vmid_mask = 0;
5142 int i;
5143
5144 /* Calculate trap config vmid mask */
5145 for (i = first_vmid; i < last_vmid; i++)
5146 trap_config_vmid_mask |= (1 << i);
5147
5148 data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG,
5149 VMID_SEL, trap_config_vmid_mask);
5150 data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,
5151 TRAP_EN, 1);
5152 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data);
5153 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
5154
5155 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0);
5156 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0);
5157 }
5158
gfx_v10_0_init_compute_vmid(struct amdgpu_device * adev)5159 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
5160 {
5161 int i;
5162 uint32_t sh_mem_bases;
5163
5164 /*
5165 * Configure apertures:
5166 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
5167 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
5168 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
5169 */
5170 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
5171
5172 mutex_lock(&adev->srbm_mutex);
5173 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5174 nv_grbm_select(adev, 0, 0, 0, i);
5175 /* CP and shaders */
5176 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5177 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
5178 }
5179 nv_grbm_select(adev, 0, 0, 0, 0);
5180 mutex_unlock(&adev->srbm_mutex);
5181
5182 /*
5183 * Initialize all compute VMIDs to have no GDS, GWS, or OA
5184 * access. These should be enabled by FW for target VMIDs.
5185 */
5186 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5187 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
5188 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
5189 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
5190 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
5191 }
5192
5193 gfx_v10_0_debug_trap_config_init(adev, adev->vm_manager.first_kfd_vmid,
5194 AMDGPU_NUM_VMID);
5195 }
5196
gfx_v10_0_init_gds_vmid(struct amdgpu_device * adev)5197 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
5198 {
5199 int vmid;
5200
5201 /*
5202 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
5203 * access. Compute VMIDs should be enabled by FW for target VMIDs,
5204 * the driver can enable them for graphics. VMID0 should maintain
5205 * access so that HWS firmware can save/restore entries.
5206 */
5207 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
5208 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
5209 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
5210 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
5211 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
5212 }
5213 }
5214
5215
gfx_v10_0_tcp_harvest(struct amdgpu_device * adev)5216 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
5217 {
5218 int i, j, k;
5219 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
5220 u32 tmp, wgp_active_bitmap = 0;
5221 u32 gcrd_targets_disable_tcp = 0;
5222 u32 utcl_invreq_disable = 0;
5223 /*
5224 * GCRD_TARGETS_DISABLE field contains
5225 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
5226 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
5227 */
5228 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
5229 2 * max_wgp_per_sh + /* TCP */
5230 max_wgp_per_sh + /* SQC */
5231 4); /* GL1C */
5232 /*
5233 * UTCL1_UTCL0_INVREQ_DISABLE field contains
5234 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
5235 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
5236 */
5237 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
5238 2 * max_wgp_per_sh + /* TCP */
5239 2 * max_wgp_per_sh + /* SQC */
5240 4 + /* RMI */
5241 1); /* SQG */
5242
5243 mutex_lock(&adev->grbm_idx_mutex);
5244 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5245 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5246 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
5247 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
5248 /*
5249 * Set corresponding TCP bits for the inactive WGPs in
5250 * GCRD_SA_TARGETS_DISABLE
5251 */
5252 gcrd_targets_disable_tcp = 0;
5253 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
5254 utcl_invreq_disable = 0;
5255
5256 for (k = 0; k < max_wgp_per_sh; k++) {
5257 if (!(wgp_active_bitmap & (1 << k))) {
5258 gcrd_targets_disable_tcp |= 3 << (2 * k);
5259 gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2));
5260 utcl_invreq_disable |= (3 << (2 * k)) |
5261 (3 << (2 * (max_wgp_per_sh + k)));
5262 }
5263 }
5264
5265 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
5266 /* only override TCP & SQC bits */
5267 tmp &= (0xffffffffU << (4 * max_wgp_per_sh));
5268 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
5269 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
5270
5271 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
5272 /* only override TCP & SQC bits */
5273 tmp &= (0xffffffffU << (3 * max_wgp_per_sh));
5274 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
5275 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
5276 }
5277 }
5278
5279 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
5280 mutex_unlock(&adev->grbm_idx_mutex);
5281 }
5282
gfx_v10_0_get_tcc_info(struct amdgpu_device * adev)5283 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
5284 {
5285 /* TCCs are global (not instanced). */
5286 uint32_t tcc_disable;
5287
5288 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) {
5289 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
5290 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
5291 } else {
5292 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
5293 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
5294 }
5295
5296 adev->gfx.config.tcc_disabled_mask =
5297 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
5298 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
5299 }
5300
gfx_v10_0_constants_init(struct amdgpu_device * adev)5301 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
5302 {
5303 u32 tmp;
5304 int i;
5305
5306 if (!amdgpu_sriov_vf(adev))
5307 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
5308
5309 gfx_v10_0_setup_rb(adev);
5310 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
5311 gfx_v10_0_get_tcc_info(adev);
5312 adev->gfx.config.pa_sc_tile_steering_override =
5313 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
5314
5315 /* XXX SH_MEM regs */
5316 /* where to put LDS, scratch, GPUVM in FSA64 space */
5317 mutex_lock(&adev->srbm_mutex);
5318 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
5319 nv_grbm_select(adev, 0, 0, 0, i);
5320 /* CP and shaders */
5321 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5322 if (i != 0) {
5323 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
5324 (adev->gmc.private_aperture_start >> 48));
5325 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
5326 (adev->gmc.shared_aperture_start >> 48));
5327 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
5328 }
5329 }
5330 nv_grbm_select(adev, 0, 0, 0, 0);
5331
5332 mutex_unlock(&adev->srbm_mutex);
5333
5334 gfx_v10_0_init_compute_vmid(adev);
5335 gfx_v10_0_init_gds_vmid(adev);
5336
5337 }
5338
gfx_v10_0_get_cpg_int_cntl(struct amdgpu_device * adev,int me,int pipe)5339 static u32 gfx_v10_0_get_cpg_int_cntl(struct amdgpu_device *adev,
5340 int me, int pipe)
5341 {
5342 if (me != 0)
5343 return 0;
5344
5345 switch (pipe) {
5346 case 0:
5347 return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
5348 case 1:
5349 return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
5350 default:
5351 return 0;
5352 }
5353 }
5354
gfx_v10_0_get_cpc_int_cntl(struct amdgpu_device * adev,int me,int pipe)5355 static u32 gfx_v10_0_get_cpc_int_cntl(struct amdgpu_device *adev,
5356 int me, int pipe)
5357 {
5358 /*
5359 * amdgpu controls only the first MEC. That's why this function only
5360 * handles the setting of interrupts for this specific MEC. All other
5361 * pipes' interrupts are set by amdkfd.
5362 */
5363 if (me != 1)
5364 return 0;
5365
5366 switch (pipe) {
5367 case 0:
5368 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
5369 case 1:
5370 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
5371 case 2:
5372 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
5373 case 3:
5374 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
5375 default:
5376 return 0;
5377 }
5378 }
5379
gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device * adev,bool enable)5380 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
5381 bool enable)
5382 {
5383 u32 tmp, cp_int_cntl_reg;
5384 int i, j;
5385
5386 if (amdgpu_sriov_vf(adev))
5387 return;
5388
5389 for (i = 0; i < adev->gfx.me.num_me; i++) {
5390 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
5391 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);
5392
5393 if (cp_int_cntl_reg) {
5394 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
5395 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
5396 enable ? 1 : 0);
5397 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
5398 enable ? 1 : 0);
5399 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
5400 enable ? 1 : 0);
5401 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
5402 enable ? 1 : 0);
5403 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp);
5404 }
5405 }
5406 }
5407 }
5408
gfx_v10_0_init_csb(struct amdgpu_device * adev)5409 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5410 {
5411 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5412
5413 /* csib */
5414 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) {
5415 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
5416 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5417 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
5418 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5419 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5420 } else {
5421 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5422 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5423 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5424 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5425 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5426 }
5427 return 0;
5428 }
5429
gfx_v10_0_rlc_stop(struct amdgpu_device * adev)5430 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5431 {
5432 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5433
5434 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5435 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5436 }
5437
gfx_v10_0_rlc_reset(struct amdgpu_device * adev)5438 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5439 {
5440 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5441 udelay(50);
5442 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5443 udelay(50);
5444 }
5445
gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device * adev,bool enable)5446 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5447 bool enable)
5448 {
5449 uint32_t rlc_pg_cntl;
5450
5451 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5452
5453 if (!enable) {
5454 /* RLC_PG_CNTL[23] = 0 (default)
5455 * RLC will wait for handshake acks with SMU
5456 * GFXOFF will be enabled
5457 * RLC_PG_CNTL[23] = 1
5458 * RLC will not issue any message to SMU
5459 * hence no handshake between SMU & RLC
5460 * GFXOFF will be disabled
5461 */
5462 rlc_pg_cntl |= 0x800000;
5463 } else
5464 rlc_pg_cntl &= ~0x800000;
5465 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5466 }
5467
gfx_v10_0_rlc_start(struct amdgpu_device * adev)5468 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5469 {
5470 /*
5471 * TODO: enable rlc & smu handshake until smu
5472 * and gfxoff feature works as expected
5473 */
5474 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5475 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5476
5477 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5478 udelay(50);
5479 }
5480
gfx_v10_0_rlc_enable_srm(struct amdgpu_device * adev)5481 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5482 {
5483 uint32_t tmp;
5484
5485 /* enable Save Restore Machine */
5486 tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);
5487 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5488 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5489 WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp);
5490 }
5491
gfx_v10_0_rlc_load_microcode(struct amdgpu_device * adev)5492 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5493 {
5494 const struct rlc_firmware_header_v2_0 *hdr;
5495 const __le32 *fw_data;
5496 unsigned int i, fw_size;
5497
5498 if (!adev->gfx.rlc_fw)
5499 return -EINVAL;
5500
5501 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5502 amdgpu_ucode_print_rlc_hdr(&hdr->header);
5503
5504 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5505 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5506 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5507
5508 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5509 RLCG_UCODE_LOADING_START_ADDRESS);
5510
5511 for (i = 0; i < fw_size; i++)
5512 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5513 le32_to_cpup(fw_data++));
5514
5515 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5516
5517 return 0;
5518 }
5519
gfx_v10_0_rlc_resume(struct amdgpu_device * adev)5520 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5521 {
5522 int r;
5523
5524 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
5525 adev->psp.autoload_supported) {
5526
5527 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5528 if (r)
5529 return r;
5530
5531 gfx_v10_0_init_csb(adev);
5532
5533 gfx_v10_0_update_spm_vmid_internal(adev, 0xf);
5534
5535 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5536 gfx_v10_0_rlc_enable_srm(adev);
5537 } else {
5538 if (amdgpu_sriov_vf(adev)) {
5539 gfx_v10_0_init_csb(adev);
5540 return 0;
5541 }
5542
5543 adev->gfx.rlc.funcs->stop(adev);
5544
5545 /* disable CG */
5546 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5547
5548 /* disable PG */
5549 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5550
5551 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5552 /* legacy rlc firmware loading */
5553 r = gfx_v10_0_rlc_load_microcode(adev);
5554 if (r)
5555 return r;
5556 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5557 /* rlc backdoor autoload firmware */
5558 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5559 if (r)
5560 return r;
5561 }
5562
5563 gfx_v10_0_init_csb(adev);
5564
5565 gfx_v10_0_update_spm_vmid_internal(adev, 0xf);
5566
5567 adev->gfx.rlc.funcs->start(adev);
5568
5569 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5570 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5571 if (r)
5572 return r;
5573 }
5574 }
5575
5576 return 0;
5577 }
5578
5579 static struct {
5580 FIRMWARE_ID id;
5581 unsigned int offset;
5582 unsigned int size;
5583 } rlc_autoload_info[FIRMWARE_ID_MAX];
5584
gfx_v10_0_parse_rlc_toc(struct amdgpu_device * adev)5585 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5586 {
5587 int ret;
5588 RLC_TABLE_OF_CONTENT *rlc_toc;
5589
5590 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE,
5591 AMDGPU_GEM_DOMAIN_GTT,
5592 &adev->gfx.rlc.rlc_toc_bo,
5593 &adev->gfx.rlc.rlc_toc_gpu_addr,
5594 (void **)&adev->gfx.rlc.rlc_toc_buf);
5595 if (ret) {
5596 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5597 return ret;
5598 }
5599
5600 /* Copy toc from psp sos fw to rlc toc buffer */
5601 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes);
5602
5603 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5604 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5605 (rlc_toc->id < FIRMWARE_ID_MAX)) {
5606 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5607 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5608 /* Offset needs 4KB alignment */
5609 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5610 }
5611
5612 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5613 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5614 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5615
5616 rlc_toc++;
5617 }
5618
5619 return 0;
5620 }
5621
gfx_v10_0_calc_toc_total_size(struct amdgpu_device * adev)5622 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5623 {
5624 uint32_t total_size = 0;
5625 FIRMWARE_ID id;
5626 int ret;
5627
5628 ret = gfx_v10_0_parse_rlc_toc(adev);
5629 if (ret) {
5630 dev_err(adev->dev, "failed to parse rlc toc\n");
5631 return 0;
5632 }
5633
5634 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5635 total_size += rlc_autoload_info[id].size;
5636
5637 /* In case the offset in rlc toc ucode is aligned */
5638 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5639 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5640 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5641
5642 return total_size;
5643 }
5644
gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device * adev)5645 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5646 {
5647 int r;
5648 uint32_t total_size;
5649
5650 total_size = gfx_v10_0_calc_toc_total_size(adev);
5651
5652 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5653 AMDGPU_GEM_DOMAIN_GTT,
5654 &adev->gfx.rlc.rlc_autoload_bo,
5655 &adev->gfx.rlc.rlc_autoload_gpu_addr,
5656 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5657 if (r) {
5658 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5659 return r;
5660 }
5661
5662 return 0;
5663 }
5664
gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device * adev)5665 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5666 {
5667 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5668 &adev->gfx.rlc.rlc_toc_gpu_addr,
5669 (void **)&adev->gfx.rlc.rlc_toc_buf);
5670 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5671 &adev->gfx.rlc.rlc_autoload_gpu_addr,
5672 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5673 }
5674
gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device * adev,FIRMWARE_ID id,const void * fw_data,uint32_t fw_size)5675 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5676 FIRMWARE_ID id,
5677 const void *fw_data,
5678 uint32_t fw_size)
5679 {
5680 uint32_t toc_offset;
5681 uint32_t toc_fw_size;
5682 char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5683
5684 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5685 return;
5686
5687 toc_offset = rlc_autoload_info[id].offset;
5688 toc_fw_size = rlc_autoload_info[id].size;
5689
5690 if (fw_size == 0)
5691 fw_size = toc_fw_size;
5692
5693 if (fw_size > toc_fw_size)
5694 fw_size = toc_fw_size;
5695
5696 memcpy(ptr + toc_offset, fw_data, fw_size);
5697
5698 if (fw_size < toc_fw_size)
5699 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5700 }
5701
gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device * adev)5702 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5703 {
5704 void *data;
5705 uint32_t size;
5706
5707 data = adev->gfx.rlc.rlc_toc_buf;
5708 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5709
5710 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5711 FIRMWARE_ID_RLC_TOC,
5712 data, size);
5713 }
5714
gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device * adev)5715 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5716 {
5717 const __le32 *fw_data;
5718 uint32_t fw_size;
5719 const struct gfx_firmware_header_v1_0 *cp_hdr;
5720 const struct rlc_firmware_header_v2_0 *rlc_hdr;
5721
5722 /* pfp ucode */
5723 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5724 adev->gfx.pfp_fw->data;
5725 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5726 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5727 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5728 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5729 FIRMWARE_ID_CP_PFP,
5730 fw_data, fw_size);
5731
5732 /* ce ucode */
5733 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5734 adev->gfx.ce_fw->data;
5735 fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5736 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5737 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5738 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5739 FIRMWARE_ID_CP_CE,
5740 fw_data, fw_size);
5741
5742 /* me ucode */
5743 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5744 adev->gfx.me_fw->data;
5745 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5746 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5747 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5748 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5749 FIRMWARE_ID_CP_ME,
5750 fw_data, fw_size);
5751
5752 /* rlc ucode */
5753 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5754 adev->gfx.rlc_fw->data;
5755 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5756 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5757 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5758 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5759 FIRMWARE_ID_RLC_G_UCODE,
5760 fw_data, fw_size);
5761
5762 /* mec1 ucode */
5763 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5764 adev->gfx.mec_fw->data;
5765 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5766 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5767 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5768 cp_hdr->jt_size * 4;
5769 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5770 FIRMWARE_ID_CP_MEC,
5771 fw_data, fw_size);
5772 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5773 }
5774
5775 /* Temporarily put sdma part here */
gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device * adev)5776 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5777 {
5778 const __le32 *fw_data;
5779 uint32_t fw_size;
5780 const struct sdma_firmware_header_v1_0 *sdma_hdr;
5781 int i;
5782
5783 for (i = 0; i < adev->sdma.num_instances; i++) {
5784 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5785 adev->sdma.instance[i].fw->data;
5786 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5787 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5788 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5789
5790 if (i == 0) {
5791 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5792 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5793 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5794 FIRMWARE_ID_SDMA0_JT,
5795 (uint32_t *)fw_data +
5796 sdma_hdr->jt_offset,
5797 sdma_hdr->jt_size * 4);
5798 } else if (i == 1) {
5799 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5800 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5801 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5802 FIRMWARE_ID_SDMA1_JT,
5803 (uint32_t *)fw_data +
5804 sdma_hdr->jt_offset,
5805 sdma_hdr->jt_size * 4);
5806 }
5807 }
5808 }
5809
gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device * adev)5810 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5811 {
5812 uint32_t rlc_g_offset, rlc_g_size, tmp;
5813 uint64_t gpu_addr;
5814
5815 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5816 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5817 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5818
5819 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5820 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5821 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5822
5823 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5824 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5825 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5826
5827 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5828 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5829 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5830 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5831 return -EINVAL;
5832 }
5833
5834 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5835 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5836 DRM_ERROR("RLC ROM should halt itself\n");
5837 return -EINVAL;
5838 }
5839
5840 return 0;
5841 }
5842
gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device * adev)5843 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5844 {
5845 uint32_t usec_timeout = 50000; /* wait for 50ms */
5846 uint32_t tmp;
5847 int i;
5848 uint64_t addr;
5849
5850 /* Trigger an invalidation of the L1 instruction caches */
5851 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5852 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5853 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5854
5855 /* Wait for invalidation complete */
5856 for (i = 0; i < usec_timeout; i++) {
5857 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5858 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5859 INVALIDATE_CACHE_COMPLETE))
5860 break;
5861 udelay(1);
5862 }
5863
5864 if (i >= usec_timeout) {
5865 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5866 return -EINVAL;
5867 }
5868
5869 /* Program me ucode address into intruction cache address register */
5870 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5871 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5872 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5873 lower_32_bits(addr) & 0xFFFFF000);
5874 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5875 upper_32_bits(addr));
5876
5877 return 0;
5878 }
5879
gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device * adev)5880 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5881 {
5882 uint32_t usec_timeout = 50000; /* wait for 50ms */
5883 uint32_t tmp;
5884 int i;
5885 uint64_t addr;
5886
5887 /* Trigger an invalidation of the L1 instruction caches */
5888 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5889 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5890 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5891
5892 /* Wait for invalidation complete */
5893 for (i = 0; i < usec_timeout; i++) {
5894 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5895 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5896 INVALIDATE_CACHE_COMPLETE))
5897 break;
5898 udelay(1);
5899 }
5900
5901 if (i >= usec_timeout) {
5902 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5903 return -EINVAL;
5904 }
5905
5906 /* Program ce ucode address into intruction cache address register */
5907 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5908 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5909 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5910 lower_32_bits(addr) & 0xFFFFF000);
5911 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5912 upper_32_bits(addr));
5913
5914 return 0;
5915 }
5916
gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device * adev)5917 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5918 {
5919 uint32_t usec_timeout = 50000; /* wait for 50ms */
5920 uint32_t tmp;
5921 int i;
5922 uint64_t addr;
5923
5924 /* Trigger an invalidation of the L1 instruction caches */
5925 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5926 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5927 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5928
5929 /* Wait for invalidation complete */
5930 for (i = 0; i < usec_timeout; i++) {
5931 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5932 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5933 INVALIDATE_CACHE_COMPLETE))
5934 break;
5935 udelay(1);
5936 }
5937
5938 if (i >= usec_timeout) {
5939 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5940 return -EINVAL;
5941 }
5942
5943 /* Program pfp ucode address into intruction cache address register */
5944 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5945 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5946 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5947 lower_32_bits(addr) & 0xFFFFF000);
5948 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5949 upper_32_bits(addr));
5950
5951 return 0;
5952 }
5953
gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device * adev)5954 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5955 {
5956 uint32_t usec_timeout = 50000; /* wait for 50ms */
5957 uint32_t tmp;
5958 int i;
5959 uint64_t addr;
5960
5961 /* Trigger an invalidation of the L1 instruction caches */
5962 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5963 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5964 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5965
5966 /* Wait for invalidation complete */
5967 for (i = 0; i < usec_timeout; i++) {
5968 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5969 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5970 INVALIDATE_CACHE_COMPLETE))
5971 break;
5972 udelay(1);
5973 }
5974
5975 if (i >= usec_timeout) {
5976 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5977 return -EINVAL;
5978 }
5979
5980 /* Program mec1 ucode address into intruction cache address register */
5981 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5982 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5983 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5984 lower_32_bits(addr) & 0xFFFFF000);
5985 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5986 upper_32_bits(addr));
5987
5988 return 0;
5989 }
5990
gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device * adev)5991 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5992 {
5993 uint32_t cp_status;
5994 uint32_t bootload_status;
5995 int i, r;
5996
5997 for (i = 0; i < adev->usec_timeout; i++) {
5998 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5999 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
6000 if ((cp_status == 0) &&
6001 (REG_GET_FIELD(bootload_status,
6002 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
6003 break;
6004 }
6005 udelay(1);
6006 }
6007
6008 if (i >= adev->usec_timeout) {
6009 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
6010 return -ETIMEDOUT;
6011 }
6012
6013 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
6014 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
6015 if (r)
6016 return r;
6017
6018 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
6019 if (r)
6020 return r;
6021
6022 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
6023 if (r)
6024 return r;
6025
6026 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
6027 if (r)
6028 return r;
6029 }
6030
6031 return 0;
6032 }
6033
gfx_v10_0_cp_gfx_enable(struct amdgpu_device * adev,bool enable)6034 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
6035 {
6036 int i;
6037 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
6038
6039 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
6040 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
6041 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
6042
6043 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2))
6044 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
6045 else
6046 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
6047
6048 if (amdgpu_in_reset(adev) && !enable)
6049 return 0;
6050
6051 for (i = 0; i < adev->usec_timeout; i++) {
6052 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
6053 break;
6054 udelay(1);
6055 }
6056
6057 if (i >= adev->usec_timeout)
6058 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
6059
6060 return 0;
6061 }
6062
gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device * adev)6063 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
6064 {
6065 int r;
6066 const struct gfx_firmware_header_v1_0 *pfp_hdr;
6067 const __le32 *fw_data;
6068 unsigned int i, fw_size;
6069 uint32_t tmp;
6070 uint32_t usec_timeout = 50000; /* wait for 50ms */
6071
6072 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
6073 adev->gfx.pfp_fw->data;
6074
6075 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
6076
6077 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
6078 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
6079 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
6080
6081 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
6082 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6083 &adev->gfx.pfp.pfp_fw_obj,
6084 &adev->gfx.pfp.pfp_fw_gpu_addr,
6085 (void **)&adev->gfx.pfp.pfp_fw_ptr);
6086 if (r) {
6087 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
6088 gfx_v10_0_pfp_fini(adev);
6089 return r;
6090 }
6091
6092 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
6093
6094 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
6095 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
6096
6097 /* Trigger an invalidation of the L1 instruction caches */
6098 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
6099 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6100 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
6101
6102 /* Wait for invalidation complete */
6103 for (i = 0; i < usec_timeout; i++) {
6104 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
6105 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
6106 INVALIDATE_CACHE_COMPLETE))
6107 break;
6108 udelay(1);
6109 }
6110
6111 if (i >= usec_timeout) {
6112 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6113 return -EINVAL;
6114 }
6115
6116 if (amdgpu_emu_mode == 1)
6117 amdgpu_device_flush_hdp(adev, NULL);
6118
6119 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
6120 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
6121 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
6122 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
6123 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6124 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
6125 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
6126 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
6127 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
6128 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
6129
6130 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
6131
6132 for (i = 0; i < pfp_hdr->jt_size; i++)
6133 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
6134 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
6135
6136 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
6137
6138 return 0;
6139 }
6140
gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device * adev)6141 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
6142 {
6143 int r;
6144 const struct gfx_firmware_header_v1_0 *ce_hdr;
6145 const __le32 *fw_data;
6146 unsigned int i, fw_size;
6147 uint32_t tmp;
6148 uint32_t usec_timeout = 50000; /* wait for 50ms */
6149
6150 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
6151 adev->gfx.ce_fw->data;
6152
6153 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
6154
6155 fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
6156 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
6157 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
6158
6159 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
6160 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6161 &adev->gfx.ce.ce_fw_obj,
6162 &adev->gfx.ce.ce_fw_gpu_addr,
6163 (void **)&adev->gfx.ce.ce_fw_ptr);
6164 if (r) {
6165 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
6166 gfx_v10_0_ce_fini(adev);
6167 return r;
6168 }
6169
6170 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
6171
6172 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
6173 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
6174
6175 /* Trigger an invalidation of the L1 instruction caches */
6176 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
6177 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6178 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
6179
6180 /* Wait for invalidation complete */
6181 for (i = 0; i < usec_timeout; i++) {
6182 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
6183 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
6184 INVALIDATE_CACHE_COMPLETE))
6185 break;
6186 udelay(1);
6187 }
6188
6189 if (i >= usec_timeout) {
6190 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6191 return -EINVAL;
6192 }
6193
6194 if (amdgpu_emu_mode == 1)
6195 amdgpu_device_flush_hdp(adev, NULL);
6196
6197 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
6198 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
6199 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
6200 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
6201 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6202 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
6203 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
6204 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
6205 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
6206
6207 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
6208
6209 for (i = 0; i < ce_hdr->jt_size; i++)
6210 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
6211 le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
6212
6213 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
6214
6215 return 0;
6216 }
6217
gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device * adev)6218 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
6219 {
6220 int r;
6221 const struct gfx_firmware_header_v1_0 *me_hdr;
6222 const __le32 *fw_data;
6223 unsigned int i, fw_size;
6224 uint32_t tmp;
6225 uint32_t usec_timeout = 50000; /* wait for 50ms */
6226
6227 me_hdr = (const struct gfx_firmware_header_v1_0 *)
6228 adev->gfx.me_fw->data;
6229
6230 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
6231
6232 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
6233 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
6234 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
6235
6236 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
6237 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6238 &adev->gfx.me.me_fw_obj,
6239 &adev->gfx.me.me_fw_gpu_addr,
6240 (void **)&adev->gfx.me.me_fw_ptr);
6241 if (r) {
6242 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
6243 gfx_v10_0_me_fini(adev);
6244 return r;
6245 }
6246
6247 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
6248
6249 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
6250 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
6251
6252 /* Trigger an invalidation of the L1 instruction caches */
6253 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6254 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6255 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
6256
6257 /* Wait for invalidation complete */
6258 for (i = 0; i < usec_timeout; i++) {
6259 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6260 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
6261 INVALIDATE_CACHE_COMPLETE))
6262 break;
6263 udelay(1);
6264 }
6265
6266 if (i >= usec_timeout) {
6267 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6268 return -EINVAL;
6269 }
6270
6271 if (amdgpu_emu_mode == 1)
6272 amdgpu_device_flush_hdp(adev, NULL);
6273
6274 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
6275 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
6276 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
6277 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
6278 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6279 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
6280 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
6281 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
6282 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
6283
6284 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
6285
6286 for (i = 0; i < me_hdr->jt_size; i++)
6287 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
6288 le32_to_cpup(fw_data + me_hdr->jt_offset + i));
6289
6290 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
6291
6292 return 0;
6293 }
6294
gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device * adev)6295 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
6296 {
6297 int r;
6298
6299 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
6300 return -EINVAL;
6301
6302 gfx_v10_0_cp_gfx_enable(adev, false);
6303
6304 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
6305 if (r) {
6306 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
6307 return r;
6308 }
6309
6310 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
6311 if (r) {
6312 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
6313 return r;
6314 }
6315
6316 r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
6317 if (r) {
6318 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
6319 return r;
6320 }
6321
6322 return 0;
6323 }
6324
gfx_v10_0_cp_gfx_start(struct amdgpu_device * adev)6325 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
6326 {
6327 struct amdgpu_ring *ring;
6328 const struct cs_section_def *sect = NULL;
6329 const struct cs_extent_def *ext = NULL;
6330 int r, i;
6331 int ctx_reg_offset;
6332
6333 /* init the CP */
6334 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
6335 adev->gfx.config.max_hw_contexts - 1);
6336 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
6337
6338 gfx_v10_0_cp_gfx_enable(adev, true);
6339
6340 ring = &adev->gfx.gfx_ring[0];
6341 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
6342 if (r) {
6343 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6344 return r;
6345 }
6346
6347 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6348 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
6349
6350 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6351 amdgpu_ring_write(ring, 0x80000000);
6352 amdgpu_ring_write(ring, 0x80000000);
6353
6354 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
6355 for (ext = sect->section; ext->extent != NULL; ++ext) {
6356 if (sect->id == SECT_CONTEXT) {
6357 amdgpu_ring_write(ring,
6358 PACKET3(PACKET3_SET_CONTEXT_REG,
6359 ext->reg_count));
6360 amdgpu_ring_write(ring, ext->reg_index -
6361 PACKET3_SET_CONTEXT_REG_START);
6362 for (i = 0; i < ext->reg_count; i++)
6363 amdgpu_ring_write(ring, ext->extent[i]);
6364 }
6365 }
6366 }
6367
6368 ctx_reg_offset =
6369 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
6370 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
6371 amdgpu_ring_write(ring, ctx_reg_offset);
6372 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
6373
6374 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6375 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
6376
6377 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6378 amdgpu_ring_write(ring, 0);
6379
6380 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
6381 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
6382 amdgpu_ring_write(ring, 0x8000);
6383 amdgpu_ring_write(ring, 0x8000);
6384
6385 amdgpu_ring_commit(ring);
6386
6387 /* submit cs packet to copy state 0 to next available state */
6388 if (adev->gfx.num_gfx_rings > 1) {
6389 /* maximum supported gfx ring is 2 */
6390 ring = &adev->gfx.gfx_ring[1];
6391 r = amdgpu_ring_alloc(ring, 2);
6392 if (r) {
6393 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6394 return r;
6395 }
6396
6397 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6398 amdgpu_ring_write(ring, 0);
6399
6400 amdgpu_ring_commit(ring);
6401 }
6402 return 0;
6403 }
6404
gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device * adev,CP_PIPE_ID pipe)6405 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
6406 CP_PIPE_ID pipe)
6407 {
6408 u32 tmp;
6409
6410 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
6411 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
6412
6413 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
6414 }
6415
gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device * adev,struct amdgpu_ring * ring)6416 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
6417 struct amdgpu_ring *ring)
6418 {
6419 u32 tmp;
6420
6421 if (!amdgpu_async_gfx_ring) {
6422 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6423 if (ring->use_doorbell) {
6424 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6425 DOORBELL_OFFSET, ring->doorbell_index);
6426 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6427 DOORBELL_EN, 1);
6428 } else {
6429 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6430 DOORBELL_EN, 0);
6431 }
6432 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6433 }
6434 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6435 case IP_VERSION(10, 3, 0):
6436 case IP_VERSION(10, 3, 2):
6437 case IP_VERSION(10, 3, 1):
6438 case IP_VERSION(10, 3, 4):
6439 case IP_VERSION(10, 3, 5):
6440 case IP_VERSION(10, 3, 6):
6441 case IP_VERSION(10, 3, 3):
6442 case IP_VERSION(10, 3, 7):
6443 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6444 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6445 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6446
6447 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6448 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6449 break;
6450 default:
6451 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6452 DOORBELL_RANGE_LOWER, ring->doorbell_index);
6453 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6454
6455 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6456 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6457 break;
6458 }
6459 }
6460
gfx_v10_0_cp_gfx_resume(struct amdgpu_device * adev)6461 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6462 {
6463 struct amdgpu_ring *ring;
6464 u32 tmp;
6465 u32 rb_bufsz;
6466 u64 rb_addr, rptr_addr, wptr_gpu_addr;
6467
6468 /* Set the write pointer delay */
6469 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6470
6471 /* set the RB to use vmid 0 */
6472 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6473
6474 /* Init gfx ring 0 for pipe 0 */
6475 mutex_lock(&adev->srbm_mutex);
6476 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6477
6478 /* Set ring buffer size */
6479 ring = &adev->gfx.gfx_ring[0];
6480 rb_bufsz = order_base_2(ring->ring_size / 8);
6481 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6482 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6483 #ifdef __BIG_ENDIAN
6484 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6485 #endif
6486 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6487
6488 /* Initialize the ring buffer's write pointers */
6489 ring->wptr = 0;
6490 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6491 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6492
6493 /* set the wb address whether it's enabled or not */
6494 rptr_addr = ring->rptr_gpu_addr;
6495 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6496 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6497 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6498
6499 wptr_gpu_addr = ring->wptr_gpu_addr;
6500 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6501 lower_32_bits(wptr_gpu_addr));
6502 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6503 upper_32_bits(wptr_gpu_addr));
6504
6505 mdelay(1);
6506 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6507
6508 rb_addr = ring->gpu_addr >> 8;
6509 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6510 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6511
6512 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6513
6514 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6515 mutex_unlock(&adev->srbm_mutex);
6516
6517 /* Init gfx ring 1 for pipe 1 */
6518 if (adev->gfx.num_gfx_rings > 1) {
6519 mutex_lock(&adev->srbm_mutex);
6520 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6521 /* maximum supported gfx ring is 2 */
6522 ring = &adev->gfx.gfx_ring[1];
6523 rb_bufsz = order_base_2(ring->ring_size / 8);
6524 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6525 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6526 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6527 /* Initialize the ring buffer's write pointers */
6528 ring->wptr = 0;
6529 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6530 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6531 /* Set the wb address whether it's enabled or not */
6532 rptr_addr = ring->rptr_gpu_addr;
6533 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6534 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6535 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6536 wptr_gpu_addr = ring->wptr_gpu_addr;
6537 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6538 lower_32_bits(wptr_gpu_addr));
6539 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6540 upper_32_bits(wptr_gpu_addr));
6541
6542 mdelay(1);
6543 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6544
6545 rb_addr = ring->gpu_addr >> 8;
6546 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6547 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6548 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6549
6550 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6551 mutex_unlock(&adev->srbm_mutex);
6552 }
6553 /* Switch to pipe 0 */
6554 mutex_lock(&adev->srbm_mutex);
6555 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6556 mutex_unlock(&adev->srbm_mutex);
6557
6558 /* start the ring */
6559 gfx_v10_0_cp_gfx_start(adev);
6560
6561 return 0;
6562 }
6563
gfx_v10_0_cp_compute_enable(struct amdgpu_device * adev,bool enable)6564 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6565 {
6566 if (enable) {
6567 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6568 case IP_VERSION(10, 3, 0):
6569 case IP_VERSION(10, 3, 2):
6570 case IP_VERSION(10, 3, 1):
6571 case IP_VERSION(10, 3, 4):
6572 case IP_VERSION(10, 3, 5):
6573 case IP_VERSION(10, 3, 6):
6574 case IP_VERSION(10, 3, 3):
6575 case IP_VERSION(10, 3, 7):
6576 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6577 break;
6578 default:
6579 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6580 break;
6581 }
6582 } else {
6583 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6584 case IP_VERSION(10, 3, 0):
6585 case IP_VERSION(10, 3, 2):
6586 case IP_VERSION(10, 3, 1):
6587 case IP_VERSION(10, 3, 4):
6588 case IP_VERSION(10, 3, 5):
6589 case IP_VERSION(10, 3, 6):
6590 case IP_VERSION(10, 3, 3):
6591 case IP_VERSION(10, 3, 7):
6592 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6593 (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6594 CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6595 break;
6596 default:
6597 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6598 (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6599 CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6600 break;
6601 }
6602 adev->gfx.kiq[0].ring.sched.ready = false;
6603 }
6604 udelay(50);
6605 }
6606
gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device * adev)6607 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6608 {
6609 const struct gfx_firmware_header_v1_0 *mec_hdr;
6610 const __le32 *fw_data;
6611 unsigned int i;
6612 u32 tmp;
6613 u32 usec_timeout = 50000; /* Wait for 50 ms */
6614
6615 if (!adev->gfx.mec_fw)
6616 return -EINVAL;
6617
6618 gfx_v10_0_cp_compute_enable(adev, false);
6619
6620 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6621 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6622
6623 fw_data = (const __le32 *)
6624 (adev->gfx.mec_fw->data +
6625 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6626
6627 /* Trigger an invalidation of the L1 instruction caches */
6628 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6629 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6630 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6631
6632 /* Wait for invalidation complete */
6633 for (i = 0; i < usec_timeout; i++) {
6634 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6635 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6636 INVALIDATE_CACHE_COMPLETE))
6637 break;
6638 udelay(1);
6639 }
6640
6641 if (i >= usec_timeout) {
6642 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6643 return -EINVAL;
6644 }
6645
6646 if (amdgpu_emu_mode == 1)
6647 amdgpu_device_flush_hdp(adev, NULL);
6648
6649 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6650 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6651 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6652 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6653 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6654
6655 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6656 0xFFFFF000);
6657 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6658 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6659
6660 /* MEC1 */
6661 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6662
6663 for (i = 0; i < mec_hdr->jt_size; i++)
6664 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6665 le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6666
6667 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6668
6669 /*
6670 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6671 * different microcode than MEC1.
6672 */
6673
6674 return 0;
6675 }
6676
gfx_v10_0_kiq_setting(struct amdgpu_ring * ring)6677 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6678 {
6679 uint32_t tmp;
6680 struct amdgpu_device *adev = ring->adev;
6681
6682 /* tell RLC which is KIQ queue */
6683 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6684 case IP_VERSION(10, 3, 0):
6685 case IP_VERSION(10, 3, 2):
6686 case IP_VERSION(10, 3, 1):
6687 case IP_VERSION(10, 3, 4):
6688 case IP_VERSION(10, 3, 5):
6689 case IP_VERSION(10, 3, 6):
6690 case IP_VERSION(10, 3, 3):
6691 case IP_VERSION(10, 3, 7):
6692 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6693 tmp &= 0xffffff00;
6694 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6695 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp | 0x80);
6696 break;
6697 default:
6698 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6699 tmp &= 0xffffff00;
6700 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6701 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp | 0x80);
6702 break;
6703 }
6704 }
6705
gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device * adev,struct v10_gfx_mqd * mqd,struct amdgpu_mqd_prop * prop)6706 static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev,
6707 struct v10_gfx_mqd *mqd,
6708 struct amdgpu_mqd_prop *prop)
6709 {
6710 bool priority = 0;
6711 u32 tmp;
6712
6713 /* set up default queue priority level
6714 * 0x0 = low priority, 0x1 = high priority
6715 */
6716 if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH)
6717 priority = 1;
6718
6719 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6720 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority);
6721 mqd->cp_gfx_hqd_queue_priority = tmp;
6722 }
6723
gfx_v10_0_gfx_mqd_init(struct amdgpu_device * adev,void * m,struct amdgpu_mqd_prop * prop)6724 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
6725 struct amdgpu_mqd_prop *prop)
6726 {
6727 struct v10_gfx_mqd *mqd = m;
6728 uint64_t hqd_gpu_addr, wb_gpu_addr;
6729 uint32_t tmp;
6730 uint32_t rb_bufsz;
6731
6732 /* set up gfx hqd wptr */
6733 mqd->cp_gfx_hqd_wptr = 0;
6734 mqd->cp_gfx_hqd_wptr_hi = 0;
6735
6736 /* set the pointer to the MQD */
6737 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;
6738 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6739
6740 /* set up mqd control */
6741 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6742 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6743 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6744 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6745 mqd->cp_gfx_mqd_control = tmp;
6746
6747 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6748 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6749 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6750 mqd->cp_gfx_hqd_vmid = 0;
6751
6752 /* set up gfx queue priority */
6753 gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop);
6754
6755 /* set up time quantum */
6756 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6757 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6758 mqd->cp_gfx_hqd_quantum = tmp;
6759
6760 /* set up gfx hqd base. this is similar as CP_RB_BASE */
6761 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6762 mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6763 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6764
6765 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6766 wb_gpu_addr = prop->rptr_gpu_addr;
6767 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6768 mqd->cp_gfx_hqd_rptr_addr_hi =
6769 upper_32_bits(wb_gpu_addr) & 0xffff;
6770
6771 /* set up rb_wptr_poll addr */
6772 wb_gpu_addr = prop->wptr_gpu_addr;
6773 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6774 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6775
6776 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6777 rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
6778 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6779 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6780 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6781 #ifdef __BIG_ENDIAN
6782 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6783 #endif
6784 mqd->cp_gfx_hqd_cntl = tmp;
6785
6786 /* set up cp_doorbell_control */
6787 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6788 if (prop->use_doorbell) {
6789 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6790 DOORBELL_OFFSET, prop->doorbell_index);
6791 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6792 DOORBELL_EN, 1);
6793 } else
6794 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6795 DOORBELL_EN, 0);
6796 mqd->cp_rb_doorbell_control = tmp;
6797
6798 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6799 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6800
6801 /* active the queue */
6802 mqd->cp_gfx_hqd_active = 1;
6803
6804 return 0;
6805 }
6806
gfx_v10_0_kgq_init_queue(struct amdgpu_ring * ring,bool reset)6807 static int gfx_v10_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset)
6808 {
6809 struct amdgpu_device *adev = ring->adev;
6810 struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6811 int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6812
6813 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) {
6814 memset((void *)mqd, 0, sizeof(*mqd));
6815 mutex_lock(&adev->srbm_mutex);
6816 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6817 amdgpu_ring_init_mqd(ring);
6818
6819 /*
6820 * if there are 2 gfx rings, set the lower doorbell
6821 * range of the first ring, otherwise the range of
6822 * the second ring will override the first ring
6823 */
6824 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6825 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6826
6827 nv_grbm_select(adev, 0, 0, 0, 0);
6828 mutex_unlock(&adev->srbm_mutex);
6829 if (adev->gfx.me.mqd_backup[mqd_idx])
6830 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6831 } else {
6832 mutex_lock(&adev->srbm_mutex);
6833 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6834 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6835 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6836
6837 nv_grbm_select(adev, 0, 0, 0, 0);
6838 mutex_unlock(&adev->srbm_mutex);
6839 /* restore mqd with the backup copy */
6840 if (adev->gfx.me.mqd_backup[mqd_idx])
6841 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6842 /* reset the ring */
6843 ring->wptr = 0;
6844 *ring->wptr_cpu_addr = 0;
6845 amdgpu_ring_clear_ring(ring);
6846 }
6847
6848 return 0;
6849 }
6850
gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device * adev)6851 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6852 {
6853 int r, i;
6854
6855 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6856 r = gfx_v10_0_kgq_init_queue(&adev->gfx.gfx_ring[i], false);
6857 if (r)
6858 return r;
6859 }
6860
6861 r = amdgpu_gfx_enable_kgq(adev, 0);
6862 if (r)
6863 return r;
6864
6865 return gfx_v10_0_cp_gfx_start(adev);
6866 }
6867
gfx_v10_0_compute_mqd_init(struct amdgpu_device * adev,void * m,struct amdgpu_mqd_prop * prop)6868 static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
6869 struct amdgpu_mqd_prop *prop)
6870 {
6871 struct v10_compute_mqd *mqd = m;
6872 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6873 uint32_t tmp;
6874
6875 mqd->header = 0xC0310800;
6876 mqd->compute_pipelinestat_enable = 0x00000001;
6877 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6878 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6879 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6880 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6881 mqd->compute_misc_reserved = 0x00000003;
6882
6883 eop_base_addr = prop->eop_gpu_addr >> 8;
6884 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6885 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6886
6887 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6888 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6889 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6890 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6891
6892 mqd->cp_hqd_eop_control = tmp;
6893
6894 /* enable doorbell? */
6895 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6896
6897 if (prop->use_doorbell) {
6898 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6899 DOORBELL_OFFSET, prop->doorbell_index);
6900 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6901 DOORBELL_EN, 1);
6902 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6903 DOORBELL_SOURCE, 0);
6904 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6905 DOORBELL_HIT, 0);
6906 } else {
6907 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6908 DOORBELL_EN, 0);
6909 }
6910
6911 mqd->cp_hqd_pq_doorbell_control = tmp;
6912
6913 /* disable the queue if it's active */
6914 mqd->cp_hqd_dequeue_request = 0;
6915 mqd->cp_hqd_pq_rptr = 0;
6916 mqd->cp_hqd_pq_wptr_lo = 0;
6917 mqd->cp_hqd_pq_wptr_hi = 0;
6918
6919 /* set the pointer to the MQD */
6920 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;
6921 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6922
6923 /* set MQD vmid to 0 */
6924 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6925 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6926 mqd->cp_mqd_control = tmp;
6927
6928 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6929 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6930 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6931 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6932
6933 /* set up the HQD, this is similar to CP_RB0_CNTL */
6934 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6935 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6936 (order_base_2(prop->queue_size / 4) - 1));
6937 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6938 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
6939 #ifdef __BIG_ENDIAN
6940 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6941 #endif
6942 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
6943 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,
6944 prop->allow_tunneling);
6945 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6946 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6947 mqd->cp_hqd_pq_control = tmp;
6948
6949 /* set the wb address whether it's enabled or not */
6950 wb_gpu_addr = prop->rptr_gpu_addr;
6951 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6952 mqd->cp_hqd_pq_rptr_report_addr_hi =
6953 upper_32_bits(wb_gpu_addr) & 0xffff;
6954
6955 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6956 wb_gpu_addr = prop->wptr_gpu_addr;
6957 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6958 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6959
6960 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6961 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6962
6963 /* set the vmid for the queue */
6964 mqd->cp_hqd_vmid = 0;
6965
6966 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6967 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6968 mqd->cp_hqd_persistent_state = tmp;
6969
6970 /* set MIN_IB_AVAIL_SIZE */
6971 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6972 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6973 mqd->cp_hqd_ib_control = tmp;
6974
6975 /* set static priority for a compute queue/ring */
6976 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
6977 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
6978
6979 mqd->cp_hqd_active = prop->hqd_active;
6980
6981 return 0;
6982 }
6983
gfx_v10_0_kiq_init_register(struct amdgpu_ring * ring)6984 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6985 {
6986 struct amdgpu_device *adev = ring->adev;
6987 struct v10_compute_mqd *mqd = ring->mqd_ptr;
6988 int j;
6989
6990 /* inactivate the queue */
6991 if (amdgpu_sriov_vf(adev))
6992 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6993
6994 /* disable wptr polling */
6995 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6996
6997 /* disable the queue if it's active */
6998 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6999 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
7000 for (j = 0; j < adev->usec_timeout; j++) {
7001 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
7002 break;
7003 udelay(1);
7004 }
7005 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
7006 mqd->cp_hqd_dequeue_request);
7007 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
7008 mqd->cp_hqd_pq_rptr);
7009 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
7010 mqd->cp_hqd_pq_wptr_lo);
7011 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
7012 mqd->cp_hqd_pq_wptr_hi);
7013 }
7014
7015 /* disable doorbells */
7016 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
7017
7018 /* write the EOP addr */
7019 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
7020 mqd->cp_hqd_eop_base_addr_lo);
7021 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
7022 mqd->cp_hqd_eop_base_addr_hi);
7023
7024 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
7025 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
7026 mqd->cp_hqd_eop_control);
7027
7028 /* set the pointer to the MQD */
7029 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
7030 mqd->cp_mqd_base_addr_lo);
7031 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
7032 mqd->cp_mqd_base_addr_hi);
7033
7034 /* set MQD vmid to 0 */
7035 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
7036 mqd->cp_mqd_control);
7037
7038 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
7039 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
7040 mqd->cp_hqd_pq_base_lo);
7041 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
7042 mqd->cp_hqd_pq_base_hi);
7043
7044 /* set up the HQD, this is similar to CP_RB0_CNTL */
7045 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
7046 mqd->cp_hqd_pq_control);
7047
7048 /* set the wb address whether it's enabled or not */
7049 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
7050 mqd->cp_hqd_pq_rptr_report_addr_lo);
7051 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
7052 mqd->cp_hqd_pq_rptr_report_addr_hi);
7053
7054 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
7055 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
7056 mqd->cp_hqd_pq_wptr_poll_addr_lo);
7057 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
7058 mqd->cp_hqd_pq_wptr_poll_addr_hi);
7059
7060 /* enable the doorbell if requested */
7061 if (ring->use_doorbell) {
7062 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
7063 (adev->doorbell_index.kiq * 2) << 2);
7064 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
7065 (adev->doorbell_index.userqueue_end * 2) << 2);
7066 }
7067
7068 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
7069 mqd->cp_hqd_pq_doorbell_control);
7070
7071 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
7072 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
7073 mqd->cp_hqd_pq_wptr_lo);
7074 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
7075 mqd->cp_hqd_pq_wptr_hi);
7076
7077 /* set the vmid for the queue */
7078 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
7079
7080 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
7081 mqd->cp_hqd_persistent_state);
7082
7083 /* activate the queue */
7084 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
7085 mqd->cp_hqd_active);
7086
7087 if (ring->use_doorbell)
7088 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
7089
7090 return 0;
7091 }
7092
gfx_v10_0_kiq_init_queue(struct amdgpu_ring * ring)7093 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
7094 {
7095 struct amdgpu_device *adev = ring->adev;
7096 struct v10_compute_mqd *mqd = ring->mqd_ptr;
7097
7098 gfx_v10_0_kiq_setting(ring);
7099
7100 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
7101 /* reset MQD to a clean status */
7102 if (adev->gfx.kiq[0].mqd_backup)
7103 memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd));
7104
7105 /* reset ring buffer */
7106 ring->wptr = 0;
7107 amdgpu_ring_clear_ring(ring);
7108
7109 mutex_lock(&adev->srbm_mutex);
7110 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7111 gfx_v10_0_kiq_init_register(ring);
7112 nv_grbm_select(adev, 0, 0, 0, 0);
7113 mutex_unlock(&adev->srbm_mutex);
7114 } else {
7115 memset((void *)mqd, 0, sizeof(*mqd));
7116 if (amdgpu_sriov_vf(adev) && adev->in_suspend)
7117 amdgpu_ring_clear_ring(ring);
7118 mutex_lock(&adev->srbm_mutex);
7119 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7120 amdgpu_ring_init_mqd(ring);
7121 gfx_v10_0_kiq_init_register(ring);
7122 nv_grbm_select(adev, 0, 0, 0, 0);
7123 mutex_unlock(&adev->srbm_mutex);
7124
7125 if (adev->gfx.kiq[0].mqd_backup)
7126 memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd));
7127 }
7128
7129 return 0;
7130 }
7131
gfx_v10_0_kcq_init_queue(struct amdgpu_ring * ring,bool restore)7132 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring, bool restore)
7133 {
7134 struct amdgpu_device *adev = ring->adev;
7135 struct v10_compute_mqd *mqd = ring->mqd_ptr;
7136 int mqd_idx = ring - &adev->gfx.compute_ring[0];
7137
7138 if (!restore && !amdgpu_in_reset(adev) && !adev->in_suspend) {
7139 memset((void *)mqd, 0, sizeof(*mqd));
7140 mutex_lock(&adev->srbm_mutex);
7141 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7142 amdgpu_ring_init_mqd(ring);
7143 nv_grbm_select(adev, 0, 0, 0, 0);
7144 mutex_unlock(&adev->srbm_mutex);
7145
7146 if (adev->gfx.mec.mqd_backup[mqd_idx])
7147 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
7148 } else {
7149 /* restore MQD to a clean status */
7150 if (adev->gfx.mec.mqd_backup[mqd_idx])
7151 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
7152 /* reset ring buffer */
7153 ring->wptr = 0;
7154 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
7155 amdgpu_ring_clear_ring(ring);
7156 }
7157
7158 return 0;
7159 }
7160
gfx_v10_0_kiq_resume(struct amdgpu_device * adev)7161 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
7162 {
7163 gfx_v10_0_kiq_init_queue(&adev->gfx.kiq[0].ring);
7164 return 0;
7165 }
7166
gfx_v10_0_kcq_resume(struct amdgpu_device * adev)7167 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
7168 {
7169 int i, r;
7170
7171 gfx_v10_0_cp_compute_enable(adev, true);
7172
7173 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7174 r = gfx_v10_0_kcq_init_queue(&adev->gfx.compute_ring[i],
7175 false);
7176 if (r)
7177 return r;
7178 }
7179
7180 return amdgpu_gfx_enable_kcq(adev, 0);
7181 }
7182
gfx_v10_0_cp_resume(struct amdgpu_device * adev)7183 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
7184 {
7185 int r, i;
7186 struct amdgpu_ring *ring;
7187
7188 if (!(adev->flags & AMD_IS_APU))
7189 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7190
7191 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7192 /* legacy firmware loading */
7193 r = gfx_v10_0_cp_gfx_load_microcode(adev);
7194 if (r)
7195 return r;
7196
7197 r = gfx_v10_0_cp_compute_load_microcode(adev);
7198 if (r)
7199 return r;
7200 }
7201
7202 r = gfx_v10_0_kiq_resume(adev);
7203 if (r)
7204 return r;
7205
7206 r = gfx_v10_0_kcq_resume(adev);
7207 if (r)
7208 return r;
7209
7210 if (!amdgpu_async_gfx_ring) {
7211 r = gfx_v10_0_cp_gfx_resume(adev);
7212 if (r)
7213 return r;
7214 } else {
7215 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
7216 if (r)
7217 return r;
7218 }
7219
7220 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
7221 ring = &adev->gfx.gfx_ring[i];
7222 r = amdgpu_ring_test_helper(ring);
7223 if (r)
7224 return r;
7225 }
7226
7227 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7228 ring = &adev->gfx.compute_ring[i];
7229 r = amdgpu_ring_test_helper(ring);
7230 if (r)
7231 return r;
7232 }
7233
7234 return 0;
7235 }
7236
gfx_v10_0_cp_enable(struct amdgpu_device * adev,bool enable)7237 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
7238 {
7239 gfx_v10_0_cp_gfx_enable(adev, enable);
7240 gfx_v10_0_cp_compute_enable(adev, enable);
7241 }
7242
gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device * adev)7243 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
7244 {
7245 uint32_t data, pattern = 0xDEADBEEF;
7246
7247 /*
7248 * check if mmVGT_ESGS_RING_SIZE_UMD
7249 * has been remapped to mmVGT_ESGS_RING_SIZE
7250 */
7251 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7252 case IP_VERSION(10, 3, 0):
7253 case IP_VERSION(10, 3, 2):
7254 case IP_VERSION(10, 3, 4):
7255 case IP_VERSION(10, 3, 5):
7256 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
7257 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
7258 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7259
7260 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
7261 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7262 return true;
7263 }
7264 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
7265 break;
7266 case IP_VERSION(10, 3, 1):
7267 case IP_VERSION(10, 3, 3):
7268 case IP_VERSION(10, 3, 6):
7269 case IP_VERSION(10, 3, 7):
7270 return true;
7271 default:
7272 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
7273 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
7274 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7275
7276 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
7277 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7278 return true;
7279 }
7280 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
7281 break;
7282 }
7283
7284 return false;
7285 }
7286
gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device * adev)7287 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
7288 {
7289 uint32_t data;
7290
7291 if (amdgpu_sriov_vf(adev))
7292 return;
7293
7294 /*
7295 * Initialize cam_index to 0
7296 * index will auto-inc after each data writing
7297 */
7298 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
7299
7300 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7301 case IP_VERSION(10, 3, 0):
7302 case IP_VERSION(10, 3, 2):
7303 case IP_VERSION(10, 3, 1):
7304 case IP_VERSION(10, 3, 4):
7305 case IP_VERSION(10, 3, 5):
7306 case IP_VERSION(10, 3, 6):
7307 case IP_VERSION(10, 3, 3):
7308 case IP_VERSION(10, 3, 7):
7309 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7310 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7311 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7312 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
7313 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7314 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7315 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7316
7317 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7318 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7319 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7320 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
7321 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7322 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7323 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7324
7325 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7326 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7327 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7328 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
7329 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7330 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7331 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7332
7333 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7334 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7335 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7336 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7337 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7338 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7339 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7340
7341 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7342 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7343 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7344 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7345 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7346 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7347 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7348
7349 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7350 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7351 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7352 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7353 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7354 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7355 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7356
7357 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7358 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7359 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7360 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7361 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7362 break;
7363 default:
7364 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7365 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7366 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7367 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7368 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7369 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7370 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7371
7372 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7373 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7374 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7375 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7376 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7377 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7378 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7379
7380 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7381 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7382 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7383 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7384 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7385 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7386 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7387
7388 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7389 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7390 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7391 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7392 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7393 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7394 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7395
7396 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7397 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7398 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7399 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7400 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7401 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7402 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7403
7404 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7405 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7406 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7407 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7408 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7409 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7410 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7411
7412 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7413 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7414 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7415 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7416 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7417 break;
7418 }
7419
7420 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7421 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7422 }
7423
gfx_v10_0_disable_gpa_mode(struct amdgpu_device * adev)7424 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7425 {
7426 uint32_t data;
7427
7428 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
7429 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
7430 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
7431
7432 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
7433 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
7434 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
7435 }
7436
gfx_v10_0_hw_init(struct amdgpu_ip_block * ip_block)7437 static int gfx_v10_0_hw_init(struct amdgpu_ip_block *ip_block)
7438 {
7439 int r;
7440 struct amdgpu_device *adev = ip_block->adev;
7441
7442 if (!amdgpu_emu_mode)
7443 gfx_v10_0_init_golden_registers(adev);
7444
7445 amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size,
7446 adev->gfx.cleaner_shader_ptr);
7447
7448 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7449 /**
7450 * For gfx 10, rlc firmware loading relies on smu firmware is
7451 * loaded firstly, so in direct type, it has to load smc ucode
7452 * here before rlc.
7453 */
7454 r = amdgpu_pm_load_smu_firmware(adev, NULL);
7455 if (r)
7456 return r;
7457 gfx_v10_0_disable_gpa_mode(adev);
7458 }
7459
7460 /* if GRBM CAM not remapped, set up the remapping */
7461 if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7462 gfx_v10_0_setup_grbm_cam_remapping(adev);
7463
7464 gfx_v10_0_constants_init(adev);
7465
7466 r = gfx_v10_0_rlc_resume(adev);
7467 if (r)
7468 return r;
7469
7470 /*
7471 * init golden registers and rlc resume may override some registers,
7472 * reconfig them here
7473 */
7474 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 10) ||
7475 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) ||
7476 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2))
7477 gfx_v10_0_tcp_harvest(adev);
7478
7479 r = gfx_v10_0_cp_resume(adev);
7480 if (r)
7481 return r;
7482
7483 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0))
7484 gfx_v10_3_program_pbb_mode(adev);
7485
7486 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0) && !amdgpu_sriov_vf(adev))
7487 gfx_v10_3_set_power_brake_sequence(adev);
7488
7489 return r;
7490 }
7491
gfx_v10_0_hw_fini(struct amdgpu_ip_block * ip_block)7492 static int gfx_v10_0_hw_fini(struct amdgpu_ip_block *ip_block)
7493 {
7494 struct amdgpu_device *adev = ip_block->adev;
7495
7496 cancel_delayed_work_sync(&adev->gfx.idle_work);
7497
7498 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7499 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7500 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0);
7501
7502 /* WA added for Vangogh asic fixing the SMU suspend failure
7503 * It needs to set power gating again during gfxoff control
7504 * otherwise the gfxoff disallowing will be failed to set.
7505 */
7506 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 1))
7507 gfx_v10_0_set_powergating_state(ip_block, AMD_PG_STATE_UNGATE);
7508
7509 if (!adev->no_hw_access) {
7510 if (amdgpu_async_gfx_ring) {
7511 if (amdgpu_gfx_disable_kgq(adev, 0))
7512 DRM_ERROR("KGQ disable failed\n");
7513 }
7514
7515 if (amdgpu_gfx_disable_kcq(adev, 0))
7516 DRM_ERROR("KCQ disable failed\n");
7517 }
7518
7519 if (amdgpu_sriov_vf(adev)) {
7520 gfx_v10_0_cp_gfx_enable(adev, false);
7521 /* Remove the steps of clearing KIQ position.
7522 * It causes GFX hang when another Win guest is rendering.
7523 */
7524 return 0;
7525 }
7526 gfx_v10_0_cp_enable(adev, false);
7527 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7528
7529 return 0;
7530 }
7531
gfx_v10_0_suspend(struct amdgpu_ip_block * ip_block)7532 static int gfx_v10_0_suspend(struct amdgpu_ip_block *ip_block)
7533 {
7534 return gfx_v10_0_hw_fini(ip_block);
7535 }
7536
gfx_v10_0_resume(struct amdgpu_ip_block * ip_block)7537 static int gfx_v10_0_resume(struct amdgpu_ip_block *ip_block)
7538 {
7539 return gfx_v10_0_hw_init(ip_block);
7540 }
7541
gfx_v10_0_is_idle(struct amdgpu_ip_block * ip_block)7542 static bool gfx_v10_0_is_idle(struct amdgpu_ip_block *ip_block)
7543 {
7544 struct amdgpu_device *adev = ip_block->adev;
7545
7546 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7547 GRBM_STATUS, GUI_ACTIVE))
7548 return false;
7549 else
7550 return true;
7551 }
7552
gfx_v10_0_wait_for_idle(struct amdgpu_ip_block * ip_block)7553 static int gfx_v10_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
7554 {
7555 unsigned int i;
7556 u32 tmp;
7557 struct amdgpu_device *adev = ip_block->adev;
7558
7559 for (i = 0; i < adev->usec_timeout; i++) {
7560 /* read MC_STATUS */
7561 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7562 GRBM_STATUS__GUI_ACTIVE_MASK;
7563
7564 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7565 return 0;
7566 udelay(1);
7567 }
7568 return -ETIMEDOUT;
7569 }
7570
gfx_v10_0_soft_reset(struct amdgpu_ip_block * ip_block)7571 static int gfx_v10_0_soft_reset(struct amdgpu_ip_block *ip_block)
7572 {
7573 u32 grbm_soft_reset = 0;
7574 u32 tmp;
7575 struct amdgpu_device *adev = ip_block->adev;
7576
7577 /* GRBM_STATUS */
7578 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7579 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7580 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7581 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7582 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7583 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7584 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7585 GRBM_SOFT_RESET, SOFT_RESET_CP,
7586 1);
7587 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7588 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7589 1);
7590 }
7591
7592 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7593 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7594 GRBM_SOFT_RESET, SOFT_RESET_CP,
7595 1);
7596 }
7597
7598 /* GRBM_STATUS2 */
7599 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7600 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7601 case IP_VERSION(10, 3, 0):
7602 case IP_VERSION(10, 3, 2):
7603 case IP_VERSION(10, 3, 1):
7604 case IP_VERSION(10, 3, 4):
7605 case IP_VERSION(10, 3, 5):
7606 case IP_VERSION(10, 3, 6):
7607 case IP_VERSION(10, 3, 3):
7608 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7609 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7610 GRBM_SOFT_RESET,
7611 SOFT_RESET_RLC,
7612 1);
7613 break;
7614 default:
7615 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7616 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7617 GRBM_SOFT_RESET,
7618 SOFT_RESET_RLC,
7619 1);
7620 break;
7621 }
7622
7623 if (grbm_soft_reset) {
7624 /* stop the rlc */
7625 gfx_v10_0_rlc_stop(adev);
7626
7627 /* Disable GFX parsing/prefetching */
7628 gfx_v10_0_cp_gfx_enable(adev, false);
7629
7630 /* Disable MEC parsing/prefetching */
7631 gfx_v10_0_cp_compute_enable(adev, false);
7632
7633 if (grbm_soft_reset) {
7634 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7635 tmp |= grbm_soft_reset;
7636 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7637 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7638 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7639
7640 udelay(50);
7641
7642 tmp &= ~grbm_soft_reset;
7643 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7644 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7645 }
7646
7647 /* Wait a little for things to settle down */
7648 udelay(50);
7649 }
7650 return 0;
7651 }
7652
gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device * adev)7653 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7654 {
7655 uint64_t clock, clock_lo, clock_hi, hi_check;
7656
7657 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7658 case IP_VERSION(10, 1, 3):
7659 case IP_VERSION(10, 1, 4):
7660 preempt_disable();
7661 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
7662 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
7663 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
7664 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7665 * roughly every 42 seconds.
7666 */
7667 if (hi_check != clock_hi) {
7668 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
7669 clock_hi = hi_check;
7670 }
7671 preempt_enable();
7672 clock = clock_lo | (clock_hi << 32ULL);
7673 break;
7674 case IP_VERSION(10, 3, 1):
7675 case IP_VERSION(10, 3, 3):
7676 case IP_VERSION(10, 3, 7):
7677 preempt_disable();
7678 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7679 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7680 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7681 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7682 * roughly every 42 seconds.
7683 */
7684 if (hi_check != clock_hi) {
7685 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7686 clock_hi = hi_check;
7687 }
7688 preempt_enable();
7689 clock = clock_lo | (clock_hi << 32ULL);
7690 break;
7691 case IP_VERSION(10, 3, 6):
7692 preempt_disable();
7693 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7694 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7695 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7696 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7697 * roughly every 42 seconds.
7698 */
7699 if (hi_check != clock_hi) {
7700 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7701 clock_hi = hi_check;
7702 }
7703 preempt_enable();
7704 clock = clock_lo | (clock_hi << 32ULL);
7705 break;
7706 default:
7707 preempt_disable();
7708 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7709 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7710 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7711 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7712 * roughly every 42 seconds.
7713 */
7714 if (hi_check != clock_hi) {
7715 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7716 clock_hi = hi_check;
7717 }
7718 preempt_enable();
7719 clock = clock_lo | (clock_hi << 32ULL);
7720 break;
7721 }
7722 return clock;
7723 }
7724
gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring * ring,uint32_t vmid,uint32_t gds_base,uint32_t gds_size,uint32_t gws_base,uint32_t gws_size,uint32_t oa_base,uint32_t oa_size)7725 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7726 uint32_t vmid,
7727 uint32_t gds_base, uint32_t gds_size,
7728 uint32_t gws_base, uint32_t gws_size,
7729 uint32_t oa_base, uint32_t oa_size)
7730 {
7731 struct amdgpu_device *adev = ring->adev;
7732
7733 /* GDS Base */
7734 gfx_v10_0_write_data_to_reg(ring, 0, false,
7735 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7736 gds_base);
7737
7738 /* GDS Size */
7739 gfx_v10_0_write_data_to_reg(ring, 0, false,
7740 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7741 gds_size);
7742
7743 /* GWS */
7744 gfx_v10_0_write_data_to_reg(ring, 0, false,
7745 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7746 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7747
7748 /* OA */
7749 gfx_v10_0_write_data_to_reg(ring, 0, false,
7750 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7751 (1 << (oa_size + oa_base)) - (1 << oa_base));
7752 }
7753
gfx_v10_0_early_init(struct amdgpu_ip_block * ip_block)7754 static int gfx_v10_0_early_init(struct amdgpu_ip_block *ip_block)
7755 {
7756 struct amdgpu_device *adev = ip_block->adev;
7757
7758 adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
7759
7760 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7761 case IP_VERSION(10, 1, 10):
7762 case IP_VERSION(10, 1, 1):
7763 case IP_VERSION(10, 1, 2):
7764 case IP_VERSION(10, 1, 3):
7765 case IP_VERSION(10, 1, 4):
7766 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7767 break;
7768 case IP_VERSION(10, 3, 0):
7769 case IP_VERSION(10, 3, 2):
7770 case IP_VERSION(10, 3, 1):
7771 case IP_VERSION(10, 3, 4):
7772 case IP_VERSION(10, 3, 5):
7773 case IP_VERSION(10, 3, 6):
7774 case IP_VERSION(10, 3, 3):
7775 case IP_VERSION(10, 3, 7):
7776 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7777 break;
7778 default:
7779 break;
7780 }
7781
7782 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7783 AMDGPU_MAX_COMPUTE_RINGS);
7784
7785 gfx_v10_0_set_kiq_pm4_funcs(adev);
7786 gfx_v10_0_set_ring_funcs(adev);
7787 gfx_v10_0_set_irq_funcs(adev);
7788 gfx_v10_0_set_gds_init(adev);
7789 gfx_v10_0_set_rlc_funcs(adev);
7790 gfx_v10_0_set_mqd_funcs(adev);
7791
7792 /* init rlcg reg access ctrl */
7793 gfx_v10_0_init_rlcg_reg_access_ctrl(adev);
7794
7795 return gfx_v10_0_init_microcode(adev);
7796 }
7797
gfx_v10_0_late_init(struct amdgpu_ip_block * ip_block)7798 static int gfx_v10_0_late_init(struct amdgpu_ip_block *ip_block)
7799 {
7800 struct amdgpu_device *adev = ip_block->adev;
7801 int r;
7802
7803 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7804 if (r)
7805 return r;
7806
7807 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7808 if (r)
7809 return r;
7810
7811 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0);
7812 if (r)
7813 return r;
7814
7815 return 0;
7816 }
7817
gfx_v10_0_is_rlc_enabled(struct amdgpu_device * adev)7818 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7819 {
7820 uint32_t rlc_cntl;
7821
7822 /* if RLC is not enabled, do nothing */
7823 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7824 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7825 }
7826
gfx_v10_0_set_safe_mode(struct amdgpu_device * adev,int xcc_id)7827 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
7828 {
7829 uint32_t data;
7830 unsigned int i;
7831
7832 data = RLC_SAFE_MODE__CMD_MASK;
7833 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7834
7835 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7836 case IP_VERSION(10, 3, 0):
7837 case IP_VERSION(10, 3, 2):
7838 case IP_VERSION(10, 3, 1):
7839 case IP_VERSION(10, 3, 4):
7840 case IP_VERSION(10, 3, 5):
7841 case IP_VERSION(10, 3, 6):
7842 case IP_VERSION(10, 3, 3):
7843 case IP_VERSION(10, 3, 7):
7844 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7845
7846 /* wait for RLC_SAFE_MODE */
7847 for (i = 0; i < adev->usec_timeout; i++) {
7848 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7849 RLC_SAFE_MODE, CMD))
7850 break;
7851 udelay(1);
7852 }
7853 break;
7854 default:
7855 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7856
7857 /* wait for RLC_SAFE_MODE */
7858 for (i = 0; i < adev->usec_timeout; i++) {
7859 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7860 RLC_SAFE_MODE, CMD))
7861 break;
7862 udelay(1);
7863 }
7864 break;
7865 }
7866 }
7867
gfx_v10_0_unset_safe_mode(struct amdgpu_device * adev,int xcc_id)7868 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
7869 {
7870 uint32_t data;
7871
7872 data = RLC_SAFE_MODE__CMD_MASK;
7873 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7874 case IP_VERSION(10, 3, 0):
7875 case IP_VERSION(10, 3, 2):
7876 case IP_VERSION(10, 3, 1):
7877 case IP_VERSION(10, 3, 4):
7878 case IP_VERSION(10, 3, 5):
7879 case IP_VERSION(10, 3, 6):
7880 case IP_VERSION(10, 3, 3):
7881 case IP_VERSION(10, 3, 7):
7882 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7883 break;
7884 default:
7885 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7886 break;
7887 }
7888 }
7889
gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)7890 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7891 bool enable)
7892 {
7893 uint32_t data, def;
7894
7895 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
7896 return;
7897
7898 /* It is disabled by HW by default */
7899 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7900 /* 0 - Disable some blocks' MGCG */
7901 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7902 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7903 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7904 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7905
7906 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7907 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7908 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7909 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7910 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7911 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7912 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7913 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7914
7915 if (def != data)
7916 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7917
7918 /* MGLS is a global flag to control all MGLS in GFX */
7919 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7920 /* 2 - RLC memory Light sleep */
7921 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7922 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7923 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7924 if (def != data)
7925 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7926 }
7927 /* 3 - CP memory Light sleep */
7928 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7929 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7930 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7931 if (def != data)
7932 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7933 }
7934 }
7935 } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7936 /* 1 - MGCG_OVERRIDE */
7937 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7938 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7939 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7940 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7941 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7942 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7943 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7944 if (def != data)
7945 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7946
7947 /* 2 - disable MGLS in CP */
7948 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7949 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7950 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7951 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7952 }
7953
7954 /* 3 - disable MGLS in RLC */
7955 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7956 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7957 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7958 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7959 }
7960
7961 }
7962 }
7963
gfx_v10_0_update_3d_clock_gating(struct amdgpu_device * adev,bool enable)7964 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7965 bool enable)
7966 {
7967 uint32_t data, def;
7968
7969 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)))
7970 return;
7971
7972 /* Enable 3D CGCG/CGLS */
7973 if (enable) {
7974 /* write cmd to clear cgcg/cgls ov */
7975 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7976
7977 /* unset CGCG override */
7978 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7979 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7980
7981 /* update CGCG and CGLS override bits */
7982 if (def != data)
7983 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7984
7985 /* enable 3Dcgcg FSM(0x0000363f) */
7986 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7987 data = 0;
7988
7989 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7990 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7991 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7992
7993 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7994 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7995 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7996
7997 if (def != data)
7998 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7999
8000 /* set IDLE_POLL_COUNT(0x00900100) */
8001 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
8002 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
8003 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
8004 if (def != data)
8005 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
8006 } else {
8007 /* Disable CGCG/CGLS */
8008 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
8009
8010 /* disable cgcg, cgls should be disabled */
8011 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
8012 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
8013
8014 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
8015 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
8016
8017 /* disable cgcg and cgls in FSM */
8018 if (def != data)
8019 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
8020 }
8021 }
8022
gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device * adev,bool enable)8023 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
8024 bool enable)
8025 {
8026 uint32_t def, data;
8027
8028 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)))
8029 return;
8030
8031 if (enable) {
8032 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8033
8034 /* unset CGCG override */
8035 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8036 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
8037
8038 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8039 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
8040
8041 /* update CGCG and CGLS override bits */
8042 if (def != data)
8043 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8044
8045 /* enable cgcg FSM(0x0000363F) */
8046 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
8047 data = 0;
8048
8049 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8050 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
8051 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
8052
8053 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8054 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
8055 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
8056
8057 if (def != data)
8058 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
8059
8060 /* set IDLE_POLL_COUNT(0x00900100) */
8061 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
8062 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
8063 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
8064 if (def != data)
8065 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
8066 } else {
8067 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
8068
8069 /* reset CGCG/CGLS bits */
8070 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8071 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
8072
8073 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8074 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
8075
8076 /* disable cgcg and cgls in FSM */
8077 if (def != data)
8078 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
8079 }
8080 }
8081
gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device * adev,bool enable)8082 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
8083 bool enable)
8084 {
8085 uint32_t def, data;
8086
8087 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
8088 return;
8089
8090 if (enable) {
8091 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8092 /* unset FGCG override */
8093 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
8094 /* update FGCG override bits */
8095 if (def != data)
8096 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8097
8098 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
8099 /* unset RLC SRAM CLK GATER override */
8100 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
8101 /* update RLC SRAM CLK GATER override bits */
8102 if (def != data)
8103 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
8104 } else {
8105 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8106 /* reset FGCG bits */
8107 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
8108 /* disable FGCG*/
8109 if (def != data)
8110 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8111
8112 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
8113 /* reset RLC SRAM CLK GATER bits */
8114 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
8115 /* disable RLC SRAM CLK*/
8116 if (def != data)
8117 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
8118 }
8119 }
8120
gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device * adev)8121 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev)
8122 {
8123 uint32_t reg_data = 0;
8124 uint32_t reg_idx = 0;
8125 uint32_t i;
8126
8127 const uint32_t tcp_ctrl_regs[] = {
8128 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
8129 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
8130 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8131 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8132 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8133 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8134 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8135 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8136 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8137 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8138 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG,
8139 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG,
8140 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8141 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8142 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8143 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8144 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8145 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8146 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8147 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8148 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8149 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8150 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG,
8151 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG
8152 };
8153
8154 const uint32_t tcp_ctrl_regs_nv12[] = {
8155 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
8156 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
8157 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8158 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8159 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8160 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8161 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8162 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8163 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8164 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8165 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8166 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8167 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8168 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8169 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8170 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8171 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8172 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8173 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8174 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8175 };
8176
8177 const uint32_t sm_ctlr_regs[] = {
8178 mmCGTS_SA0_QUAD0_SM_CTRL_REG,
8179 mmCGTS_SA0_QUAD1_SM_CTRL_REG,
8180 mmCGTS_SA1_QUAD0_SM_CTRL_REG,
8181 mmCGTS_SA1_QUAD1_SM_CTRL_REG
8182 };
8183
8184 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) {
8185 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) {
8186 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8187 tcp_ctrl_regs_nv12[i];
8188 reg_data = RREG32(reg_idx);
8189 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8190 WREG32(reg_idx, reg_data);
8191 }
8192 } else {
8193 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) {
8194 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8195 tcp_ctrl_regs[i];
8196 reg_data = RREG32(reg_idx);
8197 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8198 WREG32(reg_idx, reg_data);
8199 }
8200 }
8201
8202 for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) {
8203 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] +
8204 sm_ctlr_regs[i];
8205 reg_data = RREG32(reg_idx);
8206 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK;
8207 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT;
8208 WREG32(reg_idx, reg_data);
8209 }
8210 }
8211
gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device * adev,bool enable)8212 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
8213 bool enable)
8214 {
8215 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
8216
8217 if (enable) {
8218 /* enable FGCG firstly*/
8219 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8220 /* CGCG/CGLS should be enabled after MGCG/MGLS
8221 * === MGCG + MGLS ===
8222 */
8223 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8224 /* === CGCG /CGLS for GFX 3D Only === */
8225 gfx_v10_0_update_3d_clock_gating(adev, enable);
8226 /* === CGCG + CGLS === */
8227 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8228
8229 if ((amdgpu_ip_version(adev, GC_HWIP, 0) ==
8230 IP_VERSION(10, 1, 10)) ||
8231 (amdgpu_ip_version(adev, GC_HWIP, 0) ==
8232 IP_VERSION(10, 1, 1)) ||
8233 (amdgpu_ip_version(adev, GC_HWIP, 0) ==
8234 IP_VERSION(10, 1, 2)))
8235 gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev);
8236 } else {
8237 /* CGCG/CGLS should be disabled before MGCG/MGLS
8238 * === CGCG + CGLS ===
8239 */
8240 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8241 /* === CGCG /CGLS for GFX 3D Only === */
8242 gfx_v10_0_update_3d_clock_gating(adev, enable);
8243 /* === MGCG + MGLS === */
8244 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8245 /* disable fgcg at last*/
8246 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8247 }
8248
8249 if (adev->cg_flags &
8250 (AMD_CG_SUPPORT_GFX_MGCG |
8251 AMD_CG_SUPPORT_GFX_CGLS |
8252 AMD_CG_SUPPORT_GFX_CGCG |
8253 AMD_CG_SUPPORT_GFX_3D_CGCG |
8254 AMD_CG_SUPPORT_GFX_3D_CGLS))
8255 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
8256
8257 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
8258
8259 return 0;
8260 }
8261
gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device * adev,unsigned int vmid)8262 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
8263 unsigned int vmid)
8264 {
8265 u32 reg, pre_data, data;
8266
8267 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
8268 /* not for *_SOC15 */
8269 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev))
8270 pre_data = RREG32_NO_KIQ(reg);
8271 else
8272 pre_data = RREG32(reg);
8273
8274 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK);
8275 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
8276
8277 if (pre_data != data) {
8278 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) {
8279 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
8280 } else
8281 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
8282 }
8283 }
8284
gfx_v10_0_update_spm_vmid(struct amdgpu_device * adev,struct amdgpu_ring * ring,unsigned int vmid)8285 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid)
8286 {
8287 amdgpu_gfx_off_ctrl(adev, false);
8288
8289 gfx_v10_0_update_spm_vmid_internal(adev, vmid);
8290
8291 amdgpu_gfx_off_ctrl(adev, true);
8292 }
8293
gfx_v10_0_check_rlcg_range(struct amdgpu_device * adev,uint32_t offset,struct soc15_reg_rlcg * entries,int arr_size)8294 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
8295 uint32_t offset,
8296 struct soc15_reg_rlcg *entries, int arr_size)
8297 {
8298 int i;
8299 uint32_t reg;
8300
8301 if (!entries)
8302 return false;
8303
8304 for (i = 0; i < arr_size; i++) {
8305 const struct soc15_reg_rlcg *entry;
8306
8307 entry = &entries[i];
8308 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
8309 if (offset == reg)
8310 return true;
8311 }
8312
8313 return false;
8314 }
8315
gfx_v10_0_is_rlcg_access_range(struct amdgpu_device * adev,u32 offset)8316 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
8317 {
8318 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
8319 }
8320
gfx_v10_cntl_power_gating(struct amdgpu_device * adev,bool enable)8321 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
8322 {
8323 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
8324
8325 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
8326 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8327 else
8328 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8329
8330 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
8331
8332 /*
8333 * CGPG enablement required and the register to program the hysteresis value
8334 * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
8335 * in refclk count. Note that RLC FW is modified to take 16 bits from
8336 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
8337 *
8338 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part)
8339 * of CGPG enablement starting point.
8340 * Power/performance team will optimize it and might give a new value later.
8341 */
8342 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
8343 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
8344 case IP_VERSION(10, 3, 1):
8345 case IP_VERSION(10, 3, 3):
8346 case IP_VERSION(10, 3, 6):
8347 case IP_VERSION(10, 3, 7):
8348 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
8349 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
8350 break;
8351 default:
8352 break;
8353 }
8354 }
8355 }
8356
gfx_v10_cntl_pg(struct amdgpu_device * adev,bool enable)8357 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
8358 {
8359 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
8360
8361 gfx_v10_cntl_power_gating(adev, enable);
8362
8363 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
8364 }
8365
8366 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
8367 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8368 .set_safe_mode = gfx_v10_0_set_safe_mode,
8369 .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8370 .init = gfx_v10_0_rlc_init,
8371 .get_csb_size = gfx_v10_0_get_csb_size,
8372 .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8373 .resume = gfx_v10_0_rlc_resume,
8374 .stop = gfx_v10_0_rlc_stop,
8375 .reset = gfx_v10_0_rlc_reset,
8376 .start = gfx_v10_0_rlc_start,
8377 .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8378 };
8379
8380 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
8381 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8382 .set_safe_mode = gfx_v10_0_set_safe_mode,
8383 .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8384 .init = gfx_v10_0_rlc_init,
8385 .get_csb_size = gfx_v10_0_get_csb_size,
8386 .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8387 .resume = gfx_v10_0_rlc_resume,
8388 .stop = gfx_v10_0_rlc_stop,
8389 .reset = gfx_v10_0_rlc_reset,
8390 .start = gfx_v10_0_rlc_start,
8391 .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8392 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
8393 };
8394
gfx_v10_0_set_powergating_state(struct amdgpu_ip_block * ip_block,enum amd_powergating_state state)8395 static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
8396 enum amd_powergating_state state)
8397 {
8398 struct amdgpu_device *adev = ip_block->adev;
8399 bool enable = (state == AMD_PG_STATE_GATE);
8400
8401 if (amdgpu_sriov_vf(adev))
8402 return 0;
8403
8404 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
8405 case IP_VERSION(10, 1, 10):
8406 case IP_VERSION(10, 1, 1):
8407 case IP_VERSION(10, 1, 2):
8408 case IP_VERSION(10, 3, 0):
8409 case IP_VERSION(10, 3, 2):
8410 case IP_VERSION(10, 3, 4):
8411 case IP_VERSION(10, 3, 5):
8412 amdgpu_gfx_off_ctrl(adev, enable);
8413 break;
8414 case IP_VERSION(10, 3, 1):
8415 case IP_VERSION(10, 3, 3):
8416 case IP_VERSION(10, 3, 6):
8417 case IP_VERSION(10, 3, 7):
8418 if (!enable)
8419 amdgpu_gfx_off_ctrl(adev, false);
8420
8421 gfx_v10_cntl_pg(adev, enable);
8422
8423 if (enable)
8424 amdgpu_gfx_off_ctrl(adev, true);
8425
8426 break;
8427 default:
8428 break;
8429 }
8430 return 0;
8431 }
8432
gfx_v10_0_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)8433 static int gfx_v10_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
8434 enum amd_clockgating_state state)
8435 {
8436 struct amdgpu_device *adev = ip_block->adev;
8437
8438 if (amdgpu_sriov_vf(adev))
8439 return 0;
8440
8441 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
8442 case IP_VERSION(10, 1, 10):
8443 case IP_VERSION(10, 1, 1):
8444 case IP_VERSION(10, 1, 2):
8445 case IP_VERSION(10, 3, 0):
8446 case IP_VERSION(10, 3, 2):
8447 case IP_VERSION(10, 3, 1):
8448 case IP_VERSION(10, 3, 4):
8449 case IP_VERSION(10, 3, 5):
8450 case IP_VERSION(10, 3, 6):
8451 case IP_VERSION(10, 3, 3):
8452 case IP_VERSION(10, 3, 7):
8453 gfx_v10_0_update_gfx_clock_gating(adev,
8454 state == AMD_CG_STATE_GATE);
8455 break;
8456 default:
8457 break;
8458 }
8459 return 0;
8460 }
8461
gfx_v10_0_get_clockgating_state(struct amdgpu_ip_block * ip_block,u64 * flags)8462 static void gfx_v10_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)
8463 {
8464 struct amdgpu_device *adev = ip_block->adev;
8465 int data;
8466
8467 /* AMD_CG_SUPPORT_GFX_FGCG */
8468 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8469 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
8470 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
8471
8472 /* AMD_CG_SUPPORT_GFX_MGCG */
8473 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8474 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
8475 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
8476
8477 /* AMD_CG_SUPPORT_GFX_CGCG */
8478 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
8479 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
8480 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
8481
8482 /* AMD_CG_SUPPORT_GFX_CGLS */
8483 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
8484 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
8485
8486 /* AMD_CG_SUPPORT_GFX_RLC_LS */
8487 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
8488 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
8489 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
8490
8491 /* AMD_CG_SUPPORT_GFX_CP_LS */
8492 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
8493 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
8494 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
8495
8496 /* AMD_CG_SUPPORT_GFX_3D_CGCG */
8497 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
8498 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
8499 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
8500
8501 /* AMD_CG_SUPPORT_GFX_3D_CGLS */
8502 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
8503 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
8504 }
8505
gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring * ring)8506 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
8507 {
8508 /* gfx10 is 32bit rptr*/
8509 return *(uint32_t *)ring->rptr_cpu_addr;
8510 }
8511
gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring * ring)8512 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
8513 {
8514 struct amdgpu_device *adev = ring->adev;
8515 u64 wptr;
8516
8517 /* XXX check if swapping is necessary on BE */
8518 if (ring->use_doorbell) {
8519 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8520 } else {
8521 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
8522 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
8523 }
8524
8525 return wptr;
8526 }
8527
gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring * ring)8528 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
8529 {
8530 struct amdgpu_device *adev = ring->adev;
8531
8532 if (ring->use_doorbell) {
8533 /* XXX check if swapping is necessary on BE */
8534 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
8535 ring->wptr);
8536 WDOORBELL64(ring->doorbell_index, ring->wptr);
8537 } else {
8538 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR,
8539 lower_32_bits(ring->wptr));
8540 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI,
8541 upper_32_bits(ring->wptr));
8542 }
8543 }
8544
gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring * ring)8545 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8546 {
8547 /* gfx10 hardware is 32bit rptr */
8548 return *(uint32_t *)ring->rptr_cpu_addr;
8549 }
8550
gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring * ring)8551 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8552 {
8553 u64 wptr;
8554
8555 /* XXX check if swapping is necessary on BE */
8556 if (ring->use_doorbell)
8557 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8558 else
8559 BUG();
8560 return wptr;
8561 }
8562
gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring * ring)8563 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8564 {
8565 struct amdgpu_device *adev = ring->adev;
8566
8567 if (ring->use_doorbell) {
8568 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
8569 ring->wptr);
8570 WDOORBELL64(ring->doorbell_index, ring->wptr);
8571 } else {
8572 BUG(); /* only DOORBELL method supported on gfx10 now */
8573 }
8574 }
8575
gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring * ring)8576 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8577 {
8578 struct amdgpu_device *adev = ring->adev;
8579 u32 ref_and_mask, reg_mem_engine;
8580 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8581
8582 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8583 switch (ring->me) {
8584 case 1:
8585 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8586 break;
8587 case 2:
8588 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8589 break;
8590 default:
8591 return;
8592 }
8593 reg_mem_engine = 0;
8594 } else {
8595 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe;
8596 reg_mem_engine = 1; /* pfp */
8597 }
8598
8599 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8600 adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8601 adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8602 ref_and_mask, ref_and_mask, 0x20);
8603 }
8604
gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)8605 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8606 struct amdgpu_job *job,
8607 struct amdgpu_ib *ib,
8608 uint32_t flags)
8609 {
8610 unsigned int vmid = AMDGPU_JOB_GET_VMID(job);
8611 u32 header, control = 0;
8612
8613 if (ib->flags & AMDGPU_IB_FLAG_CE)
8614 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8615 else
8616 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8617
8618 control |= ib->length_dw | (vmid << 24);
8619
8620 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8621 control |= INDIRECT_BUFFER_PRE_ENB(1);
8622
8623 if (flags & AMDGPU_IB_PREEMPTED)
8624 control |= INDIRECT_BUFFER_PRE_RESUME(1);
8625
8626 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8627 gfx_v10_0_ring_emit_de_meta(ring,
8628 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8629 }
8630
8631 amdgpu_ring_write(ring, header);
8632 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8633 amdgpu_ring_write(ring,
8634 #ifdef __BIG_ENDIAN
8635 (2 << 0) |
8636 #endif
8637 lower_32_bits(ib->gpu_addr));
8638 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8639 amdgpu_ring_write(ring, control);
8640 }
8641
gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)8642 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8643 struct amdgpu_job *job,
8644 struct amdgpu_ib *ib,
8645 uint32_t flags)
8646 {
8647 unsigned int vmid = AMDGPU_JOB_GET_VMID(job);
8648 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8649
8650 /* Currently, there is a high possibility to get wave ID mismatch
8651 * between ME and GDS, leading to a hw deadlock, because ME generates
8652 * different wave IDs than the GDS expects. This situation happens
8653 * randomly when at least 5 compute pipes use GDS ordered append.
8654 * The wave IDs generated by ME are also wrong after suspend/resume.
8655 * Those are probably bugs somewhere else in the kernel driver.
8656 *
8657 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8658 * GDS to 0 for this ring (me/pipe).
8659 */
8660 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8661 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8662 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8663 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8664 }
8665
8666 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8667 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8668 amdgpu_ring_write(ring,
8669 #ifdef __BIG_ENDIAN
8670 (2 << 0) |
8671 #endif
8672 lower_32_bits(ib->gpu_addr));
8673 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8674 amdgpu_ring_write(ring, control);
8675 }
8676
gfx_v10_0_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned int flags)8677 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8678 u64 seq, unsigned int flags)
8679 {
8680 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8681 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8682
8683 /* RELEASE_MEM - flush caches, send int */
8684 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8685 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8686 PACKET3_RELEASE_MEM_GCR_GL2_WB |
8687 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8688 PACKET3_RELEASE_MEM_GCR_GLM_WB |
8689 PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8690 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8691 PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8692 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8693 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8694
8695 /*
8696 * the address should be Qword aligned if 64bit write, Dword
8697 * aligned if only send 32bit data low (discard data high)
8698 */
8699 if (write64bit)
8700 BUG_ON(addr & 0x7);
8701 else
8702 BUG_ON(addr & 0x3);
8703 amdgpu_ring_write(ring, lower_32_bits(addr));
8704 amdgpu_ring_write(ring, upper_32_bits(addr));
8705 amdgpu_ring_write(ring, lower_32_bits(seq));
8706 amdgpu_ring_write(ring, upper_32_bits(seq));
8707 amdgpu_ring_write(ring, 0);
8708 }
8709
gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring * ring)8710 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8711 {
8712 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8713 uint32_t seq = ring->fence_drv.sync_seq;
8714 uint64_t addr = ring->fence_drv.gpu_addr;
8715
8716 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8717 upper_32_bits(addr), seq, 0xffffffff, 4);
8718 }
8719
gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring * ring,uint16_t pasid,uint32_t flush_type,bool all_hub,uint8_t dst_sel)8720 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
8721 uint16_t pasid, uint32_t flush_type,
8722 bool all_hub, uint8_t dst_sel)
8723 {
8724 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
8725 amdgpu_ring_write(ring,
8726 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |
8727 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
8728 PACKET3_INVALIDATE_TLBS_PASID(pasid) |
8729 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
8730 }
8731
gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned int vmid,uint64_t pd_addr)8732 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8733 unsigned int vmid, uint64_t pd_addr)
8734 {
8735 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8736
8737 /* compute doesn't have PFP */
8738 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8739 /* sync PFP to ME, otherwise we might get invalid PFP reads */
8740 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8741 amdgpu_ring_write(ring, 0x0);
8742 }
8743 }
8744
gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned int flags)8745 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8746 u64 seq, unsigned int flags)
8747 {
8748 struct amdgpu_device *adev = ring->adev;
8749
8750 /* we only allocate 32bit for each seq wb address */
8751 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8752
8753 /* write fence seq to the "addr" */
8754 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8755 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8756 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8757 amdgpu_ring_write(ring, lower_32_bits(addr));
8758 amdgpu_ring_write(ring, upper_32_bits(addr));
8759 amdgpu_ring_write(ring, lower_32_bits(seq));
8760
8761 if (flags & AMDGPU_FENCE_FLAG_INT) {
8762 /* set register to trigger INT */
8763 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8764 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8765 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8766 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8767 amdgpu_ring_write(ring, 0);
8768 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8769 }
8770 }
8771
gfx_v10_0_ring_emit_sb(struct amdgpu_ring * ring)8772 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8773 {
8774 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8775 amdgpu_ring_write(ring, 0);
8776 }
8777
gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring * ring,uint32_t flags)8778 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8779 uint32_t flags)
8780 {
8781 uint32_t dw2 = 0;
8782
8783 if (ring->adev->gfx.mcbp)
8784 gfx_v10_0_ring_emit_ce_meta(ring,
8785 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8786
8787 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8788 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8789 /* set load_global_config & load_global_uconfig */
8790 dw2 |= 0x8001;
8791 /* set load_cs_sh_regs */
8792 dw2 |= 0x01000000;
8793 /* set load_per_context_state & load_gfx_sh_regs for GFX */
8794 dw2 |= 0x10002;
8795
8796 /* set load_ce_ram if preamble presented */
8797 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8798 dw2 |= 0x10000000;
8799 } else {
8800 /* still load_ce_ram if this is the first time preamble presented
8801 * although there is no context switch happens.
8802 */
8803 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8804 dw2 |= 0x10000000;
8805 }
8806
8807 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8808 amdgpu_ring_write(ring, dw2);
8809 amdgpu_ring_write(ring, 0);
8810 }
8811
gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring * ring,uint64_t addr)8812 static unsigned int gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring,
8813 uint64_t addr)
8814 {
8815 unsigned int ret;
8816
8817 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8818 amdgpu_ring_write(ring, lower_32_bits(addr));
8819 amdgpu_ring_write(ring, upper_32_bits(addr));
8820 /* discard following DWs if *cond_exec_gpu_addr==0 */
8821 amdgpu_ring_write(ring, 0);
8822 ret = ring->wptr & ring->buf_mask;
8823 /* patch dummy value later */
8824 amdgpu_ring_write(ring, 0);
8825
8826 return ret;
8827 }
8828
gfx_v10_0_ring_preempt_ib(struct amdgpu_ring * ring)8829 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8830 {
8831 int i, r = 0;
8832 struct amdgpu_device *adev = ring->adev;
8833 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
8834 struct amdgpu_ring *kiq_ring = &kiq->ring;
8835 unsigned long flags;
8836
8837 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8838 return -EINVAL;
8839
8840 spin_lock_irqsave(&kiq->ring_lock, flags);
8841
8842 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8843 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8844 return -ENOMEM;
8845 }
8846
8847 /* assert preemption condition */
8848 amdgpu_ring_set_preempt_cond_exec(ring, false);
8849
8850 /* assert IB preemption, emit the trailing fence */
8851 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8852 ring->trail_fence_gpu_addr,
8853 ++ring->trail_seq);
8854 amdgpu_ring_commit(kiq_ring);
8855
8856 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8857
8858 /* poll the trailing fence */
8859 for (i = 0; i < adev->usec_timeout; i++) {
8860 if (ring->trail_seq ==
8861 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8862 break;
8863 udelay(1);
8864 }
8865
8866 if (i >= adev->usec_timeout) {
8867 r = -EINVAL;
8868 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8869 }
8870
8871 /* deassert preemption condition */
8872 amdgpu_ring_set_preempt_cond_exec(ring, true);
8873 return r;
8874 }
8875
gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring * ring,bool resume)8876 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8877 {
8878 struct amdgpu_device *adev = ring->adev;
8879 struct v10_ce_ib_state ce_payload = {0};
8880 uint64_t offset, ce_payload_gpu_addr;
8881 void *ce_payload_cpu_addr;
8882 int cnt;
8883
8884 cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8885
8886 offset = offsetof(struct v10_gfx_meta_data, ce_payload);
8887 ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
8888 ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
8889
8890 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8891 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8892 WRITE_DATA_DST_SEL(8) |
8893 WR_CONFIRM) |
8894 WRITE_DATA_CACHE_POLICY(0));
8895 amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr));
8896 amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr));
8897
8898 if (resume)
8899 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr,
8900 sizeof(ce_payload) >> 2);
8901 else
8902 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8903 sizeof(ce_payload) >> 2);
8904 }
8905
gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring * ring,bool resume)8906 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8907 {
8908 struct amdgpu_device *adev = ring->adev;
8909 struct v10_de_ib_state de_payload = {0};
8910 uint64_t offset, gds_addr, de_payload_gpu_addr;
8911 void *de_payload_cpu_addr;
8912 int cnt;
8913
8914 offset = offsetof(struct v10_gfx_meta_data, de_payload);
8915 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
8916 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
8917
8918 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) +
8919 AMDGPU_CSA_SIZE - adev->gds.gds_size,
8920 PAGE_SIZE);
8921
8922 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8923 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8924
8925 cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8926 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8927 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8928 WRITE_DATA_DST_SEL(8) |
8929 WR_CONFIRM) |
8930 WRITE_DATA_CACHE_POLICY(0));
8931 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));
8932 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));
8933
8934 if (resume)
8935 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr,
8936 sizeof(de_payload) >> 2);
8937 else
8938 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8939 sizeof(de_payload) >> 2);
8940 }
8941
gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring * ring,bool start,bool secure)8942 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8943 bool secure)
8944 {
8945 uint32_t v = secure ? FRAME_TMZ : 0;
8946
8947 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8948 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8949 }
8950
gfx_v10_0_ring_emit_rreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t reg_val_offs)8951 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8952 uint32_t reg_val_offs)
8953 {
8954 struct amdgpu_device *adev = ring->adev;
8955
8956 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8957 amdgpu_ring_write(ring, 0 | /* src: register*/
8958 (5 << 8) | /* dst: memory */
8959 (1 << 20)); /* write confirm */
8960 amdgpu_ring_write(ring, reg);
8961 amdgpu_ring_write(ring, 0);
8962 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8963 reg_val_offs * 4));
8964 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8965 reg_val_offs * 4));
8966 }
8967
gfx_v10_0_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)8968 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8969 uint32_t val)
8970 {
8971 uint32_t cmd = 0;
8972
8973 switch (ring->funcs->type) {
8974 case AMDGPU_RING_TYPE_GFX:
8975 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8976 break;
8977 case AMDGPU_RING_TYPE_KIQ:
8978 cmd = (1 << 16); /* no inc addr */
8979 break;
8980 default:
8981 cmd = WR_CONFIRM;
8982 break;
8983 }
8984 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8985 amdgpu_ring_write(ring, cmd);
8986 amdgpu_ring_write(ring, reg);
8987 amdgpu_ring_write(ring, 0);
8988 amdgpu_ring_write(ring, val);
8989 }
8990
gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)8991 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8992 uint32_t val, uint32_t mask)
8993 {
8994 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8995 }
8996
gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring * ring,uint32_t reg0,uint32_t reg1,uint32_t ref,uint32_t mask)8997 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8998 uint32_t reg0, uint32_t reg1,
8999 uint32_t ref, uint32_t mask)
9000 {
9001 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
9002 struct amdgpu_device *adev = ring->adev;
9003 bool fw_version_ok = false;
9004
9005 fw_version_ok = adev->gfx.cp_fw_write_wait;
9006
9007 if (fw_version_ok)
9008 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
9009 ref, mask, 0x20);
9010 else
9011 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
9012 ref, mask);
9013 }
9014
gfx_v10_0_ring_soft_recovery(struct amdgpu_ring * ring,unsigned int vmid)9015 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
9016 unsigned int vmid)
9017 {
9018 struct amdgpu_device *adev = ring->adev;
9019 uint32_t value = 0;
9020
9021 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
9022 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
9023 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
9024 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
9025 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
9026 WREG32_SOC15(GC, 0, mmSQ_CMD, value);
9027 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
9028 }
9029
9030 static void
gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device * adev,uint32_t me,uint32_t pipe,enum amdgpu_interrupt_state state)9031 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
9032 uint32_t me, uint32_t pipe,
9033 enum amdgpu_interrupt_state state)
9034 {
9035 uint32_t cp_int_cntl, cp_int_cntl_reg;
9036
9037 if (!me) {
9038 switch (pipe) {
9039 case 0:
9040 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
9041 break;
9042 case 1:
9043 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
9044 break;
9045 default:
9046 DRM_DEBUG("invalid pipe %d\n", pipe);
9047 return;
9048 }
9049 } else {
9050 DRM_DEBUG("invalid me %d\n", me);
9051 return;
9052 }
9053
9054 switch (state) {
9055 case AMDGPU_IRQ_STATE_DISABLE:
9056 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9057 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9058 TIME_STAMP_INT_ENABLE, 0);
9059 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9060 break;
9061 case AMDGPU_IRQ_STATE_ENABLE:
9062 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9063 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9064 TIME_STAMP_INT_ENABLE, 1);
9065 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9066 break;
9067 default:
9068 break;
9069 }
9070 }
9071
gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device * adev,int me,int pipe,enum amdgpu_interrupt_state state)9072 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
9073 int me, int pipe,
9074 enum amdgpu_interrupt_state state)
9075 {
9076 u32 mec_int_cntl, mec_int_cntl_reg;
9077
9078 /*
9079 * amdgpu controls only the first MEC. That's why this function only
9080 * handles the setting of interrupts for this specific MEC. All other
9081 * pipes' interrupts are set by amdkfd.
9082 */
9083
9084 if (me == 1) {
9085 switch (pipe) {
9086 case 0:
9087 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9088 break;
9089 case 1:
9090 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
9091 break;
9092 case 2:
9093 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
9094 break;
9095 case 3:
9096 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
9097 break;
9098 default:
9099 DRM_DEBUG("invalid pipe %d\n", pipe);
9100 return;
9101 }
9102 } else {
9103 DRM_DEBUG("invalid me %d\n", me);
9104 return;
9105 }
9106
9107 switch (state) {
9108 case AMDGPU_IRQ_STATE_DISABLE:
9109 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
9110 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9111 TIME_STAMP_INT_ENABLE, 0);
9112 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
9113 break;
9114 case AMDGPU_IRQ_STATE_ENABLE:
9115 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
9116 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9117 TIME_STAMP_INT_ENABLE, 1);
9118 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
9119 break;
9120 default:
9121 break;
9122 }
9123 }
9124
gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type,enum amdgpu_interrupt_state state)9125 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
9126 struct amdgpu_irq_src *src,
9127 unsigned int type,
9128 enum amdgpu_interrupt_state state)
9129 {
9130 switch (type) {
9131 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
9132 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
9133 break;
9134 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
9135 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
9136 break;
9137 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
9138 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
9139 break;
9140 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
9141 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
9142 break;
9143 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
9144 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
9145 break;
9146 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
9147 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
9148 break;
9149 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
9150 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
9151 break;
9152 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
9153 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
9154 break;
9155 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
9156 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
9157 break;
9158 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
9159 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
9160 break;
9161 default:
9162 break;
9163 }
9164 return 0;
9165 }
9166
gfx_v10_0_eop_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)9167 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
9168 struct amdgpu_irq_src *source,
9169 struct amdgpu_iv_entry *entry)
9170 {
9171 int i;
9172 u8 me_id, pipe_id, queue_id;
9173 struct amdgpu_ring *ring;
9174
9175 DRM_DEBUG("IH: CP EOP\n");
9176
9177 me_id = (entry->ring_id & 0x0c) >> 2;
9178 pipe_id = (entry->ring_id & 0x03) >> 0;
9179 queue_id = (entry->ring_id & 0x70) >> 4;
9180
9181 switch (me_id) {
9182 case 0:
9183 if (pipe_id == 0)
9184 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
9185 else
9186 amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
9187 break;
9188 case 1:
9189 case 2:
9190 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9191 ring = &adev->gfx.compute_ring[i];
9192 /* Per-queue interrupt is supported for MEC starting from VI.
9193 * The interrupt can only be enabled/disabled per pipe instead
9194 * of per queue.
9195 */
9196 if ((ring->me == me_id) &&
9197 (ring->pipe == pipe_id) &&
9198 (ring->queue == queue_id))
9199 amdgpu_fence_process(ring);
9200 }
9201 break;
9202 }
9203
9204 return 0;
9205 }
9206
gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int type,enum amdgpu_interrupt_state state)9207 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
9208 struct amdgpu_irq_src *source,
9209 unsigned int type,
9210 enum amdgpu_interrupt_state state)
9211 {
9212 u32 cp_int_cntl_reg, cp_int_cntl;
9213 int i, j;
9214
9215 switch (state) {
9216 case AMDGPU_IRQ_STATE_DISABLE:
9217 case AMDGPU_IRQ_STATE_ENABLE:
9218 for (i = 0; i < adev->gfx.me.num_me; i++) {
9219 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
9220 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);
9221
9222 if (cp_int_cntl_reg) {
9223 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9224 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9225 PRIV_REG_INT_ENABLE,
9226 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9227 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9228 }
9229 }
9230 }
9231 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
9232 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
9233 /* MECs start at 1 */
9234 cp_int_cntl_reg = gfx_v10_0_get_cpc_int_cntl(adev, i + 1, j);
9235
9236 if (cp_int_cntl_reg) {
9237 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9238 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9239 PRIV_REG_INT_ENABLE,
9240 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9241 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9242 }
9243 }
9244 }
9245 break;
9246 default:
9247 break;
9248 }
9249
9250 return 0;
9251 }
9252
gfx_v10_0_set_bad_op_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)9253 static int gfx_v10_0_set_bad_op_fault_state(struct amdgpu_device *adev,
9254 struct amdgpu_irq_src *source,
9255 unsigned type,
9256 enum amdgpu_interrupt_state state)
9257 {
9258 u32 cp_int_cntl_reg, cp_int_cntl;
9259 int i, j;
9260
9261 switch (state) {
9262 case AMDGPU_IRQ_STATE_DISABLE:
9263 case AMDGPU_IRQ_STATE_ENABLE:
9264 for (i = 0; i < adev->gfx.me.num_me; i++) {
9265 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
9266 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);
9267
9268 if (cp_int_cntl_reg) {
9269 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9270 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9271 OPCODE_ERROR_INT_ENABLE,
9272 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9273 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9274 }
9275 }
9276 }
9277 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
9278 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
9279 /* MECs start at 1 */
9280 cp_int_cntl_reg = gfx_v10_0_get_cpc_int_cntl(adev, i + 1, j);
9281
9282 if (cp_int_cntl_reg) {
9283 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9284 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9285 OPCODE_ERROR_INT_ENABLE,
9286 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9287 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9288 }
9289 }
9290 }
9291 break;
9292 default:
9293 break;
9294 }
9295 return 0;
9296 }
9297
gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int type,enum amdgpu_interrupt_state state)9298 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
9299 struct amdgpu_irq_src *source,
9300 unsigned int type,
9301 enum amdgpu_interrupt_state state)
9302 {
9303 u32 cp_int_cntl_reg, cp_int_cntl;
9304 int i, j;
9305
9306 switch (state) {
9307 case AMDGPU_IRQ_STATE_DISABLE:
9308 case AMDGPU_IRQ_STATE_ENABLE:
9309 for (i = 0; i < adev->gfx.me.num_me; i++) {
9310 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
9311 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);
9312
9313 if (cp_int_cntl_reg) {
9314 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9315 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9316 PRIV_INSTR_INT_ENABLE,
9317 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9318 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9319 }
9320 }
9321 }
9322 break;
9323 default:
9324 break;
9325 }
9326
9327 return 0;
9328 }
9329
gfx_v10_0_handle_priv_fault(struct amdgpu_device * adev,struct amdgpu_iv_entry * entry)9330 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
9331 struct amdgpu_iv_entry *entry)
9332 {
9333 u8 me_id, pipe_id, queue_id;
9334 struct amdgpu_ring *ring;
9335 int i;
9336
9337 me_id = (entry->ring_id & 0x0c) >> 2;
9338 pipe_id = (entry->ring_id & 0x03) >> 0;
9339 queue_id = (entry->ring_id & 0x70) >> 4;
9340
9341 switch (me_id) {
9342 case 0:
9343 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
9344 ring = &adev->gfx.gfx_ring[i];
9345 if (ring->me == me_id && ring->pipe == pipe_id &&
9346 ring->queue == queue_id)
9347 drm_sched_fault(&ring->sched);
9348 }
9349 break;
9350 case 1:
9351 case 2:
9352 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9353 ring = &adev->gfx.compute_ring[i];
9354 if (ring->me == me_id && ring->pipe == pipe_id &&
9355 ring->queue == queue_id)
9356 drm_sched_fault(&ring->sched);
9357 }
9358 break;
9359 default:
9360 BUG();
9361 }
9362 }
9363
gfx_v10_0_priv_reg_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)9364 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
9365 struct amdgpu_irq_src *source,
9366 struct amdgpu_iv_entry *entry)
9367 {
9368 DRM_ERROR("Illegal register access in command stream\n");
9369 gfx_v10_0_handle_priv_fault(adev, entry);
9370 return 0;
9371 }
9372
gfx_v10_0_bad_op_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)9373 static int gfx_v10_0_bad_op_irq(struct amdgpu_device *adev,
9374 struct amdgpu_irq_src *source,
9375 struct amdgpu_iv_entry *entry)
9376 {
9377 DRM_ERROR("Illegal opcode in command stream \n");
9378 gfx_v10_0_handle_priv_fault(adev, entry);
9379 return 0;
9380 }
9381
gfx_v10_0_priv_inst_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)9382 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
9383 struct amdgpu_irq_src *source,
9384 struct amdgpu_iv_entry *entry)
9385 {
9386 DRM_ERROR("Illegal instruction in command stream\n");
9387 gfx_v10_0_handle_priv_fault(adev, entry);
9388 return 0;
9389 }
9390
gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type,enum amdgpu_interrupt_state state)9391 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
9392 struct amdgpu_irq_src *src,
9393 unsigned int type,
9394 enum amdgpu_interrupt_state state)
9395 {
9396 uint32_t tmp, target;
9397 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
9398
9399 if (ring->me == 1)
9400 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9401 else
9402 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
9403 target += ring->pipe;
9404
9405 switch (type) {
9406 case AMDGPU_CP_KIQ_IRQ_DRIVER0:
9407 if (state == AMDGPU_IRQ_STATE_DISABLE) {
9408 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9409 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9410 GENERIC2_INT_ENABLE, 0);
9411 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9412
9413 tmp = RREG32_SOC15_IP(GC, target);
9414 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9415 GENERIC2_INT_ENABLE, 0);
9416 WREG32_SOC15_IP(GC, target, tmp);
9417 } else {
9418 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9419 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9420 GENERIC2_INT_ENABLE, 1);
9421 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9422
9423 tmp = RREG32_SOC15_IP(GC, target);
9424 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9425 GENERIC2_INT_ENABLE, 1);
9426 WREG32_SOC15_IP(GC, target, tmp);
9427 }
9428 break;
9429 default:
9430 BUG(); /* kiq only support GENERIC2_INT now */
9431 break;
9432 }
9433 return 0;
9434 }
9435
gfx_v10_0_kiq_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)9436 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
9437 struct amdgpu_irq_src *source,
9438 struct amdgpu_iv_entry *entry)
9439 {
9440 u8 me_id, pipe_id, queue_id;
9441 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
9442
9443 me_id = (entry->ring_id & 0x0c) >> 2;
9444 pipe_id = (entry->ring_id & 0x03) >> 0;
9445 queue_id = (entry->ring_id & 0x70) >> 4;
9446 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
9447 me_id, pipe_id, queue_id);
9448
9449 amdgpu_fence_process(ring);
9450 return 0;
9451 }
9452
gfx_v10_0_emit_mem_sync(struct amdgpu_ring * ring)9453 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
9454 {
9455 const unsigned int gcr_cntl =
9456 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
9457 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
9458 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
9459 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
9460 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
9461 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
9462 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
9463 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
9464
9465 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
9466 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
9467 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
9468 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
9469 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */
9470 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
9471 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */
9472 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
9473 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
9474 }
9475
gfx_v10_ring_insert_nop(struct amdgpu_ring * ring,uint32_t num_nop)9476 static void gfx_v10_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop)
9477 {
9478 /* Header itself is a NOP packet */
9479 if (num_nop == 1) {
9480 amdgpu_ring_write(ring, ring->funcs->nop);
9481 return;
9482 }
9483
9484 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/
9485 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe)));
9486
9487 /* Header is at index 0, followed by num_nops - 1 NOP packet's */
9488 amdgpu_ring_insert_nop(ring, num_nop - 1);
9489 }
9490
gfx_v10_0_reset_kgq(struct amdgpu_ring * ring,unsigned int vmid)9491 static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid)
9492 {
9493 struct amdgpu_device *adev = ring->adev;
9494 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
9495 struct amdgpu_ring *kiq_ring = &kiq->ring;
9496 unsigned long flags;
9497 u32 tmp;
9498 u64 addr;
9499 int r;
9500
9501 if (amdgpu_sriov_vf(adev))
9502 return -EINVAL;
9503
9504 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
9505 return -EINVAL;
9506
9507 spin_lock_irqsave(&kiq->ring_lock, flags);
9508
9509 if (amdgpu_ring_alloc(kiq_ring, 5 + 7 + 7 + kiq->pmf->map_queues_size)) {
9510 spin_unlock_irqrestore(&kiq->ring_lock, flags);
9511 return -ENOMEM;
9512 }
9513
9514 addr = amdgpu_bo_gpu_offset(ring->mqd_obj) +
9515 offsetof(struct v10_gfx_mqd, cp_gfx_hqd_active);
9516 tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);
9517 if (ring->pipe == 0)
9518 tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE0_QUEUES, 1 << ring->queue);
9519 else
9520 tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE1_QUEUES, 1 << ring->queue);
9521
9522 gfx_v10_0_ring_emit_wreg(kiq_ring,
9523 SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), tmp);
9524 gfx_v10_0_wait_reg_mem(kiq_ring, 0, 1, 0,
9525 lower_32_bits(addr), upper_32_bits(addr),
9526 0, 1, 0x20);
9527 gfx_v10_0_ring_emit_reg_wait(kiq_ring,
9528 SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), 0, 0xffffffff);
9529 kiq->pmf->kiq_map_queues(kiq_ring, ring);
9530 amdgpu_ring_commit(kiq_ring);
9531
9532 spin_unlock_irqrestore(&kiq->ring_lock, flags);
9533
9534 r = amdgpu_ring_test_ring(kiq_ring);
9535 if (r)
9536 return r;
9537
9538 r = gfx_v10_0_kgq_init_queue(ring, true);
9539 if (r) {
9540 DRM_ERROR("fail to init kgq\n");
9541 return r;
9542 }
9543
9544 return amdgpu_ring_test_ring(ring);
9545 }
9546
gfx_v10_0_reset_kcq(struct amdgpu_ring * ring,unsigned int vmid)9547 static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring,
9548 unsigned int vmid)
9549 {
9550 struct amdgpu_device *adev = ring->adev;
9551 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
9552 struct amdgpu_ring *kiq_ring = &kiq->ring;
9553 unsigned long flags;
9554 int i, r;
9555
9556 if (amdgpu_sriov_vf(adev))
9557 return -EINVAL;
9558
9559 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
9560 return -EINVAL;
9561
9562 spin_lock_irqsave(&kiq->ring_lock, flags);
9563
9564 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
9565 spin_unlock_irqrestore(&kiq->ring_lock, flags);
9566 return -ENOMEM;
9567 }
9568
9569 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES,
9570 0, 0);
9571 amdgpu_ring_commit(kiq_ring);
9572 spin_unlock_irqrestore(&kiq->ring_lock, flags);
9573
9574 r = amdgpu_ring_test_ring(kiq_ring);
9575 if (r)
9576 return r;
9577
9578 /* make sure dequeue is complete*/
9579 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
9580 mutex_lock(&adev->srbm_mutex);
9581 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
9582 for (i = 0; i < adev->usec_timeout; i++) {
9583 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
9584 break;
9585 udelay(1);
9586 }
9587 if (i >= adev->usec_timeout)
9588 r = -ETIMEDOUT;
9589 nv_grbm_select(adev, 0, 0, 0, 0);
9590 mutex_unlock(&adev->srbm_mutex);
9591 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
9592 if (r) {
9593 dev_err(adev->dev, "fail to wait on hqd deactivate\n");
9594 return r;
9595 }
9596
9597 r = gfx_v10_0_kcq_init_queue(ring, true);
9598 if (r) {
9599 dev_err(adev->dev, "fail to init kcq\n");
9600 return r;
9601 }
9602
9603 spin_lock_irqsave(&kiq->ring_lock, flags);
9604 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size)) {
9605 spin_unlock_irqrestore(&kiq->ring_lock, flags);
9606 return -ENOMEM;
9607 }
9608 kiq->pmf->kiq_map_queues(kiq_ring, ring);
9609 amdgpu_ring_commit(kiq_ring);
9610 spin_unlock_irqrestore(&kiq->ring_lock, flags);
9611
9612 r = amdgpu_ring_test_ring(kiq_ring);
9613 if (r)
9614 return r;
9615
9616 return amdgpu_ring_test_ring(ring);
9617 }
9618
gfx_v10_ip_print(struct amdgpu_ip_block * ip_block,struct drm_printer * p)9619 static void gfx_v10_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
9620 {
9621 struct amdgpu_device *adev = ip_block->adev;
9622 uint32_t i, j, k, reg, index = 0;
9623 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
9624
9625 if (!adev->gfx.ip_dump_core)
9626 return;
9627
9628 for (i = 0; i < reg_count; i++)
9629 drm_printf(p, "%-50s \t 0x%08x\n",
9630 gc_reg_list_10_1[i].reg_name,
9631 adev->gfx.ip_dump_core[i]);
9632
9633 /* print compute queue registers for all instances */
9634 if (!adev->gfx.ip_dump_compute_queues)
9635 return;
9636
9637 reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
9638 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n",
9639 adev->gfx.mec.num_mec,
9640 adev->gfx.mec.num_pipe_per_mec,
9641 adev->gfx.mec.num_queue_per_pipe);
9642
9643 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
9644 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
9645 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
9646 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);
9647 for (reg = 0; reg < reg_count; reg++) {
9648 drm_printf(p, "%-50s \t 0x%08x\n",
9649 gc_cp_reg_list_10[reg].reg_name,
9650 adev->gfx.ip_dump_compute_queues[index + reg]);
9651 }
9652 index += reg_count;
9653 }
9654 }
9655 }
9656
9657 /* print gfx queue registers for all instances */
9658 if (!adev->gfx.ip_dump_gfx_queues)
9659 return;
9660
9661 index = 0;
9662 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
9663 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n",
9664 adev->gfx.me.num_me,
9665 adev->gfx.me.num_pipe_per_me,
9666 adev->gfx.me.num_queue_per_pipe);
9667
9668 for (i = 0; i < adev->gfx.me.num_me; i++) {
9669 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
9670 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
9671 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k);
9672 for (reg = 0; reg < reg_count; reg++) {
9673 drm_printf(p, "%-50s \t 0x%08x\n",
9674 gc_gfx_queue_reg_list_10[reg].reg_name,
9675 adev->gfx.ip_dump_gfx_queues[index + reg]);
9676 }
9677 index += reg_count;
9678 }
9679 }
9680 }
9681 }
9682
gfx_v10_ip_dump(struct amdgpu_ip_block * ip_block)9683 static void gfx_v10_ip_dump(struct amdgpu_ip_block *ip_block)
9684 {
9685 struct amdgpu_device *adev = ip_block->adev;
9686 uint32_t i, j, k, reg, index = 0;
9687 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
9688
9689 if (!adev->gfx.ip_dump_core)
9690 return;
9691
9692 amdgpu_gfx_off_ctrl(adev, false);
9693 for (i = 0; i < reg_count; i++)
9694 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));
9695 amdgpu_gfx_off_ctrl(adev, true);
9696
9697 /* dump compute queue registers for all instances */
9698 if (!adev->gfx.ip_dump_compute_queues)
9699 return;
9700
9701 reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
9702 amdgpu_gfx_off_ctrl(adev, false);
9703 mutex_lock(&adev->srbm_mutex);
9704 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
9705 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
9706 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
9707 /* ME0 is for GFX so start from 1 for CP */
9708 nv_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0);
9709
9710 for (reg = 0; reg < reg_count; reg++) {
9711 adev->gfx.ip_dump_compute_queues[index + reg] =
9712 RREG32(SOC15_REG_ENTRY_OFFSET(
9713 gc_cp_reg_list_10[reg]));
9714 }
9715 index += reg_count;
9716 }
9717 }
9718 }
9719 nv_grbm_select(adev, 0, 0, 0, 0);
9720 mutex_unlock(&adev->srbm_mutex);
9721 amdgpu_gfx_off_ctrl(adev, true);
9722
9723 /* dump gfx queue registers for all instances */
9724 if (!adev->gfx.ip_dump_gfx_queues)
9725 return;
9726
9727 index = 0;
9728 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
9729 amdgpu_gfx_off_ctrl(adev, false);
9730 mutex_lock(&adev->srbm_mutex);
9731 for (i = 0; i < adev->gfx.me.num_me; i++) {
9732 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
9733 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
9734 nv_grbm_select(adev, i, j, k, 0);
9735
9736 for (reg = 0; reg < reg_count; reg++) {
9737 adev->gfx.ip_dump_gfx_queues[index + reg] =
9738 RREG32(SOC15_REG_ENTRY_OFFSET(
9739 gc_gfx_queue_reg_list_10[reg]));
9740 }
9741 index += reg_count;
9742 }
9743 }
9744 }
9745 nv_grbm_select(adev, 0, 0, 0, 0);
9746 mutex_unlock(&adev->srbm_mutex);
9747 amdgpu_gfx_off_ctrl(adev, true);
9748 }
9749
gfx_v10_0_ring_emit_cleaner_shader(struct amdgpu_ring * ring)9750 static void gfx_v10_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring)
9751 {
9752 /* Emit the cleaner shader */
9753 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0));
9754 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */
9755 }
9756
gfx_v10_0_ring_begin_use(struct amdgpu_ring * ring)9757 static void gfx_v10_0_ring_begin_use(struct amdgpu_ring *ring)
9758 {
9759 amdgpu_gfx_profile_ring_begin_use(ring);
9760
9761 amdgpu_gfx_enforce_isolation_ring_begin_use(ring);
9762 }
9763
gfx_v10_0_ring_end_use(struct amdgpu_ring * ring)9764 static void gfx_v10_0_ring_end_use(struct amdgpu_ring *ring)
9765 {
9766 amdgpu_gfx_profile_ring_end_use(ring);
9767
9768 amdgpu_gfx_enforce_isolation_ring_end_use(ring);
9769 }
9770
9771 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
9772 .name = "gfx_v10_0",
9773 .early_init = gfx_v10_0_early_init,
9774 .late_init = gfx_v10_0_late_init,
9775 .sw_init = gfx_v10_0_sw_init,
9776 .sw_fini = gfx_v10_0_sw_fini,
9777 .hw_init = gfx_v10_0_hw_init,
9778 .hw_fini = gfx_v10_0_hw_fini,
9779 .suspend = gfx_v10_0_suspend,
9780 .resume = gfx_v10_0_resume,
9781 .is_idle = gfx_v10_0_is_idle,
9782 .wait_for_idle = gfx_v10_0_wait_for_idle,
9783 .soft_reset = gfx_v10_0_soft_reset,
9784 .set_clockgating_state = gfx_v10_0_set_clockgating_state,
9785 .set_powergating_state = gfx_v10_0_set_powergating_state,
9786 .get_clockgating_state = gfx_v10_0_get_clockgating_state,
9787 .dump_ip_state = gfx_v10_ip_dump,
9788 .print_ip_state = gfx_v10_ip_print,
9789 };
9790
9791 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
9792 .type = AMDGPU_RING_TYPE_GFX,
9793 .align_mask = 0xff,
9794 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9795 .support_64bit_ptrs = true,
9796 .secure_submission_supported = true,
9797 .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
9798 .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
9799 .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
9800 .emit_frame_size = /* totally 242 maximum if 16 IBs */
9801 5 + /* COND_EXEC */
9802 7 + /* PIPELINE_SYNC */
9803 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9804 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9805 4 + /* VM_FLUSH */
9806 8 + /* FENCE for VM_FLUSH */
9807 20 + /* GDS switch */
9808 4 + /* double SWITCH_BUFFER,
9809 * the first COND_EXEC jump to the place
9810 * just prior to this double SWITCH_BUFFER
9811 */
9812 5 + /* COND_EXEC */
9813 7 + /* HDP_flush */
9814 4 + /* VGT_flush */
9815 14 + /* CE_META */
9816 31 + /* DE_META */
9817 3 + /* CNTX_CTRL */
9818 5 + /* HDP_INVL */
9819 8 + 8 + /* FENCE x2 */
9820 2 + /* SWITCH_BUFFER */
9821 8 + /* gfx_v10_0_emit_mem_sync */
9822 2, /* gfx_v10_0_ring_emit_cleaner_shader */
9823 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
9824 .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
9825 .emit_fence = gfx_v10_0_ring_emit_fence,
9826 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9827 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9828 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9829 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9830 .test_ring = gfx_v10_0_ring_test_ring,
9831 .test_ib = gfx_v10_0_ring_test_ib,
9832 .insert_nop = gfx_v10_ring_insert_nop,
9833 .pad_ib = amdgpu_ring_generic_pad_ib,
9834 .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
9835 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
9836 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
9837 .preempt_ib = gfx_v10_0_ring_preempt_ib,
9838 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
9839 .emit_wreg = gfx_v10_0_ring_emit_wreg,
9840 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9841 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9842 .soft_recovery = gfx_v10_0_ring_soft_recovery,
9843 .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9844 .reset = gfx_v10_0_reset_kgq,
9845 .emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader,
9846 .begin_use = gfx_v10_0_ring_begin_use,
9847 .end_use = gfx_v10_0_ring_end_use,
9848 };
9849
9850 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
9851 .type = AMDGPU_RING_TYPE_COMPUTE,
9852 .align_mask = 0xff,
9853 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9854 .support_64bit_ptrs = true,
9855 .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9856 .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9857 .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9858 .emit_frame_size =
9859 20 + /* gfx_v10_0_ring_emit_gds_switch */
9860 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9861 5 + /* hdp invalidate */
9862 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9863 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9864 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9865 2 + /* gfx_v10_0_ring_emit_vm_flush */
9866 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
9867 8 + /* gfx_v10_0_emit_mem_sync */
9868 2, /* gfx_v10_0_ring_emit_cleaner_shader */
9869 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9870 .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9871 .emit_fence = gfx_v10_0_ring_emit_fence,
9872 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9873 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9874 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9875 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9876 .test_ring = gfx_v10_0_ring_test_ring,
9877 .test_ib = gfx_v10_0_ring_test_ib,
9878 .insert_nop = gfx_v10_ring_insert_nop,
9879 .pad_ib = amdgpu_ring_generic_pad_ib,
9880 .emit_wreg = gfx_v10_0_ring_emit_wreg,
9881 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9882 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9883 .soft_recovery = gfx_v10_0_ring_soft_recovery,
9884 .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9885 .reset = gfx_v10_0_reset_kcq,
9886 .emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader,
9887 .begin_use = gfx_v10_0_ring_begin_use,
9888 .end_use = gfx_v10_0_ring_end_use,
9889 };
9890
9891 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
9892 .type = AMDGPU_RING_TYPE_KIQ,
9893 .align_mask = 0xff,
9894 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9895 .support_64bit_ptrs = true,
9896 .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9897 .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9898 .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9899 .emit_frame_size =
9900 20 + /* gfx_v10_0_ring_emit_gds_switch */
9901 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9902 5 + /*hdp invalidate */
9903 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9904 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9905 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9906 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
9907 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9908 .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9909 .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
9910 .test_ring = gfx_v10_0_ring_test_ring,
9911 .test_ib = gfx_v10_0_ring_test_ib,
9912 .insert_nop = amdgpu_ring_insert_nop,
9913 .pad_ib = amdgpu_ring_generic_pad_ib,
9914 .emit_rreg = gfx_v10_0_ring_emit_rreg,
9915 .emit_wreg = gfx_v10_0_ring_emit_wreg,
9916 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9917 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9918 };
9919
gfx_v10_0_set_ring_funcs(struct amdgpu_device * adev)9920 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
9921 {
9922 int i;
9923
9924 adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq;
9925
9926 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
9927 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
9928
9929 for (i = 0; i < adev->gfx.num_compute_rings; i++)
9930 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
9931 }
9932
9933 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
9934 .set = gfx_v10_0_set_eop_interrupt_state,
9935 .process = gfx_v10_0_eop_irq,
9936 };
9937
9938 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
9939 .set = gfx_v10_0_set_priv_reg_fault_state,
9940 .process = gfx_v10_0_priv_reg_irq,
9941 };
9942
9943 static const struct amdgpu_irq_src_funcs gfx_v10_0_bad_op_irq_funcs = {
9944 .set = gfx_v10_0_set_bad_op_fault_state,
9945 .process = gfx_v10_0_bad_op_irq,
9946 };
9947
9948 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
9949 .set = gfx_v10_0_set_priv_inst_fault_state,
9950 .process = gfx_v10_0_priv_inst_irq,
9951 };
9952
9953 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
9954 .set = gfx_v10_0_kiq_set_interrupt_state,
9955 .process = gfx_v10_0_kiq_irq,
9956 };
9957
gfx_v10_0_set_irq_funcs(struct amdgpu_device * adev)9958 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
9959 {
9960 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
9961 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
9962
9963 adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
9964 adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs;
9965
9966 adev->gfx.priv_reg_irq.num_types = 1;
9967 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
9968
9969 adev->gfx.bad_op_irq.num_types = 1;
9970 adev->gfx.bad_op_irq.funcs = &gfx_v10_0_bad_op_irq_funcs;
9971
9972 adev->gfx.priv_inst_irq.num_types = 1;
9973 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
9974 }
9975
gfx_v10_0_set_rlc_funcs(struct amdgpu_device * adev)9976 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
9977 {
9978 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
9979 case IP_VERSION(10, 1, 10):
9980 case IP_VERSION(10, 1, 1):
9981 case IP_VERSION(10, 1, 3):
9982 case IP_VERSION(10, 1, 4):
9983 case IP_VERSION(10, 3, 2):
9984 case IP_VERSION(10, 3, 1):
9985 case IP_VERSION(10, 3, 4):
9986 case IP_VERSION(10, 3, 5):
9987 case IP_VERSION(10, 3, 6):
9988 case IP_VERSION(10, 3, 3):
9989 case IP_VERSION(10, 3, 7):
9990 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
9991 break;
9992 case IP_VERSION(10, 1, 2):
9993 case IP_VERSION(10, 3, 0):
9994 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
9995 break;
9996 default:
9997 break;
9998 }
9999 }
10000
gfx_v10_0_set_gds_init(struct amdgpu_device * adev)10001 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
10002 {
10003 unsigned int total_cu = adev->gfx.config.max_cu_per_sh *
10004 adev->gfx.config.max_sh_per_se *
10005 adev->gfx.config.max_shader_engines;
10006
10007 adev->gds.gds_size = 0x10000;
10008 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
10009 adev->gds.gws_size = 64;
10010 adev->gds.oa_size = 16;
10011 }
10012
gfx_v10_0_set_mqd_funcs(struct amdgpu_device * adev)10013 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev)
10014 {
10015 /* set gfx eng mqd */
10016 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size =
10017 sizeof(struct v10_gfx_mqd);
10018 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =
10019 gfx_v10_0_gfx_mqd_init;
10020 /* set compute eng mqd */
10021 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =
10022 sizeof(struct v10_compute_mqd);
10023 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
10024 gfx_v10_0_compute_mqd_init;
10025 }
10026
gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device * adev,u32 bitmap)10027 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
10028 u32 bitmap)
10029 {
10030 u32 data;
10031
10032 if (!bitmap)
10033 return;
10034
10035 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
10036 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
10037
10038 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
10039 }
10040
gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device * adev)10041 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
10042 {
10043 u32 disabled_mask =
10044 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
10045 u32 efuse_setting = 0;
10046 u32 vbios_setting = 0;
10047
10048 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
10049 efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
10050 efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
10051
10052 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
10053 vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
10054 vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
10055
10056 disabled_mask |= efuse_setting | vbios_setting;
10057
10058 return (~disabled_mask);
10059 }
10060
gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device * adev)10061 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
10062 {
10063 u32 wgp_idx, wgp_active_bitmap;
10064 u32 cu_bitmap_per_wgp, cu_active_bitmap;
10065
10066 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
10067 cu_active_bitmap = 0;
10068
10069 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
10070 /* if there is one WGP enabled, it means 2 CUs will be enabled */
10071 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
10072 if (wgp_active_bitmap & (1 << wgp_idx))
10073 cu_active_bitmap |= cu_bitmap_per_wgp;
10074 }
10075
10076 return cu_active_bitmap;
10077 }
10078
gfx_v10_0_get_cu_info(struct amdgpu_device * adev,struct amdgpu_cu_info * cu_info)10079 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
10080 struct amdgpu_cu_info *cu_info)
10081 {
10082 int i, j, k, counter, active_cu_number = 0;
10083 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
10084 unsigned int disable_masks[4 * 2];
10085
10086 if (!adev || !cu_info)
10087 return -EINVAL;
10088
10089 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
10090
10091 mutex_lock(&adev->grbm_idx_mutex);
10092 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
10093 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
10094 bitmap = i * adev->gfx.config.max_sh_per_se + j;
10095 if (((amdgpu_ip_version(adev, GC_HWIP, 0) ==
10096 IP_VERSION(10, 3, 0)) ||
10097 (amdgpu_ip_version(adev, GC_HWIP, 0) ==
10098 IP_VERSION(10, 3, 3)) ||
10099 (amdgpu_ip_version(adev, GC_HWIP, 0) ==
10100 IP_VERSION(10, 3, 6)) ||
10101 (amdgpu_ip_version(adev, GC_HWIP, 0) ==
10102 IP_VERSION(10, 3, 7))) &&
10103 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
10104 continue;
10105 mask = 1;
10106 ao_bitmap = 0;
10107 counter = 0;
10108 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
10109 if (i < 4 && j < 2)
10110 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
10111 adev, disable_masks[i * 2 + j]);
10112 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
10113 cu_info->bitmap[0][i][j] = bitmap;
10114
10115 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
10116 if (bitmap & mask) {
10117 if (counter < adev->gfx.config.max_cu_per_sh)
10118 ao_bitmap |= mask;
10119 counter++;
10120 }
10121 mask <<= 1;
10122 }
10123 active_cu_number += counter;
10124 if (i < 2 && j < 2)
10125 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
10126 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
10127 }
10128 }
10129 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
10130 mutex_unlock(&adev->grbm_idx_mutex);
10131
10132 cu_info->number = active_cu_number;
10133 cu_info->ao_cu_mask = ao_cu_mask;
10134 cu_info->simd_per_cu = NUM_SIMD_PER_CU;
10135
10136 return 0;
10137 }
10138
gfx_v10_3_get_disabled_sa(struct amdgpu_device * adev)10139 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
10140 {
10141 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
10142
10143 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
10144 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
10145 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
10146
10147 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
10148 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
10149 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
10150
10151 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
10152 adev->gfx.config.max_shader_engines);
10153 disabled_sa = efuse_setting | vbios_setting;
10154 disabled_sa &= max_sa_mask;
10155
10156 return disabled_sa;
10157 }
10158
gfx_v10_3_program_pbb_mode(struct amdgpu_device * adev)10159 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
10160 {
10161 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
10162 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
10163
10164 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
10165
10166 max_sa_per_se = adev->gfx.config.max_sh_per_se;
10167 max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
10168 max_shader_engines = adev->gfx.config.max_shader_engines;
10169
10170 for (se_index = 0; max_shader_engines > se_index; se_index++) {
10171 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
10172 disabled_sa_per_se &= max_sa_per_se_mask;
10173 if (disabled_sa_per_se == max_sa_per_se_mask) {
10174 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
10175 break;
10176 }
10177 }
10178 }
10179
gfx_v10_3_set_power_brake_sequence(struct amdgpu_device * adev)10180 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
10181 {
10182 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
10183 (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
10184 (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
10185 (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
10186
10187 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
10188 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
10189 (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
10190 (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
10191 (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
10192 (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
10193
10194 WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
10195 (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
10196 (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
10197 (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
10198
10199 WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
10200
10201 WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
10202 (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
10203 }
10204
10205 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = {
10206 .type = AMD_IP_BLOCK_TYPE_GFX,
10207 .major = 10,
10208 .minor = 0,
10209 .rev = 0,
10210 .funcs = &gfx_v10_0_ip_funcs,
10211 };
10212