xref: /linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_funnel_regs.h (revision 9a87ffc99ec8eb8d35eed7c4f816d75f5cc9662e)
1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright 2016-2020 HabanaLabs, Ltd.
4  * All Rights Reserved.
5  *
6  */
7 
8 /************************************
9  ** This is an auto-generated file **
10  **       DO NOT EDIT BELOW        **
11  ************************************/
12 
13 #ifndef ASIC_REG_DCORE0_TPC0_EML_FUNNEL_REGS_H_
14 #define ASIC_REG_DCORE0_TPC0_EML_FUNNEL_REGS_H_
15 
16 /*
17  *****************************************
18  *   DCORE0_TPC0_EML_FUNNEL
19  *   (Prototype: FUNNEL_2X1)
20  *****************************************
21  */
22 
23 #define mmDCORE0_TPC0_EML_FUNNEL_CTRL_REG 0x6000
24 
25 #define mmDCORE0_TPC0_EML_FUNNEL_PRIORITY_CTRL_REG 0x6004
26 
27 #define mmDCORE0_TPC0_EML_FUNNEL_ITATBDATA0 0x6EEC
28 
29 #define mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR2 0x6EF0
30 
31 #define mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR1 0x6EF4
32 
33 #define mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR0 0x6EF8
34 
35 #define mmDCORE0_TPC0_EML_FUNNEL_ITCTRL 0x6F00
36 
37 #define mmDCORE0_TPC0_EML_FUNNEL_CLAIMSET 0x6FA0
38 
39 #define mmDCORE0_TPC0_EML_FUNNEL_CLAIMCLR 0x6FA4
40 
41 #define mmDCORE0_TPC0_EML_FUNNEL_LOCKACCESS 0x6FB0
42 
43 #define mmDCORE0_TPC0_EML_FUNNEL_LOCKSTATUS 0x6FB4
44 
45 #define mmDCORE0_TPC0_EML_FUNNEL_AUTHSTATUS 0x6FB8
46 
47 #define mmDCORE0_TPC0_EML_FUNNEL_DEVID 0x6FC8
48 
49 #define mmDCORE0_TPC0_EML_FUNNEL_DEVTYPE 0x6FCC
50 
51 #define mmDCORE0_TPC0_EML_FUNNEL_PIDR4 0x6FD0
52 
53 #define mmDCORE0_TPC0_EML_FUNNEL_PERIPHID5 0x6FD4
54 
55 #define mmDCORE0_TPC0_EML_FUNNEL_PERIPHID6 0x6FD8
56 
57 #define mmDCORE0_TPC0_EML_FUNNEL_PERIPHID7 0x6FDC
58 
59 #define mmDCORE0_TPC0_EML_FUNNEL_PIDR0 0x6FE0
60 
61 #define mmDCORE0_TPC0_EML_FUNNEL_PIDR1 0x6FE4
62 
63 #define mmDCORE0_TPC0_EML_FUNNEL_PIDR2 0x6FE8
64 
65 #define mmDCORE0_TPC0_EML_FUNNEL_PIDR3 0x6FEC
66 
67 #define mmDCORE0_TPC0_EML_FUNNEL_CID0 0x6FF0
68 
69 #define mmDCORE0_TPC0_EML_FUNNEL_CID1 0x6FF4
70 
71 #define mmDCORE0_TPC0_EML_FUNNEL_CID2 0x6FF8
72 
73 #define mmDCORE0_TPC0_EML_FUNNEL_CID3 0x6FFC
74 
75 #endif /* ASIC_REG_DCORE0_TPC0_EML_FUNNEL_REGS_H_ */
76