xref: /linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_axuser_nonsecured_regs.h (revision 9a87ffc99ec8eb8d35eed7c4f816d75f5cc9662e)
1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright 2016-2020 HabanaLabs, Ltd.
4  * All Rights Reserved.
5  *
6  */
7 
8 /************************************
9  ** This is an auto-generated file **
10  **       DO NOT EDIT BELOW        **
11  ************************************/
12 
13 #ifndef ASIC_REG_DCORE0_EDMA0_QM_AXUSER_NONSECURED_REGS_H_
14 #define ASIC_REG_DCORE0_EDMA0_QM_AXUSER_NONSECURED_REGS_H_
15 
16 /*
17  *****************************************
18  *   DCORE0_EDMA0_QM_AXUSER_NONSECURED
19  *   (Prototype: AXUSER)
20  *****************************************
21  */
22 
23 #define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_ASID 0x41CAB80
24 
25 #define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_MMU_BP 0x41CAB84
26 
27 #define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_STRONG_ORDER 0x41CAB88
28 
29 #define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_NO_SNOOP 0x41CAB8C
30 
31 #define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_WR_REDUCTION 0x41CAB90
32 
33 #define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_RD_ATOMIC 0x41CAB94
34 
35 #define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_QOS 0x41CAB98
36 
37 #define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_RSVD 0x41CAB9C
38 
39 #define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_EMEM_CPAGE 0x41CABA0
40 
41 #define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_CORE 0x41CABA4
42 
43 #define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_E2E_COORD 0x41CABA8
44 
45 #define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_WR_OVRD_LO 0x41CABB0
46 
47 #define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_WR_OVRD_HI 0x41CABB4
48 
49 #define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_RD_OVRD_LO 0x41CABB8
50 
51 #define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_RD_OVRD_HI 0x41CABBC
52 
53 #define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_LB_COORD 0x41CABC0
54 
55 #define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_LB_LOCK 0x41CABC4
56 
57 #define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_LB_RSVD 0x41CABC8
58 
59 #define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_LB_OVRD 0x41CABCC
60 
61 #endif /* ASIC_REG_DCORE0_EDMA0_QM_AXUSER_NONSECURED_REGS_H_ */
62