xref: /linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_dec0_cmd_regs.h (revision 9a87ffc99ec8eb8d35eed7c4f816d75f5cc9662e) 
1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright 2016-2020 HabanaLabs, Ltd.
4  * All Rights Reserved.
5  *
6  */
7 
8 /************************************
9  ** This is an auto-generated file **
10  **       DO NOT EDIT BELOW        **
11  ************************************/
12 
13 #ifndef ASIC_REG_DCORE0_DEC0_CMD_REGS_H_
14 #define ASIC_REG_DCORE0_DEC0_CMD_REGS_H_
15 
16 /*
17  *****************************************
18  *   DCORE0_DEC0_CMD
19  *   (Prototype: VSI_CMD)
20  *****************************************
21  */
22 
23 #define mmDCORE0_DEC0_CMD_SWREG0 0x41E0000
24 
25 #define mmDCORE0_DEC0_CMD_SWREG1 0x41E0004
26 
27 #define mmDCORE0_DEC0_CMD_SWREG2 0x41E0008
28 
29 #define mmDCORE0_DEC0_CMD_SWREG3 0x41E000C
30 
31 #define mmDCORE0_DEC0_CMD_SWREG4 0x41E0010
32 
33 #define mmDCORE0_DEC0_CMD_SWREG5 0x41E0014
34 
35 #define mmDCORE0_DEC0_CMD_SWREG6 0x41E0018
36 
37 #define mmDCORE0_DEC0_CMD_SWREG7 0x41E001C
38 
39 #define mmDCORE0_DEC0_CMD_SWREG8 0x41E0020
40 
41 #define mmDCORE0_DEC0_CMD_SWREG9 0x41E0024
42 
43 #define mmDCORE0_DEC0_CMD_SWREG10 0x41E0028
44 
45 #define mmDCORE0_DEC0_CMD_SWREG11 0x41E002C
46 
47 #define mmDCORE0_DEC0_CMD_SWREG12 0x41E0030
48 
49 #define mmDCORE0_DEC0_CMD_SWREG13 0x41E0034
50 
51 #define mmDCORE0_DEC0_CMD_SWREG14 0x41E0038
52 
53 #define mmDCORE0_DEC0_CMD_SWREG15 0x41E003C
54 
55 #define mmDCORE0_DEC0_CMD_SWREG16 0x41E0040
56 
57 #define mmDCORE0_DEC0_CMD_SWREG17 0x41E0044
58 
59 #define mmDCORE0_DEC0_CMD_SWREG18 0x41E0048
60 
61 #define mmDCORE0_DEC0_CMD_SWREG19 0x41E004C
62 
63 #define mmDCORE0_DEC0_CMD_SWREG20 0x41E0050
64 
65 #define mmDCORE0_DEC0_CMD_SWREG21 0x41E0054
66 
67 #define mmDCORE0_DEC0_CMD_SWREG22 0x41E0058
68 
69 #define mmDCORE0_DEC0_CMD_SWREG23 0x41E005C
70 
71 #define mmDCORE0_DEC0_CMD_SWREG24 0x41E0060
72 
73 #define mmDCORE0_DEC0_CMD_SWREG25 0x41E0064
74 
75 #define mmDCORE0_DEC0_CMD_SWREG26 0x41E0068
76 
77 #define mmDCORE0_DEC0_CMD_SWREG64 0x41E0100
78 
79 #define mmDCORE0_DEC0_CMD_SWREG65 0x41E0104
80 
81 #define mmDCORE0_DEC0_CMD_SWREG66 0x41E0108
82 
83 #define mmDCORE0_DEC0_CMD_SWREG67 0x41E010C
84 
85 #endif /* ASIC_REG_DCORE0_DEC0_CMD_REGS_H_ */
86