1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #ifndef SI_H 25 #define SI_H 26 27 #define TAHITI_RB_BITMAP_WIDTH_PER_SH 2 28 29 #define SI_MAX_SH_GPRS 256 30 #define SI_MAX_TEMP_GPRS 16 31 #define SI_MAX_SH_THREADS 256 32 #define SI_MAX_SH_STACK_ENTRIES 4096 33 #define SI_MAX_FRC_EOV_CNT 16384 34 #define SI_MAX_BACKENDS 8 35 #define SI_MAX_BACKENDS_MASK 0xFF 36 #define SI_MAX_BACKENDS_PER_SE_MASK 0x0F 37 #define SI_MAX_SIMDS 12 38 #define SI_MAX_SIMDS_MASK 0x0FFF 39 #define SI_MAX_SIMDS_PER_SE_MASK 0x00FF 40 #define SI_MAX_PIPES 8 41 #define SI_MAX_PIPES_MASK 0xFF 42 #define SI_MAX_PIPES_PER_SIMD_MASK 0x3F 43 #define SI_MAX_LDS_NUM 0xFFFF 44 #define SI_MAX_TCC 16 45 #define SI_MAX_TCC_MASK 0xFFFF 46 #define SI_MAX_CTLACKS_ASSERTION_WAIT 100 47 48 /* SMC IND accessor regs */ 49 #define SMC_IND_INDEX_0 0x80 50 #define SMC_IND_DATA_0 0x81 51 52 #define SMC_IND_ACCESS_CNTL 0x8A 53 # define AUTO_INCREMENT_IND_0 (1 << 0) 54 #define SMC_MESSAGE_0 0x8B 55 #define SMC_RESP_0 0x8C 56 57 /* CG IND registers are accessed via SMC indirect space + SMC_CG_IND_START */ 58 #define SMC_CG_IND_START 0xc0030000 59 #define SMC_CG_IND_END 0xc0040000 60 61 #define CG_CGTT_LOCAL_0 0x400 62 #define CG_CGTT_LOCAL_1 0x401 63 64 /* SMC IND registers */ 65 #define SMC_SYSCON_RESET_CNTL 0x80000000 66 # define RST_REG (1 << 0) 67 #define SMC_SYSCON_CLOCK_CNTL_0 0x80000004 68 # define CK_DISABLE (1 << 0) 69 # define CKEN (1 << 24) 70 71 #define VGA_HDP_CONTROL 0xCA 72 #define VGA_MEMORY_DISABLE (1 << 4) 73 74 #define DCCG_DISP_SLOW_SELECT_REG 0x13F 75 #define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0) 76 #define DCCG_DISP1_SLOW_SELECT_MASK (7 << 0) 77 #define DCCG_DISP1_SLOW_SELECT_SHIFT 0 78 #define DCCG_DISP2_SLOW_SELECT(x) ((x) << 4) 79 #define DCCG_DISP2_SLOW_SELECT_MASK (7 << 4) 80 #define DCCG_DISP2_SLOW_SELECT_SHIFT 4 81 82 #define CG_SPLL_FUNC_CNTL 0x180 83 #define SPLL_RESET (1 << 0) 84 #define SPLL_SLEEP (1 << 1) 85 #define SPLL_BYPASS_EN (1 << 3) 86 #define SPLL_REF_DIV(x) ((x) << 4) 87 #define SPLL_REF_DIV_MASK (0x3f << 4) 88 #define SPLL_PDIV_A(x) ((x) << 20) 89 #define SPLL_PDIV_A_MASK (0x7f << 20) 90 #define SPLL_PDIV_A_SHIFT 20 91 #define CG_SPLL_FUNC_CNTL_2 0x181 92 #define SCLK_MUX_SEL(x) ((x) << 0) 93 #define SCLK_MUX_SEL_MASK (0x1ff << 0) 94 #define SPLL_CTLREQ_CHG (1 << 23) 95 #define SCLK_MUX_UPDATE (1 << 26) 96 #define CG_SPLL_FUNC_CNTL_3 0x182 97 #define SPLL_FB_DIV(x) ((x) << 0) 98 #define SPLL_FB_DIV_MASK (0x3ffffff << 0) 99 #define SPLL_FB_DIV_SHIFT 0 100 #define SPLL_DITHEN (1 << 28) 101 #define CG_SPLL_FUNC_CNTL_4 0x183 102 103 #define SPLL_STATUS 0x185 104 #define SPLL_CHG_STATUS (1 << 1) 105 #define SPLL_CNTL_MODE 0x186 106 #define SPLL_SW_DIR_CONTROL (1 << 0) 107 # define SPLL_REFCLK_SEL(x) ((x) << 26) 108 # define SPLL_REFCLK_SEL_MASK (3 << 26) 109 110 #define CG_SPLL_SPREAD_SPECTRUM 0x188 111 #define SSEN (1 << 0) 112 #define CLK_S(x) ((x) << 4) 113 #define CLK_S_MASK (0xfff << 4) 114 #define CLK_S_SHIFT 4 115 #define CG_SPLL_SPREAD_SPECTRUM_2 0x189 116 #define CLK_V(x) ((x) << 0) 117 #define CLK_V_MASK (0x3ffffff << 0) 118 #define CLK_V_SHIFT 0 119 120 #define CG_SPLL_AUTOSCALE_CNTL 0x18b 121 # define AUTOSCALE_ON_SS_CLEAR (1 << 9) 122 123 /* discrete uvd clocks */ 124 #define CG_UPLL_FUNC_CNTL 0x18d 125 # define UPLL_RESET_MASK 0x00000001 126 # define UPLL_SLEEP_MASK 0x00000002 127 # define UPLL_BYPASS_EN_MASK 0x00000004 128 # define UPLL_CTLREQ_MASK 0x00000008 129 # define UPLL_VCO_MODE_MASK 0x00000600 130 # define UPLL_REF_DIV_MASK 0x003F0000 131 # define UPLL_CTLACK_MASK 0x40000000 132 # define UPLL_CTLACK2_MASK 0x80000000 133 #define CG_UPLL_FUNC_CNTL_2 0x18e 134 # define UPLL_PDIV_A(x) ((x) << 0) 135 # define UPLL_PDIV_A_MASK 0x0000007F 136 # define UPLL_PDIV_B(x) ((x) << 8) 137 # define UPLL_PDIV_B_MASK 0x00007F00 138 # define VCLK_SRC_SEL(x) ((x) << 20) 139 # define VCLK_SRC_SEL_MASK 0x01F00000 140 # define DCLK_SRC_SEL(x) ((x) << 25) 141 # define DCLK_SRC_SEL_MASK 0x3E000000 142 #define CG_UPLL_FUNC_CNTL_3 0x18f 143 # define UPLL_FB_DIV(x) ((x) << 0) 144 # define UPLL_FB_DIV_MASK 0x01FFFFFF 145 #define CG_UPLL_FUNC_CNTL_4 0x191 146 # define UPLL_SPARE_ISPARE9 0x00020000 147 #define CG_UPLL_FUNC_CNTL_5 0x192 148 # define RESET_ANTI_MUX_MASK 0x00000200 149 #define CG_UPLL_SPREAD_SPECTRUM 0x194 150 # define SSEN_MASK 0x00000001 151 152 #define MPLL_BYPASSCLK_SEL 0x197 153 # define MPLL_CLKOUT_SEL(x) ((x) << 8) 154 # define MPLL_CLKOUT_SEL_MASK 0xFF00 155 156 #define CG_CLKPIN_CNTL 0x198 157 # define XTALIN_DIVIDE (1 << 1) 158 # define BCLK_AS_XCLK (1 << 2) 159 #define CG_CLKPIN_CNTL_2 0x199 160 # define FORCE_BIF_REFCLK_EN (1 << 3) 161 # define MUX_TCLK_TO_XCLK (1 << 8) 162 163 #define THM_CLK_CNTL 0x19b 164 # define CMON_CLK_SEL(x) ((x) << 0) 165 # define CMON_CLK_SEL_MASK 0xFF 166 # define TMON_CLK_SEL(x) ((x) << 8) 167 # define TMON_CLK_SEL_MASK 0xFF00 168 #define MISC_CLK_CNTL 0x19c 169 # define DEEP_SLEEP_CLK_SEL(x) ((x) << 0) 170 # define DEEP_SLEEP_CLK_SEL_MASK 0xFF 171 # define ZCLK_SEL(x) ((x) << 8) 172 # define ZCLK_SEL_MASK 0xFF00 173 174 #define CG_THERMAL_CTRL 0x1c0 175 #define DPM_EVENT_SRC(x) ((x) << 0) 176 #define DPM_EVENT_SRC_MASK (7 << 0) 177 #define DIG_THERM_DPM(x) ((x) << 14) 178 #define DIG_THERM_DPM_MASK 0x003FC000 179 #define DIG_THERM_DPM_SHIFT 14 180 #define CG_THERMAL_STATUS 0x1c1 181 #define FDO_PWM_DUTY(x) ((x) << 9) 182 #define FDO_PWM_DUTY_MASK (0xff << 9) 183 #define FDO_PWM_DUTY_SHIFT 9 184 #define CG_THERMAL_INT 0x1c2 185 #define DIG_THERM_INTH(x) ((x) << 8) 186 #define DIG_THERM_INTH_MASK 0x0000FF00 187 #define DIG_THERM_INTH_SHIFT 8 188 #define DIG_THERM_INTL(x) ((x) << 16) 189 #define DIG_THERM_INTL_MASK 0x00FF0000 190 #define DIG_THERM_INTL_SHIFT 16 191 #define THERM_INT_MASK_HIGH (1 << 24) 192 #define THERM_INT_MASK_LOW (1 << 25) 193 194 #define CG_MULT_THERMAL_CTRL 0x1c4 195 #define TEMP_SEL(x) ((x) << 20) 196 #define TEMP_SEL_MASK (0xff << 20) 197 #define TEMP_SEL_SHIFT 20 198 #define CG_MULT_THERMAL_STATUS 0x1c5 199 #define ASIC_MAX_TEMP(x) ((x) << 0) 200 #define ASIC_MAX_TEMP_MASK 0x000001ff 201 #define ASIC_MAX_TEMP_SHIFT 0 202 #define CTF_TEMP(x) ((x) << 9) 203 #define CTF_TEMP_MASK 0x0003fe00 204 #define CTF_TEMP_SHIFT 9 205 206 #define CG_FDO_CTRL0 0x1d5 207 #define FDO_STATIC_DUTY(x) ((x) << 0) 208 #define FDO_STATIC_DUTY_MASK 0x000000FF 209 #define FDO_STATIC_DUTY_SHIFT 0 210 #define CG_FDO_CTRL1 0x1d6 211 #define FMAX_DUTY100(x) ((x) << 0) 212 #define FMAX_DUTY100_MASK 0x000000FF 213 #define FMAX_DUTY100_SHIFT 0 214 #define CG_FDO_CTRL2 0x1d7 215 #define TMIN(x) ((x) << 0) 216 #define TMIN_MASK 0x000000FF 217 #define TMIN_SHIFT 0 218 #define FDO_PWM_MODE(x) ((x) << 11) 219 #define FDO_PWM_MODE_MASK (7 << 11) 220 #define FDO_PWM_MODE_SHIFT 11 221 #define TACH_PWM_RESP_RATE(x) ((x) << 25) 222 #define TACH_PWM_RESP_RATE_MASK (0x7f << 25) 223 #define TACH_PWM_RESP_RATE_SHIFT 25 224 225 #define CG_TACH_CTRL 0x1dc 226 # define EDGE_PER_REV(x) ((x) << 0) 227 # define EDGE_PER_REV_MASK (0x7 << 0) 228 # define EDGE_PER_REV_SHIFT 0 229 # define TARGET_PERIOD(x) ((x) << 3) 230 # define TARGET_PERIOD_MASK 0xfffffff8 231 # define TARGET_PERIOD_SHIFT 3 232 #define CG_TACH_STATUS 0x1dd 233 # define TACH_PERIOD(x) ((x) << 0) 234 # define TACH_PERIOD_MASK 0xffffffff 235 # define TACH_PERIOD_SHIFT 0 236 237 #define GENERAL_PWRMGT 0x1e0 238 # define GLOBAL_PWRMGT_EN (1 << 0) 239 # define STATIC_PM_EN (1 << 1) 240 # define THERMAL_PROTECTION_DIS (1 << 2) 241 # define THERMAL_PROTECTION_TYPE (1 << 3) 242 # define SW_SMIO_INDEX(x) ((x) << 6) 243 # define SW_SMIO_INDEX_MASK (1 << 6) 244 # define SW_SMIO_INDEX_SHIFT 6 245 # define VOLT_PWRMGT_EN (1 << 10) 246 # define DYN_SPREAD_SPECTRUM_EN (1 << 23) 247 #define CG_TPC 0x1e1 248 #define SCLK_PWRMGT_CNTL 0x1e2 249 # define SCLK_PWRMGT_OFF (1 << 0) 250 # define SCLK_LOW_D1 (1 << 1) 251 # define FIR_RESET (1 << 4) 252 # define FIR_FORCE_TREND_SEL (1 << 5) 253 # define FIR_TREND_MODE (1 << 6) 254 # define DYN_GFX_CLK_OFF_EN (1 << 7) 255 # define GFX_CLK_FORCE_ON (1 << 8) 256 # define GFX_CLK_REQUEST_OFF (1 << 9) 257 # define GFX_CLK_FORCE_OFF (1 << 10) 258 # define GFX_CLK_OFF_ACPI_D1 (1 << 11) 259 # define GFX_CLK_OFF_ACPI_D2 (1 << 12) 260 # define GFX_CLK_OFF_ACPI_D3 (1 << 13) 261 # define DYN_LIGHT_SLEEP_EN (1 << 14) 262 263 #define TARGET_AND_CURRENT_PROFILE_INDEX 0x1e6 264 # define CURRENT_STATE_INDEX_MASK (0xf << 4) 265 # define CURRENT_STATE_INDEX_SHIFT 4 266 267 #define CG_FTV 0x1ef 268 269 #define CG_FFCT_0 0x1f0 270 # define UTC_0(x) ((x) << 0) 271 # define UTC_0_MASK (0x3ff << 0) 272 # define DTC_0(x) ((x) << 10) 273 # define DTC_0_MASK (0x3ff << 10) 274 275 #define CG_BSP 0x1ff 276 # define BSP(x) ((x) << 0) 277 # define BSP_MASK (0xffff << 0) 278 # define BSU(x) ((x) << 16) 279 # define BSU_MASK (0xf << 16) 280 #define CG_AT 0x200 281 # define CG_R(x) ((x) << 0) 282 # define CG_R_MASK (0xffff << 0) 283 # define CG_L(x) ((x) << 16) 284 # define CG_L_MASK (0xffff << 16) 285 286 #define CG_GIT 0x201 287 # define CG_GICST(x) ((x) << 0) 288 # define CG_GICST_MASK (0xffff << 0) 289 # define CG_GIPOT(x) ((x) << 16) 290 # define CG_GIPOT_MASK (0xffff << 16) 291 292 #define CG_SSP 0x203 293 # define SST(x) ((x) << 0) 294 # define SST_MASK (0xffff << 0) 295 # define SSTU(x) ((x) << 16) 296 # define SSTU_MASK (0xf << 16) 297 298 #define CG_DISPLAY_GAP_CNTL 0x20a 299 # define DISP1_GAP(x) ((x) << 0) 300 # define DISP1_GAP_MASK (3 << 0) 301 # define DISP2_GAP(x) ((x) << 2) 302 # define DISP2_GAP_MASK (3 << 2) 303 # define VBI_TIMER_COUNT(x) ((x) << 4) 304 # define VBI_TIMER_COUNT_MASK (0x3fff << 4) 305 # define VBI_TIMER_UNIT(x) ((x) << 20) 306 # define VBI_TIMER_UNIT_MASK (7 << 20) 307 # define DISP1_GAP_MCHG(x) ((x) << 24) 308 # define DISP1_GAP_MCHG_MASK (3 << 24) 309 # define DISP2_GAP_MCHG(x) ((x) << 26) 310 # define DISP2_GAP_MCHG_MASK (3 << 26) 311 312 #define CG_ULV_CONTROL 0x21e 313 #define CG_ULV_PARAMETER 0x21f 314 315 #define SMC_SCRATCH0 0x221 316 317 #define CG_CAC_CTRL 0x22e 318 # define CAC_WINDOW(x) ((x) << 0) 319 # define CAC_WINDOW_MASK 0x00ffffff 320 321 #define DMIF_ADDR_CONFIG 0x2F5 322 323 #define DMIF_ADDR_CALC 0x300 324 325 #define PIPE0_DMIF_BUFFER_CONTROL 0x0328 326 # define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0) 327 # define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4) 328 329 #define SRBM_STATUS 0x394 330 #define GRBM_RQ_PENDING (1 << 5) 331 #define VMC_BUSY (1 << 8) 332 #define MCB_BUSY (1 << 9) 333 #define MCB_NON_DISPLAY_BUSY (1 << 10) 334 #define MCC_BUSY (1 << 11) 335 #define MCD_BUSY (1 << 12) 336 #define SEM_BUSY (1 << 14) 337 #define IH_BUSY (1 << 17) 338 339 #define SRBM_SOFT_RESET 0x398 340 #define SOFT_RESET_BIF (1 << 1) 341 #define SOFT_RESET_DC (1 << 5) 342 #define SOFT_RESET_DMA1 (1 << 6) 343 #define SOFT_RESET_GRBM (1 << 8) 344 #define SOFT_RESET_HDP (1 << 9) 345 #define SOFT_RESET_IH (1 << 10) 346 #define SOFT_RESET_MC (1 << 11) 347 #define SOFT_RESET_ROM (1 << 14) 348 #define SOFT_RESET_SEM (1 << 15) 349 #define SOFT_RESET_VMC (1 << 17) 350 #define SOFT_RESET_DMA (1 << 20) 351 #define SOFT_RESET_TST (1 << 21) 352 #define SOFT_RESET_REGBB (1 << 22) 353 #define SOFT_RESET_ORB (1 << 23) 354 355 #define CC_SYS_RB_BACKEND_DISABLE 0x3A0 356 #define GC_USER_SYS_RB_BACKEND_DISABLE 0x3A1 357 358 #define SRBM_READ_ERROR 0x3A6 359 #define SRBM_INT_CNTL 0x3A8 360 #define SRBM_INT_ACK 0x3AA 361 362 #define SRBM_STATUS2 0x3B1 363 #define DMA_BUSY (1 << 5) 364 #define DMA1_BUSY (1 << 6) 365 366 #define VM_L2_CNTL 0x500 367 #define ENABLE_L2_CACHE (1 << 0) 368 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 369 #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2) 370 #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4) 371 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 372 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 373 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15) 374 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19) 375 #define VM_L2_CNTL2 0x501 376 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 377 #define INVALIDATE_L2_CACHE (1 << 1) 378 #define INVALIDATE_CACHE_MODE(x) ((x) << 26) 379 #define INVALIDATE_PTE_AND_PDE_CACHES 0 380 #define INVALIDATE_ONLY_PTE_CACHES 1 381 #define INVALIDATE_ONLY_PDE_CACHES 2 382 #define VM_L2_CNTL3 0x502 383 #define BANK_SELECT(x) ((x) << 0) 384 #define L2_CACHE_UPDATE_MODE(x) ((x) << 6) 385 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 386 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 387 #define VM_L2_STATUS 0x503 388 #define L2_BUSY (1 << 0) 389 #define VM_CONTEXT0_CNTL 0x504 390 #define ENABLE_CONTEXT (1 << 0) 391 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 392 #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) 393 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 394 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) 395 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) 396 #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) 397 #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) 398 #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) 399 #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) 400 #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) 401 #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) 402 #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) 403 #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) 404 #define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24) 405 #define VM_CONTEXT1_CNTL 0x505 406 #define VM_CONTEXT0_CNTL2 0x50C 407 #define VM_CONTEXT1_CNTL2 0x50D 408 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x50E 409 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x50F 410 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x510 411 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x511 412 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x512 413 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x513 414 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x514 415 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x515 416 417 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x53f 418 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x537 419 #define PROTECTIONS_MASK (0xf << 0) 420 #define PROTECTIONS_SHIFT 0 421 /* bit 0: range 422 * bit 1: pde0 423 * bit 2: valid 424 * bit 3: read 425 * bit 4: write 426 */ 427 #define MEMORY_CLIENT_ID_MASK (0xff << 12) 428 #define MEMORY_CLIENT_ID_SHIFT 12 429 #define MEMORY_CLIENT_RW_MASK (1 << 24) 430 #define MEMORY_CLIENT_RW_SHIFT 24 431 #define FAULT_VMID_MASK (0xf << 25) 432 #define FAULT_VMID_SHIFT 25 433 434 #define VM_INVALIDATE_REQUEST 0x51E 435 #define VM_INVALIDATE_RESPONSE 0x51F 436 437 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x546 438 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x547 439 440 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x54F 441 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x550 442 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x551 443 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x552 444 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x553 445 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x554 446 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x555 447 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x556 448 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x557 449 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x558 450 451 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x55F 452 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x560 453 454 #define VM_L2_CG 0x570 455 #define MC_CG_ENABLE (1 << 18) 456 #define MC_LS_ENABLE (1 << 19) 457 458 #define MC_SHARED_CHMAP 0x801 459 #define NOOFCHAN_SHIFT 12 460 #define NOOFCHAN_MASK 0x0000f000 461 #define MC_SHARED_CHREMAP 0x802 462 463 #define MC_VM_FB_LOCATION 0x809 464 #define MC_VM_AGP_TOP 0x80A 465 #define MC_VM_AGP_BOT 0x80B 466 #define MC_VM_AGP_BASE 0x80C 467 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x80D 468 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x80E 469 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x80F 470 471 #define MC_VM_MX_L1_TLB_CNTL 0x819 472 #define ENABLE_L1_TLB (1 << 0) 473 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 474 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 475 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 476 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 477 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 478 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 479 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 480 481 #define MC_SHARED_BLACKOUT_CNTL 0x82B 482 483 #define MC_HUB_MISC_HUB_CG 0x82E 484 #define MC_HUB_MISC_VM_CG 0x82F 485 486 #define MC_HUB_MISC_SIP_CG 0x830 487 488 #define MC_XPB_CLK_GAT 0x91E 489 490 #define MC_CITF_MISC_RD_CG 0x992 491 #define MC_CITF_MISC_WR_CG 0x993 492 #define MC_CITF_MISC_VM_CG 0x994 493 494 #define MC_ARB_RAMCFG 0x9D8 495 #define NOOFBANK_SHIFT 0 496 #define NOOFBANK_MASK 0x00000003 497 #define NOOFRANK_SHIFT 2 498 #define NOOFRANK_MASK 0x00000004 499 #define NOOFROWS_SHIFT 3 500 #define NOOFROWS_MASK 0x00000038 501 #define NOOFCOLS_SHIFT 6 502 #define NOOFCOLS_MASK 0x000000C0 503 #define CHANSIZE_SHIFT 8 504 #define CHANSIZE_MASK 0x00000100 505 #define CHANSIZE_OVERRIDE (1 << 11) 506 #define NOOFGROUPS_SHIFT 12 507 #define NOOFGROUPS_MASK 0x00001000 508 509 #define MC_ARB_DRAM_TIMING 0x9DD 510 #define MC_ARB_DRAM_TIMING2 0x9DE 511 512 #define MC_ARB_BURST_TIME 0xA02 513 #define STATE0(x) ((x) << 0) 514 #define STATE0_MASK (0x1f << 0) 515 #define STATE0_SHIFT 0 516 #define STATE1(x) ((x) << 5) 517 #define STATE1_MASK (0x1f << 5) 518 #define STATE1_SHIFT 5 519 #define STATE2(x) ((x) << 10) 520 #define STATE2_MASK (0x1f << 10) 521 #define STATE2_SHIFT 10 522 #define STATE3(x) ((x) << 15) 523 #define STATE3_MASK (0x1f << 15) 524 #define STATE3_SHIFT 15 525 526 #define MC_SEQ_TRAIN_WAKEUP_CNTL 0xA3A 527 #define TRAIN_DONE_D0 (1 << 30) 528 #define TRAIN_DONE_D1 (1 << 31) 529 530 #define MC_SEQ_SUP_CNTL 0xA32 531 #define RUN_MASK (1 << 0) 532 #define MC_SEQ_SUP_PGM 0xA33 533 #define MC_PMG_AUTO_CMD 0xA34 534 535 #define MC_IO_PAD_CNTL_D0 0xA74 536 #define MEM_FALL_OUT_CMD (1 << 8) 537 538 #define MC_SEQ_RAS_TIMING 0xA28 539 #define MC_SEQ_CAS_TIMING 0xA29 540 #define MC_SEQ_MISC_TIMING 0xA2A 541 #define MC_SEQ_MISC_TIMING2 0xA2B 542 #define MC_SEQ_PMG_TIMING 0xA2C 543 #define MC_SEQ_RD_CTL_D0 0xA2D 544 #define MC_SEQ_RD_CTL_D1 0xA2E 545 #define MC_SEQ_WR_CTL_D0 0xA2F 546 #define MC_SEQ_WR_CTL_D1 0xA30 547 548 #define MC_SEQ_MISC0 0xA80 549 #define MC_SEQ_MISC0_VEN_ID_SHIFT 8 550 #define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00 551 #define MC_SEQ_MISC0_VEN_ID_VALUE 3 552 #define MC_SEQ_MISC0_REV_ID_SHIFT 12 553 #define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000 554 #define MC_SEQ_MISC0_REV_ID_VALUE 1 555 #define MC_SEQ_MISC0_GDDR5_SHIFT 28 556 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 557 #define MC_SEQ_MISC0_GDDR5_VALUE 5 558 #define MC_SEQ_MISC1 0xA81 559 #define MC_SEQ_RESERVE_M 0xA82 560 #define MC_PMG_CMD_EMRS 0xA83 561 562 #define MC_SEQ_IO_DEBUG_INDEX 0xA91 563 #define MC_SEQ_IO_DEBUG_DATA 0xA92 564 565 #define MC_SEQ_MISC5 0xA95 566 #define MC_SEQ_MISC6 0xA96 567 568 #define MC_SEQ_MISC7 0xA99 569 570 #define MC_SEQ_RAS_TIMING_LP 0xA9B 571 #define MC_SEQ_CAS_TIMING_LP 0xA9C 572 #define MC_SEQ_MISC_TIMING_LP 0xA9D 573 #define MC_SEQ_MISC_TIMING2_LP 0xA9E 574 #define MC_SEQ_WR_CTL_D0_LP 0xA9F 575 #define MC_SEQ_WR_CTL_D1_LP 0xAA0 576 #define MC_SEQ_PMG_CMD_EMRS_LP 0xAA1 577 #define MC_SEQ_PMG_CMD_MRS_LP 0xAA2 578 579 #define MC_PMG_CMD_MRS 0xAAB 580 581 #define MC_SEQ_RD_CTL_D0_LP 0xAC7 582 #define MC_SEQ_RD_CTL_D1_LP 0xAC8 583 584 #define MC_PMG_CMD_MRS1 0xAD1 585 #define MC_SEQ_PMG_CMD_MRS1_LP 0xAD2 586 #define MC_SEQ_PMG_TIMING_LP 0xAD3 587 588 #define MC_SEQ_WR_CTL_2 0xAD5 589 #define MC_SEQ_WR_CTL_2_LP 0xAD6 590 #define MC_PMG_CMD_MRS2 0xAD7 591 #define MC_SEQ_PMG_CMD_MRS2_LP 0xAD8 592 593 #define MCLK_PWRMGT_CNTL 0xAE8 594 # define DLL_SPEED(x) ((x) << 0) 595 # define DLL_SPEED_MASK (0x1f << 0) 596 # define DLL_READY (1 << 6) 597 # define MC_INT_CNTL (1 << 7) 598 # define MRDCK0_PDNB (1 << 8) 599 # define MRDCK1_PDNB (1 << 9) 600 # define MRDCK0_RESET (1 << 16) 601 # define MRDCK1_RESET (1 << 17) 602 # define DLL_READY_READ (1 << 24) 603 #define DLL_CNTL 0xAE9 604 # define MRDCK0_BYPASS (1 << 24) 605 # define MRDCK1_BYPASS (1 << 25) 606 607 #define MPLL_CNTL_MODE 0xAEC 608 # define MPLL_MCLK_SEL (1 << 11) 609 #define MPLL_FUNC_CNTL 0xAED 610 #define BWCTRL(x) ((x) << 20) 611 #define BWCTRL_MASK (0xff << 20) 612 #define MPLL_FUNC_CNTL_1 0xAEE 613 #define VCO_MODE(x) ((x) << 0) 614 #define VCO_MODE_MASK (3 << 0) 615 #define CLKFRAC(x) ((x) << 4) 616 #define CLKFRAC_MASK (0xfff << 4) 617 #define CLKF(x) ((x) << 16) 618 #define CLKF_MASK (0xfff << 16) 619 #define MPLL_FUNC_CNTL_2 0xAEF 620 #define MPLL_AD_FUNC_CNTL 0xAF0 621 #define YCLK_POST_DIV(x) ((x) << 0) 622 #define YCLK_POST_DIV_MASK (7 << 0) 623 #define MPLL_DQ_FUNC_CNTL 0xAF1 624 #define YCLK_SEL(x) ((x) << 4) 625 #define YCLK_SEL_MASK (1 << 4) 626 627 #define MPLL_SS1 0xAF3 628 #define CLKV(x) ((x) << 0) 629 #define CLKV_MASK (0x3ffffff << 0) 630 #define MPLL_SS2 0xAF4 631 #define CLKS(x) ((x) << 0) 632 #define CLKS_MASK (0xfff << 0) 633 634 #define HDP_HOST_PATH_CNTL 0xB00 635 #define CLOCK_GATING_DIS (1 << 23) 636 #define HDP_NONSURFACE_BASE 0xB01 637 #define HDP_NONSURFACE_INFO 0xB02 638 #define HDP_NONSURFACE_SIZE 0xB03 639 640 #define HDP_DEBUG0 0xBCC 641 642 #define HDP_ADDR_CONFIG 0xBD2 643 #define HDP_MISC_CNTL 0xBD3 644 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 645 #define HDP_MEM_POWER_LS 0xBD4 646 #define HDP_LS_ENABLE (1 << 0) 647 648 #define ATC_MISC_CG 0xCD4 649 650 #define IH_RB_CNTL 0xF80 651 # define IH_RB_ENABLE (1 << 0) 652 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ 653 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 654 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 655 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 656 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 657 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 658 #define IH_RB_BASE 0xF81 659 #define IH_RB_RPTR 0xF82 660 #define IH_RB_WPTR 0xF83 661 # define RB_OVERFLOW (1 << 0) 662 # define WPTR_OFFSET_MASK 0x3fffc 663 #define IH_RB_WPTR_ADDR_HI 0xF84 664 #define IH_RB_WPTR_ADDR_LO 0xF85 665 #define IH_CNTL 0xF86 666 # define ENABLE_INTR (1 << 0) 667 # define IH_MC_SWAP(x) ((x) << 1) 668 # define IH_MC_SWAP_NONE 0 669 # define IH_MC_SWAP_16BIT 1 670 # define IH_MC_SWAP_32BIT 2 671 # define IH_MC_SWAP_64BIT 3 672 # define RPTR_REARM (1 << 4) 673 # define MC_WRREQ_CREDIT(x) ((x) << 15) 674 # define MC_WR_CLEAN_CNT(x) ((x) << 20) 675 # define MC_VMID(x) ((x) << 25) 676 677 #define CONFIG_MEMSIZE 0x150A 678 679 #define INTERRUPT_CNTL 0x151A 680 # define IH_DUMMY_RD_OVERRIDE (1 << 0) 681 # define IH_DUMMY_RD_EN (1 << 1) 682 # define IH_REQ_NONSNOOP_EN (1 << 3) 683 # define GEN_IH_INT_EN (1 << 8) 684 #define INTERRUPT_CNTL2 0x151B 685 686 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x1520 687 688 #define BIF_FB_EN 0x1524 689 #define FB_READ_EN (1 << 0) 690 #define FB_WRITE_EN (1 << 1) 691 692 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x1528 693 694 /* DCE6 ELD audio interface */ 695 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28 /* LPCM */ 696 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29 /* AC3 */ 697 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2A /* MPEG1 */ 698 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2B /* MP3 */ 699 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2C /* MPEG2 */ 700 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2D /* AAC */ 701 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2E /* DTS */ 702 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2F /* ATRAC */ 703 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30 /* one bit audio - leave at 0 (default) */ 704 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31 /* Dolby Digital */ 705 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32 /* DTS-HD */ 706 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33 /* MAT-MLP */ 707 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34 /* DTS */ 708 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35 /* WMA Pro */ 709 # define MAX_CHANNELS(x) (((x) & 0x7) << 0) 710 /* max channels minus one. 7 = 8 channels */ 711 # define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8) 712 # define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16) 713 # define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */ 714 /* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO 715 * bit0 = 32 kHz 716 * bit1 = 44.1 kHz 717 * bit2 = 48 kHz 718 * bit3 = 88.2 kHz 719 * bit4 = 96 kHz 720 * bit5 = 176.4 kHz 721 * bit6 = 192 kHz 722 */ 723 724 #define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37 725 # define VIDEO_LIPSYNC(x) (((x) & 0xff) << 0) 726 # define AUDIO_LIPSYNC(x) (((x) & 0xff) << 8) 727 /* VIDEO_LIPSYNC, AUDIO_LIPSYNC 728 * 0 = invalid 729 * x = legal delay value 730 * 255 = sync not supported 731 */ 732 #define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38 733 # define HBR_CAPABLE (1 << 0) /* enabled by default */ 734 735 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a 736 # define MANUFACTURER_ID(x) (((x) & 0xffff) << 0) 737 # define PRODUCT_ID(x) (((x) & 0xffff) << 16) 738 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b 739 # define SINK_DESCRIPTION_LEN(x) (((x) & 0xff) << 0) 740 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c 741 # define PORT_ID0(x) (((x) & 0xffffffff) << 0) 742 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d 743 # define PORT_ID1(x) (((x) & 0xffffffff) << 0) 744 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e 745 # define DESCRIPTION0(x) (((x) & 0xff) << 0) 746 # define DESCRIPTION1(x) (((x) & 0xff) << 8) 747 # define DESCRIPTION2(x) (((x) & 0xff) << 16) 748 # define DESCRIPTION3(x) (((x) & 0xff) << 24) 749 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f 750 # define DESCRIPTION4(x) (((x) & 0xff) << 0) 751 # define DESCRIPTION5(x) (((x) & 0xff) << 8) 752 # define DESCRIPTION6(x) (((x) & 0xff) << 16) 753 # define DESCRIPTION7(x) (((x) & 0xff) << 24) 754 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40 755 # define DESCRIPTION8(x) (((x) & 0xff) << 0) 756 # define DESCRIPTION9(x) (((x) & 0xff) << 8) 757 # define DESCRIPTION10(x) (((x) & 0xff) << 16) 758 # define DESCRIPTION11(x) (((x) & 0xff) << 24) 759 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41 760 # define DESCRIPTION12(x) (((x) & 0xff) << 0) 761 # define DESCRIPTION13(x) (((x) & 0xff) << 8) 762 # define DESCRIPTION14(x) (((x) & 0xff) << 16) 763 # define DESCRIPTION15(x) (((x) & 0xff) << 24) 764 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42 765 # define DESCRIPTION16(x) (((x) & 0xff) << 0) 766 # define DESCRIPTION17(x) (((x) & 0xff) << 8) 767 768 #define AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54 769 # define AUDIO_ENABLED (1 << 31) 770 771 #define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 772 #define PORT_CONNECTIVITY_MASK (3 << 30) 773 #define PORT_CONNECTIVITY_SHIFT 30 774 775 #define DC_LB_MEMORY_SPLIT 0x1AC3 776 #define DC_LB_MEMORY_CONFIG(x) ((x) << 20) 777 778 #define PRIORITY_A_CNT 0x1AC6 779 #define PRIORITY_MARK_MASK 0x7fff 780 #define PRIORITY_OFF (1 << 16) 781 #define PRIORITY_ALWAYS_ON (1 << 20) 782 #define PRIORITY_B_CNT 0x1AC7 783 784 #define DPG_PIPE_ARBITRATION_CONTROL3 0x1B32 785 # define LATENCY_WATERMARK_MASK(x) ((x) << 16) 786 #define DPG_PIPE_LATENCY_CONTROL 0x1B33 787 # define LATENCY_LOW_WATERMARK(x) ((x) << 0) 788 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 789 790 /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */ 791 #define VLINE_STATUS 0x1AEE 792 # define VLINE_OCCURRED (1 << 0) 793 # define VLINE_ACK (1 << 4) 794 # define VLINE_STAT (1 << 12) 795 # define VLINE_INTERRUPT (1 << 16) 796 # define VLINE_INTERRUPT_TYPE (1 << 17) 797 /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */ 798 #define VBLANK_STATUS 0x1AEF 799 # define VBLANK_OCCURRED (1 << 0) 800 # define VBLANK_ACK (1 << 4) 801 # define VBLANK_STAT (1 << 12) 802 # define VBLANK_INTERRUPT (1 << 16) 803 # define VBLANK_INTERRUPT_TYPE (1 << 17) 804 805 /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */ 806 #define INT_MASK 0x1AD0 807 # define VBLANK_INT_MASK (1 << 0) 808 # define VLINE_INT_MASK (1 << 4) 809 810 #define DISP_INTERRUPT_STATUS 0x183D 811 # define LB_D1_VLINE_INTERRUPT (1 << 2) 812 # define LB_D1_VBLANK_INTERRUPT (1 << 3) 813 # define DC_HPD1_INTERRUPT (1 << 17) 814 # define DC_HPD1_RX_INTERRUPT (1 << 18) 815 # define DACA_AUTODETECT_INTERRUPT (1 << 22) 816 # define DACB_AUTODETECT_INTERRUPT (1 << 23) 817 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 818 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 819 #define DISP_INTERRUPT_STATUS_CONTINUE 0x183E 820 # define LB_D2_VLINE_INTERRUPT (1 << 2) 821 # define LB_D2_VBLANK_INTERRUPT (1 << 3) 822 # define DC_HPD2_INTERRUPT (1 << 17) 823 # define DC_HPD2_RX_INTERRUPT (1 << 18) 824 # define DISP_TIMER_INTERRUPT (1 << 24) 825 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x183F 826 # define LB_D3_VLINE_INTERRUPT (1 << 2) 827 # define LB_D3_VBLANK_INTERRUPT (1 << 3) 828 # define DC_HPD3_INTERRUPT (1 << 17) 829 # define DC_HPD3_RX_INTERRUPT (1 << 18) 830 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x1840 831 # define LB_D4_VLINE_INTERRUPT (1 << 2) 832 # define LB_D4_VBLANK_INTERRUPT (1 << 3) 833 # define DC_HPD4_INTERRUPT (1 << 17) 834 # define DC_HPD4_RX_INTERRUPT (1 << 18) 835 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x1853 836 # define LB_D5_VLINE_INTERRUPT (1 << 2) 837 # define LB_D5_VBLANK_INTERRUPT (1 << 3) 838 # define DC_HPD5_INTERRUPT (1 << 17) 839 # define DC_HPD5_RX_INTERRUPT (1 << 18) 840 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x1854 841 # define LB_D6_VLINE_INTERRUPT (1 << 2) 842 # define LB_D6_VBLANK_INTERRUPT (1 << 3) 843 # define DC_HPD6_INTERRUPT (1 << 17) 844 # define DC_HPD6_RX_INTERRUPT (1 << 18) 845 846 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ 847 #define GRPH_INT_STATUS 0x1A16 848 # define GRPH_PFLIP_INT_OCCURRED (1 << 0) 849 # define GRPH_PFLIP_INT_CLEAR (1 << 8) 850 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ 851 #define GRPH_INT_CONTROL 0x1A17 852 # define GRPH_PFLIP_INT_MASK (1 << 0) 853 # define GRPH_PFLIP_INT_TYPE (1 << 8) 854 855 #define DAC_AUTODETECT_INT_CONTROL 0x19F2 856 857 #define DC_HPD1_INT_STATUS 0x1807 858 #define DC_HPD2_INT_STATUS 0x180A 859 #define DC_HPD3_INT_STATUS 0x180D 860 #define DC_HPD4_INT_STATUS 0x1810 861 #define DC_HPD5_INT_STATUS 0x1813 862 #define DC_HPD6_INT_STATUS 0x1816 863 # define DC_HPDx_INT_STATUS (1 << 0) 864 # define DC_HPDx_SENSE (1 << 1) 865 # define DC_HPDx_RX_INT_STATUS (1 << 8) 866 867 #define DC_HPD1_INT_CONTROL 0x1808 868 #define DC_HPD2_INT_CONTROL 0x180B 869 #define DC_HPD3_INT_CONTROL 0x180E 870 #define DC_HPD4_INT_CONTROL 0x1811 871 #define DC_HPD5_INT_CONTROL 0x1814 872 #define DC_HPD6_INT_CONTROL 0x1817 873 # define DC_HPDx_INT_ACK (1 << 0) 874 # define DC_HPDx_INT_POLARITY (1 << 8) 875 # define DC_HPDx_INT_EN (1 << 16) 876 # define DC_HPDx_RX_INT_ACK (1 << 20) 877 # define DC_HPDx_RX_INT_EN (1 << 24) 878 879 #define DC_HPD1_CONTROL 0x1809 880 #define DC_HPD2_CONTROL 0x180C 881 #define DC_HPD3_CONTROL 0x180F 882 #define DC_HPD4_CONTROL 0x1812 883 #define DC_HPD5_CONTROL 0x1815 884 #define DC_HPD6_CONTROL 0x1818 885 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 886 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 887 # define DC_HPDx_EN (1 << 28) 888 889 #define DPG_PIPE_STUTTER_CONTROL 0x1B35 890 # define STUTTER_ENABLE (1 << 0) 891 892 /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ 893 #define CRTC_STATUS_FRAME_COUNT 0x1BA6 894 895 /* Audio clocks */ 896 #define DCCG_AUDIO_DTO0_PHASE 0x05b0 897 #define DCCG_AUDIO_DTO0_MODULE 0x05b4 898 #define DCCG_AUDIO_DTO1_PHASE 0x05c0 899 #define DCCG_AUDIO_DTO1_MODULE 0x05c4 900 901 #define GRBM_CNTL 0x2000 902 #define GRBM_READ_TIMEOUT(x) ((x) << 0) 903 904 #define GRBM_STATUS2 0x2002 905 #define RLC_RQ_PENDING (1 << 0) 906 #define RLC_BUSY (1 << 8) 907 #define TC_BUSY (1 << 9) 908 909 #define GRBM_STATUS 0x2004 910 #define CMDFIFO_AVAIL_MASK 0x0000000F 911 #define RING2_RQ_PENDING (1 << 4) 912 #define SRBM_RQ_PENDING (1 << 5) 913 #define RING1_RQ_PENDING (1 << 6) 914 #define CF_RQ_PENDING (1 << 7) 915 #define PF_RQ_PENDING (1 << 8) 916 #define GDS_DMA_RQ_PENDING (1 << 9) 917 #define GRBM_EE_BUSY (1 << 10) 918 #define DB_CLEAN (1 << 12) 919 #define CB_CLEAN (1 << 13) 920 #define TA_BUSY (1 << 14) 921 #define GDS_BUSY (1 << 15) 922 #define VGT_BUSY (1 << 17) 923 #define IA_BUSY_NO_DMA (1 << 18) 924 #define IA_BUSY (1 << 19) 925 #define SX_BUSY (1 << 20) 926 #define SPI_BUSY (1 << 22) 927 #define BCI_BUSY (1 << 23) 928 #define SC_BUSY (1 << 24) 929 #define PA_BUSY (1 << 25) 930 #define DB_BUSY (1 << 26) 931 #define CP_COHERENCY_BUSY (1 << 28) 932 #define CP_BUSY (1 << 29) 933 #define CB_BUSY (1 << 30) 934 #define GUI_ACTIVE (1 << 31) 935 #define GRBM_STATUS_SE0 0x2005 936 #define GRBM_STATUS_SE1 0x2006 937 #define SE_DB_CLEAN (1 << 1) 938 #define SE_CB_CLEAN (1 << 2) 939 #define SE_BCI_BUSY (1 << 22) 940 #define SE_VGT_BUSY (1 << 23) 941 #define SE_PA_BUSY (1 << 24) 942 #define SE_TA_BUSY (1 << 25) 943 #define SE_SX_BUSY (1 << 26) 944 #define SE_SPI_BUSY (1 << 27) 945 #define SE_SC_BUSY (1 << 29) 946 #define SE_DB_BUSY (1 << 30) 947 #define SE_CB_BUSY (1 << 31) 948 949 #define GRBM_INT_CNTL 0x2018 950 # define RDERR_INT_ENABLE (1 << 0) 951 # define GUI_IDLE_INT_ENABLE (1 << 19) 952 953 #define CP_STRMOUT_CNTL 0x213F 954 #define SCRATCH_REG0 0x2140 955 #define SCRATCH_REG1 0x2141 956 #define SCRATCH_REG2 0x2142 957 #define SCRATCH_REG3 0x2143 958 #define SCRATCH_REG4 0x2144 959 #define SCRATCH_REG5 0x2145 960 #define SCRATCH_REG6 0x2146 961 #define SCRATCH_REG7 0x2147 962 963 #define SCRATCH_UMSK 0x2150 964 #define SCRATCH_ADDR 0x2151 965 966 #define CP_SEM_WAIT_TIMER 0x216F 967 968 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x2172 969 970 #define CP_ME_CNTL 0x21B6 971 #define CP_CE_HALT (1 << 24) 972 #define CP_PFP_HALT (1 << 26) 973 #define CP_ME_HALT (1 << 28) 974 975 #define CP_COHER_CNTL2 0x217A 976 977 #define CP_RB2_RPTR 0x21BE 978 #define CP_RB1_RPTR 0x21BF 979 #define CP_RB0_RPTR 0x21C0 980 #define CP_RB_WPTR_DELAY 0x21C1 981 982 #define CP_QUEUE_THRESHOLDS 0x21D8 983 #define ROQ_IB1_START(x) ((x) << 0) 984 #define ROQ_IB2_START(x) ((x) << 8) 985 #define CP_MEQ_THRESHOLDS 0x21D9 986 #define MEQ1_START(x) ((x) << 0) 987 #define MEQ2_START(x) ((x) << 8) 988 989 #define CP_PERFMON_CNTL 0x21FF 990 991 #define VGT_VTX_VECT_EJECT_REG 0x222C 992 993 #define VGT_ESGS_RING_SIZE 0x2232 994 #define VGT_GSVS_RING_SIZE 0x2233 995 996 #define VGT_GS_VERTEX_REUSE 0x2235 997 998 #define VGT_PRIMITIVE_TYPE 0x2256 999 #define VGT_INDEX_TYPE 0x2257 1000 1001 #define VGT_NUM_INDICES 0x225C 1002 #define VGT_NUM_INSTANCES 0x225D 1003 1004 #define VGT_TF_RING_SIZE 0x2262 1005 1006 #define VGT_HS_OFFCHIP_PARAM 0x226C 1007 1008 #define VGT_TF_MEMORY_BASE 0x226E 1009 1010 #define PA_CL_ENHANCE 0x2285 1011 #define CLIP_VTX_REORDER_ENA (1 << 0) 1012 #define NUM_CLIP_SEQ(x) ((x) << 1) 1013 1014 #define PA_SU_LINE_STIPPLE_VALUE 0x2298 1015 1016 #define PA_SC_LINE_STIPPLE_STATE 0x22C4 1017 1018 #define PA_SC_FORCE_EOV_MAX_CNTS 0x22C9 1019 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 1020 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 1021 1022 #define PA_SC_FIFO_SIZE 0x22F3 1023 #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) 1024 #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) 1025 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) 1026 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) 1027 1028 #define PA_SC_ENHANCE 0x22FC 1029 1030 #define SQ_CONFIG 0x2300 1031 1032 #define SQC_CACHES 0x2302 1033 1034 #define SQ_POWER_THROTTLE 0x2396 1035 #define MIN_POWER(x) ((x) << 0) 1036 #define MIN_POWER_MASK (0x3fff << 0) 1037 #define MIN_POWER_SHIFT 0 1038 #define MAX_POWER(x) ((x) << 16) 1039 #define MAX_POWER_MASK (0x3fff << 16) 1040 #define MAX_POWER_SHIFT 0 1041 #define SQ_POWER_THROTTLE2 0x2397 1042 #define MAX_POWER_DELTA(x) ((x) << 0) 1043 #define MAX_POWER_DELTA_MASK (0x3fff << 0) 1044 #define MAX_POWER_DELTA_SHIFT 0 1045 #define STI_SIZE(x) ((x) << 16) 1046 #define STI_SIZE_MASK (0x3ff << 16) 1047 #define STI_SIZE_SHIFT 16 1048 #define LTI_RATIO(x) ((x) << 27) 1049 #define LTI_RATIO_MASK (0xf << 27) 1050 #define LTI_RATIO_SHIFT 27 1051 1052 #define SX_DEBUG_1 0x2418 1053 1054 #define SPI_STATIC_THREAD_MGMT_1 0x2438 1055 #define SPI_STATIC_THREAD_MGMT_2 0x2439 1056 #define SPI_STATIC_THREAD_MGMT_3 0x243A 1057 #define SPI_PS_MAX_WAVE_ID 0x243B 1058 1059 #define SPI_CONFIG_CNTL 0x2440 1060 1061 #define SPI_CONFIG_CNTL_1 0x244F 1062 #define VTX_DONE_DELAY(x) ((x) << 0) 1063 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 1064 1065 #define CGTS_TCC_DISABLE 0x2452 1066 #define CGTS_USER_TCC_DISABLE 0x2453 1067 #define TCC_DISABLE_MASK 0xFFFF0000 1068 #define TCC_DISABLE_SHIFT 16 1069 #define CGTS_SM_CTRL_REG 0x2454 1070 #define OVERRIDE (1 << 21) 1071 #define LS_OVERRIDE (1 << 22) 1072 1073 #define SPI_LB_CU_MASK 0x24D5 1074 1075 #define TA_CNTL_AUX 0x2542 1076 1077 #define CC_RB_BACKEND_DISABLE 0x263D 1078 #define BACKEND_DISABLE(x) ((x) << 16) 1079 #define GB_ADDR_CONFIG 0x263E 1080 #define NUM_PIPES(x) ((x) << 0) 1081 #define NUM_PIPES_MASK 0x00000007 1082 #define NUM_PIPES_SHIFT 0 1083 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 1084 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 1085 #define PIPE_INTERLEAVE_SIZE_SHIFT 4 1086 #define NUM_SHADER_ENGINES(x) ((x) << 12) 1087 #define NUM_SHADER_ENGINES_MASK 0x00003000 1088 #define NUM_SHADER_ENGINES_SHIFT 12 1089 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 1090 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 1091 #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 1092 #define NUM_GPUS(x) ((x) << 20) 1093 #define NUM_GPUS_MASK 0x00700000 1094 #define NUM_GPUS_SHIFT 20 1095 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 1096 #define MULTI_GPU_TILE_SIZE_MASK 0x03000000 1097 #define MULTI_GPU_TILE_SIZE_SHIFT 24 1098 #define ROW_SIZE(x) ((x) << 28) 1099 #define ROW_SIZE_MASK 0x30000000 1100 #define ROW_SIZE_SHIFT 28 1101 1102 #define CB_PERFCOUNTER0_SELECT0 0x2688 1103 #define CB_PERFCOUNTER0_SELECT1 0x2689 1104 #define CB_PERFCOUNTER1_SELECT0 0x268A 1105 #define CB_PERFCOUNTER1_SELECT1 0x268B 1106 #define CB_PERFCOUNTER2_SELECT0 0x268C 1107 #define CB_PERFCOUNTER2_SELECT1 0x268D 1108 #define CB_PERFCOUNTER3_SELECT0 0x268E 1109 #define CB_PERFCOUNTER3_SELECT1 0x268F 1110 1111 #define CB_CGTT_SCLK_CTRL 0x2698 1112 1113 #define TCP_CHAN_STEER_LO 0x2B03 1114 #define TCP_CHAN_STEER_HI 0x2B94 1115 1116 #define CP_RB0_BASE 0x3040 1117 #define CP_RB0_CNTL 0x3041 1118 #define RB_BUFSZ(x) ((x) << 0) 1119 #define RB_BLKSZ(x) ((x) << 8) 1120 #define BUF_SWAP_32BIT (2 << 16) 1121 #define RB_NO_UPDATE (1 << 27) 1122 #define RB_RPTR_WR_ENA (1 << 31) 1123 1124 #define CP_RB0_RPTR_ADDR 0x3043 1125 #define CP_RB0_RPTR_ADDR_HI 0x3044 1126 #define CP_RB0_WPTR 0x3045 1127 1128 #define CP_PFP_UCODE_ADDR 0x3054 1129 #define CP_PFP_UCODE_DATA 0x3055 1130 #define CP_ME_RAM_RADDR 0x3056 1131 #define CP_ME_RAM_WADDR 0x3057 1132 #define CP_ME_RAM_DATA 0x3058 1133 1134 #define CP_CE_UCODE_ADDR 0x305A 1135 #define CP_CE_UCODE_DATA 0x305B 1136 1137 #define CP_RB1_BASE 0x3060 1138 #define CP_RB1_CNTL 0x3061 1139 #define CP_RB1_RPTR_ADDR 0x3062 1140 #define CP_RB1_RPTR_ADDR_HI 0x3063 1141 #define CP_RB1_WPTR 0x3064 1142 #define CP_RB2_BASE 0x3065 1143 #define CP_RB2_CNTL 0x3066 1144 #define CP_RB2_RPTR_ADDR 0x3067 1145 #define CP_RB2_RPTR_ADDR_HI 0x3068 1146 #define CP_RB2_WPTR 0x3069 1147 #define CP_INT_CNTL_RING0 0x306A 1148 #define CP_INT_CNTL_RING1 0x306B 1149 #define CP_INT_CNTL_RING2 0x306C 1150 # define CNTX_BUSY_INT_ENABLE (1 << 19) 1151 # define CNTX_EMPTY_INT_ENABLE (1 << 20) 1152 # define WAIT_MEM_SEM_INT_ENABLE (1 << 21) 1153 # define TIME_STAMP_INT_ENABLE (1 << 26) 1154 # define CP_RINGID2_INT_ENABLE (1 << 29) 1155 # define CP_RINGID1_INT_ENABLE (1 << 30) 1156 # define CP_RINGID0_INT_ENABLE (1 << 31) 1157 #define CP_INT_STATUS_RING0 0x306D 1158 #define CP_INT_STATUS_RING1 0x306E 1159 #define CP_INT_STATUS_RING2 0x306F 1160 # define WAIT_MEM_SEM_INT_STAT (1 << 21) 1161 # define TIME_STAMP_INT_STAT (1 << 26) 1162 # define CP_RINGID2_INT_STAT (1 << 29) 1163 # define CP_RINGID1_INT_STAT (1 << 30) 1164 # define CP_RINGID0_INT_STAT (1 << 31) 1165 1166 // #define PA_SC_RASTER_CONFIG 0xA0D4 1167 # define RB_XSEL2(x) ((x) << 4) 1168 # define RB_XSEL2_MASK (0x3 << 4) 1169 # define RB_XSEL (1 << 6) 1170 # define RB_YSEL (1 << 7) 1171 # define PKR_MAP(x) ((x) << 8) 1172 # define PKR_XSEL(x) ((x) << 10) 1173 # define PKR_XSEL_MASK (0x3 << 10) 1174 # define PKR_YSEL(x) ((x) << 12) 1175 # define PKR_YSEL_MASK (0x3 << 12) 1176 # define SC_MAP(x) ((x) << 16) 1177 # define SC_MAP_MASK (0x3 << 16) 1178 # define SC_XSEL(x) ((x) << 18) 1179 # define SC_XSEL_MASK (0x3 << 18) 1180 # define SC_YSEL(x) ((x) << 20) 1181 # define SC_YSEL_MASK (0x3 << 20) 1182 # define SE_MAP(x) ((x) << 24) 1183 # define SE_XSEL(x) ((x) << 26) 1184 # define SE_XSEL_MASK (0x3 << 26) 1185 # define SE_YSEL(x) ((x) << 28) 1186 # define SE_YSEL_MASK (0x3 << 28) 1187 1188 /* PIF PHY0 registers idx/data 0x8/0xc */ 1189 #define PB0_PIF_CNTL 0x10 1190 # define LS2_EXIT_TIME(x) ((x) << 17) 1191 # define LS2_EXIT_TIME_MASK (0x7 << 17) 1192 # define LS2_EXIT_TIME_SHIFT 17 1193 #define PB0_PIF_PAIRING 0x11 1194 # define MULTI_PIF (1 << 25) 1195 #define PB0_PIF_PWRDOWN_0 0x12 1196 # define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7) 1197 # define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7) 1198 # define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7 1199 # define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10) 1200 # define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10) 1201 # define PLL_POWER_STATE_IN_OFF_0_SHIFT 10 1202 # define PLL_RAMP_UP_TIME_0(x) ((x) << 24) 1203 # define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24) 1204 # define PLL_RAMP_UP_TIME_0_SHIFT 24 1205 #define PB0_PIF_PWRDOWN_1 0x13 1206 # define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7) 1207 # define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7) 1208 # define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7 1209 # define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10) 1210 # define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10) 1211 # define PLL_POWER_STATE_IN_OFF_1_SHIFT 10 1212 # define PLL_RAMP_UP_TIME_1(x) ((x) << 24) 1213 # define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24) 1214 # define PLL_RAMP_UP_TIME_1_SHIFT 24 1215 1216 #define PB0_PIF_PWRDOWN_2 0x17 1217 # define PLL_POWER_STATE_IN_TXS2_2(x) ((x) << 7) 1218 # define PLL_POWER_STATE_IN_TXS2_2_MASK (0x7 << 7) 1219 # define PLL_POWER_STATE_IN_TXS2_2_SHIFT 7 1220 # define PLL_POWER_STATE_IN_OFF_2(x) ((x) << 10) 1221 # define PLL_POWER_STATE_IN_OFF_2_MASK (0x7 << 10) 1222 # define PLL_POWER_STATE_IN_OFF_2_SHIFT 10 1223 # define PLL_RAMP_UP_TIME_2(x) ((x) << 24) 1224 # define PLL_RAMP_UP_TIME_2_MASK (0x7 << 24) 1225 # define PLL_RAMP_UP_TIME_2_SHIFT 24 1226 #define PB0_PIF_PWRDOWN_3 0x18 1227 # define PLL_POWER_STATE_IN_TXS2_3(x) ((x) << 7) 1228 # define PLL_POWER_STATE_IN_TXS2_3_MASK (0x7 << 7) 1229 # define PLL_POWER_STATE_IN_TXS2_3_SHIFT 7 1230 # define PLL_POWER_STATE_IN_OFF_3(x) ((x) << 10) 1231 # define PLL_POWER_STATE_IN_OFF_3_MASK (0x7 << 10) 1232 # define PLL_POWER_STATE_IN_OFF_3_SHIFT 10 1233 # define PLL_RAMP_UP_TIME_3(x) ((x) << 24) 1234 # define PLL_RAMP_UP_TIME_3_MASK (0x7 << 24) 1235 # define PLL_RAMP_UP_TIME_3_SHIFT 24 1236 /* PIF PHY1 registers idx/data 0x10/0x14 */ 1237 #define PB1_PIF_CNTL 0x10 1238 #define PB1_PIF_PAIRING 0x11 1239 #define PB1_PIF_PWRDOWN_0 0x12 1240 #define PB1_PIF_PWRDOWN_1 0x13 1241 1242 #define PB1_PIF_PWRDOWN_2 0x17 1243 #define PB1_PIF_PWRDOWN_3 0x18 1244 /* PCIE registers idx/data 0x30/0x34 */ 1245 #define PCIE_CNTL2 0x1c /* PCIE */ 1246 # define SLV_MEM_LS_EN (1 << 16) 1247 # define SLV_MEM_AGGRESSIVE_LS_EN (1 << 17) 1248 # define MST_MEM_LS_EN (1 << 18) 1249 # define REPLAY_MEM_LS_EN (1 << 19) 1250 #define PCIE_LC_STATUS1 0x28 /* PCIE */ 1251 # define LC_REVERSE_RCVR (1 << 0) 1252 # define LC_REVERSE_XMIT (1 << 1) 1253 # define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2) 1254 # define LC_OPERATING_LINK_WIDTH_SHIFT 2 1255 # define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5) 1256 # define LC_DETECTED_LINK_WIDTH_SHIFT 5 1257 1258 #define PCIE_P_CNTL 0x40 /* PCIE */ 1259 # define P_IGNORE_EDB_ERR (1 << 6) 1260 1261 /* PCIE PORT registers idx/data 0x38/0x3c */ 1262 #define PCIE_LC_CNTL 0xa0 1263 # define LC_L0S_INACTIVITY(x) ((x) << 8) 1264 # define LC_L0S_INACTIVITY_MASK (0xf << 8) 1265 # define LC_L0S_INACTIVITY_SHIFT 8 1266 # define LC_L1_INACTIVITY(x) ((x) << 12) 1267 # define LC_L1_INACTIVITY_MASK (0xf << 12) 1268 # define LC_L1_INACTIVITY_SHIFT 12 1269 # define LC_PMI_TO_L1_DIS (1 << 16) 1270 # define LC_ASPM_TO_L1_DIS (1 << 24) 1271 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 1272 # define LC_LINK_WIDTH_SHIFT 0 1273 # define LC_LINK_WIDTH_MASK 0x7 1274 # define LC_LINK_WIDTH_X0 0 1275 # define LC_LINK_WIDTH_X1 1 1276 # define LC_LINK_WIDTH_X2 2 1277 # define LC_LINK_WIDTH_X4 3 1278 # define LC_LINK_WIDTH_X8 4 1279 # define LC_LINK_WIDTH_X16 6 1280 # define LC_LINK_WIDTH_RD_SHIFT 4 1281 # define LC_LINK_WIDTH_RD_MASK 0x70 1282 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 1283 # define LC_RECONFIG_NOW (1 << 8) 1284 # define LC_RENEGOTIATION_SUPPORT (1 << 9) 1285 # define LC_RENEGOTIATE_EN (1 << 10) 1286 # define LC_SHORT_RECONFIG_EN (1 << 11) 1287 # define LC_UPCONFIGURE_SUPPORT (1 << 12) 1288 # define LC_UPCONFIGURE_DIS (1 << 13) 1289 # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21) 1290 # define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21) 1291 # define LC_DYN_LANES_PWR_STATE_SHIFT 21 1292 #define PCIE_LC_N_FTS_CNTL 0xa3 /* PCIE_P */ 1293 # define LC_XMIT_N_FTS(x) ((x) << 0) 1294 # define LC_XMIT_N_FTS_MASK (0xff << 0) 1295 # define LC_XMIT_N_FTS_SHIFT 0 1296 # define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8) 1297 # define LC_N_FTS_MASK (0xff << 24) 1298 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 1299 # define LC_GEN2_EN_STRAP (1 << 0) 1300 # define LC_GEN3_EN_STRAP (1 << 1) 1301 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2) 1302 # define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3) 1303 # define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT 3 1304 # define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5) 1305 # define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6) 1306 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7) 1307 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8) 1308 # define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9) 1309 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10) 1310 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 10 1311 # define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */ 1312 # define LC_CURRENT_DATA_RATE_SHIFT 13 1313 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16) 1314 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18) 1315 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19) 1316 # define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20) 1317 # define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21) 1318 1319 #define PCIE_LC_CNTL2 0xb1 1320 # define LC_ALLOW_PDWN_IN_L1 (1 << 17) 1321 # define LC_ALLOW_PDWN_IN_L23 (1 << 18) 1322 1323 #define PCIE_LC_CNTL3 0xb5 /* PCIE_P */ 1324 # define LC_GO_TO_RECOVERY (1 << 30) 1325 #define PCIE_LC_CNTL4 0xb6 /* PCIE_P */ 1326 # define LC_REDO_EQ (1 << 5) 1327 # define LC_SET_QUIESCE (1 << 13) 1328 1329 /* 1330 * UVD 1331 */ 1332 #define UVD_UDEC_ADDR_CONFIG 0x3bd3 1333 #define UVD_UDEC_DB_ADDR_CONFIG 0x3bd4 1334 #define UVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 1335 #define UVD_RBC_RB_RPTR 0x3da4 1336 #define UVD_RBC_RB_WPTR 0x3da5 1337 #define UVD_STATUS 0x3daf 1338 1339 #define UVD_CGC_CTRL 0x3dc2 1340 # define DCM (1 << 0) 1341 # define CG_DT(x) ((x) << 2) 1342 # define CG_DT_MASK (0xf << 2) 1343 # define CLK_OD(x) ((x) << 6) 1344 # define CLK_OD_MASK (0x1f << 6) 1345 1346 /* UVD CTX indirect */ 1347 #define UVD_CGC_MEM_CTRL 0xC0 1348 #define UVD_CGC_CTRL2 0xC1 1349 # define DYN_OR_EN (1 << 0) 1350 # define DYN_RR_EN (1 << 1) 1351 # define G_DIV_ID(x) ((x) << 2) 1352 # define G_DIV_ID_MASK (0x7 << 2) 1353 1354 /* 1355 * PM4 1356 */ 1357 #define PACKET_TYPE0 0 1358 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 1359 ((reg) & 0xFFFF) | \ 1360 ((n) & 0x3FFF) << 16) 1361 #define CP_PACKET2 0x80000000 1362 #define PACKET2_PAD_SHIFT 0 1363 #define PACKET2_PAD_MASK (0x3fffffff << 0) 1364 1365 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 1366 #define RADEON_PACKET_TYPE3 3 1367 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ 1368 (((op) & 0xFF) << 8) | \ 1369 ((n) & 0x3FFF) << 16) 1370 1371 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 1372 1373 /* Packet 3 types */ 1374 #define PACKET3_NOP 0x10 1375 #define PACKET3_SET_BASE 0x11 1376 #define PACKET3_BASE_INDEX(x) ((x) << 0) 1377 #define GDS_PARTITION_BASE 2 1378 #define CE_PARTITION_BASE 3 1379 #define PACKET3_CLEAR_STATE 0x12 1380 #define PACKET3_INDEX_BUFFER_SIZE 0x13 1381 #define PACKET3_DISPATCH_DIRECT 0x15 1382 #define PACKET3_DISPATCH_INDIRECT 0x16 1383 #define PACKET3_ALLOC_GDS 0x1B 1384 #define PACKET3_WRITE_GDS_RAM 0x1C 1385 #define PACKET3_ATOMIC_GDS 0x1D 1386 #define PACKET3_ATOMIC 0x1E 1387 #define PACKET3_OCCLUSION_QUERY 0x1F 1388 #define PACKET3_SET_PREDICATION 0x20 1389 #define PACKET3_REG_RMW 0x21 1390 #define PACKET3_COND_EXEC 0x22 1391 #define PACKET3_PRED_EXEC 0x23 1392 #define PACKET3_DRAW_INDIRECT 0x24 1393 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 1394 #define PACKET3_INDEX_BASE 0x26 1395 #define PACKET3_DRAW_INDEX_2 0x27 1396 #define PACKET3_CONTEXT_CONTROL 0x28 1397 #define PACKET3_INDEX_TYPE 0x2A 1398 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 1399 #define PACKET3_DRAW_INDEX_AUTO 0x2D 1400 #define PACKET3_DRAW_INDEX_IMMD 0x2E 1401 #define PACKET3_NUM_INSTANCES 0x2F 1402 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 1403 #define PACKET3_INDIRECT_BUFFER_CONST 0x31 1404 #define PACKET3_INDIRECT_BUFFER 0x3F 1405 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 1406 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 1407 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 1408 #define PACKET3_WRITE_DATA 0x37 1409 #define WRITE_DATA_DST_SEL(x) ((x) << 8) 1410 /* 0 - register 1411 * 1 - memory (sync - via GRBM) 1412 * 2 - tc/l2 1413 * 3 - gds 1414 * 4 - reserved 1415 * 5 - memory (async - direct) 1416 */ 1417 #define WR_ONE_ADDR (1 << 16) 1418 #define WR_CONFIRM (1 << 20) 1419 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 1420 /* 0 - me 1421 * 1 - pfp 1422 * 2 - ce 1423 */ 1424 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 1425 #define PACKET3_MEM_SEMAPHORE 0x39 1426 #define PACKET3_MPEG_INDEX 0x3A 1427 #define PACKET3_COPY_DW 0x3B 1428 #define PACKET3_WAIT_REG_MEM 0x3C 1429 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 1430 /* 0 - always 1431 * 1 - < 1432 * 2 - <= 1433 * 3 - == 1434 * 4 - != 1435 * 5 - >= 1436 * 6 - > 1437 */ 1438 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 1439 /* 0 - reg 1440 * 1 - mem 1441 */ 1442 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 1443 /* 0 - me 1444 * 1 - pfp 1445 */ 1446 #define PACKET3_MEM_WRITE 0x3D 1447 #define PACKET3_COPY_DATA 0x40 1448 #define PACKET3_CP_DMA 0x41 1449 /* 1. header 1450 * 2. SRC_ADDR_LO or DATA [31:0] 1451 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | 1452 * SRC_ADDR_HI [7:0] 1453 * 4. DST_ADDR_LO [31:0] 1454 * 5. DST_ADDR_HI [7:0] 1455 * 6. COMMAND [30:21] | BYTE_COUNT [20:0] 1456 */ 1457 # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) 1458 /* 0 - DST_ADDR 1459 * 1 - GDS 1460 */ 1461 # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) 1462 /* 0 - ME 1463 * 1 - PFP 1464 */ 1465 # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) 1466 /* 0 - SRC_ADDR 1467 * 1 - GDS 1468 * 2 - DATA 1469 */ 1470 # define PACKET3_CP_DMA_CP_SYNC (1 << 31) 1471 /* COMMAND */ 1472 # define PACKET3_CP_DMA_DIS_WC (1 << 21) 1473 # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) 1474 /* 0 - none 1475 * 1 - 8 in 16 1476 * 2 - 8 in 32 1477 * 3 - 8 in 64 1478 */ 1479 # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) 1480 /* 0 - none 1481 * 1 - 8 in 16 1482 * 2 - 8 in 32 1483 * 3 - 8 in 64 1484 */ 1485 # define PACKET3_CP_DMA_CMD_SAS (1 << 26) 1486 /* 0 - memory 1487 * 1 - register 1488 */ 1489 # define PACKET3_CP_DMA_CMD_DAS (1 << 27) 1490 /* 0 - memory 1491 * 1 - register 1492 */ 1493 # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) 1494 # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) 1495 # define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30) 1496 #define PACKET3_PFP_SYNC_ME 0x42 1497 #define PACKET3_SURFACE_SYNC 0x43 1498 # define PACKET3_DEST_BASE_0_ENA (1 << 0) 1499 # define PACKET3_DEST_BASE_1_ENA (1 << 1) 1500 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 1501 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 1502 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 1503 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 1504 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 1505 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 1506 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 1507 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 1508 # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 1509 # define PACKET3_DEST_BASE_2_ENA (1 << 19) 1510 # define PACKET3_DEST_BASE_3_ENA (1 << 21) 1511 # define PACKET3_TCL1_ACTION_ENA (1 << 22) 1512 # define PACKET3_TC_ACTION_ENA (1 << 23) 1513 # define PACKET3_CB_ACTION_ENA (1 << 25) 1514 # define PACKET3_DB_ACTION_ENA (1 << 26) 1515 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 1516 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 1517 #define PACKET3_ME_INITIALIZE 0x44 1518 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 1519 #define PACKET3_COND_WRITE 0x45 1520 #define PACKET3_EVENT_WRITE 0x46 1521 #define EVENT_TYPE(x) ((x) << 0) 1522 #define EVENT_INDEX(x) ((x) << 8) 1523 /* 0 - any non-TS event 1524 * 1 - ZPASS_DONE 1525 * 2 - SAMPLE_PIPELINESTAT 1526 * 3 - SAMPLE_STREAMOUTSTAT* 1527 * 4 - *S_PARTIAL_FLUSH 1528 * 5 - EOP events 1529 * 6 - EOS events 1530 * 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT 1531 */ 1532 #define INV_L2 (1 << 20) 1533 /* INV TC L2 cache when EVENT_INDEX = 7 */ 1534 #define PACKET3_EVENT_WRITE_EOP 0x47 1535 #define DATA_SEL(x) ((x) << 29) 1536 /* 0 - discard 1537 * 1 - send low 32bit data 1538 * 2 - send 64bit data 1539 * 3 - send 64bit counter value 1540 */ 1541 #define INT_SEL(x) ((x) << 24) 1542 /* 0 - none 1543 * 1 - interrupt only (DATA_SEL = 0) 1544 * 2 - interrupt when data write is confirmed 1545 */ 1546 #define PACKET3_EVENT_WRITE_EOS 0x48 1547 #define PACKET3_PREAMBLE_CNTL 0x4A 1548 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 1549 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 1550 #define PACKET3_ONE_REG_WRITE 0x57 1551 #define PACKET3_LOAD_CONFIG_REG 0x5F 1552 #define PACKET3_LOAD_CONTEXT_REG 0x60 1553 #define PACKET3_LOAD_SH_REG 0x61 1554 #define PACKET3_SET_CONFIG_REG 0x68 1555 #define PACKET3_SET_CONFIG_REG_START 0x00002000 1556 #define PACKET3_SET_CONFIG_REG_END 0x00002c00 1557 #define PACKET3_SET_CONTEXT_REG 0x69 1558 #define PACKET3_SET_CONTEXT_REG_START 0x000a000 1559 #define PACKET3_SET_CONTEXT_REG_END 0x000a400 1560 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 1561 #define PACKET3_SET_RESOURCE_INDIRECT 0x74 1562 #define PACKET3_SET_SH_REG 0x76 1563 #define PACKET3_SET_SH_REG_START 0x00002c00 1564 #define PACKET3_SET_SH_REG_END 0x00003000 1565 #define PACKET3_SET_SH_REG_OFFSET 0x77 1566 #define PACKET3_ME_WRITE 0x7A 1567 #define PACKET3_SCRATCH_RAM_WRITE 0x7D 1568 #define PACKET3_SCRATCH_RAM_READ 0x7E 1569 #define PACKET3_CE_WRITE 0x7F 1570 #define PACKET3_LOAD_CONST_RAM 0x80 1571 #define PACKET3_WRITE_CONST_RAM 0x81 1572 #define PACKET3_WRITE_CONST_RAM_OFFSET 0x82 1573 #define PACKET3_DUMP_CONST_RAM 0x83 1574 #define PACKET3_INCREMENT_CE_COUNTER 0x84 1575 #define PACKET3_INCREMENT_DE_COUNTER 0x85 1576 #define PACKET3_WAIT_ON_CE_COUNTER 0x86 1577 #define PACKET3_WAIT_ON_DE_COUNTER 0x87 1578 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 1579 #define PACKET3_SET_CE_DE_COUNTERS 0x89 1580 #define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A 1581 #define PACKET3_SWITCH_BUFFER 0x8B 1582 1583 /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */ 1584 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ 1585 #define DMA1_REGISTER_OFFSET 0x200 /* not a register */ 1586 1587 #define DMA_RB_CNTL 0x3400 1588 # define DMA_RB_ENABLE (1 << 0) 1589 # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ 1590 # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 1591 # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) 1592 # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 1593 # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 1594 #define DMA_RB_BASE 0x3401 1595 #define DMA_RB_RPTR 0x3402 1596 #define DMA_RB_WPTR 0x3403 1597 1598 #define DMA_RB_RPTR_ADDR_HI 0x3407 1599 #define DMA_RB_RPTR_ADDR_LO 0x3408 1600 1601 #define DMA_IB_CNTL 0x3409 1602 # define DMA_IB_ENABLE (1 << 0) 1603 # define DMA_IB_SWAP_ENABLE (1 << 4) 1604 # define CMD_VMID_FORCE (1 << 31) 1605 #define DMA_IB_RPTR 0x340a 1606 #define DMA_CNTL 0x340b 1607 # define TRAP_ENABLE (1 << 0) 1608 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 1609 # define SEM_WAIT_INT_ENABLE (1 << 2) 1610 # define DATA_SWAP_ENABLE (1 << 3) 1611 # define FENCE_SWAP_ENABLE (1 << 4) 1612 # define CTXEMPTY_INT_ENABLE (1 << 28) 1613 #define DMA_STATUS_REG 0x340d 1614 # define DMA_IDLE (1 << 0) 1615 #define DMA_TILING_CONFIG 0x342e 1616 1617 #define DMA_POWER_CNTL 0x342f 1618 # define MEM_POWER_OVERRIDE (1 << 8) 1619 #define DMA_CLK_CTRL 0x3430 1620 1621 #define DMA_PG 0x3435 1622 # define PG_CNTL_ENABLE (1 << 0) 1623 #define DMA_PGFSM_CONFIG 0x3436 1624 #define DMA_PGFSM_WRITE 0x3437 1625 1626 #define DMA_PACKET(cmd, b, t, s, n) ((((cmd) & 0xF) << 28) | \ 1627 (((b) & 0x1) << 26) | \ 1628 (((t) & 0x1) << 23) | \ 1629 (((s) & 0x1) << 22) | \ 1630 (((n) & 0xFFFFF) << 0)) 1631 1632 #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \ 1633 (((vmid) & 0xF) << 20) | \ 1634 (((n) & 0xFFFFF) << 0)) 1635 1636 #define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \ 1637 (1 << 26) | \ 1638 (1 << 21) | \ 1639 (((n) & 0xFFFFF) << 0)) 1640 1641 /* async DMA Packet types */ 1642 #define DMA_PACKET_WRITE 0x2 1643 #define DMA_PACKET_COPY 0x3 1644 #define DMA_PACKET_INDIRECT_BUFFER 0x4 1645 #define DMA_PACKET_SEMAPHORE 0x5 1646 #define DMA_PACKET_FENCE 0x6 1647 #define DMA_PACKET_TRAP 0x7 1648 #define DMA_PACKET_SRBM_WRITE 0x9 1649 #define DMA_PACKET_CONSTANT_FILL 0xd 1650 #define DMA_PACKET_POLL_REG_MEM 0xe 1651 #define DMA_PACKET_NOP 0xf 1652 1653 #define VCE_STATUS 0x20004 1654 #define VCE_VCPU_CNTL 0x20014 1655 #define VCE_CLK_EN (1 << 0) 1656 #define VCE_VCPU_CACHE_OFFSET0 0x20024 1657 #define VCE_VCPU_CACHE_SIZE0 0x20028 1658 #define VCE_VCPU_CACHE_OFFSET1 0x2002c 1659 #define VCE_VCPU_CACHE_SIZE1 0x20030 1660 #define VCE_VCPU_CACHE_OFFSET2 0x20034 1661 #define VCE_VCPU_CACHE_SIZE2 0x20038 1662 #define VCE_SOFT_RESET 0x20120 1663 #define VCE_ECPU_SOFT_RESET (1 << 0) 1664 #define VCE_FME_SOFT_RESET (1 << 2) 1665 #define VCE_RB_BASE_LO2 0x2016c 1666 #define VCE_RB_BASE_HI2 0x20170 1667 #define VCE_RB_SIZE2 0x20174 1668 #define VCE_RB_RPTR2 0x20178 1669 #define VCE_RB_WPTR2 0x2017c 1670 #define VCE_RB_BASE_LO 0x20180 1671 #define VCE_RB_BASE_HI 0x20184 1672 #define VCE_RB_SIZE 0x20188 1673 #define VCE_RB_RPTR 0x2018c 1674 #define VCE_RB_WPTR 0x20190 1675 #define VCE_CLOCK_GATING_A 0x202f8 1676 #define VCE_CLOCK_GATING_B 0x202fc 1677 #define VCE_UENC_CLOCK_GATING 0x205bc 1678 #define VCE_UENC_REG_CLOCK_GATING 0x205c0 1679 #define VCE_FW_REG_STATUS 0x20e10 1680 # define VCE_FW_REG_STATUS_BUSY (1 << 0) 1681 # define VCE_FW_REG_STATUS_PASS (1 << 3) 1682 # define VCE_FW_REG_STATUS_DONE (1 << 11) 1683 #define VCE_LMI_FW_START_KEYSEL 0x20e18 1684 #define VCE_LMI_FW_PERIODIC_CTRL 0x20e20 1685 #define VCE_LMI_CTRL2 0x20e74 1686 #define VCE_LMI_CTRL 0x20e98 1687 #define VCE_LMI_VM_CTRL 0x20ea0 1688 #define VCE_LMI_SWAP_CNTL 0x20eb4 1689 #define VCE_LMI_SWAP_CNTL1 0x20eb8 1690 #define VCE_LMI_CACHE_CTRL 0x20ef4 1691 1692 #define VCE_CMD_NO_OP 0x00000000 1693 #define VCE_CMD_END 0x00000001 1694 #define VCE_CMD_IB 0x00000002 1695 #define VCE_CMD_FENCE 0x00000003 1696 #define VCE_CMD_TRAP 0x00000004 1697 #define VCE_CMD_IB_AUTO 0x00000005 1698 #define VCE_CMD_SEMAPHORE 0x00000006 1699 1700 1701 //#dce stupp 1702 /* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */ 1703 #define CRTC0_REGISTER_OFFSET (0x1b7c - 0x1b7c) //(0x6df0 - 0x6df0)/4 1704 #define CRTC1_REGISTER_OFFSET (0x1e7c - 0x1b7c) //(0x79f0 - 0x6df0)/4 1705 #define CRTC2_REGISTER_OFFSET (0x417c - 0x1b7c) //(0x105f0 - 0x6df0)/4 1706 #define CRTC3_REGISTER_OFFSET (0x447c - 0x1b7c) //(0x111f0 - 0x6df0)/4 1707 #define CRTC4_REGISTER_OFFSET (0x477c - 0x1b7c) //(0x11df0 - 0x6df0)/4 1708 #define CRTC5_REGISTER_OFFSET (0x4a7c - 0x1b7c) //(0x129f0 - 0x6df0)/4 1709 1710 /* hpd instance offsets */ 1711 #define HPD0_REGISTER_OFFSET (0x1807 - 0x1807) 1712 #define HPD1_REGISTER_OFFSET (0x180a - 0x1807) 1713 #define HPD2_REGISTER_OFFSET (0x180d - 0x1807) 1714 #define HPD3_REGISTER_OFFSET (0x1810 - 0x1807) 1715 #define HPD4_REGISTER_OFFSET (0x1813 - 0x1807) 1716 #define HPD5_REGISTER_OFFSET (0x1816 - 0x1807) 1717 1718 /* audio endpt instance offsets */ 1719 #define AUD0_REGISTER_OFFSET (0x1780 - 0x1780) 1720 #define AUD1_REGISTER_OFFSET (0x1786 - 0x1780) 1721 #define AUD2_REGISTER_OFFSET (0x178c - 0x1780) 1722 #define AUD3_REGISTER_OFFSET (0x1792 - 0x1780) 1723 #define AUD4_REGISTER_OFFSET (0x1798 - 0x1780) 1724 #define AUD5_REGISTER_OFFSET (0x179d - 0x1780) 1725 #define AUD6_REGISTER_OFFSET (0x17a4 - 0x1780) 1726 1727 #define CURSOR_WIDTH 64 1728 #define CURSOR_HEIGHT 64 1729 #define AMDGPU_MM_INDEX 0x0000 1730 #define AMDGPU_MM_DATA 0x0001 1731 1732 #define VERDE_NUM_CRTC 6 1733 #define BLACKOUT_MODE_MASK 0x00000007 1734 #define VGA_RENDER_CONTROL 0xC0 1735 #define R_000300_VGA_RENDER_CONTROL 0xC0 1736 #define C_000300_VGA_VSTATUS_CNTL 0xFFFCFFFF 1737 #define EVERGREEN_CRTC_STATUS 0x1BA3 1738 #define EVERGREEN_CRTC_V_BLANK (1 << 0) 1739 #define EVERGREEN_CRTC_STATUS_POSITION 0x1BA4 1740 /* CRTC blocks at 0x6df0, 0x79f0, 0x105f0, 0x111f0, 0x11df0, 0x129f0 */ 1741 #define EVERGREEN_CRTC_V_BLANK_START_END 0x1b8d 1742 #define EVERGREEN_CRTC_CONTROL 0x1b9c 1743 #define EVERGREEN_CRTC_MASTER_EN (1 << 0) 1744 #define EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE (1 << 24) 1745 #define EVERGREEN_CRTC_BLANK_CONTROL 0x1b9d 1746 #define EVERGREEN_CRTC_BLANK_DATA_EN (1 << 8) 1747 #define EVERGREEN_CRTC_V_BLANK (1 << 0) 1748 #define EVERGREEN_CRTC_STATUS_HV_COUNT 0x1ba8 1749 #define EVERGREEN_CRTC_UPDATE_LOCK 0x1bb5 1750 #define EVERGREEN_MASTER_UPDATE_LOCK 0x1bbd 1751 #define EVERGREEN_MASTER_UPDATE_MODE 0x1bbe 1752 #define EVERGREEN_GRPH_UPDATE_LOCK (1 << 16) 1753 #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 1754 #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 1755 #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 1756 #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 1757 #define EVERGREEN_GRPH_UPDATE 0x1a11 1758 #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0xc4 1759 #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0xc9 1760 #define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING (1 << 2) 1761 1762 #define EVERGREEN_DATA_FORMAT 0x1ac0 1763 # define EVERGREEN_INTERLEAVE_EN (1 << 0) 1764 1765 #define R600_D1GRPH_ARRAY_MODE_LINEAR_GENERAL (0 << 20) 1766 #define R600_D1GRPH_ARRAY_MODE_LINEAR_ALIGNED (1 << 20) 1767 #define R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1 (2 << 20) 1768 #define R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1 (4 << 20) 1769 1770 #define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a45 1771 #define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1845 1772 1773 #define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1847 1774 #define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a47 1775 1776 #define R600_D1GRPH_SWAP_CONTROL 0x1843 1777 #define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0) 1778 #define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0) 1779 #define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0) 1780 #define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0) 1781 1782 #define AVIVO_D1VGA_CONTROL 0x00cc 1783 # define AVIVO_DVGA_CONTROL_MODE_ENABLE (1 << 0) 1784 # define AVIVO_DVGA_CONTROL_TIMING_SELECT (1 << 8) 1785 # define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1 << 9) 1786 # define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1 << 10) 1787 # define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1 << 16) 1788 # define AVIVO_DVGA_CONTROL_ROTATE (1 << 24) 1789 #define AVIVO_D2VGA_CONTROL 0x00ce 1790 1791 #define R600_BUS_CNTL 0x1508 1792 # define R600_BIOS_ROM_DIS (1 << 1) 1793 1794 #define R600_ROM_CNTL 0x580 1795 # define R600_SCK_OVERWRITE (1 << 1) 1796 # define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28 1797 # define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28) 1798 1799 #define FMT_BIT_DEPTH_CONTROL 0x1bf2 1800 #define FMT_TRUNCATE_EN (1 << 0) 1801 #define FMT_TRUNCATE_DEPTH (1 << 4) 1802 #define FMT_SPATIAL_DITHER_EN (1 << 8) 1803 #define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9) 1804 #define FMT_SPATIAL_DITHER_DEPTH (1 << 12) 1805 #define FMT_FRAME_RANDOM_ENABLE (1 << 13) 1806 #define FMT_RGB_RANDOM_ENABLE (1 << 14) 1807 #define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15) 1808 #define FMT_TEMPORAL_DITHER_EN (1 << 16) 1809 #define FMT_TEMPORAL_DITHER_DEPTH (1 << 20) 1810 #define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21) 1811 #define FMT_TEMPORAL_LEVEL (1 << 24) 1812 #define FMT_TEMPORAL_DITHER_RESET (1 << 25) 1813 #define FMT_25FRC_SEL(x) ((x) << 26) 1814 #define FMT_50FRC_SEL(x) ((x) << 28) 1815 #define FMT_75FRC_SEL(x) ((x) << 30) 1816 1817 #define EVERGREEN_DC_LUT_CONTROL 0x1a80 1818 #define EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE 0x1a81 1819 #define EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN 0x1a82 1820 #define EVERGREEN_DC_LUT_BLACK_OFFSET_RED 0x1a83 1821 #define EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE 0x1a84 1822 #define EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN 0x1a85 1823 #define EVERGREEN_DC_LUT_WHITE_OFFSET_RED 0x1a86 1824 #define EVERGREEN_DC_LUT_30_COLOR 0x1a7c 1825 #define EVERGREEN_DC_LUT_RW_INDEX 0x1a79 1826 #define EVERGREEN_DC_LUT_WRITE_EN_MASK 0x1a7e 1827 #define EVERGREEN_DC_LUT_RW_MODE 0x1a78 1828 1829 #define EVERGREEN_GRPH_ENABLE 0x1a00 1830 #define EVERGREEN_GRPH_CONTROL 0x1a01 1831 #define EVERGREEN_GRPH_DEPTH(x) (((x) & 0x3) << 0) 1832 #define EVERGREEN_GRPH_DEPTH_8BPP 0 1833 #define EVERGREEN_GRPH_DEPTH_16BPP 1 1834 #define EVERGREEN_GRPH_DEPTH_32BPP 2 1835 #define EVERGREEN_GRPH_NUM_BANKS(x) (((x) & 0x3) << 2) 1836 #define EVERGREEN_ADDR_SURF_2_BANK 0 1837 #define EVERGREEN_ADDR_SURF_4_BANK 1 1838 #define EVERGREEN_ADDR_SURF_8_BANK 2 1839 #define EVERGREEN_ADDR_SURF_16_BANK 3 1840 #define EVERGREEN_GRPH_Z(x) (((x) & 0x3) << 4) 1841 #define EVERGREEN_GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6) 1842 #define EVERGREEN_ADDR_SURF_BANK_WIDTH_1 0 1843 #define EVERGREEN_ADDR_SURF_BANK_WIDTH_2 1 1844 #define EVERGREEN_ADDR_SURF_BANK_WIDTH_4 2 1845 #define EVERGREEN_ADDR_SURF_BANK_WIDTH_8 3 1846 #define EVERGREEN_GRPH_FORMAT(x) (((x) & 0x7) << 8) 1847 1848 #define EVERGREEN_GRPH_FORMAT_INDEXED 0 1849 #define EVERGREEN_GRPH_FORMAT_ARGB1555 0 1850 #define EVERGREEN_GRPH_FORMAT_ARGB565 1 1851 #define EVERGREEN_GRPH_FORMAT_ARGB4444 2 1852 #define EVERGREEN_GRPH_FORMAT_AI88 3 1853 #define EVERGREEN_GRPH_FORMAT_MONO16 4 1854 #define EVERGREEN_GRPH_FORMAT_BGRA5551 5 1855 1856 /* 32 BPP */ 1857 #define EVERGREEN_GRPH_FORMAT_ARGB8888 0 1858 #define EVERGREEN_GRPH_FORMAT_ARGB2101010 1 1859 #define EVERGREEN_GRPH_FORMAT_32BPP_DIG 2 1860 #define EVERGREEN_GRPH_FORMAT_8B_ARGB2101010 3 1861 #define EVERGREEN_GRPH_FORMAT_BGRA1010102 4 1862 #define EVERGREEN_GRPH_FORMAT_8B_BGRA1010102 5 1863 #define EVERGREEN_GRPH_FORMAT_RGB111110 6 1864 #define EVERGREEN_GRPH_FORMAT_BGR101111 7 1865 #define EVERGREEN_GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11) 1866 #define EVERGREEN_ADDR_SURF_BANK_HEIGHT_1 0 1867 #define EVERGREEN_ADDR_SURF_BANK_HEIGHT_2 1 1868 #define EVERGREEN_ADDR_SURF_BANK_HEIGHT_4 2 1869 #define EVERGREEN_ADDR_SURF_BANK_HEIGHT_8 3 1870 #define EVERGREEN_GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13) 1871 #define EVERGREEN_ADDR_SURF_TILE_SPLIT_64B 0 1872 #define EVERGREEN_ADDR_SURF_TILE_SPLIT_128B 1 1873 #define EVERGREEN_ADDR_SURF_TILE_SPLIT_256B 2 1874 #define EVERGREEN_ADDR_SURF_TILE_SPLIT_512B 3 1875 #define EVERGREEN_ADDR_SURF_TILE_SPLIT_1KB 4 1876 #define EVERGREEN_ADDR_SURF_TILE_SPLIT_2KB 5 1877 #define EVERGREEN_ADDR_SURF_TILE_SPLIT_4KB 6 1878 #define EVERGREEN_GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18) 1879 #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1 0 1880 #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2 1 1881 #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4 2 1882 #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8 3 1883 #define EVERGREEN_GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20) 1884 #define EVERGREEN_GRPH_ARRAY_LINEAR_GENERAL 0 1885 #define EVERGREEN_GRPH_ARRAY_LINEAR_ALIGNED 1 1886 #define EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1 2 1887 #define EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1 4 1888 #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1 0 1889 #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2 1 1890 #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4 2 1891 #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8 3 1892 1893 #define EVERGREEN_GRPH_SWAP_CONTROL 0x1a03 1894 #define EVERGREEN_GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0) 1895 # define EVERGREEN_GRPH_ENDIAN_NONE 0 1896 # define EVERGREEN_GRPH_ENDIAN_8IN16 1 1897 # define EVERGREEN_GRPH_ENDIAN_8IN32 2 1898 # define EVERGREEN_GRPH_ENDIAN_8IN64 3 1899 #define EVERGREEN_GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4) 1900 # define EVERGREEN_GRPH_RED_SEL_R 0 1901 # define EVERGREEN_GRPH_RED_SEL_G 1 1902 # define EVERGREEN_GRPH_RED_SEL_B 2 1903 # define EVERGREEN_GRPH_RED_SEL_A 3 1904 #define EVERGREEN_GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6) 1905 # define EVERGREEN_GRPH_GREEN_SEL_G 0 1906 # define EVERGREEN_GRPH_GREEN_SEL_B 1 1907 # define EVERGREEN_GRPH_GREEN_SEL_A 2 1908 # define EVERGREEN_GRPH_GREEN_SEL_R 3 1909 #define EVERGREEN_GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8) 1910 # define EVERGREEN_GRPH_BLUE_SEL_B 0 1911 # define EVERGREEN_GRPH_BLUE_SEL_A 1 1912 # define EVERGREEN_GRPH_BLUE_SEL_R 2 1913 # define EVERGREEN_GRPH_BLUE_SEL_G 3 1914 #define EVERGREEN_GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10) 1915 # define EVERGREEN_GRPH_ALPHA_SEL_A 0 1916 # define EVERGREEN_GRPH_ALPHA_SEL_R 1 1917 # define EVERGREEN_GRPH_ALPHA_SEL_G 2 1918 # define EVERGREEN_GRPH_ALPHA_SEL_B 3 1919 1920 #define EVERGREEN_D3VGA_CONTROL 0xf8 1921 #define EVERGREEN_D4VGA_CONTROL 0xf9 1922 #define EVERGREEN_D5VGA_CONTROL 0xfa 1923 #define EVERGREEN_D6VGA_CONTROL 0xfb 1924 1925 #define EVERGREEN_GRPH_SURFACE_ADDRESS_MASK 0xffffff00 1926 1927 #define EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL 0x1a02 1928 #define EVERGREEN_LUT_10BIT_BYPASS_EN (1 << 8) 1929 1930 #define EVERGREEN_GRPH_PITCH 0x1a06 1931 #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 1932 #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 1933 #define EVERGREEN_GRPH_SURFACE_OFFSET_X 0x1a09 1934 #define EVERGREEN_GRPH_SURFACE_OFFSET_Y 0x1a0a 1935 #define EVERGREEN_GRPH_X_START 0x1a0b 1936 #define EVERGREEN_GRPH_Y_START 0x1a0c 1937 #define EVERGREEN_GRPH_X_END 0x1a0d 1938 #define EVERGREEN_GRPH_Y_END 0x1a0e 1939 #define EVERGREEN_GRPH_UPDATE 0x1a11 1940 #define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING (1 << 2) 1941 #define EVERGREEN_GRPH_UPDATE_LOCK (1 << 16) 1942 #define EVERGREEN_GRPH_FLIP_CONTROL 0x1a12 1943 #define EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN (1 << 0) 1944 1945 #define EVERGREEN_VIEWPORT_START 0x1b5c 1946 #define EVERGREEN_VIEWPORT_SIZE 0x1b5d 1947 #define EVERGREEN_DESKTOP_HEIGHT 0x1ac1 1948 1949 /* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */ 1950 #define EVERGREEN_CUR_CONTROL 0x1a66 1951 # define EVERGREEN_CURSOR_EN (1 << 0) 1952 # define EVERGREEN_CURSOR_MODE(x) (((x) & 0x3) << 8) 1953 # define EVERGREEN_CURSOR_MONO 0 1954 # define EVERGREEN_CURSOR_24_1 1 1955 # define EVERGREEN_CURSOR_24_8_PRE_MULT 2 1956 # define EVERGREEN_CURSOR_24_8_UNPRE_MULT 3 1957 # define EVERGREEN_CURSOR_2X_MAGNIFY (1 << 16) 1958 # define EVERGREEN_CURSOR_FORCE_MC_ON (1 << 20) 1959 # define EVERGREEN_CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24) 1960 # define EVERGREEN_CURSOR_URGENT_ALWAYS 0 1961 # define EVERGREEN_CURSOR_URGENT_1_8 1 1962 # define EVERGREEN_CURSOR_URGENT_1_4 2 1963 # define EVERGREEN_CURSOR_URGENT_3_8 3 1964 # define EVERGREEN_CURSOR_URGENT_1_2 4 1965 #define EVERGREEN_CUR_SURFACE_ADDRESS 0x1a67 1966 # define EVERGREEN_CUR_SURFACE_ADDRESS_MASK 0xfffff000 1967 #define EVERGREEN_CUR_SIZE 0x1a68 1968 #define EVERGREEN_CUR_SURFACE_ADDRESS_HIGH 0x1a69 1969 #define EVERGREEN_CUR_POSITION 0x1a6a 1970 #define EVERGREEN_CUR_HOT_SPOT 0x1a6b 1971 #define EVERGREEN_CUR_COLOR1 0x1a6c 1972 #define EVERGREEN_CUR_COLOR2 0x1a6d 1973 #define EVERGREEN_CUR_UPDATE 0x1a6e 1974 # define EVERGREEN_CURSOR_UPDATE_PENDING (1 << 0) 1975 # define EVERGREEN_CURSOR_UPDATE_TAKEN (1 << 1) 1976 # define EVERGREEN_CURSOR_UPDATE_LOCK (1 << 16) 1977 # define EVERGREEN_CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24) 1978 1979 1980 #define NI_INPUT_CSC_CONTROL 0x1a35 1981 # define NI_INPUT_CSC_GRPH_MODE(x) (((x) & 0x3) << 0) 1982 # define NI_INPUT_CSC_BYPASS 0 1983 # define NI_INPUT_CSC_PROG_COEFF 1 1984 # define NI_INPUT_CSC_PROG_SHARED_MATRIXA 2 1985 # define NI_INPUT_CSC_OVL_MODE(x) (((x) & 0x3) << 4) 1986 1987 #define NI_OUTPUT_CSC_CONTROL 0x1a3c 1988 # define NI_OUTPUT_CSC_GRPH_MODE(x) (((x) & 0x7) << 0) 1989 # define NI_OUTPUT_CSC_BYPASS 0 1990 # define NI_OUTPUT_CSC_TV_RGB 1 1991 # define NI_OUTPUT_CSC_YCBCR_601 2 1992 # define NI_OUTPUT_CSC_YCBCR_709 3 1993 # define NI_OUTPUT_CSC_PROG_COEFF 4 1994 # define NI_OUTPUT_CSC_PROG_SHARED_MATRIXB 5 1995 # define NI_OUTPUT_CSC_OVL_MODE(x) (((x) & 0x7) << 4) 1996 1997 #define NI_DEGAMMA_CONTROL 0x1a58 1998 # define NI_GRPH_DEGAMMA_MODE(x) (((x) & 0x3) << 0) 1999 # define NI_DEGAMMA_BYPASS 0 2000 # define NI_DEGAMMA_SRGB_24 1 2001 # define NI_DEGAMMA_XVYCC_222 2 2002 # define NI_OVL_DEGAMMA_MODE(x) (((x) & 0x3) << 4) 2003 # define NI_ICON_DEGAMMA_MODE(x) (((x) & 0x3) << 8) 2004 # define NI_CURSOR_DEGAMMA_MODE(x) (((x) & 0x3) << 12) 2005 2006 #define NI_GAMUT_REMAP_CONTROL 0x1a59 2007 # define NI_GRPH_GAMUT_REMAP_MODE(x) (((x) & 0x3) << 0) 2008 # define NI_GAMUT_REMAP_BYPASS 0 2009 # define NI_GAMUT_REMAP_PROG_COEFF 1 2010 # define NI_GAMUT_REMAP_PROG_SHARED_MATRIXA 2 2011 # define NI_GAMUT_REMAP_PROG_SHARED_MATRIXB 3 2012 # define NI_OVL_GAMUT_REMAP_MODE(x) (((x) & 0x3) << 4) 2013 2014 #define NI_REGAMMA_CONTROL 0x1aa0 2015 # define NI_GRPH_REGAMMA_MODE(x) (((x) & 0x7) << 0) 2016 # define NI_REGAMMA_BYPASS 0 2017 # define NI_REGAMMA_SRGB_24 1 2018 # define NI_REGAMMA_XVYCC_222 2 2019 # define NI_REGAMMA_PROG_A 3 2020 # define NI_REGAMMA_PROG_B 4 2021 # define NI_OVL_REGAMMA_MODE(x) (((x) & 0x7) << 4) 2022 2023 2024 #define NI_PRESCALE_GRPH_CONTROL 0x1a2d 2025 # define NI_GRPH_PRESCALE_BYPASS (1 << 4) 2026 2027 #define NI_PRESCALE_OVL_CONTROL 0x1a31 2028 # define NI_OVL_PRESCALE_BYPASS (1 << 4) 2029 2030 #define NI_INPUT_GAMMA_CONTROL 0x1a10 2031 # define NI_GRPH_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 0) 2032 # define NI_INPUT_GAMMA_USE_LUT 0 2033 # define NI_INPUT_GAMMA_BYPASS 1 2034 # define NI_INPUT_GAMMA_SRGB_24 2 2035 # define NI_INPUT_GAMMA_XVYCC_222 3 2036 # define NI_OVL_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 4) 2037 2038 #define BLACKOUT_MODE_MASK 0x00000007 2039 #define VGA_RENDER_CONTROL 0xC0 2040 #define R_000300_VGA_RENDER_CONTROL 0xC0 2041 #define C_000300_VGA_VSTATUS_CNTL 0xFFFCFFFF 2042 #define EVERGREEN_CRTC_STATUS 0x1BA3 2043 #define EVERGREEN_CRTC_V_BLANK (1 << 0) 2044 #define EVERGREEN_CRTC_STATUS_POSITION 0x1BA4 2045 /* CRTC blocks at 0x6df0, 0x79f0, 0x105f0, 0x111f0, 0x11df0, 0x129f0 */ 2046 #define EVERGREEN_CRTC_V_BLANK_START_END 0x1b8d 2047 #define EVERGREEN_CRTC_CONTROL 0x1b9c 2048 # define EVERGREEN_CRTC_MASTER_EN (1 << 0) 2049 # define EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE (1 << 24) 2050 #define EVERGREEN_CRTC_BLANK_CONTROL 0x1b9d 2051 # define EVERGREEN_CRTC_BLANK_DATA_EN (1 << 8) 2052 # define EVERGREEN_CRTC_V_BLANK (1 << 0) 2053 #define EVERGREEN_CRTC_STATUS_HV_COUNT 0x1ba8 2054 #define EVERGREEN_CRTC_UPDATE_LOCK 0x1bb5 2055 #define EVERGREEN_MASTER_UPDATE_LOCK 0x1bbd 2056 #define EVERGREEN_MASTER_UPDATE_MODE 0x1bbe 2057 #define EVERGREEN_GRPH_UPDATE_LOCK (1 << 16) 2058 #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 2059 #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 2060 #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 2061 #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 2062 #define EVERGREEN_GRPH_UPDATE 0x1a11 2063 #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0xc4 2064 #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0xc9 2065 #define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING (1 << 2) 2066 2067 #define mmVM_CONTEXT1_CNTL__xxRANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10 2068 #define mmVM_CONTEXT1_CNTL__xxRANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 2069 #define mmVM_CONTEXT1_CNTL__xxDUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80 2070 #define mmVM_CONTEXT1_CNTL__xxDUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 2071 #define mmVM_CONTEXT1_CNTL__xxPDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400 2072 #define mmVM_CONTEXT1_CNTL__xxPDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 2073 #define mmVM_CONTEXT1_CNTL__xxVALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000 2074 #define mmVM_CONTEXT1_CNTL__xxVALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd 2075 #define mmVM_CONTEXT1_CNTL__xxREAD_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000 2076 #define mmVM_CONTEXT1_CNTL__xxREAD_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 2077 #define mmVM_CONTEXT1_CNTL__xxWRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000 2078 #define mmVM_CONTEXT1_CNTL__xxWRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 2079 2080 #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxVMID_MASK 0x1e000000 2081 #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxVMID__SHIFT 0x19 2082 #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxPROTECTIONS_MASK 0xff 2083 #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxPROTECTIONS__SHIFT 0x0 2084 #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_ID_MASK 0xff000 2085 #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_ID__SHIFT 0xc 2086 #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_RW_MASK 0x1000000 2087 #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_RW__SHIFT 0x18 2088 2089 #define mmMC_SHARED_BLACKOUT_CNTL__xxBLACKOUT_MODE_MASK 0x7 2090 #define mmMC_SHARED_BLACKOUT_CNTL__xxBLACKOUT_MODE__SHIFT 0x0 2091 2092 #define mmBIF_FB_EN__xxFB_READ_EN_MASK 0x1 2093 #define mmBIF_FB_EN__xxFB_READ_EN__SHIFT 0x0 2094 #define mmBIF_FB_EN__xxFB_WRITE_EN_MASK 0x2 2095 #define mmBIF_FB_EN__xxFB_WRITE_EN__SHIFT 0x1 2096 2097 #define mmSRBM_SOFT_RESET__xxSOFT_RESET_VMC_MASK 0x20000 2098 #define mmSRBM_SOFT_RESET__xxSOFT_RESET_VMC__SHIFT 0x11 2099 #define mmSRBM_SOFT_RESET__xxSOFT_RESET_MC_MASK 0x800 2100 #define mmSRBM_SOFT_RESET__xxSOFT_RESET_MC__SHIFT 0xb 2101 2102 #define MC_SEQ_MISC0__MT__MASK 0xf0000000 2103 #define MC_SEQ_MISC0__MT__GDDR1 0x10000000 2104 #define MC_SEQ_MISC0__MT__DDR2 0x20000000 2105 #define MC_SEQ_MISC0__MT__GDDR3 0x30000000 2106 #define MC_SEQ_MISC0__MT__GDDR4 0x40000000 2107 #define MC_SEQ_MISC0__MT__GDDR5 0x50000000 2108 #define MC_SEQ_MISC0__MT__HBM 0x60000000 2109 #define MC_SEQ_MISC0__MT__DDR3 0xB0000000 2110 2111 #define CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK 0x4000000 2112 #define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12) 2113 #define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 2114 #define PACKET3_SEM_SEL_WAIT (0x7 << 29) 2115 2116 #define CONFIG_CNTL 0x1509 2117 #define CC_DRM_ID_STRAPS 0X1559 2118 #define AMDGPU_PCIE_INDEX 0xc 2119 #define AMDGPU_PCIE_DATA 0xd 2120 2121 #define DMA_SEM_INCOMPLETE_TIMER_CNTL 0x3411 2122 #define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0x3412 2123 #define DMA_MODE 0x342f 2124 #define DMA_RB_RPTR_ADDR_HI 0x3407 2125 #define DMA_RB_RPTR_ADDR_LO 0x3408 2126 #define DMA_BUSY_MASK 0x20 2127 #define DMA1_BUSY_MASK 0X40 2128 #define SDMA_MAX_INSTANCE 2 2129 2130 #define PCIE_BUS_CLK 10000 2131 #define TCLK (PCIE_BUS_CLK / 10) 2132 #define PCIE_PORT_INDEX 0xe 2133 #define PCIE_PORT_DATA 0xf 2134 #define EVERGREEN_PIF_PHY0_INDEX 0x8 2135 #define EVERGREEN_PIF_PHY0_DATA 0xc 2136 #define EVERGREEN_PIF_PHY1_INDEX 0x10 2137 #define EVERGREEN_PIF_PHY1_DATA 0x14 2138 2139 #define MC_VM_FB_OFFSET 0x81a 2140 2141 /* Discrete VCE clocks */ 2142 #define CG_VCEPLL_FUNC_CNTL 0xc0030600 2143 #define VCEPLL_RESET_MASK 0x00000001 2144 #define VCEPLL_SLEEP_MASK 0x00000002 2145 #define VCEPLL_BYPASS_EN_MASK 0x00000004 2146 #define VCEPLL_CTLREQ_MASK 0x00000008 2147 #define VCEPLL_VCO_MODE_MASK 0x00000600 2148 #define VCEPLL_REF_DIV_MASK 0x003F0000 2149 #define VCEPLL_CTLACK_MASK 0x40000000 2150 #define VCEPLL_CTLACK2_MASK 0x80000000 2151 2152 #define CG_VCEPLL_FUNC_CNTL_2 0xc0030601 2153 #define VCEPLL_PDIV_A(x) ((x) << 0) 2154 #define VCEPLL_PDIV_A_MASK 0x0000007F 2155 #define VCEPLL_PDIV_B(x) ((x) << 8) 2156 #define VCEPLL_PDIV_B_MASK 0x00007F00 2157 #define EVCLK_SRC_SEL(x) ((x) << 20) 2158 #define EVCLK_SRC_SEL_MASK 0x01F00000 2159 #define ECCLK_SRC_SEL(x) ((x) << 25) 2160 #define ECCLK_SRC_SEL_MASK 0x3E000000 2161 2162 #define CG_VCEPLL_FUNC_CNTL_3 0xc0030602 2163 #define VCEPLL_FB_DIV(x) ((x) << 0) 2164 #define VCEPLL_FB_DIV_MASK 0x01FFFFFF 2165 2166 #define CG_VCEPLL_FUNC_CNTL_4 0xc0030603 2167 2168 #define CG_VCEPLL_FUNC_CNTL_5 0xc0030604 2169 #define CG_VCEPLL_SPREAD_SPECTRUM 0xc0030606 2170 #define VCEPLL_SSEN_MASK 0x00000001 2171 2172 2173 #endif 2174