1 /* 2 * Copyright (C) 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef _gc_9_4_1_OFFSET_HEADER 22 #define _gc_9_4_1_OFFSET_HEADER 23 24 // addressBlock: gc_grbmdec 25 // base address: 0x8000 26 #define mmGRBM_CNTL 0x0000 27 #define mmGRBM_CNTL_BASE_IDX 0 28 #define mmGRBM_SKEW_CNTL 0x0001 29 #define mmGRBM_SKEW_CNTL_BASE_IDX 0 30 #define mmGRBM_STATUS2 0x0002 31 #define mmGRBM_STATUS2_BASE_IDX 0 32 #define mmGRBM_PWR_CNTL 0x0003 33 #define mmGRBM_PWR_CNTL_BASE_IDX 0 34 #define mmGRBM_STATUS 0x0004 35 #define mmGRBM_STATUS_BASE_IDX 0 36 #define mmGRBM_STATUS_SE0 0x0005 37 #define mmGRBM_STATUS_SE0_BASE_IDX 0 38 #define mmGRBM_STATUS_SE1 0x0006 39 #define mmGRBM_STATUS_SE1_BASE_IDX 0 40 #define mmGRBM_SOFT_RESET 0x0008 41 #define mmGRBM_SOFT_RESET_BASE_IDX 0 42 #define mmGRBM_GFX_CLKEN_CNTL 0x000c 43 #define mmGRBM_GFX_CLKEN_CNTL_BASE_IDX 0 44 #define mmGRBM_WAIT_IDLE_CLOCKS 0x000d 45 #define mmGRBM_WAIT_IDLE_CLOCKS_BASE_IDX 0 46 #define mmGRBM_STATUS_SE2 0x000e 47 #define mmGRBM_STATUS_SE2_BASE_IDX 0 48 #define mmGRBM_STATUS_SE3 0x000f 49 #define mmGRBM_STATUS_SE3_BASE_IDX 0 50 #define mmGRBM_READ_ERROR 0x0016 51 #define mmGRBM_READ_ERROR_BASE_IDX 0 52 #define mmGRBM_READ_ERROR2 0x0017 53 #define mmGRBM_READ_ERROR2_BASE_IDX 0 54 #define mmGRBM_INT_CNTL 0x0018 55 #define mmGRBM_INT_CNTL_BASE_IDX 0 56 #define mmGRBM_TRAP_OP 0x0019 57 #define mmGRBM_TRAP_OP_BASE_IDX 0 58 #define mmGRBM_TRAP_ADDR 0x001a 59 #define mmGRBM_TRAP_ADDR_BASE_IDX 0 60 #define mmGRBM_TRAP_ADDR_MSK 0x001b 61 #define mmGRBM_TRAP_ADDR_MSK_BASE_IDX 0 62 #define mmGRBM_TRAP_WD 0x001c 63 #define mmGRBM_TRAP_WD_BASE_IDX 0 64 #define mmGRBM_TRAP_WD_MSK 0x001d 65 #define mmGRBM_TRAP_WD_MSK_BASE_IDX 0 66 #define mmGRBM_DSM_BYPASS 0x001e 67 #define mmGRBM_DSM_BYPASS_BASE_IDX 0 68 #define mmGRBM_WRITE_ERROR 0x001f 69 #define mmGRBM_WRITE_ERROR_BASE_IDX 0 70 #define mmGRBM_IOV_ERROR 0x0020 71 #define mmGRBM_IOV_ERROR_BASE_IDX 0 72 #define mmGRBM_CHIP_REVISION 0x0021 73 #define mmGRBM_CHIP_REVISION_BASE_IDX 0 74 #define mmGRBM_GFX_CNTL 0x0022 75 #define mmGRBM_GFX_CNTL_BASE_IDX 0 76 #define mmGRBM_RSMU_CFG 0x0023 77 #define mmGRBM_RSMU_CFG_BASE_IDX 0 78 #define mmGRBM_IH_CREDIT 0x0024 79 #define mmGRBM_IH_CREDIT_BASE_IDX 0 80 #define mmGRBM_PWR_CNTL2 0x0025 81 #define mmGRBM_PWR_CNTL2_BASE_IDX 0 82 #define mmGRBM_UTCL2_INVAL_RANGE_START 0x0026 83 #define mmGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX 0 84 #define mmGRBM_UTCL2_INVAL_RANGE_END 0x0027 85 #define mmGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX 0 86 #define mmGRBM_RSMU_READ_ERROR 0x0028 87 #define mmGRBM_RSMU_READ_ERROR_BASE_IDX 0 88 #define mmGRBM_CHICKEN_BITS 0x0029 89 #define mmGRBM_CHICKEN_BITS_BASE_IDX 0 90 #define mmGRBM_FENCE_RANGE0 0x002a 91 #define mmGRBM_FENCE_RANGE0_BASE_IDX 0 92 #define mmGRBM_FENCE_RANGE1 0x002b 93 #define mmGRBM_FENCE_RANGE1_BASE_IDX 0 94 #define mmGRBM_NOWHERE 0x003f 95 #define mmGRBM_NOWHERE_BASE_IDX 0 96 #define mmGRBM_SCRATCH_REG0 0x0040 97 #define mmGRBM_SCRATCH_REG0_BASE_IDX 0 98 #define mmGRBM_SCRATCH_REG1 0x0041 99 #define mmGRBM_SCRATCH_REG1_BASE_IDX 0 100 #define mmGRBM_SCRATCH_REG2 0x0042 101 #define mmGRBM_SCRATCH_REG2_BASE_IDX 0 102 #define mmGRBM_SCRATCH_REG3 0x0043 103 #define mmGRBM_SCRATCH_REG3_BASE_IDX 0 104 #define mmGRBM_SCRATCH_REG4 0x0044 105 #define mmGRBM_SCRATCH_REG4_BASE_IDX 0 106 #define mmGRBM_SCRATCH_REG5 0x0045 107 #define mmGRBM_SCRATCH_REG5_BASE_IDX 0 108 #define mmGRBM_SCRATCH_REG6 0x0046 109 #define mmGRBM_SCRATCH_REG6_BASE_IDX 0 110 #define mmGRBM_SCRATCH_REG7 0x0047 111 #define mmGRBM_SCRATCH_REG7_BASE_IDX 0 112 113 // addressBlock: gc_cppdec2 114 // base address: 0xc600 115 #define mmCPF_EDC_TAG_CNT 0x1189 116 #define mmCPF_EDC_TAG_CNT_BASE_IDX 0 117 #define mmCPF_EDC_ROQ_CNT 0x118a 118 #define mmCPF_EDC_ROQ_CNT_BASE_IDX 0 119 #define mmCPG_EDC_TAG_CNT 0x118b 120 #define mmCPG_EDC_TAG_CNT_BASE_IDX 0 121 #define mmCPG_EDC_DMA_CNT 0x118d 122 #define mmCPG_EDC_DMA_CNT_BASE_IDX 0 123 #define mmCPC_EDC_SCRATCH_CNT 0x118e 124 #define mmCPC_EDC_SCRATCH_CNT_BASE_IDX 0 125 #define mmCPC_EDC_UCODE_CNT 0x118f 126 #define mmCPC_EDC_UCODE_CNT_BASE_IDX 0 127 #define mmDC_EDC_STATE_CNT 0x1191 128 #define mmDC_EDC_STATE_CNT_BASE_IDX 0 129 #define mmDC_EDC_CSINVOC_CNT 0x1192 130 #define mmDC_EDC_CSINVOC_CNT_BASE_IDX 0 131 #define mmDC_EDC_RESTORE_CNT 0x1193 132 #define mmDC_EDC_RESTORE_CNT_BASE_IDX 0 133 134 // addressBlock: gc_gdsdec 135 // base address: 0x9700 136 #define mmGDS_EDC_CNT 0x05c5 137 #define mmGDS_EDC_CNT_BASE_IDX 0 138 #define mmGDS_EDC_GRBM_CNT 0x05c6 139 #define mmGDS_EDC_GRBM_CNT_BASE_IDX 0 140 #define mmGDS_EDC_OA_DED 0x05c7 141 #define mmGDS_EDC_OA_DED_BASE_IDX 0 142 #define mmGDS_EDC_OA_PHY_CNT 0x05cb 143 #define mmGDS_EDC_OA_PHY_CNT_BASE_IDX 0 144 #define mmGDS_EDC_OA_PIPE_CNT 0x05cc 145 #define mmGDS_EDC_OA_PIPE_CNT_BASE_IDX 0 146 147 // addressBlock: gc_shsdec 148 // base address: 0x9000 149 #define mmSPI_EDC_CNT 0x0445 150 #define mmSPI_EDC_CNT_BASE_IDX 0 151 152 // addressBlock: gc_sqdec 153 // base address: 0x8c00 154 #define mmSQC_EDC_CNT2 0x032c 155 #define mmSQC_EDC_CNT2_BASE_IDX 0 156 #define mmSQC_EDC_CNT3 0x032d 157 #define mmSQC_EDC_CNT3_BASE_IDX 0 158 #define mmSQC_EDC_PARITY_CNT3 0x032e 159 #define mmSQC_EDC_PARITY_CNT3_BASE_IDX 0 160 #define mmSQC_EDC_CNT 0x03a2 161 #define mmSQC_EDC_CNT_BASE_IDX 0 162 #define mmSQ_EDC_SEC_CNT 0x03a3 163 #define mmSQ_EDC_SEC_CNT_BASE_IDX 0 164 #define mmSQ_EDC_DED_CNT 0x03a4 165 #define mmSQ_EDC_DED_CNT_BASE_IDX 0 166 #define mmSQ_EDC_INFO 0x03a5 167 #define mmSQ_EDC_INFO_BASE_IDX 0 168 #define mmSQ_EDC_CNT 0x03a6 169 #define mmSQ_EDC_CNT_BASE_IDX 0 170 171 // addressBlock: gc_tpdec 172 // base address: 0x9400 173 #define mmTA_EDC_CNT 0x0586 174 #define mmTA_EDC_CNT_BASE_IDX 0 175 176 // addressBlock: gc_tcdec 177 // base address: 0xac00 178 #define mmTCP_EDC_CNT 0x0b17 179 #define mmTCP_EDC_CNT_BASE_IDX 0 180 #define mmTCP_EDC_CNT_NEW 0x0b18 181 #define mmTCP_EDC_CNT_NEW_BASE_IDX 0 182 #define mmTCP_ATC_EDC_GATCL1_CNT 0x12b1 183 #define mmTCP_ATC_EDC_GATCL1_CNT_BASE_IDX 0 184 #define mmTCI_EDC_CNT 0x0b60 185 #define mmTCI_EDC_CNT_BASE_IDX 0 186 #define mmTCC_EDC_CNT 0x0b82 187 #define mmTCC_EDC_CNT_BASE_IDX 0 188 #define mmTCC_EDC_CNT2 0x0b83 189 #define mmTCC_EDC_CNT2_BASE_IDX 0 190 #define mmTCA_EDC_CNT 0x0bc5 191 #define mmTCA_EDC_CNT_BASE_IDX 0 192 193 // addressBlock: gc_tpdec 194 // base address: 0x9400 195 #define mmTD_EDC_CNT 0x052e 196 #define mmTD_EDC_CNT_BASE_IDX 0 197 #define mmTA_EDC_CNT 0x0586 198 #define mmTA_EDC_CNT_BASE_IDX 0 199 200 // addressBlock: gc_ea_gceadec2 201 // base address: 0x9c00 202 #define mmGCEA_EDC_CNT 0x0706 203 #define mmGCEA_EDC_CNT_BASE_IDX 0 204 #define mmGCEA_EDC_CNT2 0x0707 205 #define mmGCEA_EDC_CNT2_BASE_IDX 0 206 #define mmGCEA_EDC_CNT3 0x071b 207 #define mmGCEA_EDC_CNT3_BASE_IDX 0 208 #define mmGCEA_ERR_STATUS 0x0712 209 #define mmGCEA_ERR_STATUS_BASE_IDX 0 210 211 // addressBlock: gc_gfxudec 212 // base address: 0x30000 213 #define mmSCRATCH_REG0 0x2040 214 #define mmSCRATCH_REG0_BASE_IDX 1 215 #define mmSCRATCH_REG1 0x2041 216 #define mmSCRATCH_REG1_BASE_IDX 1 217 #define mmSCRATCH_REG2 0x2042 218 #define mmSCRATCH_REG2_BASE_IDX 1 219 #define mmSCRATCH_REG3 0x2043 220 #define mmSCRATCH_REG3_BASE_IDX 1 221 #define mmSCRATCH_REG4 0x2044 222 #define mmSCRATCH_REG4_BASE_IDX 1 223 #define mmSCRATCH_REG5 0x2045 224 #define mmSCRATCH_REG5_BASE_IDX 1 225 #define mmSCRATCH_REG6 0x2046 226 #define mmSCRATCH_REG6_BASE_IDX 1 227 #define mmSCRATCH_REG7 0x2047 228 #define mmSCRATCH_REG7_BASE_IDX 1 229 #define mmGRBM_GFX_INDEX 0x2200 230 #define mmGRBM_GFX_INDEX_BASE_IDX 1 231 232 // addressBlock: gc_utcl2_atcl2dec 233 // base address: 0xa000 234 #define mmATC_L2_CACHE_4K_DSM_INDEX 0x080e 235 #define mmATC_L2_CACHE_4K_DSM_INDEX_BASE_IDX 0 236 #define mmATC_L2_CACHE_2M_DSM_INDEX 0x080f 237 #define mmATC_L2_CACHE_2M_DSM_INDEX_BASE_IDX 0 238 #define mmATC_L2_CACHE_4K_DSM_CNTL 0x0810 239 #define mmATC_L2_CACHE_4K_DSM_CNTL_BASE_IDX 0 240 #define mmATC_L2_CACHE_2M_DSM_CNTL 0x0811 241 #define mmATC_L2_CACHE_2M_DSM_CNTL_BASE_IDX 0 242 243 // addressBlock: gc_utcl2_vml2pfdec 244 // base address: 0xa100 245 #define mmVML2_MEM_ECC_INDEX 0x0860 246 #define mmVML2_MEM_ECC_INDEX_BASE_IDX 0 247 #define mmVML2_WALKER_MEM_ECC_INDEX 0x0861 248 #define mmVML2_WALKER_MEM_ECC_INDEX_BASE_IDX 0 249 #define mmUTCL2_MEM_ECC_INDEX 0x0862 250 #define mmUTCL2_MEM_ECC_INDEX_BASE_IDX 0 251 252 #define mmVML2_MEM_ECC_CNTL 0x0863 253 #define mmVML2_MEM_ECC_CNTL_BASE_IDX 0 254 #define mmVML2_WALKER_MEM_ECC_CNTL 0x0864 255 #define mmVML2_WALKER_MEM_ECC_CNTL_BASE_IDX 0 256 #define mmUTCL2_MEM_ECC_CNTL 0x0865 257 #define mmUTCL2_MEM_ECC_CNTL_BASE_IDX 0 258 259 // addressBlock: gc_rlcpdec 260 // base address: 0x3b000 261 #define mmRLC_EDC_CNT 0x4d40 262 #define mmRLC_EDC_CNT_BASE_IDX 1 263 #define mmRLC_EDC_CNT2 0x4d41 264 #define mmRLC_EDC_CNT2_BASE_IDX 1 265 266 #endif 267