1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/mlx5/driver.h>
34 #include <linux/mlx5/eswitch.h>
35 #include "mlx5_core.h"
36 #include "../../mlxfw/mlxfw.h"
37 #include "lib/tout.h"
38
39 enum {
40 MCQS_IDENTIFIER_BOOT_IMG = 0x1,
41 MCQS_IDENTIFIER_OEM_NVCONFIG = 0x4,
42 MCQS_IDENTIFIER_MLNX_NVCONFIG = 0x5,
43 MCQS_IDENTIFIER_CS_TOKEN = 0x6,
44 MCQS_IDENTIFIER_DBG_TOKEN = 0x7,
45 MCQS_IDENTIFIER_GEARBOX = 0xA,
46 };
47
48 enum {
49 MCQS_UPDATE_STATE_IDLE,
50 MCQS_UPDATE_STATE_IN_PROGRESS,
51 MCQS_UPDATE_STATE_APPLIED,
52 MCQS_UPDATE_STATE_ACTIVE,
53 MCQS_UPDATE_STATE_ACTIVE_PENDING_RESET,
54 MCQS_UPDATE_STATE_FAILED,
55 MCQS_UPDATE_STATE_CANCELED,
56 MCQS_UPDATE_STATE_BUSY,
57 };
58
59 enum {
60 MCQI_INFO_TYPE_CAPABILITIES = 0x0,
61 MCQI_INFO_TYPE_VERSION = 0x1,
62 MCQI_INFO_TYPE_ACTIVATION_METHOD = 0x5,
63 };
64
65 enum {
66 MCQI_FW_RUNNING_VERSION = 0,
67 MCQI_FW_STORED_VERSION = 1,
68 };
69
mlx5_query_board_id(struct mlx5_core_dev * dev)70 int mlx5_query_board_id(struct mlx5_core_dev *dev)
71 {
72 u32 *out;
73 int outlen = MLX5_ST_SZ_BYTES(query_adapter_out);
74 u32 in[MLX5_ST_SZ_DW(query_adapter_in)] = {};
75 int err;
76
77 out = kzalloc(outlen, GFP_KERNEL);
78 if (!out)
79 return -ENOMEM;
80
81 MLX5_SET(query_adapter_in, in, opcode, MLX5_CMD_OP_QUERY_ADAPTER);
82 err = mlx5_cmd_exec_inout(dev, query_adapter, in, out);
83 if (err)
84 goto out;
85
86 memcpy(dev->board_id,
87 MLX5_ADDR_OF(query_adapter_out, out,
88 query_adapter_struct.vsd_contd_psid),
89 MLX5_FLD_SZ_BYTES(query_adapter_out,
90 query_adapter_struct.vsd_contd_psid));
91
92 out:
93 kfree(out);
94 return err;
95 }
96
mlx5_core_query_vendor_id(struct mlx5_core_dev * mdev,u32 * vendor_id)97 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id)
98 {
99 u32 *out;
100 int outlen = MLX5_ST_SZ_BYTES(query_adapter_out);
101 u32 in[MLX5_ST_SZ_DW(query_adapter_in)] = {};
102 int err;
103
104 out = kzalloc(outlen, GFP_KERNEL);
105 if (!out)
106 return -ENOMEM;
107
108 MLX5_SET(query_adapter_in, in, opcode, MLX5_CMD_OP_QUERY_ADAPTER);
109 err = mlx5_cmd_exec_inout(mdev, query_adapter, in, out);
110 if (err)
111 goto out;
112
113 *vendor_id = MLX5_GET(query_adapter_out, out,
114 query_adapter_struct.ieee_vendor_id);
115 out:
116 kfree(out);
117 return err;
118 }
119 EXPORT_SYMBOL(mlx5_core_query_vendor_id);
120
mlx5_get_pcam_reg(struct mlx5_core_dev * dev)121 static int mlx5_get_pcam_reg(struct mlx5_core_dev *dev)
122 {
123 return mlx5_query_pcam_reg(dev, dev->caps.pcam,
124 MLX5_PCAM_FEATURE_ENHANCED_FEATURES,
125 MLX5_PCAM_REGS_5000_TO_507F);
126 }
127
mlx5_get_mcam_access_reg_group(struct mlx5_core_dev * dev,enum mlx5_mcam_reg_groups group)128 static int mlx5_get_mcam_access_reg_group(struct mlx5_core_dev *dev,
129 enum mlx5_mcam_reg_groups group)
130 {
131 return mlx5_query_mcam_reg(dev, dev->caps.mcam[group],
132 MLX5_MCAM_FEATURE_ENHANCED_FEATURES, group);
133 }
134
mlx5_get_qcam_reg(struct mlx5_core_dev * dev)135 static int mlx5_get_qcam_reg(struct mlx5_core_dev *dev)
136 {
137 return mlx5_query_qcam_reg(dev, dev->caps.qcam,
138 MLX5_QCAM_FEATURE_ENHANCED_FEATURES,
139 MLX5_QCAM_REGS_FIRST_128);
140 }
141
mlx5_query_hca_caps(struct mlx5_core_dev * dev)142 int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
143 {
144 int err;
145
146 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_CUR);
147 if (err)
148 return err;
149
150 if (MLX5_CAP_GEN(dev, port_selection_cap)) {
151 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_PORT_SELECTION, HCA_CAP_OPMOD_GET_CUR);
152 if (err)
153 return err;
154 }
155
156 if (MLX5_CAP_GEN(dev, hca_cap_2)) {
157 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_GENERAL_2, HCA_CAP_OPMOD_GET_CUR);
158 if (err)
159 return err;
160 }
161
162 if (MLX5_CAP_GEN(dev, eth_net_offloads)) {
163 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ETHERNET_OFFLOADS,
164 HCA_CAP_OPMOD_GET_CUR);
165 if (err)
166 return err;
167 }
168
169 if (MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) {
170 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
171 HCA_CAP_OPMOD_GET_CUR);
172 if (err)
173 return err;
174 }
175
176 if (MLX5_CAP_GEN(dev, pg)) {
177 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ODP, HCA_CAP_OPMOD_GET_CUR);
178 if (err)
179 return err;
180 }
181
182 if (MLX5_CAP_GEN(dev, atomic)) {
183 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ATOMIC, HCA_CAP_OPMOD_GET_CUR);
184 if (err)
185 return err;
186 }
187
188 if (MLX5_CAP_GEN(dev, roce)) {
189 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ROCE, HCA_CAP_OPMOD_GET_CUR);
190 if (err)
191 return err;
192 }
193
194 if (MLX5_CAP_GEN(dev, nic_flow_table) ||
195 MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) {
196 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_FLOW_TABLE, HCA_CAP_OPMOD_GET_CUR);
197 if (err)
198 return err;
199 }
200
201 if (MLX5_ESWITCH_MANAGER(dev)) {
202 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ESWITCH_FLOW_TABLE,
203 HCA_CAP_OPMOD_GET_CUR);
204 if (err)
205 return err;
206
207 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ESWITCH, HCA_CAP_OPMOD_GET_CUR);
208 if (err)
209 return err;
210 }
211
212 if (MLX5_CAP_GEN(dev, qos)) {
213 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_QOS, HCA_CAP_OPMOD_GET_CUR);
214 if (err)
215 return err;
216 }
217
218 if (MLX5_CAP_GEN(dev, debug))
219 mlx5_core_get_caps_mode(dev, MLX5_CAP_DEBUG, HCA_CAP_OPMOD_GET_CUR);
220
221 if (MLX5_CAP_GEN(dev, pcam_reg))
222 mlx5_get_pcam_reg(dev);
223
224 if (MLX5_CAP_GEN(dev, mcam_reg)) {
225 mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_FIRST_128);
226 mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_0x9100_0x917F);
227 mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_0x9180_0x91FF);
228 }
229
230 if (MLX5_CAP_GEN(dev, qcam_reg))
231 mlx5_get_qcam_reg(dev);
232
233 if (MLX5_CAP_GEN(dev, device_memory)) {
234 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_DEV_MEM, HCA_CAP_OPMOD_GET_CUR);
235 if (err)
236 return err;
237 }
238
239 if (MLX5_CAP_GEN(dev, event_cap)) {
240 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_DEV_EVENT, HCA_CAP_OPMOD_GET_CUR);
241 if (err)
242 return err;
243 }
244
245 if (MLX5_CAP_GEN(dev, tls_tx) || MLX5_CAP_GEN(dev, tls_rx)) {
246 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_TLS, HCA_CAP_OPMOD_GET_CUR);
247 if (err)
248 return err;
249 }
250
251 if (MLX5_CAP_GEN_64(dev, general_obj_types) &
252 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) {
253 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_VDPA_EMULATION, HCA_CAP_OPMOD_GET_CUR);
254 if (err)
255 return err;
256 }
257
258 if (MLX5_CAP_GEN(dev, ipsec_offload)) {
259 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_IPSEC, HCA_CAP_OPMOD_GET_CUR);
260 if (err)
261 return err;
262 }
263
264 if (MLX5_CAP_GEN(dev, crypto)) {
265 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_CRYPTO, HCA_CAP_OPMOD_GET_CUR);
266 if (err)
267 return err;
268 }
269
270 if (MLX5_CAP_GEN_64(dev, general_obj_types) &
271 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD) {
272 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_MACSEC, HCA_CAP_OPMOD_GET_CUR);
273 if (err)
274 return err;
275 }
276
277 if (MLX5_CAP_GEN(dev, adv_virtualization)) {
278 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ADV_VIRTUALIZATION,
279 HCA_CAP_OPMOD_GET_CUR);
280 if (err)
281 return err;
282 }
283
284 if (MLX5_CAP_GEN(dev, shampo)) {
285 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_SHAMPO, HCA_CAP_OPMOD_GET_CUR);
286 if (err)
287 return err;
288 }
289
290 if (MLX5_CAP_GEN(dev, adv_rdma)) {
291 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ADV_RDMA,
292 HCA_CAP_OPMOD_GET_CUR);
293 if (err)
294 return err;
295 }
296
297 return 0;
298 }
299
mlx5_cmd_init_hca(struct mlx5_core_dev * dev,u32 * sw_owner_id)300 int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, u32 *sw_owner_id)
301 {
302 u32 in[MLX5_ST_SZ_DW(init_hca_in)] = {};
303 int i;
304
305 MLX5_SET(init_hca_in, in, opcode, MLX5_CMD_OP_INIT_HCA);
306
307 if (MLX5_CAP_GEN(dev, sw_owner_id)) {
308 for (i = 0; i < 4; i++)
309 MLX5_ARRAY_SET(init_hca_in, in, sw_owner_id, i,
310 sw_owner_id[i]);
311 }
312
313 if (MLX5_CAP_GEN_2_MAX(dev, sw_vhca_id_valid) &&
314 dev->priv.sw_vhca_id > 0)
315 MLX5_SET(init_hca_in, in, sw_vhca_id, dev->priv.sw_vhca_id);
316
317 return mlx5_cmd_exec_in(dev, init_hca, in);
318 }
319
mlx5_cmd_teardown_hca(struct mlx5_core_dev * dev)320 int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev)
321 {
322 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {};
323
324 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
325 return mlx5_cmd_exec_in(dev, teardown_hca, in);
326 }
327
mlx5_cmd_force_teardown_hca(struct mlx5_core_dev * dev)328 int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev)
329 {
330 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0};
331 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0};
332 int force_state;
333 int ret;
334
335 if (!MLX5_CAP_GEN(dev, force_teardown)) {
336 mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n");
337 return -EOPNOTSUPP;
338 }
339
340 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
341 MLX5_SET(teardown_hca_in, in, profile, MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE);
342
343 ret = mlx5_cmd_exec_polling(dev, in, sizeof(in), out, sizeof(out));
344 if (ret)
345 return ret;
346
347 force_state = MLX5_GET(teardown_hca_out, out, state);
348 if (force_state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) {
349 mlx5_core_warn(dev, "teardown with force mode failed, doing normal teardown\n");
350 return -EIO;
351 }
352
353 return 0;
354 }
355
mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev * dev)356 int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev)
357 {
358 unsigned long end, delay_ms = mlx5_tout_ms(dev, TEARDOWN);
359 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {};
360 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {};
361 int state;
362 int ret;
363
364 if (!MLX5_CAP_GEN(dev, fast_teardown)) {
365 mlx5_core_dbg(dev, "fast teardown is not supported in the firmware\n");
366 return -EOPNOTSUPP;
367 }
368
369 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
370 MLX5_SET(teardown_hca_in, in, profile,
371 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN);
372
373 ret = mlx5_cmd_exec_inout(dev, teardown_hca, in, out);
374 if (ret)
375 return ret;
376
377 state = MLX5_GET(teardown_hca_out, out, state);
378 if (state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) {
379 mlx5_core_warn(dev, "teardown with fast mode failed\n");
380 return -EIO;
381 }
382
383 mlx5_set_nic_state(dev, MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED);
384
385 /* Loop until device state turns to disable */
386 end = jiffies + msecs_to_jiffies(delay_ms);
387 do {
388 if (mlx5_get_nic_state(dev) == MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED)
389 break;
390 if (pci_channel_offline(dev->pdev)) {
391 mlx5_core_err(dev, "PCI channel offline, stop waiting for NIC IFC\n");
392 return -EACCES;
393 }
394
395 cond_resched();
396 } while (!time_after(jiffies, end));
397
398 if (mlx5_get_nic_state(dev) != MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED) {
399 dev_err(&dev->pdev->dev, "NIC IFC still %d after %lums.\n",
400 mlx5_get_nic_state(dev), delay_ms);
401 return -EIO;
402 }
403
404 return 0;
405 }
406
407 enum mlxsw_reg_mcc_instruction {
408 MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01,
409 MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02,
410 MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03,
411 MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04,
412 MLX5_REG_MCC_INSTRUCTION_ACTIVATE = 0x06,
413 MLX5_REG_MCC_INSTRUCTION_CANCEL = 0x08,
414 };
415
mlx5_reg_mcc_set(struct mlx5_core_dev * dev,enum mlxsw_reg_mcc_instruction instr,u16 component_index,u32 update_handle,u32 component_size)416 static int mlx5_reg_mcc_set(struct mlx5_core_dev *dev,
417 enum mlxsw_reg_mcc_instruction instr,
418 u16 component_index, u32 update_handle,
419 u32 component_size)
420 {
421 u32 out[MLX5_ST_SZ_DW(mcc_reg)];
422 u32 in[MLX5_ST_SZ_DW(mcc_reg)];
423
424 memset(in, 0, sizeof(in));
425
426 MLX5_SET(mcc_reg, in, instruction, instr);
427 MLX5_SET(mcc_reg, in, component_index, component_index);
428 MLX5_SET(mcc_reg, in, update_handle, update_handle);
429 MLX5_SET(mcc_reg, in, component_size, component_size);
430
431 return mlx5_core_access_reg(dev, in, sizeof(in), out,
432 sizeof(out), MLX5_REG_MCC, 0, 1);
433 }
434
mlx5_reg_mcc_query(struct mlx5_core_dev * dev,u32 * update_handle,u8 * error_code,u8 * control_state)435 static int mlx5_reg_mcc_query(struct mlx5_core_dev *dev,
436 u32 *update_handle, u8 *error_code,
437 u8 *control_state)
438 {
439 u32 out[MLX5_ST_SZ_DW(mcc_reg)];
440 u32 in[MLX5_ST_SZ_DW(mcc_reg)];
441 int err;
442
443 memset(in, 0, sizeof(in));
444 memset(out, 0, sizeof(out));
445 MLX5_SET(mcc_reg, in, update_handle, *update_handle);
446
447 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
448 sizeof(out), MLX5_REG_MCC, 0, 0);
449 if (err)
450 goto out;
451
452 *update_handle = MLX5_GET(mcc_reg, out, update_handle);
453 *error_code = MLX5_GET(mcc_reg, out, error_code);
454 *control_state = MLX5_GET(mcc_reg, out, control_state);
455
456 out:
457 return err;
458 }
459
mlx5_reg_mcda_set(struct mlx5_core_dev * dev,u32 update_handle,u32 offset,u16 size,u8 * data)460 static int mlx5_reg_mcda_set(struct mlx5_core_dev *dev,
461 u32 update_handle,
462 u32 offset, u16 size,
463 u8 *data)
464 {
465 int err, in_size = MLX5_ST_SZ_BYTES(mcda_reg) + size;
466 u32 out[MLX5_ST_SZ_DW(mcda_reg)];
467 int i, j, dw_size = size >> 2;
468 __be32 data_element;
469 u32 *in;
470
471 in = kzalloc(in_size, GFP_KERNEL);
472 if (!in)
473 return -ENOMEM;
474
475 MLX5_SET(mcda_reg, in, update_handle, update_handle);
476 MLX5_SET(mcda_reg, in, offset, offset);
477 MLX5_SET(mcda_reg, in, size, size);
478
479 for (i = 0; i < dw_size; i++) {
480 j = i * 4;
481 data_element = htonl(*(u32 *)&data[j]);
482 memcpy(MLX5_ADDR_OF(mcda_reg, in, data) + j, &data_element, 4);
483 }
484
485 err = mlx5_core_access_reg(dev, in, in_size, out,
486 sizeof(out), MLX5_REG_MCDA, 0, 1);
487 kfree(in);
488 return err;
489 }
490
mlx5_reg_mcqi_query(struct mlx5_core_dev * dev,u16 component_index,bool read_pending,u8 info_type,u16 data_size,void * mcqi_data)491 static int mlx5_reg_mcqi_query(struct mlx5_core_dev *dev,
492 u16 component_index, bool read_pending,
493 u8 info_type, u16 data_size, void *mcqi_data)
494 {
495 u32 out[MLX5_ST_SZ_DW(mcqi_reg) + MLX5_UN_SZ_DW(mcqi_reg_data)] = {};
496 u32 in[MLX5_ST_SZ_DW(mcqi_reg)] = {};
497 void *data;
498 int err;
499
500 MLX5_SET(mcqi_reg, in, component_index, component_index);
501 MLX5_SET(mcqi_reg, in, read_pending_component, read_pending);
502 MLX5_SET(mcqi_reg, in, info_type, info_type);
503 MLX5_SET(mcqi_reg, in, data_size, data_size);
504
505 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
506 MLX5_ST_SZ_BYTES(mcqi_reg) + data_size,
507 MLX5_REG_MCQI, 0, 0);
508 if (err)
509 return err;
510
511 data = MLX5_ADDR_OF(mcqi_reg, out, data);
512 memcpy(mcqi_data, data, data_size);
513
514 return 0;
515 }
516
mlx5_reg_mcqi_caps_query(struct mlx5_core_dev * dev,u16 component_index,u32 * max_component_size,u8 * log_mcda_word_size,u16 * mcda_max_write_size)517 static int mlx5_reg_mcqi_caps_query(struct mlx5_core_dev *dev, u16 component_index,
518 u32 *max_component_size, u8 *log_mcda_word_size,
519 u16 *mcda_max_write_size)
520 {
521 u32 mcqi_reg[MLX5_ST_SZ_DW(mcqi_cap)] = {};
522 int err;
523
524 err = mlx5_reg_mcqi_query(dev, component_index, 0,
525 MCQI_INFO_TYPE_CAPABILITIES,
526 MLX5_ST_SZ_BYTES(mcqi_cap), mcqi_reg);
527 if (err)
528 return err;
529
530 *max_component_size = MLX5_GET(mcqi_cap, mcqi_reg, max_component_size);
531 *log_mcda_word_size = MLX5_GET(mcqi_cap, mcqi_reg, log_mcda_word_size);
532 *mcda_max_write_size = MLX5_GET(mcqi_cap, mcqi_reg, mcda_max_write_size);
533
534 return 0;
535 }
536
537 struct mlx5_mlxfw_dev {
538 struct mlxfw_dev mlxfw_dev;
539 struct mlx5_core_dev *mlx5_core_dev;
540 };
541
mlx5_component_query(struct mlxfw_dev * mlxfw_dev,u16 component_index,u32 * p_max_size,u8 * p_align_bits,u16 * p_max_write_size)542 static int mlx5_component_query(struct mlxfw_dev *mlxfw_dev,
543 u16 component_index, u32 *p_max_size,
544 u8 *p_align_bits, u16 *p_max_write_size)
545 {
546 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
547 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
548 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
549
550 if (!MLX5_CAP_GEN(dev, mcam_reg) || !MLX5_CAP_MCAM_REG(dev, mcqi)) {
551 mlx5_core_warn(dev, "caps query isn't supported by running FW\n");
552 return -EOPNOTSUPP;
553 }
554
555 return mlx5_reg_mcqi_caps_query(dev, component_index, p_max_size,
556 p_align_bits, p_max_write_size);
557 }
558
mlx5_fsm_lock(struct mlxfw_dev * mlxfw_dev,u32 * fwhandle)559 static int mlx5_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
560 {
561 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
562 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
563 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
564 u8 control_state, error_code;
565 int err;
566
567 *fwhandle = 0;
568 err = mlx5_reg_mcc_query(dev, fwhandle, &error_code, &control_state);
569 if (err)
570 return err;
571
572 if (control_state != MLXFW_FSM_STATE_IDLE)
573 return -EBUSY;
574
575 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
576 0, *fwhandle, 0);
577 }
578
mlx5_fsm_component_update(struct mlxfw_dev * mlxfw_dev,u32 fwhandle,u16 component_index,u32 component_size)579 static int mlx5_fsm_component_update(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
580 u16 component_index, u32 component_size)
581 {
582 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
583 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
584 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
585
586 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
587 component_index, fwhandle, component_size);
588 }
589
mlx5_fsm_block_download(struct mlxfw_dev * mlxfw_dev,u32 fwhandle,u8 * data,u16 size,u32 offset)590 static int mlx5_fsm_block_download(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
591 u8 *data, u16 size, u32 offset)
592 {
593 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
594 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
595 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
596
597 return mlx5_reg_mcda_set(dev, fwhandle, offset, size, data);
598 }
599
mlx5_fsm_component_verify(struct mlxfw_dev * mlxfw_dev,u32 fwhandle,u16 component_index)600 static int mlx5_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
601 u16 component_index)
602 {
603 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
604 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
605 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
606
607 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
608 component_index, fwhandle, 0);
609 }
610
mlx5_fsm_activate(struct mlxfw_dev * mlxfw_dev,u32 fwhandle)611 static int mlx5_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
612 {
613 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
614 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
615 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
616
617 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_ACTIVATE, 0,
618 fwhandle, 0);
619 }
620
mlx5_fsm_query_state(struct mlxfw_dev * mlxfw_dev,u32 fwhandle,enum mlxfw_fsm_state * fsm_state,enum mlxfw_fsm_state_err * fsm_state_err)621 static int mlx5_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
622 enum mlxfw_fsm_state *fsm_state,
623 enum mlxfw_fsm_state_err *fsm_state_err)
624 {
625 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
626 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
627 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
628 u8 control_state, error_code;
629 int err;
630
631 err = mlx5_reg_mcc_query(dev, &fwhandle, &error_code, &control_state);
632 if (err)
633 return err;
634
635 *fsm_state = control_state;
636 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
637 MLXFW_FSM_STATE_ERR_MAX);
638 return 0;
639 }
640
mlx5_fsm_cancel(struct mlxfw_dev * mlxfw_dev,u32 fwhandle)641 static void mlx5_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
642 {
643 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
644 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
645 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
646
647 mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_CANCEL, 0, fwhandle, 0);
648 }
649
mlx5_fsm_release(struct mlxfw_dev * mlxfw_dev,u32 fwhandle)650 static void mlx5_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
651 {
652 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
653 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
654 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
655
656 mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
657 fwhandle, 0);
658 }
659
mlx5_fsm_reactivate(struct mlxfw_dev * mlxfw_dev,u8 * status)660 static int mlx5_fsm_reactivate(struct mlxfw_dev *mlxfw_dev, u8 *status)
661 {
662 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
663 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
664 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
665 u32 out[MLX5_ST_SZ_DW(mirc_reg)];
666 u32 in[MLX5_ST_SZ_DW(mirc_reg)];
667 unsigned long exp_time;
668 int err;
669
670 exp_time = jiffies + msecs_to_jiffies(mlx5_tout_ms(dev, FSM_REACTIVATE));
671
672 if (!MLX5_CAP_MCAM_REG2(dev, mirc))
673 return -EOPNOTSUPP;
674
675 memset(in, 0, sizeof(in));
676
677 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
678 sizeof(out), MLX5_REG_MIRC, 0, 1);
679 if (err)
680 return err;
681
682 do {
683 memset(out, 0, sizeof(out));
684 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
685 sizeof(out), MLX5_REG_MIRC, 0, 0);
686 if (err)
687 return err;
688
689 *status = MLX5_GET(mirc_reg, out, status_code);
690 if (*status != MLXFW_FSM_REACTIVATE_STATUS_BUSY)
691 return 0;
692
693 msleep(20);
694 } while (time_before(jiffies, exp_time));
695
696 return 0;
697 }
698
699 static const struct mlxfw_dev_ops mlx5_mlxfw_dev_ops = {
700 .component_query = mlx5_component_query,
701 .fsm_lock = mlx5_fsm_lock,
702 .fsm_component_update = mlx5_fsm_component_update,
703 .fsm_block_download = mlx5_fsm_block_download,
704 .fsm_component_verify = mlx5_fsm_component_verify,
705 .fsm_activate = mlx5_fsm_activate,
706 .fsm_reactivate = mlx5_fsm_reactivate,
707 .fsm_query_state = mlx5_fsm_query_state,
708 .fsm_cancel = mlx5_fsm_cancel,
709 .fsm_release = mlx5_fsm_release
710 };
711
mlx5_firmware_flash(struct mlx5_core_dev * dev,const struct firmware * firmware,struct netlink_ext_ack * extack)712 int mlx5_firmware_flash(struct mlx5_core_dev *dev,
713 const struct firmware *firmware,
714 struct netlink_ext_ack *extack)
715 {
716 struct mlx5_mlxfw_dev mlx5_mlxfw_dev = {
717 .mlxfw_dev = {
718 .ops = &mlx5_mlxfw_dev_ops,
719 .psid = dev->board_id,
720 .psid_size = strlen(dev->board_id),
721 .devlink = priv_to_devlink(dev),
722 },
723 .mlx5_core_dev = dev
724 };
725
726 if (!MLX5_CAP_GEN(dev, mcam_reg) ||
727 !MLX5_CAP_MCAM_REG(dev, mcqi) ||
728 !MLX5_CAP_MCAM_REG(dev, mcc) ||
729 !MLX5_CAP_MCAM_REG(dev, mcda)) {
730 pr_info("%s flashing isn't supported by the running FW\n", __func__);
731 return -EOPNOTSUPP;
732 }
733
734 return mlxfw_firmware_flash(&mlx5_mlxfw_dev.mlxfw_dev,
735 firmware, extack);
736 }
737
mlx5_reg_mcqi_version_query(struct mlx5_core_dev * dev,u16 component_index,bool read_pending,u32 * mcqi_version_out)738 static int mlx5_reg_mcqi_version_query(struct mlx5_core_dev *dev,
739 u16 component_index, bool read_pending,
740 u32 *mcqi_version_out)
741 {
742 return mlx5_reg_mcqi_query(dev, component_index, read_pending,
743 MCQI_INFO_TYPE_VERSION,
744 MLX5_ST_SZ_BYTES(mcqi_version),
745 mcqi_version_out);
746 }
747
mlx5_reg_mcqs_query(struct mlx5_core_dev * dev,u32 * out,u16 component_index)748 static int mlx5_reg_mcqs_query(struct mlx5_core_dev *dev, u32 *out,
749 u16 component_index)
750 {
751 u8 out_sz = MLX5_ST_SZ_BYTES(mcqs_reg);
752 u32 in[MLX5_ST_SZ_DW(mcqs_reg)] = {};
753 int err;
754
755 memset(out, 0, out_sz);
756
757 MLX5_SET(mcqs_reg, in, component_index, component_index);
758
759 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
760 out_sz, MLX5_REG_MCQS, 0, 0);
761 return err;
762 }
763
764 /* scans component index sequentially, to find the boot img index */
mlx5_get_boot_img_component_index(struct mlx5_core_dev * dev)765 static int mlx5_get_boot_img_component_index(struct mlx5_core_dev *dev)
766 {
767 u32 out[MLX5_ST_SZ_DW(mcqs_reg)] = {};
768 u16 identifier, component_idx = 0;
769 bool quit;
770 int err;
771
772 do {
773 err = mlx5_reg_mcqs_query(dev, out, component_idx);
774 if (err)
775 return err;
776
777 identifier = MLX5_GET(mcqs_reg, out, identifier);
778 quit = !!MLX5_GET(mcqs_reg, out, last_index_flag);
779 quit |= identifier == MCQS_IDENTIFIER_BOOT_IMG;
780 } while (!quit && ++component_idx);
781
782 if (identifier != MCQS_IDENTIFIER_BOOT_IMG) {
783 mlx5_core_warn(dev, "mcqs: can't find boot_img component ix, last scanned idx %d\n",
784 component_idx);
785 return -EOPNOTSUPP;
786 }
787
788 return component_idx;
789 }
790
791 static int
mlx5_fw_image_pending(struct mlx5_core_dev * dev,int component_index,bool * pending_version_exists)792 mlx5_fw_image_pending(struct mlx5_core_dev *dev,
793 int component_index,
794 bool *pending_version_exists)
795 {
796 u32 out[MLX5_ST_SZ_DW(mcqs_reg)];
797 u8 component_update_state;
798 int err;
799
800 err = mlx5_reg_mcqs_query(dev, out, component_index);
801 if (err)
802 return err;
803
804 component_update_state = MLX5_GET(mcqs_reg, out, component_update_state);
805
806 if (component_update_state == MCQS_UPDATE_STATE_IDLE) {
807 *pending_version_exists = false;
808 } else if (component_update_state == MCQS_UPDATE_STATE_ACTIVE_PENDING_RESET) {
809 *pending_version_exists = true;
810 } else {
811 mlx5_core_warn(dev,
812 "mcqs: can't read pending fw version while fw state is %d\n",
813 component_update_state);
814 return -ENODATA;
815 }
816 return 0;
817 }
818
mlx5_fw_version_query(struct mlx5_core_dev * dev,u32 * running_ver,u32 * pending_ver)819 int mlx5_fw_version_query(struct mlx5_core_dev *dev,
820 u32 *running_ver, u32 *pending_ver)
821 {
822 u32 reg_mcqi_version[MLX5_ST_SZ_DW(mcqi_version)] = {};
823 bool pending_version_exists;
824 int component_index;
825 int err;
826
827 if (!MLX5_CAP_GEN(dev, mcam_reg) || !MLX5_CAP_MCAM_REG(dev, mcqi) ||
828 !MLX5_CAP_MCAM_REG(dev, mcqs)) {
829 mlx5_core_warn(dev, "fw query isn't supported by the FW\n");
830 return -EOPNOTSUPP;
831 }
832
833 component_index = mlx5_get_boot_img_component_index(dev);
834 if (component_index < 0)
835 return component_index;
836
837 err = mlx5_reg_mcqi_version_query(dev, component_index,
838 MCQI_FW_RUNNING_VERSION,
839 reg_mcqi_version);
840 if (err)
841 return err;
842
843 *running_ver = MLX5_GET(mcqi_version, reg_mcqi_version, version);
844
845 err = mlx5_fw_image_pending(dev, component_index, &pending_version_exists);
846 if (err)
847 return err;
848
849 if (!pending_version_exists) {
850 *pending_ver = 0;
851 return 0;
852 }
853
854 err = mlx5_reg_mcqi_version_query(dev, component_index,
855 MCQI_FW_STORED_VERSION,
856 reg_mcqi_version);
857 if (err)
858 return err;
859
860 *pending_ver = MLX5_GET(mcqi_version, reg_mcqi_version, version);
861
862 return 0;
863 }
864