1 // SPDX-License-Identifier: GPL-2.0
2
3 /*
4 * Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES
5 */
6
7 #include <linux/bitfield.h>
8 #include <linux/bitops.h>
9 #include <linux/cleanup.h>
10 #include <linux/device.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/gpio/generic.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/ioport.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm.h>
20 #include <linux/resource.h>
21 #include <linux/seq_file.h>
22 #include <linux/spinlock.h>
23 #include <linux/types.h>
24
25 /*
26 * There are 3 YU GPIO blocks:
27 * gpio[0]: HOST_GPIO0->HOST_GPIO31
28 * gpio[1]: HOST_GPIO32->HOST_GPIO63
29 * gpio[2]: HOST_GPIO64->HOST_GPIO69
30 */
31 #define MLXBF2_GPIO_MAX_PINS_PER_BLOCK 32
32
33 /*
34 * arm_gpio_lock register:
35 * bit[31] lock status: active if set
36 * bit[15:0] set lock
37 * The lock is enabled only if 0xd42f is written to this field
38 */
39 #define YU_ARM_GPIO_LOCK_ADDR 0x2801088
40 #define YU_ARM_GPIO_LOCK_SIZE 0x8
41 #define YU_LOCK_ACTIVE_BIT(val) (val >> 31)
42 #define YU_ARM_GPIO_LOCK_ACQUIRE 0xd42f
43 #define YU_ARM_GPIO_LOCK_RELEASE 0x0
44
45 /*
46 * gpio[x] block registers and their offset
47 */
48 #define YU_GPIO_DATAIN 0x04
49 #define YU_GPIO_MODE1 0x08
50 #define YU_GPIO_MODE0 0x0c
51 #define YU_GPIO_DATASET 0x14
52 #define YU_GPIO_DATACLEAR 0x18
53 #define YU_GPIO_CAUSE_RISE_EN 0x44
54 #define YU_GPIO_CAUSE_FALL_EN 0x48
55 #define YU_GPIO_MODE1_CLEAR 0x50
56 #define YU_GPIO_MODE0_SET 0x54
57 #define YU_GPIO_MODE0_CLEAR 0x58
58 #define YU_GPIO_CAUSE_OR_CAUSE_EVTEN0 0x80
59 #define YU_GPIO_CAUSE_OR_EVTEN0 0x94
60 #define YU_GPIO_CAUSE_OR_CLRCAUSE 0x98
61
62 struct mlxbf2_gpio_context_save_regs {
63 u32 gpio_mode0;
64 u32 gpio_mode1;
65 };
66
67 /* BlueField-2 gpio block context structure. */
68 struct mlxbf2_gpio_context {
69 struct gpio_generic_chip chip;
70
71 /* YU GPIO blocks address */
72 void __iomem *gpio_io;
73 struct device *dev;
74
75 struct mlxbf2_gpio_context_save_regs *csave_regs;
76 };
77
78 /* BlueField-2 gpio shared structure. */
79 struct mlxbf2_gpio_param {
80 void __iomem *io;
81 struct resource *res;
82 struct mutex *lock;
83 };
84
85 static struct resource yu_arm_gpio_lock_res =
86 DEFINE_RES_MEM_NAMED(YU_ARM_GPIO_LOCK_ADDR, YU_ARM_GPIO_LOCK_SIZE, "YU_ARM_GPIO_LOCK");
87
88 static DEFINE_MUTEX(yu_arm_gpio_lock_mutex);
89
90 static struct mlxbf2_gpio_param yu_arm_gpio_lock_param = {
91 .res = &yu_arm_gpio_lock_res,
92 .lock = &yu_arm_gpio_lock_mutex,
93 };
94
95 /* Request memory region and map yu_arm_gpio_lock resource */
mlxbf2_gpio_get_lock_res(struct platform_device * pdev)96 static int mlxbf2_gpio_get_lock_res(struct platform_device *pdev)
97 {
98 struct device *dev = &pdev->dev;
99 struct resource *res;
100 resource_size_t size;
101 int ret = 0;
102
103 mutex_lock(yu_arm_gpio_lock_param.lock);
104
105 /* Check if the memory map already exists */
106 if (yu_arm_gpio_lock_param.io)
107 goto exit;
108
109 res = yu_arm_gpio_lock_param.res;
110 size = resource_size(res);
111
112 if (!devm_request_mem_region(dev, res->start, size, res->name)) {
113 ret = -EFAULT;
114 goto exit;
115 }
116
117 yu_arm_gpio_lock_param.io = devm_ioremap(dev, res->start, size);
118 if (!yu_arm_gpio_lock_param.io)
119 ret = -ENOMEM;
120
121 exit:
122 mutex_unlock(yu_arm_gpio_lock_param.lock);
123
124 return ret;
125 }
126
127 /*
128 * Acquire the YU arm_gpio_lock to be able to change the direction
129 * mode. If the lock_active bit is already set, return an error.
130 */
mlxbf2_gpio_lock_acquire(struct mlxbf2_gpio_context * gs)131 static int mlxbf2_gpio_lock_acquire(struct mlxbf2_gpio_context *gs)
132 {
133 u32 arm_gpio_lock_val;
134
135 mutex_lock(yu_arm_gpio_lock_param.lock);
136 gpio_generic_chip_lock(&gs->chip);
137
138 arm_gpio_lock_val = readl(yu_arm_gpio_lock_param.io);
139
140 /*
141 * When lock active bit[31] is set, ModeX is write enabled
142 */
143 if (YU_LOCK_ACTIVE_BIT(arm_gpio_lock_val)) {
144 gpio_generic_chip_unlock(&gs->chip);
145 mutex_unlock(yu_arm_gpio_lock_param.lock);
146 return -EINVAL;
147 }
148
149 writel(YU_ARM_GPIO_LOCK_ACQUIRE, yu_arm_gpio_lock_param.io);
150
151 return 0;
152 }
153
154 /*
155 * Release the YU arm_gpio_lock after changing the direction mode.
156 */
mlxbf2_gpio_lock_release(struct mlxbf2_gpio_context * gs)157 static void mlxbf2_gpio_lock_release(struct mlxbf2_gpio_context *gs)
158 __releases(&gs->chip.lock)
159 __releases(yu_arm_gpio_lock_param.lock)
160 {
161 writel(YU_ARM_GPIO_LOCK_RELEASE, yu_arm_gpio_lock_param.io);
162 gpio_generic_chip_unlock(&gs->chip);
163 mutex_unlock(yu_arm_gpio_lock_param.lock);
164 }
165
166 /*
167 * mode0 and mode1 are both locked by the gpio_lock field.
168 *
169 * Together, mode0 and mode1 define the gpio Mode dependeing also
170 * on Reg_DataOut.
171 *
172 * {mode1,mode0}:{Reg_DataOut=0,Reg_DataOut=1}->{DataOut=0,DataOut=1}
173 *
174 * {0,0}:Reg_DataOut{0,1}->{Z,Z} Input PAD
175 * {0,1}:Reg_DataOut{0,1}->{0,1} Full drive Output PAD
176 * {1,0}:Reg_DataOut{0,1}->{0,Z} 0-set PAD to low, 1-float
177 * {1,1}:Reg_DataOut{0,1}->{Z,1} 0-float, 1-set PAD to high
178 */
179
180 /*
181 * Set input direction:
182 * {mode1,mode0} = {0,0}
183 */
mlxbf2_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)184 static int mlxbf2_gpio_direction_input(struct gpio_chip *chip,
185 unsigned int offset)
186 {
187 struct mlxbf2_gpio_context *gs = gpiochip_get_data(chip);
188 int ret;
189
190 /*
191 * Although the arm_gpio_lock was set in the probe function, check again
192 * if it is still enabled to be able to write to the ModeX registers.
193 */
194 ret = mlxbf2_gpio_lock_acquire(gs);
195 if (ret < 0)
196 return ret;
197
198 writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE0_CLEAR);
199 writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE1_CLEAR);
200
201 mlxbf2_gpio_lock_release(gs);
202
203 return ret;
204 }
205
206 /*
207 * Set output direction:
208 * {mode1,mode0} = {0,1}
209 */
mlxbf2_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)210 static int mlxbf2_gpio_direction_output(struct gpio_chip *chip,
211 unsigned int offset,
212 int value)
213 {
214 struct mlxbf2_gpio_context *gs = gpiochip_get_data(chip);
215 int ret = 0;
216
217 /*
218 * Although the arm_gpio_lock was set in the probe function,
219 * check again it is still enabled to be able to write to the
220 * ModeX registers.
221 */
222 ret = mlxbf2_gpio_lock_acquire(gs);
223 if (ret < 0)
224 return ret;
225
226 writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE1_CLEAR);
227 writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE0_SET);
228
229 mlxbf2_gpio_lock_release(gs);
230
231 return ret;
232 }
233
mlxbf2_gpio_irq_enable(struct irq_data * irqd)234 static void mlxbf2_gpio_irq_enable(struct irq_data *irqd)
235 {
236 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
237 struct mlxbf2_gpio_context *gs = gpiochip_get_data(gc);
238 int offset = irqd_to_hwirq(irqd);
239 u32 val;
240
241 gpiochip_enable_irq(gc, irqd_to_hwirq(irqd));
242 guard(gpio_generic_lock_irqsave)(&gs->chip);
243 val = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_CLRCAUSE);
244 val |= BIT(offset);
245 writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_CLRCAUSE);
246
247 val = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0);
248 val |= BIT(offset);
249 writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0);
250 }
251
mlxbf2_gpio_irq_disable(struct irq_data * irqd)252 static void mlxbf2_gpio_irq_disable(struct irq_data *irqd)
253 {
254 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
255 struct mlxbf2_gpio_context *gs = gpiochip_get_data(gc);
256 int offset = irqd_to_hwirq(irqd);
257 u32 val;
258
259 scoped_guard(gpio_generic_lock_irqsave, &gs->chip) {
260 val = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0);
261 val &= ~BIT(offset);
262 writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0);
263 }
264
265 gpiochip_disable_irq(gc, irqd_to_hwirq(irqd));
266 }
267
mlxbf2_gpio_irq_handler(int irq,void * ptr)268 static irqreturn_t mlxbf2_gpio_irq_handler(int irq, void *ptr)
269 {
270 struct mlxbf2_gpio_context *gs = ptr;
271 struct gpio_chip *gc = &gs->chip.gc;
272 unsigned long pending;
273 u32 level;
274
275 pending = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_CAUSE_EVTEN0);
276 writel(pending, gs->gpio_io + YU_GPIO_CAUSE_OR_CLRCAUSE);
277
278 for_each_set_bit(level, &pending, gc->ngpio)
279 generic_handle_domain_irq_safe(gc->irq.domain, level);
280
281 return IRQ_RETVAL(pending);
282 }
283
284 static int
mlxbf2_gpio_irq_set_type(struct irq_data * irqd,unsigned int type)285 mlxbf2_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
286 {
287 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
288 struct mlxbf2_gpio_context *gs = gpiochip_get_data(gc);
289 int offset = irqd_to_hwirq(irqd);
290 bool fall = false;
291 bool rise = false;
292 u32 val;
293
294 switch (type & IRQ_TYPE_SENSE_MASK) {
295 case IRQ_TYPE_EDGE_BOTH:
296 fall = true;
297 rise = true;
298 break;
299 case IRQ_TYPE_EDGE_RISING:
300 rise = true;
301 break;
302 case IRQ_TYPE_EDGE_FALLING:
303 fall = true;
304 break;
305 default:
306 return -EINVAL;
307 }
308
309 guard(gpio_generic_lock_irqsave)(&gs->chip);
310
311 if (fall) {
312 val = readl(gs->gpio_io + YU_GPIO_CAUSE_FALL_EN);
313 val |= BIT(offset);
314 writel(val, gs->gpio_io + YU_GPIO_CAUSE_FALL_EN);
315 }
316
317 if (rise) {
318 val = readl(gs->gpio_io + YU_GPIO_CAUSE_RISE_EN);
319 val |= BIT(offset);
320 writel(val, gs->gpio_io + YU_GPIO_CAUSE_RISE_EN);
321 }
322
323 return 0;
324 }
325
mlxbf2_gpio_irq_print_chip(struct irq_data * irqd,struct seq_file * p)326 static void mlxbf2_gpio_irq_print_chip(struct irq_data *irqd,
327 struct seq_file *p)
328 {
329 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
330 struct mlxbf2_gpio_context *gs = gpiochip_get_data(gc);
331
332 seq_puts(p, dev_name(gs->dev));
333 }
334
335 static const struct irq_chip mlxbf2_gpio_irq_chip = {
336 .irq_set_type = mlxbf2_gpio_irq_set_type,
337 .irq_enable = mlxbf2_gpio_irq_enable,
338 .irq_disable = mlxbf2_gpio_irq_disable,
339 .irq_print_chip = mlxbf2_gpio_irq_print_chip,
340 .flags = IRQCHIP_IMMUTABLE,
341 GPIOCHIP_IRQ_RESOURCE_HELPERS,
342 };
343
344 /* BlueField-2 GPIO driver initialization routine. */
345 static int
mlxbf2_gpio_probe(struct platform_device * pdev)346 mlxbf2_gpio_probe(struct platform_device *pdev)
347 {
348 struct gpio_generic_chip_config config;
349 struct mlxbf2_gpio_context *gs;
350 struct device *dev = &pdev->dev;
351 struct gpio_irq_chip *girq;
352 struct gpio_chip *gc;
353 unsigned int npins;
354 const char *name;
355 int ret, irq;
356
357 name = dev_name(dev);
358
359 gs = devm_kzalloc(dev, sizeof(*gs), GFP_KERNEL);
360 if (!gs)
361 return -ENOMEM;
362
363 gs->dev = dev;
364
365 /* YU GPIO block address */
366 gs->gpio_io = devm_platform_ioremap_resource(pdev, 0);
367 if (IS_ERR(gs->gpio_io))
368 return PTR_ERR(gs->gpio_io);
369
370 ret = mlxbf2_gpio_get_lock_res(pdev);
371 if (ret)
372 return dev_err_probe(dev, ret, "Failed to get yu_arm_gpio_lock resource\n");
373
374 if (device_property_read_u32(dev, "npins", &npins))
375 npins = MLXBF2_GPIO_MAX_PINS_PER_BLOCK;
376
377 gc = &gs->chip.gc;
378
379 config = (struct gpio_generic_chip_config) {
380 .dev = dev,
381 .sz = 4,
382 .dat = gs->gpio_io + YU_GPIO_DATAIN,
383 .set = gs->gpio_io + YU_GPIO_DATASET,
384 .clr = gs->gpio_io + YU_GPIO_DATACLEAR,
385 };
386
387 ret = gpio_generic_chip_init(&gs->chip, &config);
388 if (ret)
389 return dev_err_probe(dev, ret, "failed to initialize the generic GPIO chip\n");
390
391 gc->direction_input = mlxbf2_gpio_direction_input;
392 gc->direction_output = mlxbf2_gpio_direction_output;
393 gc->ngpio = npins;
394 gc->owner = THIS_MODULE;
395
396 irq = platform_get_irq_optional(pdev, 0);
397 if (irq >= 0) {
398 girq = &gs->chip.gc.irq;
399 gpio_irq_chip_set_chip(girq, &mlxbf2_gpio_irq_chip);
400 girq->handler = handle_simple_irq;
401 girq->default_type = IRQ_TYPE_NONE;
402 /* This will let us handle the parent IRQ in the driver */
403 girq->num_parents = 0;
404 girq->parents = NULL;
405 girq->parent_handler = NULL;
406
407 /*
408 * Directly request the irq here instead of passing
409 * a flow-handler because the irq is shared.
410 */
411 ret = devm_request_irq(dev, irq, mlxbf2_gpio_irq_handler,
412 IRQF_SHARED, name, gs);
413 if (ret)
414 return dev_err_probe(dev, ret, "failed to request IRQ");
415 }
416
417 platform_set_drvdata(pdev, gs);
418
419 ret = devm_gpiochip_add_data(dev, &gs->chip.gc, gs);
420 if (ret)
421 return dev_err_probe(dev, ret, "Failed adding memory mapped gpiochip\n");
422
423 return 0;
424 }
425
mlxbf2_gpio_suspend(struct device * dev)426 static int mlxbf2_gpio_suspend(struct device *dev)
427 {
428 struct mlxbf2_gpio_context *gs = dev_get_drvdata(dev);
429
430 gs->csave_regs->gpio_mode0 = readl(gs->gpio_io +
431 YU_GPIO_MODE0);
432 gs->csave_regs->gpio_mode1 = readl(gs->gpio_io +
433 YU_GPIO_MODE1);
434
435 return 0;
436 }
437
mlxbf2_gpio_resume(struct device * dev)438 static int mlxbf2_gpio_resume(struct device *dev)
439 {
440 struct mlxbf2_gpio_context *gs = dev_get_drvdata(dev);
441
442 writel(gs->csave_regs->gpio_mode0, gs->gpio_io +
443 YU_GPIO_MODE0);
444 writel(gs->csave_regs->gpio_mode1, gs->gpio_io +
445 YU_GPIO_MODE1);
446
447 return 0;
448 }
449 static DEFINE_SIMPLE_DEV_PM_OPS(mlxbf2_pm_ops, mlxbf2_gpio_suspend, mlxbf2_gpio_resume);
450
451 static const struct acpi_device_id __maybe_unused mlxbf2_gpio_acpi_match[] = {
452 { "MLNXBF22", 0 },
453 {},
454 };
455 MODULE_DEVICE_TABLE(acpi, mlxbf2_gpio_acpi_match);
456
457 static struct platform_driver mlxbf2_gpio_driver = {
458 .driver = {
459 .name = "mlxbf2_gpio",
460 .acpi_match_table = mlxbf2_gpio_acpi_match,
461 .pm = pm_sleep_ptr(&mlxbf2_pm_ops),
462 },
463 .probe = mlxbf2_gpio_probe,
464 };
465
466 module_platform_driver(mlxbf2_gpio_driver);
467
468 MODULE_DESCRIPTION("Mellanox BlueField-2 GPIO Driver");
469 MODULE_AUTHOR("Asmaa Mnebhi <asmaa@nvidia.com>");
470 MODULE_LICENSE("GPL v2");
471