1 /*
2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/dim.h>
34 #include <net/tc_act/tc_gact.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <net/geneve.h>
38 #include <linux/bpf.h>
39 #include <linux/debugfs.h>
40 #include <linux/if_bridge.h>
41 #include <linux/filter.h>
42 #include <net/netdev_lock.h>
43 #include <net/netdev_queues.h>
44 #include <net/netdev_rx_queue.h>
45 #include <net/page_pool/types.h>
46 #include <net/pkt_sched.h>
47 #include <net/xdp_sock_drv.h>
48 #include "eswitch.h"
49 #include "en.h"
50 #include "en/dim.h"
51 #include "en/txrx.h"
52 #include "en/port_buffer.h"
53 #include "en_tc.h"
54 #include "en_rep.h"
55 #include "en_accel/ipsec.h"
56 #include "en_accel/macsec.h"
57 #include "en_accel/en_accel.h"
58 #include "en_accel/ktls.h"
59 #include "lib/vxlan.h"
60 #include "lib/clock.h"
61 #include "en/port.h"
62 #include "en/xdp.h"
63 #include "lib/eq.h"
64 #include "en/monitor_stats.h"
65 #include "en/health.h"
66 #include "en/params.h"
67 #include "en/xsk/pool.h"
68 #include "en/xsk/setup.h"
69 #include "en/xsk/rx.h"
70 #include "en/xsk/tx.h"
71 #include "en/hv_vhca_stats.h"
72 #include "en/devlink.h"
73 #include "lib/mlx5.h"
74 #include "en/ptp.h"
75 #include "en/htb.h"
76 #include "qos.h"
77 #include "en/trap.h"
78 #include "lib/devcom.h"
79 #include "lib/sd.h"
80 #include "en/pcie_cong_event.h"
81
mlx5e_hw_gro_supported(struct mlx5_core_dev * mdev)82 static bool mlx5e_hw_gro_supported(struct mlx5_core_dev *mdev)
83 {
84 if (!MLX5_CAP_GEN(mdev, shampo) ||
85 !MLX5_CAP_SHAMPO(mdev, shampo_header_split_data_merge))
86 return false;
87
88 /* Our HW-GRO implementation relies on "KSM Mkey" for
89 * SHAMPO headers buffer mapping
90 */
91 if (!MLX5_CAP_GEN(mdev, fixed_buffer_size))
92 return false;
93
94 if (!MLX5_CAP_GEN_2(mdev, min_mkey_log_entity_size_fixed_buffer_valid))
95 return false;
96
97 if (MLX5_CAP_GEN_2(mdev, min_mkey_log_entity_size_fixed_buffer) >
98 MLX5E_SHAMPO_LOG_HEADER_ENTRY_SIZE)
99 return false;
100
101 return true;
102 }
103
mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev * mdev,u8 page_shift,enum mlx5e_mpwrq_umr_mode umr_mode)104 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev, u8 page_shift,
105 enum mlx5e_mpwrq_umr_mode umr_mode)
106 {
107 u16 umr_wqebbs, max_wqebbs;
108 bool striding_rq_umr;
109
110 striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) && MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
111 MLX5_CAP_ETH(mdev, reg_umr_sq);
112 if (!striding_rq_umr)
113 return false;
114
115 umr_wqebbs = mlx5e_mpwrq_umr_wqebbs(mdev, page_shift, umr_mode);
116 max_wqebbs = mlx5e_get_max_sq_aligned_wqebbs(mdev);
117 /* Sanity check; should never happen, because mlx5e_mpwrq_umr_wqebbs is
118 * calculated from mlx5e_get_max_sq_aligned_wqebbs.
119 */
120 if (WARN_ON(umr_wqebbs > max_wqebbs))
121 return false;
122
123 return true;
124 }
125
mlx5e_update_carrier(struct mlx5e_priv * priv)126 void mlx5e_update_carrier(struct mlx5e_priv *priv)
127 {
128 struct mlx5_core_dev *mdev = priv->mdev;
129 u8 port_state;
130 bool up;
131
132 port_state = mlx5_query_vport_state(mdev,
133 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
134 0);
135
136 up = port_state == VPORT_STATE_UP;
137 if (up == netif_carrier_ok(priv->netdev))
138 netif_carrier_event(priv->netdev);
139 if (up) {
140 netdev_info(priv->netdev, "Link up\n");
141 netif_carrier_on(priv->netdev);
142 mlx5e_port_manual_buffer_config(priv, 0, priv->netdev->mtu,
143 NULL, NULL, NULL);
144 } else {
145 netdev_info(priv->netdev, "Link down\n");
146 netif_carrier_off(priv->netdev);
147 }
148 }
149
mlx5e_update_carrier_work(struct work_struct * work)150 static void mlx5e_update_carrier_work(struct work_struct *work)
151 {
152 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
153 update_carrier_work);
154
155 mutex_lock(&priv->state_lock);
156 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
157 if (priv->profile->update_carrier)
158 priv->profile->update_carrier(priv);
159 mutex_unlock(&priv->state_lock);
160 }
161
mlx5e_update_stats_work(struct work_struct * work)162 static void mlx5e_update_stats_work(struct work_struct *work)
163 {
164 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
165 update_stats_work);
166
167 mutex_lock(&priv->state_lock);
168 priv->profile->update_stats(priv);
169 mutex_unlock(&priv->state_lock);
170 }
171
mlx5e_queue_update_stats(struct mlx5e_priv * priv)172 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
173 {
174 if (!priv->profile->update_stats)
175 return;
176
177 if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
178 return;
179
180 queue_work(priv->wq, &priv->update_stats_work);
181 }
182
async_event(struct notifier_block * nb,unsigned long event,void * data)183 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
184 {
185 struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
186 struct mlx5_eqe *eqe = data;
187
188 if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
189 return NOTIFY_DONE;
190
191 switch (eqe->sub_type) {
192 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
193 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
194 queue_work(priv->wq, &priv->update_carrier_work);
195 break;
196 default:
197 return NOTIFY_DONE;
198 }
199
200 return NOTIFY_OK;
201 }
202
mlx5e_enable_async_events(struct mlx5e_priv * priv)203 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
204 {
205 priv->events_nb.notifier_call = async_event;
206 mlx5_notifier_register(priv->mdev, &priv->events_nb);
207 }
208
mlx5e_disable_async_events(struct mlx5e_priv * priv)209 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
210 {
211 mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
212 }
213
mlx5e_devcom_event_mpv(int event,void * my_data,void * event_data)214 static int mlx5e_devcom_event_mpv(int event, void *my_data, void *event_data)
215 {
216 struct mlx5e_priv *slave_priv = my_data;
217
218 switch (event) {
219 case MPV_DEVCOM_MASTER_UP:
220 mlx5_devcom_comp_set_ready(slave_priv->devcom, true);
221 break;
222 case MPV_DEVCOM_MASTER_DOWN:
223 /* no need for comp set ready false since we unregister after
224 * and it hurts cleanup flow.
225 */
226 break;
227 case MPV_DEVCOM_IPSEC_MASTER_UP:
228 case MPV_DEVCOM_IPSEC_MASTER_DOWN:
229 mlx5e_ipsec_handle_mpv_event(event, my_data, event_data);
230 break;
231 }
232
233 return 0;
234 }
235
mlx5e_devcom_init_mpv(struct mlx5e_priv * priv,u64 * data)236 static int mlx5e_devcom_init_mpv(struct mlx5e_priv *priv, u64 *data)
237 {
238 priv->devcom = mlx5_devcom_register_component(priv->mdev->priv.devc,
239 MLX5_DEVCOM_MPV,
240 *data,
241 mlx5e_devcom_event_mpv,
242 priv);
243 if (IS_ERR(priv->devcom))
244 return PTR_ERR(priv->devcom);
245
246 if (mlx5_core_is_mp_master(priv->mdev)) {
247 mlx5_devcom_send_event(priv->devcom, MPV_DEVCOM_MASTER_UP,
248 MPV_DEVCOM_MASTER_UP, priv);
249 mlx5e_ipsec_send_event(priv, MPV_DEVCOM_IPSEC_MASTER_UP);
250 }
251
252 return 0;
253 }
254
mlx5e_devcom_cleanup_mpv(struct mlx5e_priv * priv)255 static void mlx5e_devcom_cleanup_mpv(struct mlx5e_priv *priv)
256 {
257 if (IS_ERR_OR_NULL(priv->devcom))
258 return;
259
260 if (mlx5_core_is_mp_master(priv->mdev)) {
261 mlx5_devcom_send_event(priv->devcom, MPV_DEVCOM_MASTER_DOWN,
262 MPV_DEVCOM_MASTER_DOWN, priv);
263 mlx5e_ipsec_send_event(priv, MPV_DEVCOM_IPSEC_MASTER_DOWN);
264 }
265
266 mlx5_devcom_unregister_component(priv->devcom);
267 }
268
blocking_event(struct notifier_block * nb,unsigned long event,void * data)269 static int blocking_event(struct notifier_block *nb, unsigned long event, void *data)
270 {
271 struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, blocking_events_nb);
272 struct mlx5_devlink_trap_event_ctx *trap_event_ctx = data;
273 int err;
274
275 switch (event) {
276 case MLX5_DRIVER_EVENT_TYPE_TRAP:
277 err = mlx5e_handle_trap_event(priv, trap_event_ctx->trap);
278 if (err) {
279 trap_event_ctx->err = err;
280 return NOTIFY_BAD;
281 }
282 break;
283 case MLX5_DRIVER_EVENT_AFFILIATION_DONE:
284 if (mlx5e_devcom_init_mpv(priv, data))
285 return NOTIFY_BAD;
286 break;
287 case MLX5_DRIVER_EVENT_AFFILIATION_REMOVED:
288 mlx5e_devcom_cleanup_mpv(priv);
289 break;
290 default:
291 return NOTIFY_DONE;
292 }
293 return NOTIFY_OK;
294 }
295
mlx5e_enable_blocking_events(struct mlx5e_priv * priv)296 static void mlx5e_enable_blocking_events(struct mlx5e_priv *priv)
297 {
298 priv->blocking_events_nb.notifier_call = blocking_event;
299 mlx5_blocking_notifier_register(priv->mdev, &priv->blocking_events_nb);
300 }
301
mlx5e_disable_blocking_events(struct mlx5e_priv * priv)302 static void mlx5e_disable_blocking_events(struct mlx5e_priv *priv)
303 {
304 mlx5_blocking_notifier_unregister(priv->mdev, &priv->blocking_events_nb);
305 }
306
mlx5e_mpwrq_umr_octowords(u32 entries,enum mlx5e_mpwrq_umr_mode umr_mode)307 static u16 mlx5e_mpwrq_umr_octowords(u32 entries, enum mlx5e_mpwrq_umr_mode umr_mode)
308 {
309 u8 umr_entry_size = mlx5e_mpwrq_umr_entry_size(umr_mode);
310 u32 sz;
311
312 sz = ALIGN(entries * umr_entry_size, MLX5_UMR_FLEX_ALIGNMENT);
313
314 return sz / MLX5_OCTWORD;
315 }
316
mlx5e_build_umr_wqe(struct mlx5e_rq * rq,struct mlx5e_icosq * sq,struct mlx5e_umr_wqe * wqe)317 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
318 struct mlx5e_icosq *sq,
319 struct mlx5e_umr_wqe *wqe)
320 {
321 struct mlx5_wqe_ctrl_seg *cseg = &wqe->hdr.ctrl;
322 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->hdr.uctrl;
323 u16 octowords;
324 u8 ds_cnt;
325
326 ds_cnt = DIV_ROUND_UP(mlx5e_mpwrq_umr_wqe_sz(rq->mdev, rq->mpwqe.page_shift,
327 rq->mpwqe.umr_mode),
328 MLX5_SEND_WQE_DS);
329
330 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
331 ds_cnt);
332 cseg->umr_mkey = rq->mpwqe.umr_mkey_be;
333
334 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
335 octowords = mlx5e_mpwrq_umr_octowords(rq->mpwqe.pages_per_wqe, rq->mpwqe.umr_mode);
336 ucseg->xlt_octowords = cpu_to_be16(octowords);
337 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
338 }
339
mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq * rq,int node)340 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, int node)
341 {
342 int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
343 size_t alloc_size;
344
345 alloc_size = array_size(wq_sz, struct_size(rq->mpwqe.info,
346 alloc_units.frag_pages,
347 rq->mpwqe.pages_per_wqe));
348
349 rq->mpwqe.info = kvzalloc_node(alloc_size, GFP_KERNEL, node);
350 if (!rq->mpwqe.info)
351 return -ENOMEM;
352
353 /* For deferred page release (release right before alloc), make sure
354 * that on first round release is not called.
355 */
356 for (int i = 0; i < wq_sz; i++) {
357 struct mlx5e_mpw_info *wi = mlx5e_get_mpw_info(rq, i);
358
359 bitmap_fill(wi->skip_release_bitmap, rq->mpwqe.pages_per_wqe);
360 }
361
362 mlx5e_build_umr_wqe(rq, rq->icosq,
363 container_of(&rq->mpwqe.umr_wqe,
364 struct mlx5e_umr_wqe, hdr));
365
366 return 0;
367 }
368
369
mlx5e_mpwrq_access_mode(enum mlx5e_mpwrq_umr_mode umr_mode)370 static u8 mlx5e_mpwrq_access_mode(enum mlx5e_mpwrq_umr_mode umr_mode)
371 {
372 switch (umr_mode) {
373 case MLX5E_MPWRQ_UMR_MODE_ALIGNED:
374 return MLX5_MKC_ACCESS_MODE_MTT;
375 case MLX5E_MPWRQ_UMR_MODE_UNALIGNED:
376 return MLX5_MKC_ACCESS_MODE_KSM;
377 case MLX5E_MPWRQ_UMR_MODE_OVERSIZED:
378 return MLX5_MKC_ACCESS_MODE_KLMS;
379 case MLX5E_MPWRQ_UMR_MODE_TRIPLE:
380 return MLX5_MKC_ACCESS_MODE_KSM;
381 }
382 WARN_ONCE(1, "MPWRQ UMR mode %d is not known\n", umr_mode);
383 return 0;
384 }
385
mlx5e_create_umr_mkey(struct mlx5_core_dev * mdev,u32 npages,u8 page_shift,u32 * umr_mkey,dma_addr_t filler_addr,enum mlx5e_mpwrq_umr_mode umr_mode,u32 xsk_chunk_size)386 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
387 u32 npages, u8 page_shift, u32 *umr_mkey,
388 dma_addr_t filler_addr,
389 enum mlx5e_mpwrq_umr_mode umr_mode,
390 u32 xsk_chunk_size)
391 {
392 struct mlx5_mtt *mtt;
393 struct mlx5_ksm *ksm;
394 struct mlx5_klm *klm;
395 u32 octwords;
396 int inlen;
397 void *mkc;
398 u32 *in;
399 int err;
400 int i;
401
402 if ((umr_mode == MLX5E_MPWRQ_UMR_MODE_UNALIGNED ||
403 umr_mode == MLX5E_MPWRQ_UMR_MODE_TRIPLE) &&
404 !MLX5_CAP_GEN(mdev, fixed_buffer_size)) {
405 mlx5_core_warn(mdev, "Unaligned AF_XDP requires fixed_buffer_size capability\n");
406 return -EINVAL;
407 }
408
409 octwords = mlx5e_mpwrq_umr_octowords(npages, umr_mode);
410
411 inlen = MLX5_FLEXIBLE_INLEN(mdev, MLX5_ST_SZ_BYTES(create_mkey_in),
412 MLX5_OCTWORD, octwords);
413 if (inlen < 0)
414 return inlen;
415
416 in = kvzalloc(inlen, GFP_KERNEL);
417 if (!in)
418 return -ENOMEM;
419
420 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
421
422 MLX5_SET(mkc, mkc, free, 1);
423 MLX5_SET(mkc, mkc, umr_en, 1);
424 MLX5_SET(mkc, mkc, lw, 1);
425 MLX5_SET(mkc, mkc, lr, 1);
426 MLX5_SET(mkc, mkc, access_mode_1_0, mlx5e_mpwrq_access_mode(umr_mode));
427 mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
428 MLX5_SET(mkc, mkc, qpn, 0xffffff);
429 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
430 MLX5_SET64(mkc, mkc, len, npages << page_shift);
431 MLX5_SET(mkc, mkc, translations_octword_size, octwords);
432 if (umr_mode == MLX5E_MPWRQ_UMR_MODE_TRIPLE)
433 MLX5_SET(mkc, mkc, log_page_size, page_shift - 2);
434 else if (umr_mode != MLX5E_MPWRQ_UMR_MODE_OVERSIZED)
435 MLX5_SET(mkc, mkc, log_page_size, page_shift);
436 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, octwords);
437
438 /* Initialize the mkey with all MTTs pointing to a default
439 * page (filler_addr). When the channels are activated, UMR
440 * WQEs will redirect the RX WQEs to the actual memory from
441 * the RQ's pool, while the gaps (wqe_overflow) remain mapped
442 * to the default page.
443 */
444 switch (umr_mode) {
445 case MLX5E_MPWRQ_UMR_MODE_OVERSIZED:
446 klm = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
447 for (i = 0; i < npages; i++) {
448 klm[i << 1] = (struct mlx5_klm) {
449 .va = cpu_to_be64(filler_addr),
450 .bcount = cpu_to_be32(xsk_chunk_size),
451 .key = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey),
452 };
453 klm[(i << 1) + 1] = (struct mlx5_klm) {
454 .va = cpu_to_be64(filler_addr),
455 .bcount = cpu_to_be32((1 << page_shift) - xsk_chunk_size),
456 .key = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey),
457 };
458 }
459 break;
460 case MLX5E_MPWRQ_UMR_MODE_UNALIGNED:
461 ksm = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
462 for (i = 0; i < npages; i++)
463 ksm[i] = (struct mlx5_ksm) {
464 .key = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey),
465 .va = cpu_to_be64(filler_addr),
466 };
467 break;
468 case MLX5E_MPWRQ_UMR_MODE_ALIGNED:
469 mtt = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
470 for (i = 0; i < npages; i++)
471 mtt[i] = (struct mlx5_mtt) {
472 .ptag = cpu_to_be64(filler_addr),
473 };
474 break;
475 case MLX5E_MPWRQ_UMR_MODE_TRIPLE:
476 ksm = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
477 for (i = 0; i < npages * 4; i++) {
478 ksm[i] = (struct mlx5_ksm) {
479 .key = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey),
480 .va = cpu_to_be64(filler_addr),
481 };
482 }
483 break;
484 }
485
486 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
487
488 kvfree(in);
489 return err;
490 }
491
mlx5e_create_umr_ksm_mkey(struct mlx5_core_dev * mdev,u64 nentries,u8 log_entry_size,u32 * umr_mkey)492 static int mlx5e_create_umr_ksm_mkey(struct mlx5_core_dev *mdev,
493 u64 nentries, u8 log_entry_size,
494 u32 *umr_mkey)
495 {
496 int inlen;
497 void *mkc;
498 u32 *in;
499 int err;
500
501 inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
502
503 in = kvzalloc(inlen, GFP_KERNEL);
504 if (!in)
505 return -ENOMEM;
506
507 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
508
509 MLX5_SET(mkc, mkc, free, 1);
510 MLX5_SET(mkc, mkc, umr_en, 1);
511 MLX5_SET(mkc, mkc, lw, 1);
512 MLX5_SET(mkc, mkc, lr, 1);
513 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_KSM);
514 mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
515 MLX5_SET(mkc, mkc, qpn, 0xffffff);
516 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
517 MLX5_SET(mkc, mkc, translations_octword_size, nentries);
518 MLX5_SET(mkc, mkc, log_page_size, log_entry_size);
519 MLX5_SET64(mkc, mkc, len, nentries << log_entry_size);
520 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
521
522 kvfree(in);
523 return err;
524 }
525
mlx5e_create_rq_umr_mkey(struct mlx5_core_dev * mdev,struct mlx5e_rq * rq)526 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
527 {
528 u32 xsk_chunk_size = rq->xsk_pool ? rq->xsk_pool->chunk_size : 0;
529 u32 wq_size = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
530 u32 num_entries, max_num_entries;
531 u32 umr_mkey;
532 int err;
533
534 max_num_entries = mlx5e_mpwrq_max_num_entries(mdev, rq->mpwqe.umr_mode);
535
536 /* Shouldn't overflow, the result is at most MLX5E_MAX_RQ_NUM_MTTS. */
537 if (WARN_ON_ONCE(check_mul_overflow(wq_size, (u32)rq->mpwqe.mtts_per_wqe,
538 &num_entries) ||
539 num_entries > max_num_entries))
540 mlx5_core_err(mdev, "%s: multiplication overflow: %u * %u > %u\n",
541 __func__, wq_size, rq->mpwqe.mtts_per_wqe,
542 max_num_entries);
543
544 err = mlx5e_create_umr_mkey(mdev, num_entries, rq->mpwqe.page_shift,
545 &umr_mkey, rq->wqe_overflow.addr,
546 rq->mpwqe.umr_mode, xsk_chunk_size);
547 rq->mpwqe.umr_mkey_be = cpu_to_be32(umr_mkey);
548 return err;
549 }
550
mlx5e_create_rq_hd_umr_mkey(struct mlx5_core_dev * mdev,u16 hd_per_wq,__be32 * umr_mkey)551 static int mlx5e_create_rq_hd_umr_mkey(struct mlx5_core_dev *mdev,
552 u16 hd_per_wq, __be32 *umr_mkey)
553 {
554 u32 max_ksm_size = BIT(MLX5_CAP_GEN(mdev, log_max_klm_list_size));
555 u32 mkey;
556 int err;
557
558 if (max_ksm_size < hd_per_wq) {
559 mlx5_core_err(mdev, "max ksm list size 0x%x is smaller than shampo header buffer list size 0x%x\n",
560 max_ksm_size, hd_per_wq);
561 return -EINVAL;
562 }
563
564 err = mlx5e_create_umr_ksm_mkey(mdev, hd_per_wq,
565 MLX5E_SHAMPO_LOG_HEADER_ENTRY_SIZE,
566 &mkey);
567 if (err)
568 return err;
569
570 *umr_mkey = cpu_to_be32(mkey);
571 return 0;
572 }
573
mlx5e_init_frags_partition(struct mlx5e_rq * rq)574 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
575 {
576 struct mlx5e_wqe_frag_info next_frag = {};
577 struct mlx5e_wqe_frag_info *prev = NULL;
578 int i;
579
580 WARN_ON(rq->xsk_pool);
581
582 next_frag.frag_page = &rq->wqe.alloc_units->frag_pages[0];
583
584 /* Skip first release due to deferred release. */
585 next_frag.flags = BIT(MLX5E_WQE_FRAG_SKIP_RELEASE);
586
587 for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
588 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
589 struct mlx5e_wqe_frag_info *frag =
590 &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
591 int f;
592
593 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
594 if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
595 /* Pages are assigned at runtime. */
596 next_frag.frag_page++;
597 next_frag.offset = 0;
598 if (prev)
599 prev->flags |= BIT(MLX5E_WQE_FRAG_LAST_IN_PAGE);
600 }
601 *frag = next_frag;
602
603 /* prepare next */
604 next_frag.offset += frag_info[f].frag_stride;
605 prev = frag;
606 }
607 }
608
609 if (prev)
610 prev->flags |= BIT(MLX5E_WQE_FRAG_LAST_IN_PAGE);
611 }
612
mlx5e_init_xsk_buffs(struct mlx5e_rq * rq)613 static void mlx5e_init_xsk_buffs(struct mlx5e_rq *rq)
614 {
615 int i;
616
617 /* Assumptions used by XSK batched allocator. */
618 WARN_ON(rq->wqe.info.num_frags != 1);
619 WARN_ON(rq->wqe.info.log_num_frags != 0);
620 WARN_ON(rq->wqe.info.arr[0].frag_stride != PAGE_SIZE);
621
622 /* Considering the above assumptions a fragment maps to a single
623 * xsk_buff.
624 */
625 for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
626 rq->wqe.frags[i].xskp = &rq->wqe.alloc_units->xsk_buffs[i];
627
628 /* Skip first release due to deferred release as WQES are
629 * not allocated yet.
630 */
631 rq->wqe.frags[i].flags |= BIT(MLX5E_WQE_FRAG_SKIP_RELEASE);
632 }
633 }
634
mlx5e_init_wqe_alloc_info(struct mlx5e_rq * rq,int node)635 static int mlx5e_init_wqe_alloc_info(struct mlx5e_rq *rq, int node)
636 {
637 int wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
638 int len = wq_sz << rq->wqe.info.log_num_frags;
639 struct mlx5e_wqe_frag_info *frags;
640 union mlx5e_alloc_units *aus;
641 int aus_sz;
642
643 if (rq->xsk_pool)
644 aus_sz = sizeof(*aus->xsk_buffs);
645 else
646 aus_sz = sizeof(*aus->frag_pages);
647
648 aus = kvzalloc_node(array_size(len, aus_sz), GFP_KERNEL, node);
649 if (!aus)
650 return -ENOMEM;
651
652 frags = kvzalloc_node(array_size(len, sizeof(*frags)), GFP_KERNEL, node);
653 if (!frags) {
654 kvfree(aus);
655 return -ENOMEM;
656 }
657
658 rq->wqe.alloc_units = aus;
659 rq->wqe.frags = frags;
660
661 if (rq->xsk_pool)
662 mlx5e_init_xsk_buffs(rq);
663 else
664 mlx5e_init_frags_partition(rq);
665
666 return 0;
667 }
668
mlx5e_free_wqe_alloc_info(struct mlx5e_rq * rq)669 static void mlx5e_free_wqe_alloc_info(struct mlx5e_rq *rq)
670 {
671 kvfree(rq->wqe.frags);
672 kvfree(rq->wqe.alloc_units);
673 }
674
mlx5e_rq_err_cqe_work(struct work_struct * recover_work)675 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
676 {
677 struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
678
679 mlx5e_reporter_rq_cqe_err(rq);
680 }
681
mlx5e_rq_timeout_work(struct work_struct * timeout_work)682 static void mlx5e_rq_timeout_work(struct work_struct *timeout_work)
683 {
684 struct mlx5e_rq *rq = container_of(timeout_work,
685 struct mlx5e_rq,
686 rx_timeout_work);
687
688 /* Acquire netdev instance lock to synchronize with channel close and
689 * reopen flows. Either successfully obtain the lock, or detect that
690 * channels are closing for another reason, making this work no longer
691 * necessary.
692 */
693 while (!netdev_trylock(rq->netdev)) {
694 if (!test_bit(MLX5E_STATE_CHANNELS_ACTIVE, &rq->priv->state))
695 return;
696 msleep(20);
697 }
698
699 mlx5e_reporter_rx_timeout(rq);
700 netdev_unlock(rq->netdev);
701 }
702
mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e_rq * rq)703 static int mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
704 {
705 rq->wqe_overflow.page = alloc_page(GFP_KERNEL);
706 if (!rq->wqe_overflow.page)
707 return -ENOMEM;
708
709 rq->wqe_overflow.addr = dma_map_page(rq->pdev, rq->wqe_overflow.page, 0,
710 PAGE_SIZE, rq->buff.map_dir);
711 if (dma_mapping_error(rq->pdev, rq->wqe_overflow.addr)) {
712 __free_page(rq->wqe_overflow.page);
713 return -ENOMEM;
714 }
715 return 0;
716 }
717
mlx5e_free_mpwqe_rq_drop_page(struct mlx5e_rq * rq)718 static void mlx5e_free_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
719 {
720 dma_unmap_page(rq->pdev, rq->wqe_overflow.addr, PAGE_SIZE,
721 rq->buff.map_dir);
722 __free_page(rq->wqe_overflow.page);
723 }
724
mlx5e_init_rxq_rq(struct mlx5e_channel * c,struct mlx5e_params * params,u32 xdp_frag_size,struct mlx5e_rq * rq)725 static int mlx5e_init_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
726 u32 xdp_frag_size, struct mlx5e_rq *rq)
727 {
728 struct mlx5_core_dev *mdev = c->mdev;
729 int err;
730
731 rq->wq_type = params->rq_wq_type;
732 rq->pdev = c->pdev;
733 rq->netdev = c->netdev;
734 rq->priv = c->priv;
735 rq->tstamp = c->tstamp;
736 rq->clock = mdev->clock;
737 rq->icosq = &c->icosq;
738 rq->ix = c->ix;
739 rq->channel = c;
740 rq->mdev = mdev;
741 rq->hw_mtu =
742 MLX5E_SW2HW_MTU(params, params->sw_mtu) - ETH_FCS_LEN * !params->scatter_fcs_en;
743 rq->xdpsq = &c->rq_xdpsq;
744 rq->stats = &c->priv->channel_stats[c->ix]->rq;
745 rq->ptp_cyc2time = mlx5_rq_ts_translator(mdev);
746 err = mlx5e_rq_set_handlers(rq, params, NULL);
747 if (err)
748 return err;
749
750 return __xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix, c->napi.napi_id,
751 xdp_frag_size);
752 }
753
mlx5e_rq_shampo_hd_info_alloc(struct mlx5e_rq * rq,u16 hd_per_wq,int node)754 static int mlx5e_rq_shampo_hd_info_alloc(struct mlx5e_rq *rq, u16 hd_per_wq,
755 int node)
756 {
757 struct mlx5e_shampo_hd *shampo = rq->mpwqe.shampo;
758
759 shampo->hd_per_wq = hd_per_wq;
760
761 shampo->bitmap = bitmap_zalloc_node(hd_per_wq, GFP_KERNEL, node);
762 shampo->pages = kvzalloc_node(array_size(hd_per_wq,
763 sizeof(*shampo->pages)),
764 GFP_KERNEL, node);
765 if (!shampo->bitmap || !shampo->pages)
766 goto err_nomem;
767
768 return 0;
769
770 err_nomem:
771 kvfree(shampo->pages);
772 bitmap_free(shampo->bitmap);
773
774 return -ENOMEM;
775 }
776
mlx5e_rq_shampo_hd_info_free(struct mlx5e_rq * rq)777 static void mlx5e_rq_shampo_hd_info_free(struct mlx5e_rq *rq)
778 {
779 kvfree(rq->mpwqe.shampo->pages);
780 bitmap_free(rq->mpwqe.shampo->bitmap);
781 }
782
mlx5_rq_needs_separate_hd_pool(struct mlx5e_rq * rq)783 static bool mlx5_rq_needs_separate_hd_pool(struct mlx5e_rq *rq)
784 {
785 struct netdev_rx_queue *rxq = __netif_get_rx_queue(rq->netdev, rq->ix);
786
787 return !!rxq->mp_params.mp_ops;
788 }
789
mlx5_rq_shampo_alloc(struct mlx5_core_dev * mdev,struct mlx5e_params * params,struct mlx5e_rq_param * rqp,struct mlx5e_rq * rq,u32 * pool_size,int node)790 static int mlx5_rq_shampo_alloc(struct mlx5_core_dev *mdev,
791 struct mlx5e_params *params,
792 struct mlx5e_rq_param *rqp,
793 struct mlx5e_rq *rq,
794 u32 *pool_size,
795 int node)
796 {
797 void *wqc = MLX5_ADDR_OF(rqc, rqp->rqc, wq);
798 u32 hd_pool_size;
799 u16 hd_per_wq;
800 int wq_size;
801 int err;
802
803 if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
804 return 0;
805
806 rq->mpwqe.shampo = kvzalloc_node(sizeof(*rq->mpwqe.shampo),
807 GFP_KERNEL, node);
808 if (!rq->mpwqe.shampo)
809 return -ENOMEM;
810
811 /* split headers data structures */
812 hd_per_wq = mlx5e_shampo_hd_per_wq(mdev, params, rqp);
813 err = mlx5e_rq_shampo_hd_info_alloc(rq, hd_per_wq, node);
814 if (err)
815 goto err_shampo_hd_info_alloc;
816
817 err = mlx5e_create_rq_hd_umr_mkey(mdev, hd_per_wq,
818 &rq->mpwqe.shampo->mkey_be);
819 if (err)
820 goto err_umr_mkey;
821
822 rq->mpwqe.shampo->hd_per_wqe =
823 mlx5e_shampo_hd_per_wqe(mdev, params, rqp);
824 wq_size = BIT(MLX5_GET(wq, wqc, log_wq_sz));
825 hd_pool_size = (rq->mpwqe.shampo->hd_per_wqe * wq_size) /
826 MLX5E_SHAMPO_WQ_HEADER_PER_PAGE;
827
828 if (mlx5_rq_needs_separate_hd_pool(rq)) {
829 /* Separate page pool for shampo headers */
830 struct page_pool_params pp_params = { };
831
832 pp_params.order = 0;
833 pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV;
834 pp_params.pool_size = hd_pool_size;
835 pp_params.nid = node;
836 pp_params.dev = rq->pdev;
837 pp_params.napi = rq->cq.napi;
838 pp_params.netdev = rq->netdev;
839 pp_params.dma_dir = rq->buff.map_dir;
840 pp_params.max_len = PAGE_SIZE;
841
842 rq->hd_page_pool = page_pool_create(&pp_params);
843 if (IS_ERR(rq->hd_page_pool)) {
844 err = PTR_ERR(rq->hd_page_pool);
845 rq->hd_page_pool = NULL;
846 goto err_hds_page_pool;
847 }
848 } else {
849 /* Common page pool, reserve space for headers. */
850 *pool_size += hd_pool_size;
851 rq->hd_page_pool = NULL;
852 }
853
854 /* gro only data structures */
855 rq->hw_gro_data = kvzalloc_node(sizeof(*rq->hw_gro_data), GFP_KERNEL, node);
856 if (!rq->hw_gro_data) {
857 err = -ENOMEM;
858 goto err_hw_gro_data;
859 }
860
861 return 0;
862
863 err_hw_gro_data:
864 page_pool_destroy(rq->hd_page_pool);
865 err_hds_page_pool:
866 mlx5_core_destroy_mkey(mdev, be32_to_cpu(rq->mpwqe.shampo->mkey_be));
867 err_umr_mkey:
868 mlx5e_rq_shampo_hd_info_free(rq);
869 err_shampo_hd_info_alloc:
870 kvfree(rq->mpwqe.shampo);
871 return err;
872 }
873
mlx5e_rq_free_shampo(struct mlx5e_rq * rq)874 static void mlx5e_rq_free_shampo(struct mlx5e_rq *rq)
875 {
876 if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
877 return;
878
879 kvfree(rq->hw_gro_data);
880 if (rq->hd_page_pool != rq->page_pool)
881 page_pool_destroy(rq->hd_page_pool);
882 mlx5e_rq_shampo_hd_info_free(rq);
883 mlx5_core_destroy_mkey(rq->mdev,
884 be32_to_cpu(rq->mpwqe.shampo->mkey_be));
885 kvfree(rq->mpwqe.shampo);
886 }
887
mlx5e_alloc_rq(struct mlx5e_params * params,struct mlx5e_xsk_param * xsk,struct mlx5e_rq_param * rqp,int node,struct mlx5e_rq * rq)888 static int mlx5e_alloc_rq(struct mlx5e_params *params,
889 struct mlx5e_xsk_param *xsk,
890 struct mlx5e_rq_param *rqp,
891 int node, struct mlx5e_rq *rq)
892 {
893 struct mlx5_core_dev *mdev = rq->mdev;
894 void *rqc = rqp->rqc;
895 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
896 u32 pool_size;
897 int wq_sz;
898 int err;
899 int i;
900
901 rqp->wq.db_numa_node = node;
902 INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
903 INIT_WORK(&rq->rx_timeout_work, mlx5e_rq_timeout_work);
904
905 if (params->xdp_prog)
906 bpf_prog_inc(params->xdp_prog);
907 RCU_INIT_POINTER(rq->xdp_prog, params->xdp_prog);
908
909 rq->buff.map_dir = params->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
910 rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
911 pool_size = 1 << params->log_rq_mtu_frames;
912
913 rq->mkey_be = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey);
914
915 switch (rq->wq_type) {
916 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
917 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
918 &rq->wq_ctrl);
919 if (err)
920 goto err_rq_xdp_prog;
921
922 err = mlx5e_alloc_mpwqe_rq_drop_page(rq);
923 if (err)
924 goto err_rq_wq_destroy;
925
926 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
927
928 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
929
930 rq->mpwqe.page_shift = mlx5e_mpwrq_page_shift(mdev, xsk);
931 rq->mpwqe.umr_mode = mlx5e_mpwrq_umr_mode(mdev, xsk);
932 rq->mpwqe.pages_per_wqe =
933 mlx5e_mpwrq_pages_per_wqe(mdev, rq->mpwqe.page_shift,
934 rq->mpwqe.umr_mode);
935 rq->mpwqe.umr_wqebbs =
936 mlx5e_mpwrq_umr_wqebbs(mdev, rq->mpwqe.page_shift,
937 rq->mpwqe.umr_mode);
938 rq->mpwqe.mtts_per_wqe =
939 mlx5e_mpwrq_mtts_per_wqe(mdev, rq->mpwqe.page_shift,
940 rq->mpwqe.umr_mode);
941
942 pool_size = rq->mpwqe.pages_per_wqe <<
943 mlx5e_mpwqe_get_log_rq_size(mdev, params, xsk);
944
945 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, xsk) && params->xdp_prog)
946 pool_size *= 2; /* additional page per packet for the linear part */
947
948 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
949 rq->mpwqe.num_strides =
950 BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
951 rq->mpwqe.min_wqe_bulk = mlx5e_mpwqe_get_min_wqe_bulk(wq_sz);
952
953 rq->buff.frame0_sz = (1 << rq->mpwqe.log_stride_sz);
954
955 err = mlx5e_create_rq_umr_mkey(mdev, rq);
956 if (err)
957 goto err_rq_drop_page;
958
959 err = mlx5e_rq_alloc_mpwqe_info(rq, node);
960 if (err)
961 goto err_rq_mkey;
962
963 err = mlx5_rq_shampo_alloc(mdev, params, rqp, rq, &pool_size, node);
964 if (err)
965 goto err_free_mpwqe_info;
966
967 break;
968 default: /* MLX5_WQ_TYPE_CYCLIC */
969 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
970 &rq->wq_ctrl);
971 if (err)
972 goto err_rq_xdp_prog;
973
974 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
975
976 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
977
978 rq->wqe.info = rqp->frags_info;
979 rq->buff.frame0_sz = rq->wqe.info.arr[0].frag_stride;
980
981 err = mlx5e_init_wqe_alloc_info(rq, node);
982 if (err)
983 goto err_rq_wq_destroy;
984 }
985
986 if (xsk) {
987 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
988 MEM_TYPE_XSK_BUFF_POOL, NULL);
989 if (err)
990 goto err_free_by_rq_type;
991 xsk_pool_set_rxq_info(rq->xsk_pool, &rq->xdp_rxq);
992 } else {
993 /* Create a page_pool and register it with rxq */
994 struct page_pool_params pp_params = { 0 };
995
996 pp_params.order = 0;
997 pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV;
998 pp_params.pool_size = pool_size;
999 pp_params.nid = node;
1000 pp_params.dev = rq->pdev;
1001 pp_params.napi = rq->cq.napi;
1002 pp_params.netdev = rq->netdev;
1003 pp_params.dma_dir = rq->buff.map_dir;
1004 pp_params.max_len = PAGE_SIZE;
1005 pp_params.queue_idx = rq->ix;
1006
1007 /* Shampo header data split allow for unreadable netmem */
1008 if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
1009 pp_params.flags |= PP_FLAG_ALLOW_UNREADABLE_NETMEM;
1010
1011 /* page_pool can be used even when there is no rq->xdp_prog,
1012 * given page_pool does not handle DMA mapping there is no
1013 * required state to clear. And page_pool gracefully handle
1014 * elevated refcnt.
1015 */
1016 rq->page_pool = page_pool_create(&pp_params);
1017 if (IS_ERR(rq->page_pool)) {
1018 err = PTR_ERR(rq->page_pool);
1019 rq->page_pool = NULL;
1020 goto err_free_by_rq_type;
1021 }
1022 if (!rq->hd_page_pool)
1023 rq->hd_page_pool = rq->page_pool;
1024 if (xdp_rxq_info_is_reg(&rq->xdp_rxq)) {
1025 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
1026 MEM_TYPE_PAGE_POOL, rq->page_pool);
1027 if (err)
1028 goto err_destroy_page_pool;
1029 }
1030 }
1031
1032 for (i = 0; i < wq_sz; i++) {
1033 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
1034 struct mlx5e_rx_wqe_ll *wqe =
1035 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
1036 u32 byte_count =
1037 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
1038 u64 dma_offset = mul_u32_u32(i, rq->mpwqe.mtts_per_wqe) <<
1039 rq->mpwqe.page_shift;
1040 u16 headroom = test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state) ?
1041 0 : rq->buff.headroom;
1042
1043 wqe->data[0].addr = cpu_to_be64(dma_offset + headroom);
1044 wqe->data[0].byte_count = cpu_to_be32(byte_count);
1045 wqe->data[0].lkey = rq->mpwqe.umr_mkey_be;
1046 } else {
1047 struct mlx5e_rx_wqe_cyc *wqe =
1048 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
1049 int f;
1050
1051 for (f = 0; f < rq->wqe.info.num_frags; f++) {
1052 u32 frag_size = rq->wqe.info.arr[f].frag_size |
1053 MLX5_HW_START_PADDING;
1054
1055 wqe->data[f].byte_count = cpu_to_be32(frag_size);
1056 wqe->data[f].lkey = rq->mkey_be;
1057 }
1058 /* check if num_frags is not a pow of two */
1059 if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
1060 wqe->data[f].byte_count = 0;
1061 wqe->data[f].lkey = params->terminate_lkey_be;
1062 wqe->data[f].addr = 0;
1063 }
1064 }
1065 }
1066
1067 return 0;
1068
1069 err_destroy_page_pool:
1070 page_pool_destroy(rq->page_pool);
1071 err_free_by_rq_type:
1072 switch (rq->wq_type) {
1073 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1074 mlx5e_rq_free_shampo(rq);
1075 err_free_mpwqe_info:
1076 kvfree(rq->mpwqe.info);
1077 err_rq_mkey:
1078 mlx5_core_destroy_mkey(mdev, be32_to_cpu(rq->mpwqe.umr_mkey_be));
1079 err_rq_drop_page:
1080 mlx5e_free_mpwqe_rq_drop_page(rq);
1081 break;
1082 default: /* MLX5_WQ_TYPE_CYCLIC */
1083 mlx5e_free_wqe_alloc_info(rq);
1084 }
1085 err_rq_wq_destroy:
1086 mlx5_wq_destroy(&rq->wq_ctrl);
1087 err_rq_xdp_prog:
1088 if (params->xdp_prog)
1089 bpf_prog_put(params->xdp_prog);
1090
1091 return err;
1092 }
1093
mlx5e_free_rq(struct mlx5e_rq * rq)1094 static void mlx5e_free_rq(struct mlx5e_rq *rq)
1095 {
1096 kvfree(rq->dim);
1097 page_pool_destroy(rq->page_pool);
1098
1099 switch (rq->wq_type) {
1100 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1101 mlx5e_rq_free_shampo(rq);
1102 kvfree(rq->mpwqe.info);
1103 mlx5_core_destroy_mkey(rq->mdev, be32_to_cpu(rq->mpwqe.umr_mkey_be));
1104 mlx5e_free_mpwqe_rq_drop_page(rq);
1105 break;
1106 default: /* MLX5_WQ_TYPE_CYCLIC */
1107 mlx5e_free_wqe_alloc_info(rq);
1108 }
1109
1110 mlx5_wq_destroy(&rq->wq_ctrl);
1111
1112 if (xdp_rxq_info_is_reg(&rq->xdp_rxq)) {
1113 struct bpf_prog *old_prog;
1114
1115 old_prog = rcu_dereference_protected(rq->xdp_prog,
1116 lockdep_is_held(&rq->priv->state_lock));
1117 if (old_prog)
1118 bpf_prog_put(old_prog);
1119 }
1120 xdp_rxq_info_unreg(&rq->xdp_rxq);
1121 }
1122
mlx5e_create_rq(struct mlx5e_rq * rq,struct mlx5e_rq_param * param,u16 q_counter)1123 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param, u16 q_counter)
1124 {
1125 struct mlx5_core_dev *mdev = rq->mdev;
1126 u8 ts_format;
1127 void *in;
1128 void *rqc;
1129 void *wq;
1130 int inlen;
1131 int err;
1132
1133 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
1134 sizeof(u64) * rq->wq_ctrl.buf.npages;
1135 in = kvzalloc(inlen, GFP_KERNEL);
1136 if (!in)
1137 return -ENOMEM;
1138
1139 ts_format = mlx5_is_real_time_rq(mdev) ?
1140 MLX5_TIMESTAMP_FORMAT_REAL_TIME :
1141 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
1142 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1143 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1144
1145 memcpy(rqc, param->rqc, sizeof(param->rqc));
1146
1147 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
1148 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1149 MLX5_SET(rqc, rqc, ts_format, ts_format);
1150 MLX5_SET(rqc, rqc, counter_set_id, q_counter);
1151 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
1152 MLX5_ADAPTER_PAGE_SHIFT);
1153 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
1154
1155 if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) {
1156 MLX5_SET(wq, wq, log_headers_buffer_entry_num,
1157 order_base_2(rq->mpwqe.shampo->hd_per_wq));
1158 MLX5_SET(wq, wq, headers_mkey,
1159 be32_to_cpu(rq->mpwqe.shampo->mkey_be));
1160 }
1161
1162 mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
1163 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1164
1165 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
1166
1167 kvfree(in);
1168
1169 return err;
1170 }
1171
mlx5e_modify_rq_state(struct mlx5e_rq * rq,int curr_state,int next_state)1172 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
1173 {
1174 struct mlx5_core_dev *mdev = rq->mdev;
1175
1176 void *in;
1177 void *rqc;
1178 int inlen;
1179 int err;
1180
1181 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1182 in = kvzalloc(inlen, GFP_KERNEL);
1183 if (!in)
1184 return -ENOMEM;
1185
1186 if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY)
1187 mlx5e_rqwq_reset(rq);
1188
1189 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1190
1191 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
1192 MLX5_SET(rqc, rqc, state, next_state);
1193
1194 err = mlx5_core_modify_rq(mdev, rq->rqn, in);
1195
1196 kvfree(in);
1197
1198 return err;
1199 }
1200
mlx5e_flush_rq_cq(struct mlx5e_rq * rq)1201 static void mlx5e_flush_rq_cq(struct mlx5e_rq *rq)
1202 {
1203 struct mlx5_cqwq *cqwq = &rq->cq.wq;
1204 struct mlx5_cqe64 *cqe;
1205
1206 if (test_bit(MLX5E_RQ_STATE_MINI_CQE_ENHANCED, &rq->state)) {
1207 while ((cqe = mlx5_cqwq_get_cqe_enhanced_comp(cqwq)))
1208 mlx5_cqwq_pop(cqwq);
1209 } else {
1210 while ((cqe = mlx5_cqwq_get_cqe(cqwq)))
1211 mlx5_cqwq_pop(cqwq);
1212 }
1213
1214 mlx5_cqwq_update_db_record(cqwq);
1215 }
1216
mlx5e_flush_rq(struct mlx5e_rq * rq,int curr_state)1217 int mlx5e_flush_rq(struct mlx5e_rq *rq, int curr_state)
1218 {
1219 struct net_device *dev = rq->netdev;
1220 int err;
1221
1222 err = mlx5e_modify_rq_state(rq, curr_state, MLX5_RQC_STATE_RST);
1223 if (err) {
1224 netdev_err(dev, "Failed to move rq 0x%x to reset\n", rq->rqn);
1225 return err;
1226 }
1227
1228 mlx5e_free_rx_descs(rq);
1229 mlx5e_flush_rq_cq(rq);
1230
1231 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1232 if (err) {
1233 netdev_err(dev, "Failed to move rq 0x%x to ready\n", rq->rqn);
1234 return err;
1235 }
1236
1237 return 0;
1238 }
1239
mlx5e_modify_rq_vsd(struct mlx5e_rq * rq,bool vsd)1240 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
1241 {
1242 struct mlx5_core_dev *mdev = rq->mdev;
1243 void *in;
1244 void *rqc;
1245 int inlen;
1246 int err;
1247
1248 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1249 in = kvzalloc(inlen, GFP_KERNEL);
1250 if (!in)
1251 return -ENOMEM;
1252
1253 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1254
1255 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
1256 MLX5_SET64(modify_rq_in, in, modify_bitmask,
1257 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
1258 MLX5_SET(rqc, rqc, vsd, vsd);
1259 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
1260
1261 err = mlx5_core_modify_rq(mdev, rq->rqn, in);
1262
1263 kvfree(in);
1264
1265 return err;
1266 }
1267
mlx5e_destroy_rq(struct mlx5e_rq * rq)1268 void mlx5e_destroy_rq(struct mlx5e_rq *rq)
1269 {
1270 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
1271 }
1272
mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq * rq,int wait_time)1273 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
1274 {
1275 unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
1276
1277 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
1278
1279 do {
1280 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
1281 return 0;
1282
1283 msleep(20);
1284 } while (time_before(jiffies, exp_time));
1285
1286 netdev_warn(rq->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
1287 rq->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
1288
1289 queue_work(rq->priv->wq, &rq->rx_timeout_work);
1290
1291 return -ETIMEDOUT;
1292 }
1293
mlx5e_free_rx_missing_descs(struct mlx5e_rq * rq)1294 void mlx5e_free_rx_missing_descs(struct mlx5e_rq *rq)
1295 {
1296 struct mlx5_wq_ll *wq;
1297 u16 head;
1298 int i;
1299
1300 if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
1301 return;
1302
1303 wq = &rq->mpwqe.wq;
1304 head = wq->head;
1305
1306 /* Release WQEs that are in missing state: they have been
1307 * popped from the list after completion but were not freed
1308 * due to deferred release.
1309 * Also free the linked-list reserved entry, hence the "+ 1".
1310 */
1311 for (i = 0; i < mlx5_wq_ll_missing(wq) + 1; i++) {
1312 rq->dealloc_wqe(rq, head);
1313 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
1314 }
1315
1316 rq->mpwqe.actual_wq_head = wq->head;
1317 rq->mpwqe.umr_in_progress = 0;
1318 rq->mpwqe.umr_completed = 0;
1319
1320 if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) {
1321 struct mlx5e_shampo_hd *shampo = rq->mpwqe.shampo;
1322 u16 len;
1323
1324 len = (shampo->pi - shampo->ci) & shampo->hd_per_wq;
1325 mlx5e_shampo_fill_umr(rq, len);
1326 }
1327 }
1328
mlx5e_free_rx_descs(struct mlx5e_rq * rq)1329 void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
1330 {
1331 __be16 wqe_ix_be;
1332 u16 wqe_ix;
1333
1334 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
1335 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
1336
1337 mlx5e_free_rx_missing_descs(rq);
1338
1339 while (!mlx5_wq_ll_is_empty(wq)) {
1340 struct mlx5e_rx_wqe_ll *wqe;
1341
1342 wqe_ix_be = *wq->tail_next;
1343 wqe_ix = be16_to_cpu(wqe_ix_be);
1344 wqe = mlx5_wq_ll_get_wqe(wq, wqe_ix);
1345 rq->dealloc_wqe(rq, wqe_ix);
1346 mlx5_wq_ll_pop(wq, wqe_ix_be,
1347 &wqe->next.next_wqe_index);
1348 }
1349
1350 if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
1351 mlx5e_shampo_dealloc_hd(rq);
1352 } else {
1353 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1354 u16 missing = mlx5_wq_cyc_missing(wq);
1355 u16 head = mlx5_wq_cyc_get_head(wq);
1356
1357 while (!mlx5_wq_cyc_is_empty(wq)) {
1358 wqe_ix = mlx5_wq_cyc_get_tail(wq);
1359 rq->dealloc_wqe(rq, wqe_ix);
1360 mlx5_wq_cyc_pop(wq);
1361 }
1362 /* Missing slots might also contain unreleased pages due to
1363 * deferred release.
1364 */
1365 while (missing--) {
1366 wqe_ix = mlx5_wq_cyc_ctr2ix(wq, head++);
1367 rq->dealloc_wqe(rq, wqe_ix);
1368 }
1369 }
1370
1371 }
1372
mlx5e_open_rq(struct mlx5e_params * params,struct mlx5e_rq_param * param,struct mlx5e_xsk_param * xsk,int node,u16 q_counter,struct mlx5e_rq * rq)1373 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
1374 struct mlx5e_xsk_param *xsk, int node, u16 q_counter,
1375 struct mlx5e_rq *rq)
1376 {
1377 struct mlx5_core_dev *mdev = rq->mdev;
1378 int err;
1379
1380 if (params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO)
1381 __set_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state);
1382
1383 err = mlx5e_alloc_rq(params, xsk, param, node, rq);
1384 if (err)
1385 return err;
1386
1387 err = mlx5e_create_rq(rq, param, q_counter);
1388 if (err)
1389 goto err_free_rq;
1390
1391 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1392 if (err)
1393 goto err_destroy_rq;
1394
1395 if (MLX5_CAP_ETH(mdev, cqe_checksum_full))
1396 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state);
1397
1398 if (rq->channel && !params->rx_dim_enabled) {
1399 rq->channel->rx_cq_moder = params->rx_cq_moderation;
1400 } else if (rq->channel) {
1401 u8 cq_period_mode;
1402
1403 cq_period_mode = params->rx_moder_use_cqe_mode ?
1404 DIM_CQ_PERIOD_MODE_START_FROM_CQE :
1405 DIM_CQ_PERIOD_MODE_START_FROM_EQE;
1406 mlx5e_reset_rx_moderation(&rq->channel->rx_cq_moder, cq_period_mode,
1407 params->rx_dim_enabled);
1408
1409 err = mlx5e_dim_rx_change(rq, params->rx_dim_enabled);
1410 if (err)
1411 goto err_destroy_rq;
1412 }
1413
1414 /* We disable csum_complete when XDP is enabled since
1415 * XDP programs might manipulate packets which will render
1416 * skb->checksum incorrect.
1417 */
1418 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || params->xdp_prog)
1419 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state);
1420
1421 /* For CQE compression on striding RQ, use stride index provided by
1422 * HW if capability is supported.
1423 */
1424 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) &&
1425 MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index))
1426 __set_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &rq->state);
1427
1428 /* For enhanced CQE compression packet processing. decompress
1429 * session according to the enhanced layout.
1430 */
1431 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS) &&
1432 MLX5_CAP_GEN(mdev, enhanced_cqe_compression))
1433 __set_bit(MLX5E_RQ_STATE_MINI_CQE_ENHANCED, &rq->state);
1434
1435 return 0;
1436
1437 err_destroy_rq:
1438 mlx5e_destroy_rq(rq);
1439 err_free_rq:
1440 mlx5e_free_rq(rq);
1441
1442 return err;
1443 }
1444
mlx5e_activate_rq(struct mlx5e_rq * rq)1445 void mlx5e_activate_rq(struct mlx5e_rq *rq)
1446 {
1447 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
1448 }
1449
mlx5e_deactivate_rq(struct mlx5e_rq * rq)1450 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
1451 {
1452 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
1453 synchronize_net(); /* Sync with NAPI to prevent mlx5e_post_rx_wqes. */
1454 }
1455
mlx5e_close_rq(struct mlx5e_rq * rq)1456 void mlx5e_close_rq(struct mlx5e_rq *rq)
1457 {
1458 if (rq->dim)
1459 cancel_work_sync(&rq->dim->work);
1460 cancel_work_sync(&rq->recover_work);
1461 cancel_work_sync(&rq->rx_timeout_work);
1462 mlx5e_destroy_rq(rq);
1463 mlx5e_free_rx_descs(rq);
1464 mlx5e_free_rq(rq);
1465 }
1466
mlx5e_profile_get_tisn(struct mlx5_core_dev * mdev,struct mlx5e_priv * priv,const struct mlx5e_profile * profile,u8 lag_port,u8 tc)1467 u32 mlx5e_profile_get_tisn(struct mlx5_core_dev *mdev,
1468 struct mlx5e_priv *priv,
1469 const struct mlx5e_profile *profile,
1470 u8 lag_port, u8 tc)
1471 {
1472 if (profile->get_tisn)
1473 return profile->get_tisn(mdev, priv, lag_port, tc);
1474
1475 return mdev->mlx5e_res.hw_objs.tisn[lag_port][tc];
1476 }
1477
mlx5e_free_xdpsq_db(struct mlx5e_xdpsq * sq)1478 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
1479 {
1480 kvfree(sq->db.xdpi_fifo.xi);
1481 kvfree(sq->db.wqe_info);
1482 }
1483
mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq * sq,int numa)1484 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
1485 {
1486 struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
1487 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1488 int entries;
1489 size_t size;
1490
1491 /* upper bound for maximum num of entries of all xmit_modes. */
1492 entries = roundup_pow_of_two(wq_sz * MLX5_SEND_WQEBB_NUM_DS *
1493 MLX5E_XDP_FIFO_ENTRIES2DS_MAX_RATIO);
1494
1495 size = array_size(sizeof(*xdpi_fifo->xi), entries);
1496 xdpi_fifo->xi = kvzalloc_node(size, GFP_KERNEL, numa);
1497 if (!xdpi_fifo->xi)
1498 return -ENOMEM;
1499
1500 xdpi_fifo->pc = &sq->xdpi_fifo_pc;
1501 xdpi_fifo->cc = &sq->xdpi_fifo_cc;
1502 xdpi_fifo->mask = entries - 1;
1503
1504 return 0;
1505 }
1506
mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq * sq,int numa)1507 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
1508 {
1509 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1510 size_t size;
1511 int err;
1512
1513 size = array_size(sizeof(*sq->db.wqe_info), wq_sz);
1514 sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1515 if (!sq->db.wqe_info)
1516 return -ENOMEM;
1517
1518 err = mlx5e_alloc_xdpsq_fifo(sq, numa);
1519 if (err) {
1520 mlx5e_free_xdpsq_db(sq);
1521 return err;
1522 }
1523
1524 return 0;
1525 }
1526
mlx5e_alloc_xdpsq(struct mlx5e_channel * c,struct mlx5e_params * params,struct xsk_buff_pool * xsk_pool,struct mlx5e_sq_param * param,struct mlx5e_xdpsq * sq,bool is_redirect)1527 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
1528 struct mlx5e_params *params,
1529 struct xsk_buff_pool *xsk_pool,
1530 struct mlx5e_sq_param *param,
1531 struct mlx5e_xdpsq *sq,
1532 bool is_redirect)
1533 {
1534 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1535 struct mlx5_core_dev *mdev = c->mdev;
1536 struct mlx5_wq_cyc *wq = &sq->wq;
1537 int err;
1538
1539 sq->pdev = c->pdev;
1540 sq->mkey_be = c->mkey_be;
1541 sq->channel = c;
1542 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map;
1543 sq->min_inline_mode = params->tx_min_inline_mode;
1544 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu) - ETH_FCS_LEN;
1545 sq->xsk_pool = xsk_pool;
1546
1547 sq->stats = sq->xsk_pool ?
1548 &c->priv->channel_stats[c->ix]->xsksq :
1549 is_redirect ?
1550 &c->priv->channel_stats[c->ix]->xdpsq :
1551 &c->priv->channel_stats[c->ix]->rq_xdpsq;
1552 sq->stop_room = param->is_mpw ? mlx5e_stop_room_for_mpwqe(mdev) :
1553 mlx5e_stop_room_for_max_wqe(mdev);
1554 sq->max_sq_mpw_wqebbs = mlx5e_get_max_sq_aligned_wqebbs(mdev);
1555
1556 param->wq.db_numa_node = cpu_to_node(c->cpu);
1557 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1558 if (err)
1559 return err;
1560 wq->db = &wq->db[MLX5_SND_DBR];
1561
1562 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1563 if (err)
1564 goto err_sq_wq_destroy;
1565
1566 return 0;
1567
1568 err_sq_wq_destroy:
1569 mlx5_wq_destroy(&sq->wq_ctrl);
1570
1571 return err;
1572 }
1573
mlx5e_free_xdpsq(struct mlx5e_xdpsq * sq)1574 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1575 {
1576 mlx5e_free_xdpsq_db(sq);
1577 mlx5_wq_destroy(&sq->wq_ctrl);
1578 }
1579
mlx5e_free_icosq_db(struct mlx5e_icosq * sq)1580 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1581 {
1582 kvfree(sq->db.wqe_info);
1583 }
1584
mlx5e_alloc_icosq_db(struct mlx5e_icosq * sq,int numa)1585 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1586 {
1587 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1588 size_t size;
1589
1590 size = array_size(wq_sz, sizeof(*sq->db.wqe_info));
1591 sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1592 if (!sq->db.wqe_info)
1593 return -ENOMEM;
1594
1595 return 0;
1596 }
1597
mlx5e_icosq_err_cqe_work(struct work_struct * recover_work)1598 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
1599 {
1600 struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1601 recover_work);
1602
1603 mlx5e_reporter_icosq_cqe_err(sq);
1604 }
1605
mlx5e_async_icosq_err_cqe_work(struct work_struct * recover_work)1606 static void mlx5e_async_icosq_err_cqe_work(struct work_struct *recover_work)
1607 {
1608 struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1609 recover_work);
1610
1611 /* Not implemented yet. */
1612
1613 netdev_warn(sq->channel->netdev, "async_icosq recovery is not implemented\n");
1614 }
1615
mlx5e_alloc_icosq(struct mlx5e_channel * c,struct mlx5e_sq_param * param,struct mlx5e_icosq * sq,work_func_t recover_work_func)1616 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1617 struct mlx5e_sq_param *param,
1618 struct mlx5e_icosq *sq,
1619 work_func_t recover_work_func)
1620 {
1621 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1622 struct mlx5_core_dev *mdev = c->mdev;
1623 struct mlx5_wq_cyc *wq = &sq->wq;
1624 int err;
1625
1626 sq->channel = c;
1627 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map;
1628 sq->reserved_room = param->stop_room;
1629
1630 param->wq.db_numa_node = cpu_to_node(c->cpu);
1631 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1632 if (err)
1633 return err;
1634 wq->db = &wq->db[MLX5_SND_DBR];
1635
1636 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1637 if (err)
1638 goto err_sq_wq_destroy;
1639
1640 INIT_WORK(&sq->recover_work, recover_work_func);
1641
1642 return 0;
1643
1644 err_sq_wq_destroy:
1645 mlx5_wq_destroy(&sq->wq_ctrl);
1646
1647 return err;
1648 }
1649
mlx5e_free_icosq(struct mlx5e_icosq * sq)1650 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1651 {
1652 mlx5e_free_icosq_db(sq);
1653 mlx5_wq_destroy(&sq->wq_ctrl);
1654 }
1655
mlx5e_free_txqsq_db(struct mlx5e_txqsq * sq)1656 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1657 {
1658 kvfree(sq->db.wqe_info);
1659 kvfree(sq->db.skb_fifo.fifo);
1660 kvfree(sq->db.dma_fifo);
1661 }
1662
mlx5e_alloc_txqsq_db(struct mlx5e_txqsq * sq,int numa)1663 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1664 {
1665 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1666 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1667
1668 sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1669 sizeof(*sq->db.dma_fifo)),
1670 GFP_KERNEL, numa);
1671 sq->db.skb_fifo.fifo = kvzalloc_node(array_size(df_sz,
1672 sizeof(*sq->db.skb_fifo.fifo)),
1673 GFP_KERNEL, numa);
1674 sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1675 sizeof(*sq->db.wqe_info)),
1676 GFP_KERNEL, numa);
1677 if (!sq->db.dma_fifo || !sq->db.skb_fifo.fifo || !sq->db.wqe_info) {
1678 mlx5e_free_txqsq_db(sq);
1679 return -ENOMEM;
1680 }
1681
1682 sq->dma_fifo_mask = df_sz - 1;
1683
1684 sq->db.skb_fifo.pc = &sq->skb_fifo_pc;
1685 sq->db.skb_fifo.cc = &sq->skb_fifo_cc;
1686 sq->db.skb_fifo.mask = df_sz - 1;
1687
1688 return 0;
1689 }
1690
mlx5e_alloc_txqsq(struct mlx5e_channel * c,int txq_ix,struct mlx5e_params * params,struct mlx5e_sq_param * param,struct mlx5e_txqsq * sq,int tc)1691 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1692 int txq_ix,
1693 struct mlx5e_params *params,
1694 struct mlx5e_sq_param *param,
1695 struct mlx5e_txqsq *sq,
1696 int tc)
1697 {
1698 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1699 struct mlx5_core_dev *mdev = c->mdev;
1700 struct mlx5_wq_cyc *wq = &sq->wq;
1701 int err;
1702
1703 sq->pdev = c->pdev;
1704 sq->clock = mdev->clock;
1705 sq->mkey_be = c->mkey_be;
1706 sq->netdev = c->netdev;
1707 sq->mdev = c->mdev;
1708 sq->channel = c;
1709 sq->priv = c->priv;
1710 sq->ch_ix = c->ix;
1711 sq->txq_ix = txq_ix;
1712 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map;
1713 sq->min_inline_mode = params->tx_min_inline_mode;
1714 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1715 sq->max_sq_mpw_wqebbs = mlx5e_get_max_sq_aligned_wqebbs(mdev);
1716 INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1717 if (mlx5_ipsec_device_caps(c->priv->mdev))
1718 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1719 if (param->is_mpw)
1720 set_bit(MLX5E_SQ_STATE_MPWQE, &sq->state);
1721 sq->stop_room = param->stop_room;
1722 sq->ptp_cyc2time = mlx5_sq_ts_translator(mdev);
1723
1724 param->wq.db_numa_node = cpu_to_node(c->cpu);
1725 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1726 if (err)
1727 return err;
1728 wq->db = &wq->db[MLX5_SND_DBR];
1729
1730 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1731 if (err)
1732 goto err_sq_wq_destroy;
1733
1734 return 0;
1735
1736 err_sq_wq_destroy:
1737 mlx5_wq_destroy(&sq->wq_ctrl);
1738
1739 return err;
1740 }
1741
mlx5e_free_txqsq(struct mlx5e_txqsq * sq)1742 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1743 {
1744 kvfree(sq->dim);
1745 mlx5e_free_txqsq_db(sq);
1746 mlx5_wq_destroy(&sq->wq_ctrl);
1747 }
1748
mlx5e_create_sq(struct mlx5_core_dev * mdev,struct mlx5e_sq_param * param,struct mlx5e_create_sq_param * csp,u32 * sqn)1749 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1750 struct mlx5e_sq_param *param,
1751 struct mlx5e_create_sq_param *csp,
1752 u32 *sqn)
1753 {
1754 u8 ts_format;
1755 void *in;
1756 void *sqc;
1757 void *wq;
1758 int inlen;
1759 int err;
1760
1761 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1762 sizeof(u64) * csp->wq_ctrl->buf.npages;
1763 in = kvzalloc(inlen, GFP_KERNEL);
1764 if (!in)
1765 return -ENOMEM;
1766
1767 ts_format = mlx5_is_real_time_sq(mdev) ?
1768 MLX5_TIMESTAMP_FORMAT_REAL_TIME :
1769 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
1770 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1771 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1772
1773 memcpy(sqc, param->sqc, sizeof(param->sqc));
1774 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1775 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1776 MLX5_SET(sqc, sqc, cqn, csp->cqn);
1777 MLX5_SET(sqc, sqc, ts_cqe_to_dest_cqn, csp->ts_cqe_to_dest_cqn);
1778 MLX5_SET(sqc, sqc, ts_format, ts_format);
1779
1780
1781 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1782 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
1783
1784 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1785 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1786
1787 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1788 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.hw_objs.bfreg.index);
1789 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
1790 MLX5_ADAPTER_PAGE_SHIFT);
1791 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
1792
1793 mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1794 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1795
1796 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1797
1798 kvfree(in);
1799
1800 return err;
1801 }
1802
mlx5e_modify_sq(struct mlx5_core_dev * mdev,u32 sqn,struct mlx5e_modify_sq_param * p)1803 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1804 struct mlx5e_modify_sq_param *p)
1805 {
1806 u64 bitmask = 0;
1807 void *in;
1808 void *sqc;
1809 int inlen;
1810 int err;
1811
1812 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1813 in = kvzalloc(inlen, GFP_KERNEL);
1814 if (!in)
1815 return -ENOMEM;
1816
1817 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1818
1819 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1820 MLX5_SET(sqc, sqc, state, p->next_state);
1821 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1822 bitmask |= 1;
1823 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1824 }
1825 if (p->qos_update && p->next_state == MLX5_SQC_STATE_RDY) {
1826 bitmask |= 1 << 2;
1827 MLX5_SET(sqc, sqc, qos_queue_group_id, p->qos_queue_group_id);
1828 }
1829 MLX5_SET64(modify_sq_in, in, modify_bitmask, bitmask);
1830
1831 err = mlx5_core_modify_sq(mdev, sqn, in);
1832
1833 kvfree(in);
1834
1835 return err;
1836 }
1837
mlx5e_destroy_sq(struct mlx5_core_dev * mdev,u32 sqn)1838 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1839 {
1840 mlx5_core_destroy_sq(mdev, sqn);
1841 }
1842
mlx5e_create_sq_rdy(struct mlx5_core_dev * mdev,struct mlx5e_sq_param * param,struct mlx5e_create_sq_param * csp,u16 qos_queue_group_id,u32 * sqn)1843 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1844 struct mlx5e_sq_param *param,
1845 struct mlx5e_create_sq_param *csp,
1846 u16 qos_queue_group_id,
1847 u32 *sqn)
1848 {
1849 struct mlx5e_modify_sq_param msp = {0};
1850 int err;
1851
1852 err = mlx5e_create_sq(mdev, param, csp, sqn);
1853 if (err)
1854 return err;
1855
1856 msp.curr_state = MLX5_SQC_STATE_RST;
1857 msp.next_state = MLX5_SQC_STATE_RDY;
1858 if (qos_queue_group_id) {
1859 msp.qos_update = true;
1860 msp.qos_queue_group_id = qos_queue_group_id;
1861 }
1862 err = mlx5e_modify_sq(mdev, *sqn, &msp);
1863 if (err)
1864 mlx5e_destroy_sq(mdev, *sqn);
1865
1866 return err;
1867 }
1868
1869 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1870 struct mlx5e_txqsq *sq, u32 rate);
1871
mlx5e_open_txqsq(struct mlx5e_channel * c,u32 tisn,int txq_ix,struct mlx5e_params * params,struct mlx5e_sq_param * param,struct mlx5e_txqsq * sq,int tc,u16 qos_queue_group_id,struct mlx5e_sq_stats * sq_stats)1872 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1873 struct mlx5e_params *params, struct mlx5e_sq_param *param,
1874 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id,
1875 struct mlx5e_sq_stats *sq_stats)
1876 {
1877 struct mlx5e_create_sq_param csp = {};
1878 u32 tx_rate;
1879 int err;
1880
1881 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1882 if (err)
1883 return err;
1884
1885 sq->stats = sq_stats;
1886
1887 csp.tisn = tisn;
1888 csp.tis_lst_sz = 1;
1889 csp.cqn = sq->cq.mcq.cqn;
1890 csp.wq_ctrl = &sq->wq_ctrl;
1891 csp.min_inline_mode = sq->min_inline_mode;
1892 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, qos_queue_group_id, &sq->sqn);
1893 if (err)
1894 goto err_free_txqsq;
1895
1896 tx_rate = c->priv->tx_rates[sq->txq_ix];
1897 if (tx_rate)
1898 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1899
1900 if (sq->channel && !params->tx_dim_enabled) {
1901 sq->channel->tx_cq_moder = params->tx_cq_moderation;
1902 } else if (sq->channel) {
1903 u8 cq_period_mode;
1904
1905 cq_period_mode = params->tx_moder_use_cqe_mode ?
1906 DIM_CQ_PERIOD_MODE_START_FROM_CQE :
1907 DIM_CQ_PERIOD_MODE_START_FROM_EQE;
1908 mlx5e_reset_tx_moderation(&sq->channel->tx_cq_moder,
1909 cq_period_mode,
1910 params->tx_dim_enabled);
1911
1912 err = mlx5e_dim_tx_change(sq, params->tx_dim_enabled);
1913 if (err)
1914 goto err_destroy_sq;
1915 }
1916
1917 return 0;
1918
1919 err_destroy_sq:
1920 mlx5e_destroy_sq(c->mdev, sq->sqn);
1921 err_free_txqsq:
1922 mlx5e_free_txqsq(sq);
1923
1924 return err;
1925 }
1926
mlx5e_activate_txqsq(struct mlx5e_txqsq * sq)1927 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1928 {
1929 sq->txq = netdev_get_tx_queue(sq->netdev, sq->txq_ix);
1930 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1931 netdev_tx_reset_queue(sq->txq);
1932 netif_tx_start_queue(sq->txq);
1933 netif_queue_set_napi(sq->netdev, sq->txq_ix, NETDEV_QUEUE_TYPE_TX, sq->cq.napi);
1934 }
1935
mlx5e_tx_disable_queue(struct netdev_queue * txq)1936 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1937 {
1938 __netif_tx_lock_bh(txq);
1939 netif_tx_stop_queue(txq);
1940 __netif_tx_unlock_bh(txq);
1941 }
1942
mlx5e_deactivate_txqsq(struct mlx5e_txqsq * sq)1943 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1944 {
1945 struct mlx5_wq_cyc *wq = &sq->wq;
1946
1947 netif_queue_set_napi(sq->netdev, sq->txq_ix, NETDEV_QUEUE_TYPE_TX, NULL);
1948 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1949 synchronize_net(); /* Sync with NAPI to prevent netif_tx_wake_queue. */
1950
1951 mlx5e_tx_disable_queue(sq->txq);
1952
1953 /* last doorbell out, godspeed .. */
1954 if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1955 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1956 struct mlx5e_tx_wqe *nop;
1957
1958 sq->db.wqe_info[pi] = (struct mlx5e_tx_wqe_info) {
1959 .num_wqebbs = 1,
1960 };
1961
1962 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1963 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1964 }
1965 }
1966
mlx5e_close_txqsq(struct mlx5e_txqsq * sq)1967 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1968 {
1969 struct mlx5_core_dev *mdev = sq->mdev;
1970 struct mlx5_rate_limit rl = {0};
1971
1972 if (sq->dim)
1973 cancel_work_sync(&sq->dim->work);
1974 cancel_work_sync(&sq->recover_work);
1975 mlx5e_destroy_sq(mdev, sq->sqn);
1976 if (sq->rate_limit) {
1977 rl.rate = sq->rate_limit;
1978 mlx5_rl_remove_rate(mdev, &rl);
1979 }
1980 mlx5e_free_txqsq_descs(sq);
1981 mlx5e_free_txqsq(sq);
1982 }
1983
mlx5e_tx_err_cqe_work(struct work_struct * recover_work)1984 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1985 {
1986 struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1987 recover_work);
1988
1989 /* Recovering queues means re-enabling NAPI, which requires the netdev
1990 * instance lock. However, SQ closing flows have to wait for work tasks
1991 * to finish while also holding the netdev instance lock. So either get
1992 * the lock or find that the SQ is no longer enabled and thus this work
1993 * is not relevant anymore.
1994 */
1995 while (!netdev_trylock(sq->netdev)) {
1996 if (!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state))
1997 return;
1998 msleep(20);
1999 }
2000
2001 mlx5e_reporter_tx_err_cqe(sq);
2002 netdev_unlock(sq->netdev);
2003 }
2004
mlx5e_get_def_tx_moderation(u8 cq_period_mode)2005 static struct dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
2006 {
2007 return (struct dim_cq_moder) {
2008 .cq_period_mode = cq_period_mode,
2009 .pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS,
2010 .usec = cq_period_mode == DIM_CQ_PERIOD_MODE_START_FROM_CQE ?
2011 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE :
2012 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC,
2013 };
2014 }
2015
mlx5e_reset_tx_moderation(struct dim_cq_moder * cq_moder,u8 cq_period_mode,bool dim_enabled)2016 bool mlx5e_reset_tx_moderation(struct dim_cq_moder *cq_moder, u8 cq_period_mode,
2017 bool dim_enabled)
2018 {
2019 bool reset_needed = cq_moder->cq_period_mode != cq_period_mode;
2020
2021 if (dim_enabled)
2022 *cq_moder = net_dim_get_def_tx_moderation(cq_period_mode);
2023 else
2024 *cq_moder = mlx5e_get_def_tx_moderation(cq_period_mode);
2025
2026 return reset_needed;
2027 }
2028
mlx5e_reset_tx_channels_moderation(struct mlx5e_channels * chs,u8 cq_period_mode,bool dim_enabled,bool keep_dim_state)2029 bool mlx5e_reset_tx_channels_moderation(struct mlx5e_channels *chs, u8 cq_period_mode,
2030 bool dim_enabled, bool keep_dim_state)
2031 {
2032 bool reset = false;
2033 int i, tc;
2034
2035 for (i = 0; i < chs->num; i++) {
2036 for (tc = 0; tc < mlx5e_get_dcb_num_tc(&chs->params); tc++) {
2037 if (keep_dim_state)
2038 dim_enabled = !!chs->c[i]->sq[tc].dim;
2039
2040 reset |= mlx5e_reset_tx_moderation(&chs->c[i]->tx_cq_moder,
2041 cq_period_mode, dim_enabled);
2042 }
2043 }
2044
2045 return reset;
2046 }
2047
mlx5e_open_icosq(struct mlx5e_channel * c,struct mlx5e_params * params,struct mlx5e_sq_param * param,struct mlx5e_icosq * sq,work_func_t recover_work_func)2048 static int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
2049 struct mlx5e_sq_param *param, struct mlx5e_icosq *sq,
2050 work_func_t recover_work_func)
2051 {
2052 struct mlx5e_create_sq_param csp = {};
2053 int err;
2054
2055 err = mlx5e_alloc_icosq(c, param, sq, recover_work_func);
2056 if (err)
2057 return err;
2058
2059 csp.cqn = sq->cq.mcq.cqn;
2060 csp.wq_ctrl = &sq->wq_ctrl;
2061 csp.min_inline_mode = params->tx_min_inline_mode;
2062 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
2063 if (err)
2064 goto err_free_icosq;
2065
2066 if (param->is_tls) {
2067 sq->ktls_resync = mlx5e_ktls_rx_resync_create_resp_list();
2068 if (IS_ERR(sq->ktls_resync)) {
2069 err = PTR_ERR(sq->ktls_resync);
2070 goto err_destroy_icosq;
2071 }
2072 }
2073 return 0;
2074
2075 err_destroy_icosq:
2076 mlx5e_destroy_sq(c->mdev, sq->sqn);
2077 err_free_icosq:
2078 mlx5e_free_icosq(sq);
2079
2080 return err;
2081 }
2082
mlx5e_activate_icosq(struct mlx5e_icosq * icosq)2083 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
2084 {
2085 set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
2086 }
2087
mlx5e_deactivate_icosq(struct mlx5e_icosq * icosq)2088 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
2089 {
2090 clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
2091 synchronize_net(); /* Sync with NAPI. */
2092 }
2093
mlx5e_close_icosq(struct mlx5e_icosq * sq)2094 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
2095 {
2096 struct mlx5e_channel *c = sq->channel;
2097
2098 if (sq->ktls_resync)
2099 mlx5e_ktls_rx_resync_destroy_resp_list(sq->ktls_resync);
2100 mlx5e_destroy_sq(c->mdev, sq->sqn);
2101 mlx5e_free_icosq_descs(sq);
2102 mlx5e_free_icosq(sq);
2103 }
2104
mlx5e_open_xdpsq(struct mlx5e_channel * c,struct mlx5e_params * params,struct mlx5e_sq_param * param,struct xsk_buff_pool * xsk_pool,struct mlx5e_xdpsq * sq,bool is_redirect)2105 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
2106 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
2107 struct mlx5e_xdpsq *sq, bool is_redirect)
2108 {
2109 struct mlx5e_create_sq_param csp = {};
2110 int err;
2111
2112 err = mlx5e_alloc_xdpsq(c, params, xsk_pool, param, sq, is_redirect);
2113 if (err)
2114 return err;
2115
2116 csp.tis_lst_sz = 1;
2117 csp.tisn = mlx5e_profile_get_tisn(c->mdev, c->priv, c->priv->profile,
2118 c->lag_port, 0); /* tc = 0 */
2119 csp.cqn = sq->cq.mcq.cqn;
2120 csp.wq_ctrl = &sq->wq_ctrl;
2121 csp.min_inline_mode = sq->min_inline_mode;
2122 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
2123
2124 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
2125 if (err)
2126 goto err_free_xdpsq;
2127
2128 mlx5e_set_xmit_fp(sq, param->is_mpw);
2129
2130 return 0;
2131
2132 err_free_xdpsq:
2133 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
2134 mlx5e_free_xdpsq(sq);
2135
2136 return err;
2137 }
2138
mlx5e_close_xdpsq(struct mlx5e_xdpsq * sq)2139 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
2140 {
2141 struct mlx5e_channel *c = sq->channel;
2142
2143 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
2144 synchronize_net(); /* Sync with NAPI. */
2145
2146 mlx5e_destroy_sq(c->mdev, sq->sqn);
2147 mlx5e_free_xdpsq_descs(sq);
2148 mlx5e_free_xdpsq(sq);
2149 }
2150
mlx5e_open_xdpredirect_sq(struct mlx5e_channel * c,struct mlx5e_params * params,struct mlx5e_channel_param * cparam,struct mlx5e_create_cq_param * ccp)2151 static struct mlx5e_xdpsq *mlx5e_open_xdpredirect_sq(struct mlx5e_channel *c,
2152 struct mlx5e_params *params,
2153 struct mlx5e_channel_param *cparam,
2154 struct mlx5e_create_cq_param *ccp)
2155 {
2156 struct mlx5e_xdpsq *xdpsq;
2157 int err;
2158
2159 xdpsq = kvzalloc_node(sizeof(*xdpsq), GFP_KERNEL, cpu_to_node(c->cpu));
2160 if (!xdpsq)
2161 return ERR_PTR(-ENOMEM);
2162
2163 err = mlx5e_open_cq(c->mdev, params->tx_cq_moderation,
2164 &cparam->xdp_sq.cqp, ccp, &xdpsq->cq);
2165 if (err)
2166 goto err_free_xdpsq;
2167
2168 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, xdpsq, true);
2169 if (err)
2170 goto err_close_xdpsq_cq;
2171
2172 return xdpsq;
2173
2174 err_close_xdpsq_cq:
2175 mlx5e_close_cq(&xdpsq->cq);
2176 err_free_xdpsq:
2177 kvfree(xdpsq);
2178
2179 return ERR_PTR(err);
2180 }
2181
mlx5e_close_xdpredirect_sq(struct mlx5e_xdpsq * xdpsq)2182 static void mlx5e_close_xdpredirect_sq(struct mlx5e_xdpsq *xdpsq)
2183 {
2184 mlx5e_close_xdpsq(xdpsq);
2185 mlx5e_close_cq(&xdpsq->cq);
2186 kvfree(xdpsq);
2187 }
2188
mlx5e_alloc_cq_common(struct mlx5_core_dev * mdev,struct net_device * netdev,struct workqueue_struct * workqueue,struct mlx5e_cq_param * param,struct mlx5e_cq * cq)2189 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
2190 struct net_device *netdev,
2191 struct workqueue_struct *workqueue,
2192 struct mlx5e_cq_param *param,
2193 struct mlx5e_cq *cq)
2194 {
2195 struct mlx5_core_cq *mcq = &cq->mcq;
2196 int err;
2197 u32 i;
2198
2199 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
2200 &cq->wq_ctrl);
2201 if (err)
2202 return err;
2203
2204 mcq->cqe_sz = 64;
2205 mcq->set_ci_db = cq->wq_ctrl.db.db;
2206 mcq->arm_db = cq->wq_ctrl.db.db + 1;
2207 *mcq->set_ci_db = 0;
2208 *mcq->arm_db = 0;
2209 mcq->vector = param->eq_ix;
2210 mcq->comp = mlx5e_completion_event;
2211 mcq->event = mlx5e_cq_error_event;
2212
2213 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
2214 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
2215
2216 cqe->op_own = 0xf1;
2217 cqe->validity_iteration_count = 0xff;
2218 }
2219
2220 cq->mdev = mdev;
2221 cq->netdev = netdev;
2222 cq->workqueue = workqueue;
2223
2224 return 0;
2225 }
2226
mlx5e_alloc_cq(struct mlx5_core_dev * mdev,struct mlx5e_cq_param * param,struct mlx5e_create_cq_param * ccp,struct mlx5e_cq * cq)2227 static int mlx5e_alloc_cq(struct mlx5_core_dev *mdev,
2228 struct mlx5e_cq_param *param,
2229 struct mlx5e_create_cq_param *ccp,
2230 struct mlx5e_cq *cq)
2231 {
2232 int err;
2233
2234 param->wq.buf_numa_node = ccp->node;
2235 param->wq.db_numa_node = ccp->node;
2236 param->eq_ix = ccp->ix;
2237
2238 err = mlx5e_alloc_cq_common(mdev, ccp->netdev, ccp->wq, param, cq);
2239
2240 cq->napi = ccp->napi;
2241 cq->ch_stats = ccp->ch_stats;
2242
2243 return err;
2244 }
2245
mlx5e_free_cq(struct mlx5e_cq * cq)2246 static void mlx5e_free_cq(struct mlx5e_cq *cq)
2247 {
2248 mlx5_wq_destroy(&cq->wq_ctrl);
2249 }
2250
mlx5e_create_cq(struct mlx5e_cq * cq,struct mlx5e_cq_param * param)2251 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
2252 {
2253 u32 out[MLX5_ST_SZ_DW(create_cq_out)];
2254 struct mlx5_core_dev *mdev = cq->mdev;
2255 struct mlx5_core_cq *mcq = &cq->mcq;
2256
2257 void *in;
2258 void *cqc;
2259 int inlen;
2260 int eqn;
2261 int err;
2262
2263 err = mlx5_comp_eqn_get(mdev, param->eq_ix, &eqn);
2264 if (err)
2265 return err;
2266
2267 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
2268 sizeof(u64) * cq->wq_ctrl.buf.npages;
2269 in = kvzalloc(inlen, GFP_KERNEL);
2270 if (!in)
2271 return -ENOMEM;
2272
2273 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
2274
2275 memcpy(cqc, param->cqc, sizeof(param->cqc));
2276
2277 mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
2278 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
2279
2280 MLX5_SET(cqc, cqc, cq_period_mode, mlx5e_cq_period_mode(param->cq_period_mode));
2281
2282 MLX5_SET(cqc, cqc, c_eqn_or_apu_element, eqn);
2283 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
2284 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
2285 MLX5_ADAPTER_PAGE_SHIFT);
2286 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
2287
2288 err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
2289
2290 kvfree(in);
2291
2292 if (err)
2293 return err;
2294
2295 mlx5e_cq_arm(cq);
2296
2297 return 0;
2298 }
2299
mlx5e_destroy_cq(struct mlx5e_cq * cq)2300 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
2301 {
2302 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
2303 }
2304
mlx5e_open_cq(struct mlx5_core_dev * mdev,struct dim_cq_moder moder,struct mlx5e_cq_param * param,struct mlx5e_create_cq_param * ccp,struct mlx5e_cq * cq)2305 int mlx5e_open_cq(struct mlx5_core_dev *mdev, struct dim_cq_moder moder,
2306 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
2307 struct mlx5e_cq *cq)
2308 {
2309 int err;
2310
2311 err = mlx5e_alloc_cq(mdev, param, ccp, cq);
2312 if (err)
2313 return err;
2314
2315 err = mlx5e_create_cq(cq, param);
2316 if (err)
2317 goto err_free_cq;
2318
2319 if (MLX5_CAP_GEN(mdev, cq_moderation) &&
2320 MLX5_CAP_GEN(mdev, cq_period_mode_modify))
2321 mlx5e_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts,
2322 mlx5e_cq_period_mode(moder.cq_period_mode));
2323 return 0;
2324
2325 err_free_cq:
2326 mlx5e_free_cq(cq);
2327
2328 return err;
2329 }
2330
mlx5e_close_cq(struct mlx5e_cq * cq)2331 void mlx5e_close_cq(struct mlx5e_cq *cq)
2332 {
2333 mlx5e_destroy_cq(cq);
2334 mlx5e_free_cq(cq);
2335 }
2336
mlx5e_modify_cq_period_mode(struct mlx5_core_dev * dev,struct mlx5_core_cq * cq,u8 cq_period_mode)2337 int mlx5e_modify_cq_period_mode(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
2338 u8 cq_period_mode)
2339 {
2340 u32 in[MLX5_ST_SZ_DW(modify_cq_in)] = {};
2341 void *cqc;
2342
2343 MLX5_SET(modify_cq_in, in, cqn, cq->cqn);
2344 cqc = MLX5_ADDR_OF(modify_cq_in, in, cq_context);
2345 MLX5_SET(cqc, cqc, cq_period_mode, mlx5e_cq_period_mode(cq_period_mode));
2346 MLX5_SET(modify_cq_in, in,
2347 modify_field_select_resize_field_select.modify_field_select.modify_field_select,
2348 MLX5_CQ_MODIFY_PERIOD_MODE);
2349
2350 return mlx5_core_modify_cq(dev, cq, in, sizeof(in));
2351 }
2352
mlx5e_modify_cq_moderation(struct mlx5_core_dev * dev,struct mlx5_core_cq * cq,u16 cq_period,u16 cq_max_count,u8 cq_period_mode)2353 int mlx5e_modify_cq_moderation(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
2354 u16 cq_period, u16 cq_max_count, u8 cq_period_mode)
2355 {
2356 u32 in[MLX5_ST_SZ_DW(modify_cq_in)] = {};
2357 void *cqc;
2358
2359 MLX5_SET(modify_cq_in, in, cqn, cq->cqn);
2360 cqc = MLX5_ADDR_OF(modify_cq_in, in, cq_context);
2361 MLX5_SET(cqc, cqc, cq_period, cq_period);
2362 MLX5_SET(cqc, cqc, cq_max_count, cq_max_count);
2363 MLX5_SET(cqc, cqc, cq_period_mode, cq_period_mode);
2364 MLX5_SET(modify_cq_in, in,
2365 modify_field_select_resize_field_select.modify_field_select.modify_field_select,
2366 MLX5_CQ_MODIFY_PERIOD | MLX5_CQ_MODIFY_COUNT | MLX5_CQ_MODIFY_PERIOD_MODE);
2367
2368 return mlx5_core_modify_cq(dev, cq, in, sizeof(in));
2369 }
2370
mlx5e_open_tx_cqs(struct mlx5e_channel * c,struct mlx5e_params * params,struct mlx5e_create_cq_param * ccp,struct mlx5e_channel_param * cparam)2371 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
2372 struct mlx5e_params *params,
2373 struct mlx5e_create_cq_param *ccp,
2374 struct mlx5e_channel_param *cparam)
2375 {
2376 int err;
2377 int tc;
2378
2379 for (tc = 0; tc < c->num_tc; tc++) {
2380 err = mlx5e_open_cq(c->mdev, params->tx_cq_moderation, &cparam->txq_sq.cqp,
2381 ccp, &c->sq[tc].cq);
2382 if (err)
2383 goto err_close_tx_cqs;
2384 }
2385
2386 return 0;
2387
2388 err_close_tx_cqs:
2389 for (tc--; tc >= 0; tc--)
2390 mlx5e_close_cq(&c->sq[tc].cq);
2391
2392 return err;
2393 }
2394
mlx5e_close_tx_cqs(struct mlx5e_channel * c)2395 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
2396 {
2397 int tc;
2398
2399 for (tc = 0; tc < c->num_tc; tc++)
2400 mlx5e_close_cq(&c->sq[tc].cq);
2401 }
2402
mlx5e_mqprio_txq_to_tc(struct netdev_tc_txq * tc_to_txq,unsigned int txq)2403 static int mlx5e_mqprio_txq_to_tc(struct netdev_tc_txq *tc_to_txq, unsigned int txq)
2404 {
2405 int tc;
2406
2407 for (tc = 0; tc < TC_MAX_QUEUE; tc++)
2408 if (txq - tc_to_txq[tc].offset < tc_to_txq[tc].count)
2409 return tc;
2410
2411 WARN(1, "Unexpected TCs configuration. No match found for txq %u", txq);
2412 return -ENOENT;
2413 }
2414
mlx5e_txq_get_qos_node_hw_id(struct mlx5e_params * params,int txq_ix,u32 * hw_id)2415 static int mlx5e_txq_get_qos_node_hw_id(struct mlx5e_params *params, int txq_ix,
2416 u32 *hw_id)
2417 {
2418 int tc;
2419
2420 if (params->mqprio.mode != TC_MQPRIO_MODE_CHANNEL) {
2421 *hw_id = 0;
2422 return 0;
2423 }
2424
2425 tc = mlx5e_mqprio_txq_to_tc(params->mqprio.tc_to_txq, txq_ix);
2426 if (tc < 0)
2427 return tc;
2428
2429 if (tc >= params->mqprio.num_tc) {
2430 WARN(1, "Unexpected TCs configuration. tc %d is out of range of %u",
2431 tc, params->mqprio.num_tc);
2432 return -EINVAL;
2433 }
2434
2435 *hw_id = params->mqprio.channel.hw_id[tc];
2436 return 0;
2437 }
2438
mlx5e_open_sqs(struct mlx5e_channel * c,struct mlx5e_params * params,struct mlx5e_channel_param * cparam)2439 static int mlx5e_open_sqs(struct mlx5e_channel *c,
2440 struct mlx5e_params *params,
2441 struct mlx5e_channel_param *cparam)
2442 {
2443 int err, tc;
2444
2445 for (tc = 0; tc < mlx5e_get_dcb_num_tc(params); tc++) {
2446 int txq_ix = c->ix + tc * params->num_channels;
2447 u32 qos_queue_group_id;
2448 u32 tisn;
2449
2450 tisn = mlx5e_profile_get_tisn(c->mdev, c->priv, c->priv->profile,
2451 c->lag_port, tc);
2452 err = mlx5e_txq_get_qos_node_hw_id(params, txq_ix, &qos_queue_group_id);
2453 if (err)
2454 goto err_close_sqs;
2455
2456 err = mlx5e_open_txqsq(c, tisn, txq_ix,
2457 params, &cparam->txq_sq, &c->sq[tc], tc,
2458 qos_queue_group_id,
2459 &c->priv->channel_stats[c->ix]->sq[tc]);
2460 if (err)
2461 goto err_close_sqs;
2462 }
2463
2464 return 0;
2465
2466 err_close_sqs:
2467 for (tc--; tc >= 0; tc--)
2468 mlx5e_close_txqsq(&c->sq[tc]);
2469
2470 return err;
2471 }
2472
mlx5e_close_sqs(struct mlx5e_channel * c)2473 static void mlx5e_close_sqs(struct mlx5e_channel *c)
2474 {
2475 int tc;
2476
2477 for (tc = 0; tc < c->num_tc; tc++)
2478 mlx5e_close_txqsq(&c->sq[tc]);
2479 }
2480
mlx5e_set_sq_maxrate(struct net_device * dev,struct mlx5e_txqsq * sq,u32 rate)2481 static int mlx5e_set_sq_maxrate(struct net_device *dev,
2482 struct mlx5e_txqsq *sq, u32 rate)
2483 {
2484 struct mlx5e_priv *priv = netdev_priv(dev);
2485 struct mlx5_core_dev *mdev = priv->mdev;
2486 struct mlx5e_modify_sq_param msp = {0};
2487 struct mlx5_rate_limit rl = {0};
2488 u16 rl_index = 0;
2489 int err;
2490
2491 if (rate == sq->rate_limit)
2492 /* nothing to do */
2493 return 0;
2494
2495 if (sq->rate_limit) {
2496 rl.rate = sq->rate_limit;
2497 /* remove current rl index to free space to next ones */
2498 mlx5_rl_remove_rate(mdev, &rl);
2499 }
2500
2501 sq->rate_limit = 0;
2502
2503 if (rate) {
2504 rl.rate = rate;
2505 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
2506 if (err) {
2507 netdev_err(dev, "Failed configuring rate %u: %d\n",
2508 rate, err);
2509 return err;
2510 }
2511 }
2512
2513 msp.curr_state = MLX5_SQC_STATE_RDY;
2514 msp.next_state = MLX5_SQC_STATE_RDY;
2515 msp.rl_index = rl_index;
2516 msp.rl_update = true;
2517 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
2518 if (err) {
2519 netdev_err(dev, "Failed configuring rate %u: %d\n",
2520 rate, err);
2521 /* remove the rate from the table */
2522 if (rate)
2523 mlx5_rl_remove_rate(mdev, &rl);
2524 return err;
2525 }
2526
2527 sq->rate_limit = rate;
2528 return 0;
2529 }
2530
mlx5e_set_tx_maxrate(struct net_device * dev,int index,u32 rate)2531 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
2532 {
2533 struct mlx5e_priv *priv = netdev_priv(dev);
2534 struct mlx5_core_dev *mdev = priv->mdev;
2535 struct mlx5e_txqsq *sq = priv->txq2sq[index];
2536 int err = 0;
2537
2538 if (!mlx5_rl_is_supported(mdev)) {
2539 netdev_err(dev, "Rate limiting is not supported on this device\n");
2540 return -EINVAL;
2541 }
2542
2543 /* rate is given in Mb/sec, HW config is in Kb/sec */
2544 rate = rate << 10;
2545
2546 /* Check whether rate in valid range, 0 is always valid */
2547 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
2548 netdev_err(dev, "TX rate %u, is not in range\n", rate);
2549 return -ERANGE;
2550 }
2551
2552 mutex_lock(&priv->state_lock);
2553 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
2554 err = mlx5e_set_sq_maxrate(dev, sq, rate);
2555 if (!err)
2556 priv->tx_rates[index] = rate;
2557 mutex_unlock(&priv->state_lock);
2558
2559 return err;
2560 }
2561
mlx5e_open_rxq_rq(struct mlx5e_channel * c,struct mlx5e_params * params,struct mlx5e_rq_param * rq_params)2562 static int mlx5e_open_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
2563 struct mlx5e_rq_param *rq_params)
2564 {
2565 u16 q_counter = c->priv->q_counter[c->sd_ix];
2566 int err;
2567
2568 err = mlx5e_init_rxq_rq(c, params, rq_params->xdp_frag_size, &c->rq);
2569 if (err)
2570 return err;
2571
2572 return mlx5e_open_rq(params, rq_params, NULL, cpu_to_node(c->cpu), q_counter, &c->rq);
2573 }
2574
mlx5e_open_queues(struct mlx5e_channel * c,struct mlx5e_params * params,struct mlx5e_channel_param * cparam)2575 static int mlx5e_open_queues(struct mlx5e_channel *c,
2576 struct mlx5e_params *params,
2577 struct mlx5e_channel_param *cparam)
2578 {
2579 const struct net_device_ops *netdev_ops = c->netdev->netdev_ops;
2580 struct dim_cq_moder icocq_moder = {0, 0};
2581 struct mlx5e_create_cq_param ccp;
2582 int err;
2583
2584 mlx5e_build_create_cq_param(&ccp, c);
2585
2586 err = mlx5e_open_cq(c->mdev, icocq_moder, &cparam->async_icosq.cqp, &ccp,
2587 &c->async_icosq.cq);
2588 if (err)
2589 return err;
2590
2591 err = mlx5e_open_cq(c->mdev, icocq_moder, &cparam->icosq.cqp, &ccp,
2592 &c->icosq.cq);
2593 if (err)
2594 goto err_close_async_icosq_cq;
2595
2596 err = mlx5e_open_tx_cqs(c, params, &ccp, cparam);
2597 if (err)
2598 goto err_close_icosq_cq;
2599
2600 if (netdev_ops->ndo_xdp_xmit) {
2601 c->xdpsq = mlx5e_open_xdpredirect_sq(c, params, cparam, &ccp);
2602 if (IS_ERR(c->xdpsq)) {
2603 err = PTR_ERR(c->xdpsq);
2604 goto err_close_tx_cqs;
2605 }
2606 }
2607
2608 err = mlx5e_open_cq(c->mdev, params->rx_cq_moderation, &cparam->rq.cqp, &ccp,
2609 &c->rq.cq);
2610 if (err)
2611 goto err_close_xdpredirect_sq;
2612
2613 err = c->xdp ? mlx5e_open_cq(c->mdev, params->tx_cq_moderation, &cparam->xdp_sq.cqp,
2614 &ccp, &c->rq_xdpsq.cq) : 0;
2615 if (err)
2616 goto err_close_rx_cq;
2617
2618 spin_lock_init(&c->async_icosq_lock);
2619
2620 err = mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq,
2621 mlx5e_async_icosq_err_cqe_work);
2622 if (err)
2623 goto err_close_rq_xdpsq_cq;
2624
2625 mutex_init(&c->icosq_recovery_lock);
2626
2627 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq,
2628 mlx5e_icosq_err_cqe_work);
2629 if (err)
2630 goto err_close_async_icosq;
2631
2632 err = mlx5e_open_sqs(c, params, cparam);
2633 if (err)
2634 goto err_close_icosq;
2635
2636 err = mlx5e_open_rxq_rq(c, params, &cparam->rq);
2637 if (err)
2638 goto err_close_sqs;
2639
2640 if (c->xdp) {
2641 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
2642 &c->rq_xdpsq, false);
2643 if (err)
2644 goto err_close_rq;
2645 }
2646
2647 return 0;
2648
2649 err_close_rq:
2650 mlx5e_close_rq(&c->rq);
2651
2652 err_close_sqs:
2653 mlx5e_close_sqs(c);
2654
2655 err_close_icosq:
2656 mlx5e_close_icosq(&c->icosq);
2657
2658 err_close_async_icosq:
2659 mlx5e_close_icosq(&c->async_icosq);
2660
2661 err_close_rq_xdpsq_cq:
2662 if (c->xdp)
2663 mlx5e_close_cq(&c->rq_xdpsq.cq);
2664
2665 err_close_rx_cq:
2666 mlx5e_close_cq(&c->rq.cq);
2667
2668 err_close_xdpredirect_sq:
2669 if (c->xdpsq)
2670 mlx5e_close_xdpredirect_sq(c->xdpsq);
2671
2672 err_close_tx_cqs:
2673 mlx5e_close_tx_cqs(c);
2674
2675 err_close_icosq_cq:
2676 mlx5e_close_cq(&c->icosq.cq);
2677
2678 err_close_async_icosq_cq:
2679 mlx5e_close_cq(&c->async_icosq.cq);
2680
2681 return err;
2682 }
2683
mlx5e_close_queues(struct mlx5e_channel * c)2684 static void mlx5e_close_queues(struct mlx5e_channel *c)
2685 {
2686 if (c->xdp)
2687 mlx5e_close_xdpsq(&c->rq_xdpsq);
2688 /* The same ICOSQ is used for UMRs for both RQ and XSKRQ. */
2689 cancel_work_sync(&c->icosq.recover_work);
2690 mlx5e_close_rq(&c->rq);
2691 mlx5e_close_sqs(c);
2692 mlx5e_close_icosq(&c->icosq);
2693 mutex_destroy(&c->icosq_recovery_lock);
2694 mlx5e_close_icosq(&c->async_icosq);
2695 if (c->xdp)
2696 mlx5e_close_cq(&c->rq_xdpsq.cq);
2697 mlx5e_close_cq(&c->rq.cq);
2698 if (c->xdpsq)
2699 mlx5e_close_xdpredirect_sq(c->xdpsq);
2700 mlx5e_close_tx_cqs(c);
2701 mlx5e_close_cq(&c->icosq.cq);
2702 mlx5e_close_cq(&c->async_icosq.cq);
2703 }
2704
mlx5e_enumerate_lag_port(struct mlx5_core_dev * mdev,int ix)2705 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
2706 {
2707 u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
2708
2709 return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
2710 }
2711
mlx5e_channel_stats_alloc(struct mlx5e_priv * priv,int ix,int cpu)2712 static int mlx5e_channel_stats_alloc(struct mlx5e_priv *priv, int ix, int cpu)
2713 {
2714 if (ix > priv->stats_nch) {
2715 netdev_warn(priv->netdev, "Unexpected channel stats index %d > %d\n", ix,
2716 priv->stats_nch);
2717 return -EINVAL;
2718 }
2719
2720 if (priv->channel_stats[ix])
2721 return 0;
2722
2723 /* Asymmetric dynamic memory allocation.
2724 * Freed in mlx5e_priv_arrays_free, not on channel closure.
2725 */
2726 netdev_dbg(priv->netdev, "Creating channel stats %d\n", ix);
2727 priv->channel_stats[ix] = kvzalloc_node(sizeof(**priv->channel_stats),
2728 GFP_KERNEL, cpu_to_node(cpu));
2729 if (!priv->channel_stats[ix])
2730 return -ENOMEM;
2731 priv->stats_nch++;
2732
2733 return 0;
2734 }
2735
mlx5e_trigger_napi_icosq(struct mlx5e_channel * c)2736 void mlx5e_trigger_napi_icosq(struct mlx5e_channel *c)
2737 {
2738 spin_lock_bh(&c->async_icosq_lock);
2739 mlx5e_trigger_irq(&c->async_icosq);
2740 spin_unlock_bh(&c->async_icosq_lock);
2741 }
2742
mlx5e_trigger_napi_sched(struct napi_struct * napi)2743 void mlx5e_trigger_napi_sched(struct napi_struct *napi)
2744 {
2745 local_bh_disable();
2746 napi_schedule(napi);
2747 local_bh_enable();
2748 }
2749
mlx5e_open_channel(struct mlx5e_priv * priv,int ix,struct mlx5e_params * params,struct xsk_buff_pool * xsk_pool,struct mlx5e_channel ** cp)2750 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
2751 struct mlx5e_params *params,
2752 struct xsk_buff_pool *xsk_pool,
2753 struct mlx5e_channel **cp)
2754 {
2755 struct net_device *netdev = priv->netdev;
2756 struct mlx5e_channel_param *cparam;
2757 struct mlx5_core_dev *mdev;
2758 struct mlx5e_xsk_param xsk;
2759 struct mlx5e_channel *c;
2760 unsigned int irq;
2761 int vec_ix;
2762 int cpu;
2763 int err;
2764
2765 mdev = mlx5_sd_ch_ix_get_dev(priv->mdev, ix);
2766 vec_ix = mlx5_sd_ch_ix_get_vec_ix(mdev, ix);
2767 cpu = mlx5_comp_vector_get_cpu(mdev, vec_ix);
2768
2769 err = mlx5_comp_irqn_get(mdev, vec_ix, &irq);
2770 if (err)
2771 return err;
2772
2773 err = mlx5e_channel_stats_alloc(priv, ix, cpu);
2774 if (err)
2775 return err;
2776
2777 c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
2778 cparam = kvzalloc(sizeof(*cparam), GFP_KERNEL);
2779 if (!c || !cparam) {
2780 err = -ENOMEM;
2781 goto err_free;
2782 }
2783
2784 err = mlx5e_build_channel_param(mdev, params, cparam);
2785 if (err)
2786 goto err_free;
2787
2788 c->priv = priv;
2789 c->mdev = mdev;
2790 c->tstamp = &priv->tstamp;
2791 c->ix = ix;
2792 c->vec_ix = vec_ix;
2793 c->sd_ix = mlx5_sd_ch_ix_get_dev_ix(mdev, ix);
2794 c->cpu = cpu;
2795 c->pdev = mlx5_core_dma_dev(mdev);
2796 c->netdev = priv->netdev;
2797 c->mkey_be = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey);
2798 c->num_tc = mlx5e_get_dcb_num_tc(params);
2799 c->xdp = !!params->xdp_prog;
2800 c->stats = &priv->channel_stats[ix]->ch;
2801 c->aff_mask = irq_get_effective_affinity_mask(irq);
2802 c->lag_port = mlx5e_enumerate_lag_port(mdev, ix);
2803
2804 netif_napi_add_config_locked(netdev, &c->napi, mlx5e_napi_poll, ix);
2805 netif_napi_set_irq_locked(&c->napi, irq);
2806
2807 err = mlx5e_open_queues(c, params, cparam);
2808 if (unlikely(err))
2809 goto err_napi_del;
2810
2811 if (xsk_pool) {
2812 mlx5e_build_xsk_param(xsk_pool, &xsk);
2813 err = mlx5e_open_xsk(priv, params, &xsk, xsk_pool, c);
2814 if (unlikely(err))
2815 goto err_close_queues;
2816 }
2817
2818 *cp = c;
2819
2820 kvfree(cparam);
2821 return 0;
2822
2823 err_close_queues:
2824 mlx5e_close_queues(c);
2825
2826 err_napi_del:
2827 netif_napi_del_locked(&c->napi);
2828
2829 err_free:
2830 kvfree(cparam);
2831 kvfree(c);
2832
2833 return err;
2834 }
2835
mlx5e_activate_channel(struct mlx5e_channel * c)2836 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2837 {
2838 int tc;
2839
2840 napi_enable_locked(&c->napi);
2841
2842 for (tc = 0; tc < c->num_tc; tc++)
2843 mlx5e_activate_txqsq(&c->sq[tc]);
2844 mlx5e_activate_icosq(&c->icosq);
2845 mlx5e_activate_icosq(&c->async_icosq);
2846
2847 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2848 mlx5e_activate_xsk(c);
2849 else
2850 mlx5e_activate_rq(&c->rq);
2851
2852 netif_queue_set_napi(c->netdev, c->ix, NETDEV_QUEUE_TYPE_RX, &c->napi);
2853 }
2854
mlx5e_deactivate_channel(struct mlx5e_channel * c)2855 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2856 {
2857 int tc;
2858
2859 netif_queue_set_napi(c->netdev, c->ix, NETDEV_QUEUE_TYPE_RX, NULL);
2860
2861 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2862 mlx5e_deactivate_xsk(c);
2863 else
2864 mlx5e_deactivate_rq(&c->rq);
2865
2866 mlx5e_deactivate_icosq(&c->async_icosq);
2867 mlx5e_deactivate_icosq(&c->icosq);
2868 for (tc = 0; tc < c->num_tc; tc++)
2869 mlx5e_deactivate_txqsq(&c->sq[tc]);
2870 mlx5e_qos_deactivate_queues(c);
2871
2872 napi_disable_locked(&c->napi);
2873 }
2874
mlx5e_close_channel(struct mlx5e_channel * c)2875 static void mlx5e_close_channel(struct mlx5e_channel *c)
2876 {
2877 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2878 mlx5e_close_xsk(c);
2879 mlx5e_close_queues(c);
2880 mlx5e_qos_close_queues(c);
2881 netif_napi_del_locked(&c->napi);
2882
2883 kvfree(c);
2884 }
2885
mlx5e_open_channels(struct mlx5e_priv * priv,struct mlx5e_channels * chs)2886 int mlx5e_open_channels(struct mlx5e_priv *priv,
2887 struct mlx5e_channels *chs)
2888 {
2889 int err = -ENOMEM;
2890 int i;
2891
2892 chs->num = chs->params.num_channels;
2893
2894 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2895 if (!chs->c)
2896 goto err_out;
2897
2898 for (i = 0; i < chs->num; i++) {
2899 struct xsk_buff_pool *xsk_pool = NULL;
2900
2901 if (chs->params.xdp_prog)
2902 xsk_pool = mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, i);
2903
2904 err = mlx5e_open_channel(priv, i, &chs->params, xsk_pool, &chs->c[i]);
2905 if (err)
2906 goto err_close_channels;
2907 }
2908
2909 if (MLX5E_GET_PFLAG(&chs->params, MLX5E_PFLAG_TX_PORT_TS) || chs->params.ptp_rx) {
2910 err = mlx5e_ptp_open(priv, &chs->params, chs->c[0]->lag_port, &chs->ptp);
2911 if (err)
2912 goto err_close_channels;
2913 }
2914
2915 if (priv->htb) {
2916 err = mlx5e_qos_open_queues(priv, chs);
2917 if (err)
2918 goto err_close_ptp;
2919 }
2920
2921 mlx5e_health_channels_update(priv);
2922 return 0;
2923
2924 err_close_ptp:
2925 if (chs->ptp)
2926 mlx5e_ptp_close(chs->ptp);
2927
2928 err_close_channels:
2929 for (i--; i >= 0; i--)
2930 mlx5e_close_channel(chs->c[i]);
2931
2932 kfree(chs->c);
2933 err_out:
2934 chs->num = 0;
2935 return err;
2936 }
2937
mlx5e_activate_channels(struct mlx5e_priv * priv,struct mlx5e_channels * chs)2938 static void mlx5e_activate_channels(struct mlx5e_priv *priv, struct mlx5e_channels *chs)
2939 {
2940 int i;
2941
2942 for (i = 0; i < chs->num; i++)
2943 mlx5e_activate_channel(chs->c[i]);
2944
2945 if (priv->htb)
2946 mlx5e_qos_activate_queues(priv);
2947
2948 for (i = 0; i < chs->num; i++)
2949 mlx5e_trigger_napi_icosq(chs->c[i]);
2950
2951 if (chs->ptp)
2952 mlx5e_ptp_activate_channel(chs->ptp);
2953 }
2954
mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels * chs)2955 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2956 {
2957 int err = 0;
2958 int i;
2959
2960 for (i = 0; i < chs->num; i++) {
2961 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2962 struct mlx5e_channel *c = chs->c[i];
2963
2964 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2965 continue;
2966
2967 err |= mlx5e_wait_for_min_rx_wqes(&c->rq, timeout);
2968
2969 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2970 * doesn't provide any Fill Ring entries at the setup stage.
2971 */
2972 }
2973
2974 return err ? -ETIMEDOUT : 0;
2975 }
2976
mlx5e_deactivate_channels(struct mlx5e_channels * chs)2977 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2978 {
2979 int i;
2980
2981 if (chs->ptp)
2982 mlx5e_ptp_deactivate_channel(chs->ptp);
2983
2984 for (i = 0; i < chs->num; i++)
2985 mlx5e_deactivate_channel(chs->c[i]);
2986 }
2987
mlx5e_close_channels(struct mlx5e_channels * chs)2988 void mlx5e_close_channels(struct mlx5e_channels *chs)
2989 {
2990 int i;
2991
2992 ASSERT_RTNL();
2993 if (chs->ptp) {
2994 mlx5e_ptp_close(chs->ptp);
2995 chs->ptp = NULL;
2996 }
2997 for (i = 0; i < chs->num; i++)
2998 mlx5e_close_channel(chs->c[i]);
2999
3000 kfree(chs->c);
3001 chs->num = 0;
3002 }
3003
mlx5e_modify_tirs_packet_merge(struct mlx5e_priv * priv)3004 static int mlx5e_modify_tirs_packet_merge(struct mlx5e_priv *priv)
3005 {
3006 struct mlx5e_rx_res *res = priv->rx_res;
3007
3008 return mlx5e_rx_res_packet_merge_set_param(res, &priv->channels.params.packet_merge);
3009 }
3010
3011 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_modify_tirs_packet_merge);
3012
mlx5e_set_mtu(struct mlx5_core_dev * mdev,struct mlx5e_params * params,u16 mtu)3013 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
3014 struct mlx5e_params *params, u16 mtu)
3015 {
3016 u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
3017 int err;
3018
3019 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
3020 if (err)
3021 return err;
3022
3023 /* Update vport context MTU */
3024 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
3025 return 0;
3026 }
3027
mlx5e_query_mtu(struct mlx5_core_dev * mdev,struct mlx5e_params * params,u16 * mtu)3028 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
3029 struct mlx5e_params *params, u16 *mtu)
3030 {
3031 u16 hw_mtu = 0;
3032 int err;
3033
3034 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
3035 if (err || !hw_mtu) /* fallback to port oper mtu */
3036 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
3037
3038 *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
3039 }
3040
mlx5e_set_dev_port_mtu(struct mlx5e_priv * priv)3041 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
3042 {
3043 struct mlx5e_params *params = &priv->channels.params;
3044 struct net_device *netdev = priv->netdev;
3045 struct mlx5_core_dev *mdev = priv->mdev;
3046 u16 mtu, prev_mtu;
3047 int err;
3048
3049 mlx5e_query_mtu(mdev, params, &prev_mtu);
3050
3051 err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
3052 if (err)
3053 return err;
3054
3055 mlx5e_query_mtu(mdev, params, &mtu);
3056 if (mtu != params->sw_mtu)
3057 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
3058 __func__, mtu, params->sw_mtu);
3059
3060 if (mtu != prev_mtu && MLX5_BUFFER_SUPPORTED(mdev)) {
3061 err = mlx5e_port_manual_buffer_config(priv, 0, mtu,
3062 NULL, NULL, NULL);
3063 if (err) {
3064 netdev_warn(netdev, "%s: Failed to set Xon/Xoff values with MTU %d (err %d), setting back to previous MTU %d\n",
3065 __func__, mtu, err, prev_mtu);
3066
3067 mlx5e_set_mtu(mdev, params, prev_mtu);
3068 return err;
3069 }
3070 }
3071
3072 params->sw_mtu = mtu;
3073 return 0;
3074 }
3075
3076 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_set_dev_port_mtu);
3077
mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv * priv)3078 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
3079 {
3080 struct mlx5e_params *params = &priv->channels.params;
3081 struct net_device *netdev = priv->netdev;
3082 struct mlx5_core_dev *mdev = priv->mdev;
3083 u16 max_mtu;
3084
3085 /* MTU range: 68 - hw-specific max */
3086 netdev->min_mtu = ETH_MIN_MTU;
3087
3088 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
3089 netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
3090 ETH_MAX_MTU);
3091 }
3092
mlx5e_netdev_set_tcs(struct net_device * netdev,u16 nch,u8 ntc,struct netdev_tc_txq * tc_to_txq)3093 static int mlx5e_netdev_set_tcs(struct net_device *netdev, u16 nch, u8 ntc,
3094 struct netdev_tc_txq *tc_to_txq)
3095 {
3096 int tc, err;
3097
3098 netdev_reset_tc(netdev);
3099
3100 if (ntc == 1)
3101 return 0;
3102
3103 err = netdev_set_num_tc(netdev, ntc);
3104 if (err) {
3105 netdev_WARN(netdev, "netdev_set_num_tc failed (%d), ntc = %d\n", err, ntc);
3106 return err;
3107 }
3108
3109 for (tc = 0; tc < ntc; tc++) {
3110 u16 count, offset;
3111
3112 count = tc_to_txq[tc].count;
3113 offset = tc_to_txq[tc].offset;
3114 netdev_set_tc_queue(netdev, tc, count, offset);
3115 }
3116
3117 return 0;
3118 }
3119
mlx5e_update_tx_netdev_queues(struct mlx5e_priv * priv)3120 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv)
3121 {
3122 int nch, ntc, num_txqs, err;
3123 int qos_queues = 0;
3124
3125 if (priv->htb)
3126 qos_queues = mlx5e_htb_cur_leaf_nodes(priv->htb);
3127
3128 nch = priv->channels.params.num_channels;
3129 ntc = mlx5e_get_dcb_num_tc(&priv->channels.params);
3130 num_txqs = nch * ntc + qos_queues;
3131 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_TX_PORT_TS))
3132 num_txqs += ntc;
3133
3134 netdev_dbg(priv->netdev, "Setting num_txqs %d\n", num_txqs);
3135 err = netif_set_real_num_tx_queues(priv->netdev, num_txqs);
3136 if (err)
3137 netdev_warn(priv->netdev, "netif_set_real_num_tx_queues failed, %d\n", err);
3138
3139 return err;
3140 }
3141
mlx5e_set_default_xps_cpumasks(struct mlx5e_priv * priv,struct mlx5e_params * params)3142 static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv,
3143 struct mlx5e_params *params)
3144 {
3145 int ix;
3146
3147 for (ix = 0; ix < params->num_channels; ix++) {
3148 int num_comp_vectors, irq, vec_ix;
3149 struct mlx5_core_dev *mdev;
3150
3151 mdev = mlx5_sd_ch_ix_get_dev(priv->mdev, ix);
3152 num_comp_vectors = mlx5_comp_vectors_max(mdev);
3153 cpumask_clear(priv->scratchpad.cpumask);
3154 vec_ix = mlx5_sd_ch_ix_get_vec_ix(mdev, ix);
3155
3156 for (irq = vec_ix; irq < num_comp_vectors; irq += params->num_channels) {
3157 int cpu = mlx5_comp_vector_get_cpu(mdev, irq);
3158
3159 cpumask_set_cpu(cpu, priv->scratchpad.cpumask);
3160 }
3161
3162 netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix);
3163 }
3164 }
3165
mlx5e_update_tc_and_tx_queues(struct mlx5e_priv * priv)3166 static int mlx5e_update_tc_and_tx_queues(struct mlx5e_priv *priv)
3167 {
3168 struct netdev_tc_txq old_tc_to_txq[TC_MAX_QUEUE], *tc_to_txq;
3169 struct net_device *netdev = priv->netdev;
3170 int old_num_txqs, old_ntc;
3171 int nch, ntc;
3172 int err;
3173 int i;
3174
3175 old_num_txqs = netdev->real_num_tx_queues;
3176 old_ntc = netdev->num_tc ? : 1;
3177 for (i = 0; i < ARRAY_SIZE(old_tc_to_txq); i++)
3178 old_tc_to_txq[i] = netdev->tc_to_txq[i];
3179
3180 nch = priv->channels.params.num_channels;
3181 ntc = priv->channels.params.mqprio.num_tc;
3182 tc_to_txq = priv->channels.params.mqprio.tc_to_txq;
3183
3184 err = mlx5e_netdev_set_tcs(netdev, nch, ntc, tc_to_txq);
3185 if (err)
3186 goto err_out;
3187 err = mlx5e_update_tx_netdev_queues(priv);
3188 if (err)
3189 goto err_tcs;
3190 mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params);
3191
3192 return 0;
3193
3194 err_tcs:
3195 WARN_ON_ONCE(mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc,
3196 old_tc_to_txq));
3197 err_out:
3198 return err;
3199 }
3200
3201 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_update_tc_and_tx_queues);
3202
mlx5e_num_channels_changed(struct mlx5e_priv * priv)3203 static int mlx5e_num_channels_changed(struct mlx5e_priv *priv)
3204 {
3205 u16 count = priv->channels.params.num_channels;
3206 struct net_device *netdev = priv->netdev;
3207 int old_num_rxqs;
3208 int err;
3209
3210 old_num_rxqs = netdev->real_num_rx_queues;
3211 err = netif_set_real_num_rx_queues(netdev, count);
3212 if (err) {
3213 netdev_warn(netdev, "%s: netif_set_real_num_rx_queues failed, %d\n",
3214 __func__, err);
3215 return err;
3216 }
3217 err = mlx5e_update_tc_and_tx_queues(priv);
3218 if (err) {
3219 /* mlx5e_update_tc_and_tx_queues can fail if channels or TCs number increases.
3220 * Since channel number changed, it increased. That means, the call to
3221 * netif_set_real_num_rx_queues below should not fail, because it
3222 * decreases the number of RX queues.
3223 */
3224 WARN_ON_ONCE(netif_set_real_num_rx_queues(netdev, old_num_rxqs));
3225 return err;
3226 }
3227
3228 /* This function may be called on attach, before priv->rx_res is created. */
3229 if (priv->rx_res) {
3230 mlx5e_rx_res_rss_update_num_channels(priv->rx_res, count);
3231
3232 if (!netif_is_rxfh_configured(priv->netdev))
3233 mlx5e_rx_res_rss_set_indir_uniform(priv->rx_res, count);
3234 }
3235
3236 return 0;
3237 }
3238
3239 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_num_channels_changed);
3240
mlx5e_build_txq_maps(struct mlx5e_priv * priv)3241 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv)
3242 {
3243 int i, ch, tc, num_tc;
3244
3245 ch = priv->channels.num;
3246 num_tc = mlx5e_get_dcb_num_tc(&priv->channels.params);
3247
3248 for (i = 0; i < ch; i++) {
3249 for (tc = 0; tc < num_tc; tc++) {
3250 struct mlx5e_channel *c = priv->channels.c[i];
3251 struct mlx5e_txqsq *sq = &c->sq[tc];
3252
3253 priv->txq2sq[sq->txq_ix] = sq;
3254 priv->txq2sq_stats[sq->txq_ix] = sq->stats;
3255 }
3256 }
3257
3258 if (!priv->channels.ptp)
3259 goto out;
3260
3261 if (!test_bit(MLX5E_PTP_STATE_TX, priv->channels.ptp->state))
3262 goto out;
3263
3264 for (tc = 0; tc < num_tc; tc++) {
3265 struct mlx5e_ptp *c = priv->channels.ptp;
3266 struct mlx5e_txqsq *sq = &c->ptpsq[tc].txqsq;
3267
3268 priv->txq2sq[sq->txq_ix] = sq;
3269 priv->txq2sq_stats[sq->txq_ix] = sq->stats;
3270 }
3271
3272 out:
3273 /* Make the change to txq2sq visible before the queue is started.
3274 * As mlx5e_xmit runs under a spinlock, there is an implicit ACQUIRE,
3275 * which pairs with this barrier.
3276 */
3277 smp_wmb();
3278 }
3279
mlx5e_activate_priv_channels(struct mlx5e_priv * priv)3280 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
3281 {
3282 mlx5e_build_txq_maps(priv);
3283 mlx5e_activate_channels(priv, &priv->channels);
3284 mlx5e_xdp_tx_enable(priv);
3285
3286 /* dev_watchdog() wants all TX queues to be started when the carrier is
3287 * OK, including the ones in range real_num_tx_queues..num_tx_queues-1.
3288 * Make it happy to avoid TX timeout false alarms.
3289 */
3290 netif_tx_start_all_queues(priv->netdev);
3291
3292 if (mlx5e_is_vport_rep(priv))
3293 mlx5e_rep_activate_channels(priv);
3294
3295 set_bit(MLX5E_STATE_CHANNELS_ACTIVE, &priv->state);
3296
3297 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
3298
3299 if (priv->rx_res)
3300 mlx5e_rx_res_channels_activate(priv->rx_res, &priv->channels);
3301 }
3302
mlx5e_cancel_tx_timeout_work(struct mlx5e_priv * priv)3303 static void mlx5e_cancel_tx_timeout_work(struct mlx5e_priv *priv)
3304 {
3305 WARN_ON_ONCE(test_bit(MLX5E_STATE_CHANNELS_ACTIVE, &priv->state));
3306 if (current_work() != &priv->tx_timeout_work)
3307 cancel_work_sync(&priv->tx_timeout_work);
3308 }
3309
mlx5e_deactivate_priv_channels(struct mlx5e_priv * priv)3310 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
3311 {
3312 if (priv->rx_res)
3313 mlx5e_rx_res_channels_deactivate(priv->rx_res);
3314
3315 clear_bit(MLX5E_STATE_CHANNELS_ACTIVE, &priv->state);
3316 mlx5e_cancel_tx_timeout_work(priv);
3317
3318 if (mlx5e_is_vport_rep(priv))
3319 mlx5e_rep_deactivate_channels(priv);
3320
3321 /* The results of ndo_select_queue are unreliable, while netdev config
3322 * is being changed (real_num_tx_queues, num_tc). Stop all queues to
3323 * prevent ndo_start_xmit from being called, so that it can assume that
3324 * the selected queue is always valid.
3325 */
3326 netif_tx_disable(priv->netdev);
3327
3328 mlx5e_xdp_tx_disable(priv);
3329 mlx5e_deactivate_channels(&priv->channels);
3330 }
3331
mlx5e_switch_priv_params(struct mlx5e_priv * priv,struct mlx5e_params * new_params,mlx5e_fp_preactivate preactivate,void * context)3332 static int mlx5e_switch_priv_params(struct mlx5e_priv *priv,
3333 struct mlx5e_params *new_params,
3334 mlx5e_fp_preactivate preactivate,
3335 void *context)
3336 {
3337 struct mlx5e_params old_params;
3338
3339 old_params = priv->channels.params;
3340 priv->channels.params = *new_params;
3341
3342 if (preactivate) {
3343 int err;
3344
3345 err = preactivate(priv, context);
3346 if (err) {
3347 priv->channels.params = old_params;
3348 return err;
3349 }
3350 }
3351
3352 return 0;
3353 }
3354
mlx5e_switch_priv_channels(struct mlx5e_priv * priv,struct mlx5e_channels * new_chs,mlx5e_fp_preactivate preactivate,void * context)3355 static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
3356 struct mlx5e_channels *new_chs,
3357 mlx5e_fp_preactivate preactivate,
3358 void *context)
3359 {
3360 struct net_device *netdev = priv->netdev;
3361 struct mlx5e_channels old_chs;
3362 int carrier_ok;
3363 int err = 0;
3364
3365 carrier_ok = netif_carrier_ok(netdev);
3366 netif_carrier_off(netdev);
3367
3368 mlx5e_deactivate_priv_channels(priv);
3369
3370 old_chs = priv->channels;
3371 priv->channels = *new_chs;
3372
3373 /* New channels are ready to roll, call the preactivate hook if needed
3374 * to modify HW settings or update kernel parameters.
3375 */
3376 if (preactivate) {
3377 err = preactivate(priv, context);
3378 if (err) {
3379 priv->channels = old_chs;
3380 goto out;
3381 }
3382 }
3383
3384 mlx5e_close_channels(&old_chs);
3385 priv->profile->update_rx(priv);
3386
3387 mlx5e_selq_apply(&priv->selq);
3388 out:
3389 mlx5e_activate_priv_channels(priv);
3390
3391 /* return carrier back if needed */
3392 if (carrier_ok)
3393 netif_carrier_on(netdev);
3394
3395 return err;
3396 }
3397
mlx5e_safe_switch_params(struct mlx5e_priv * priv,struct mlx5e_params * params,mlx5e_fp_preactivate preactivate,void * context,bool reset)3398 int mlx5e_safe_switch_params(struct mlx5e_priv *priv,
3399 struct mlx5e_params *params,
3400 mlx5e_fp_preactivate preactivate,
3401 void *context, bool reset)
3402 {
3403 struct mlx5e_channels *new_chs;
3404 int err;
3405
3406 reset &= test_bit(MLX5E_STATE_OPENED, &priv->state);
3407 if (!reset)
3408 return mlx5e_switch_priv_params(priv, params, preactivate, context);
3409
3410 new_chs = kzalloc(sizeof(*new_chs), GFP_KERNEL);
3411 if (!new_chs)
3412 return -ENOMEM;
3413 new_chs->params = *params;
3414
3415 mlx5e_selq_prepare_params(&priv->selq, &new_chs->params);
3416
3417 err = mlx5e_open_channels(priv, new_chs);
3418 if (err)
3419 goto err_cancel_selq;
3420
3421 err = mlx5e_switch_priv_channels(priv, new_chs, preactivate, context);
3422 if (err)
3423 goto err_close;
3424
3425 kfree(new_chs);
3426 return 0;
3427
3428 err_close:
3429 mlx5e_close_channels(new_chs);
3430
3431 err_cancel_selq:
3432 mlx5e_selq_cancel(&priv->selq);
3433 kfree(new_chs);
3434 return err;
3435 }
3436
mlx5e_safe_reopen_channels(struct mlx5e_priv * priv)3437 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
3438 {
3439 return mlx5e_safe_switch_params(priv, &priv->channels.params, NULL, NULL, true);
3440 }
3441
mlx5e_timestamp_init(struct mlx5e_priv * priv)3442 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
3443 {
3444 priv->tstamp.tx_type = HWTSTAMP_TX_OFF;
3445 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
3446 }
3447
mlx5e_modify_admin_state(struct mlx5_core_dev * mdev,enum mlx5_port_status state)3448 static void mlx5e_modify_admin_state(struct mlx5_core_dev *mdev,
3449 enum mlx5_port_status state)
3450 {
3451 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3452 int vport_admin_state;
3453
3454 mlx5_set_port_admin_status(mdev, state);
3455
3456 if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS ||
3457 !MLX5_CAP_GEN(mdev, uplink_follow))
3458 return;
3459
3460 if (state == MLX5_PORT_UP)
3461 vport_admin_state = MLX5_VPORT_ADMIN_STATE_AUTO;
3462 else
3463 vport_admin_state = MLX5_VPORT_ADMIN_STATE_DOWN;
3464
3465 mlx5_eswitch_set_vport_state(esw, MLX5_VPORT_UPLINK, vport_admin_state);
3466 }
3467
mlx5e_open_locked(struct net_device * netdev)3468 int mlx5e_open_locked(struct net_device *netdev)
3469 {
3470 struct mlx5e_priv *priv = netdev_priv(netdev);
3471 int err;
3472
3473 mlx5e_selq_prepare_params(&priv->selq, &priv->channels.params);
3474
3475 set_bit(MLX5E_STATE_OPENED, &priv->state);
3476
3477 err = mlx5e_open_channels(priv, &priv->channels);
3478 if (err)
3479 goto err_clear_state_opened_flag;
3480
3481 err = priv->profile->update_rx(priv);
3482 if (err)
3483 goto err_close_channels;
3484
3485 mlx5e_selq_apply(&priv->selq);
3486 mlx5e_activate_priv_channels(priv);
3487 mlx5e_apply_traps(priv, true);
3488 if (priv->profile->update_carrier)
3489 priv->profile->update_carrier(priv);
3490
3491 mlx5e_queue_update_stats(priv);
3492 return 0;
3493
3494 err_close_channels:
3495 mlx5e_close_channels(&priv->channels);
3496 err_clear_state_opened_flag:
3497 clear_bit(MLX5E_STATE_OPENED, &priv->state);
3498 mlx5e_selq_cancel(&priv->selq);
3499 return err;
3500 }
3501
mlx5e_open(struct net_device * netdev)3502 int mlx5e_open(struct net_device *netdev)
3503 {
3504 struct mlx5e_priv *priv = netdev_priv(netdev);
3505 int err;
3506
3507 mutex_lock(&priv->state_lock);
3508 err = mlx5e_open_locked(netdev);
3509 if (!err)
3510 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_UP);
3511 mutex_unlock(&priv->state_lock);
3512
3513 return err;
3514 }
3515
mlx5e_close_locked(struct net_device * netdev)3516 int mlx5e_close_locked(struct net_device *netdev)
3517 {
3518 struct mlx5e_priv *priv = netdev_priv(netdev);
3519
3520 /* May already be CLOSED in case a previous configuration operation
3521 * (e.g RX/TX queue size change) that involves close&open failed.
3522 */
3523 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3524 return 0;
3525
3526 mlx5e_apply_traps(priv, false);
3527 clear_bit(MLX5E_STATE_OPENED, &priv->state);
3528
3529 netif_carrier_off(priv->netdev);
3530 mlx5e_deactivate_priv_channels(priv);
3531 mlx5e_close_channels(&priv->channels);
3532
3533 return 0;
3534 }
3535
mlx5e_close(struct net_device * netdev)3536 int mlx5e_close(struct net_device *netdev)
3537 {
3538 struct mlx5e_priv *priv = netdev_priv(netdev);
3539 int err;
3540
3541 if (!netif_device_present(netdev))
3542 return -ENODEV;
3543
3544 mutex_lock(&priv->state_lock);
3545 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_DOWN);
3546 err = mlx5e_close_locked(netdev);
3547 mutex_unlock(&priv->state_lock);
3548
3549 return err;
3550 }
3551
mlx5e_free_drop_rq(struct mlx5e_rq * rq)3552 static void mlx5e_free_drop_rq(struct mlx5e_rq *rq)
3553 {
3554 mlx5_wq_destroy(&rq->wq_ctrl);
3555 }
3556
mlx5e_alloc_drop_rq(struct mlx5_core_dev * mdev,struct mlx5e_rq * rq,struct mlx5e_rq_param * param)3557 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3558 struct mlx5e_rq *rq,
3559 struct mlx5e_rq_param *param)
3560 {
3561 void *rqc = param->rqc;
3562 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3563 int err;
3564
3565 param->wq.db_numa_node = param->wq.buf_numa_node;
3566
3567 err = mlx5_wq_cyc_create(mdev, ¶m->wq, rqc_wq, &rq->wqe.wq,
3568 &rq->wq_ctrl);
3569 if (err)
3570 return err;
3571
3572 /* Mark as unused given "Drop-RQ" packets never reach XDP */
3573 xdp_rxq_info_unused(&rq->xdp_rxq);
3574
3575 rq->mdev = mdev;
3576
3577 return 0;
3578 }
3579
mlx5e_alloc_drop_cq(struct mlx5e_priv * priv,struct mlx5e_cq * cq,struct mlx5e_cq_param * param)3580 static int mlx5e_alloc_drop_cq(struct mlx5e_priv *priv,
3581 struct mlx5e_cq *cq,
3582 struct mlx5e_cq_param *param)
3583 {
3584 struct mlx5_core_dev *mdev = priv->mdev;
3585
3586 param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
3587 param->wq.db_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
3588
3589 return mlx5e_alloc_cq_common(priv->mdev, priv->netdev, priv->wq, param, cq);
3590 }
3591
mlx5e_open_drop_rq(struct mlx5e_priv * priv,struct mlx5e_rq * drop_rq)3592 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3593 struct mlx5e_rq *drop_rq)
3594 {
3595 struct mlx5_core_dev *mdev = priv->mdev;
3596 struct mlx5e_cq_param cq_param = {};
3597 struct mlx5e_rq_param rq_param = {};
3598 struct mlx5e_cq *cq = &drop_rq->cq;
3599 int err;
3600
3601 mlx5e_build_drop_rq_param(mdev, &rq_param);
3602
3603 err = mlx5e_alloc_drop_cq(priv, cq, &cq_param);
3604 if (err)
3605 return err;
3606
3607 err = mlx5e_create_cq(cq, &cq_param);
3608 if (err)
3609 goto err_free_cq;
3610
3611 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3612 if (err)
3613 goto err_destroy_cq;
3614
3615 err = mlx5e_create_rq(drop_rq, &rq_param, priv->drop_rq_q_counter);
3616 if (err)
3617 goto err_free_rq;
3618
3619 err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3620 if (err)
3621 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3622
3623 return 0;
3624
3625 err_free_rq:
3626 mlx5e_free_drop_rq(drop_rq);
3627
3628 err_destroy_cq:
3629 mlx5e_destroy_cq(cq);
3630
3631 err_free_cq:
3632 mlx5e_free_cq(cq);
3633
3634 return err;
3635 }
3636
mlx5e_close_drop_rq(struct mlx5e_rq * drop_rq)3637 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3638 {
3639 mlx5e_destroy_rq(drop_rq);
3640 mlx5e_free_drop_rq(drop_rq);
3641 mlx5e_destroy_cq(&drop_rq->cq);
3642 mlx5e_free_cq(&drop_rq->cq);
3643 }
3644
mlx5e_cleanup_nic_tx(struct mlx5e_priv * priv)3645 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3646 {
3647 if (priv->mqprio_rl) {
3648 mlx5e_mqprio_rl_cleanup(priv->mqprio_rl);
3649 mlx5e_mqprio_rl_free(priv->mqprio_rl);
3650 priv->mqprio_rl = NULL;
3651 }
3652 mlx5e_accel_cleanup_tx(priv);
3653 }
3654
mlx5e_modify_channels_vsd(struct mlx5e_channels * chs,bool vsd)3655 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3656 {
3657 int err;
3658 int i;
3659
3660 for (i = 0; i < chs->num; i++) {
3661 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3662 if (err)
3663 return err;
3664 }
3665 if (chs->ptp && test_bit(MLX5E_PTP_STATE_RX, chs->ptp->state))
3666 return mlx5e_modify_rq_vsd(&chs->ptp->rq, vsd);
3667
3668 return 0;
3669 }
3670
mlx5e_mqprio_build_default_tc_to_txq(struct netdev_tc_txq * tc_to_txq,int ntc,int nch)3671 static void mlx5e_mqprio_build_default_tc_to_txq(struct netdev_tc_txq *tc_to_txq,
3672 int ntc, int nch)
3673 {
3674 int tc;
3675
3676 memset(tc_to_txq, 0, sizeof(*tc_to_txq) * TC_MAX_QUEUE);
3677
3678 /* Map netdev TCs to offset 0.
3679 * We have our own UP to TXQ mapping for DCB mode of QoS
3680 */
3681 for (tc = 0; tc < ntc; tc++) {
3682 tc_to_txq[tc] = (struct netdev_tc_txq) {
3683 .count = nch,
3684 .offset = 0,
3685 };
3686 }
3687 }
3688
mlx5e_mqprio_build_tc_to_txq(struct netdev_tc_txq * tc_to_txq,struct tc_mqprio_qopt * qopt)3689 static void mlx5e_mqprio_build_tc_to_txq(struct netdev_tc_txq *tc_to_txq,
3690 struct tc_mqprio_qopt *qopt)
3691 {
3692 int tc;
3693
3694 for (tc = 0; tc < TC_MAX_QUEUE; tc++) {
3695 tc_to_txq[tc] = (struct netdev_tc_txq) {
3696 .count = qopt->count[tc],
3697 .offset = qopt->offset[tc],
3698 };
3699 }
3700 }
3701
mlx5e_params_mqprio_dcb_set(struct mlx5e_params * params,u8 num_tc)3702 static void mlx5e_params_mqprio_dcb_set(struct mlx5e_params *params, u8 num_tc)
3703 {
3704 params->mqprio.mode = TC_MQPRIO_MODE_DCB;
3705 params->mqprio.num_tc = num_tc;
3706 mlx5e_mqprio_build_default_tc_to_txq(params->mqprio.tc_to_txq, num_tc,
3707 params->num_channels);
3708 }
3709
mlx5e_mqprio_rl_update_params(struct mlx5e_params * params,struct mlx5e_mqprio_rl * rl)3710 static void mlx5e_mqprio_rl_update_params(struct mlx5e_params *params,
3711 struct mlx5e_mqprio_rl *rl)
3712 {
3713 int tc;
3714
3715 for (tc = 0; tc < TC_MAX_QUEUE; tc++) {
3716 u32 hw_id = 0;
3717
3718 if (rl)
3719 mlx5e_mqprio_rl_get_node_hw_id(rl, tc, &hw_id);
3720 params->mqprio.channel.hw_id[tc] = hw_id;
3721 }
3722 }
3723
mlx5e_params_mqprio_channel_set(struct mlx5e_params * params,struct tc_mqprio_qopt_offload * mqprio,struct mlx5e_mqprio_rl * rl)3724 static void mlx5e_params_mqprio_channel_set(struct mlx5e_params *params,
3725 struct tc_mqprio_qopt_offload *mqprio,
3726 struct mlx5e_mqprio_rl *rl)
3727 {
3728 int tc;
3729
3730 params->mqprio.mode = TC_MQPRIO_MODE_CHANNEL;
3731 params->mqprio.num_tc = mqprio->qopt.num_tc;
3732
3733 for (tc = 0; tc < TC_MAX_QUEUE; tc++)
3734 params->mqprio.channel.max_rate[tc] = mqprio->max_rate[tc];
3735
3736 mlx5e_mqprio_rl_update_params(params, rl);
3737 mlx5e_mqprio_build_tc_to_txq(params->mqprio.tc_to_txq, &mqprio->qopt);
3738 }
3739
mlx5e_params_mqprio_reset(struct mlx5e_params * params)3740 static void mlx5e_params_mqprio_reset(struct mlx5e_params *params)
3741 {
3742 mlx5e_params_mqprio_dcb_set(params, 1);
3743 }
3744
mlx5e_setup_tc_mqprio_dcb(struct mlx5e_priv * priv,struct tc_mqprio_qopt * mqprio)3745 static int mlx5e_setup_tc_mqprio_dcb(struct mlx5e_priv *priv,
3746 struct tc_mqprio_qopt *mqprio)
3747 {
3748 struct mlx5e_params new_params;
3749 u8 tc = mqprio->num_tc;
3750 int err;
3751
3752 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3753
3754 if (tc && tc != MLX5_MAX_NUM_TC)
3755 return -EINVAL;
3756
3757 new_params = priv->channels.params;
3758 mlx5e_params_mqprio_dcb_set(&new_params, tc ? tc : 1);
3759
3760 err = mlx5e_safe_switch_params(priv, &new_params,
3761 mlx5e_update_tc_and_tx_queues_ctx, NULL, true);
3762
3763 if (!err && priv->mqprio_rl) {
3764 mlx5e_mqprio_rl_cleanup(priv->mqprio_rl);
3765 mlx5e_mqprio_rl_free(priv->mqprio_rl);
3766 priv->mqprio_rl = NULL;
3767 }
3768
3769 priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3770 mlx5e_get_dcb_num_tc(&priv->channels.params));
3771 return err;
3772 }
3773
mlx5e_mqprio_channel_validate(struct mlx5e_priv * priv,struct tc_mqprio_qopt_offload * mqprio)3774 static int mlx5e_mqprio_channel_validate(struct mlx5e_priv *priv,
3775 struct tc_mqprio_qopt_offload *mqprio)
3776 {
3777 struct net_device *netdev = priv->netdev;
3778 struct mlx5e_ptp *ptp_channel;
3779 int agg_count = 0;
3780 int i;
3781
3782 ptp_channel = priv->channels.ptp;
3783 if (ptp_channel && test_bit(MLX5E_PTP_STATE_TX, ptp_channel->state)) {
3784 netdev_err(netdev,
3785 "Cannot activate MQPRIO mode channel since it conflicts with TX port TS\n");
3786 return -EINVAL;
3787 }
3788
3789 if (mqprio->qopt.offset[0] != 0 || mqprio->qopt.num_tc < 1 ||
3790 mqprio->qopt.num_tc > MLX5E_MAX_NUM_MQPRIO_CH_TC)
3791 return -EINVAL;
3792
3793 for (i = 0; i < mqprio->qopt.num_tc; i++) {
3794 if (!mqprio->qopt.count[i]) {
3795 netdev_err(netdev, "Zero size for queue-group (%d) is not supported\n", i);
3796 return -EINVAL;
3797 }
3798 if (mqprio->min_rate[i]) {
3799 netdev_err(netdev, "Min tx rate is not supported\n");
3800 return -EINVAL;
3801 }
3802
3803 if (mqprio->max_rate[i]) {
3804 int err;
3805
3806 err = mlx5e_qos_bytes_rate_check(priv->mdev, mqprio->max_rate[i]);
3807 if (err)
3808 return err;
3809 }
3810
3811 if (mqprio->qopt.offset[i] != agg_count) {
3812 netdev_err(netdev, "Discontinuous queues config is not supported\n");
3813 return -EINVAL;
3814 }
3815 agg_count += mqprio->qopt.count[i];
3816 }
3817
3818 if (priv->channels.params.num_channels != agg_count) {
3819 netdev_err(netdev, "Num of queues (%d) does not match available (%d)\n",
3820 agg_count, priv->channels.params.num_channels);
3821 return -EINVAL;
3822 }
3823
3824 return 0;
3825 }
3826
mlx5e_mqprio_rate_limit(u8 num_tc,u64 max_rate[])3827 static bool mlx5e_mqprio_rate_limit(u8 num_tc, u64 max_rate[])
3828 {
3829 int tc;
3830
3831 for (tc = 0; tc < num_tc; tc++)
3832 if (max_rate[tc])
3833 return true;
3834 return false;
3835 }
3836
mlx5e_mqprio_rl_create(struct mlx5_core_dev * mdev,u8 num_tc,u64 max_rate[])3837 static struct mlx5e_mqprio_rl *mlx5e_mqprio_rl_create(struct mlx5_core_dev *mdev,
3838 u8 num_tc, u64 max_rate[])
3839 {
3840 struct mlx5e_mqprio_rl *rl;
3841 int err;
3842
3843 if (!mlx5e_mqprio_rate_limit(num_tc, max_rate))
3844 return NULL;
3845
3846 rl = mlx5e_mqprio_rl_alloc();
3847 if (!rl)
3848 return ERR_PTR(-ENOMEM);
3849
3850 err = mlx5e_mqprio_rl_init(rl, mdev, num_tc, max_rate);
3851 if (err) {
3852 mlx5e_mqprio_rl_free(rl);
3853 return ERR_PTR(err);
3854 }
3855
3856 return rl;
3857 }
3858
mlx5e_setup_tc_mqprio_channel(struct mlx5e_priv * priv,struct tc_mqprio_qopt_offload * mqprio)3859 static int mlx5e_setup_tc_mqprio_channel(struct mlx5e_priv *priv,
3860 struct tc_mqprio_qopt_offload *mqprio)
3861 {
3862 struct mlx5e_params new_params;
3863 struct mlx5e_mqprio_rl *rl;
3864 int err;
3865
3866 err = mlx5e_mqprio_channel_validate(priv, mqprio);
3867 if (err)
3868 return err;
3869
3870 rl = mlx5e_mqprio_rl_create(priv->mdev, mqprio->qopt.num_tc, mqprio->max_rate);
3871 if (IS_ERR(rl))
3872 return PTR_ERR(rl);
3873
3874 new_params = priv->channels.params;
3875 mlx5e_params_mqprio_channel_set(&new_params, mqprio, rl);
3876
3877 err = mlx5e_safe_switch_params(priv, &new_params,
3878 mlx5e_update_tc_and_tx_queues_ctx, NULL, true);
3879 if (err) {
3880 if (rl) {
3881 mlx5e_mqprio_rl_cleanup(rl);
3882 mlx5e_mqprio_rl_free(rl);
3883 }
3884 return err;
3885 }
3886
3887 if (priv->mqprio_rl) {
3888 mlx5e_mqprio_rl_cleanup(priv->mqprio_rl);
3889 mlx5e_mqprio_rl_free(priv->mqprio_rl);
3890 }
3891 priv->mqprio_rl = rl;
3892
3893 return 0;
3894 }
3895
mlx5e_setup_tc_mqprio(struct mlx5e_priv * priv,struct tc_mqprio_qopt_offload * mqprio)3896 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3897 struct tc_mqprio_qopt_offload *mqprio)
3898 {
3899 /* MQPRIO is another toplevel qdisc that can't be attached
3900 * simultaneously with the offloaded HTB.
3901 */
3902 if (mlx5e_selq_is_htb_enabled(&priv->selq)) {
3903 NL_SET_ERR_MSG_MOD(mqprio->extack,
3904 "MQPRIO cannot be configured when HTB offload is enabled.");
3905 return -EOPNOTSUPP;
3906 }
3907
3908 switch (mqprio->mode) {
3909 case TC_MQPRIO_MODE_DCB:
3910 return mlx5e_setup_tc_mqprio_dcb(priv, &mqprio->qopt);
3911 case TC_MQPRIO_MODE_CHANNEL:
3912 return mlx5e_setup_tc_mqprio_channel(priv, mqprio);
3913 default:
3914 return -EOPNOTSUPP;
3915 }
3916 }
3917
3918 static LIST_HEAD(mlx5e_block_cb_list);
3919
mlx5e_setup_tc(struct net_device * dev,enum tc_setup_type type,void * type_data)3920 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3921 void *type_data)
3922 {
3923 struct mlx5e_priv *priv = netdev_priv(dev);
3924 bool tc_unbind = false;
3925 int err;
3926
3927 if (type == TC_SETUP_BLOCK &&
3928 ((struct flow_block_offload *)type_data)->command == FLOW_BLOCK_UNBIND)
3929 tc_unbind = true;
3930
3931 if (!netif_device_present(dev) && !tc_unbind)
3932 return -ENODEV;
3933
3934 switch (type) {
3935 case TC_SETUP_BLOCK: {
3936 struct flow_block_offload *f = type_data;
3937
3938 f->unlocked_driver_cb = true;
3939 return flow_block_cb_setup_simple(type_data,
3940 &mlx5e_block_cb_list,
3941 mlx5e_setup_tc_block_cb,
3942 priv, priv, true);
3943 }
3944 case TC_SETUP_QDISC_MQPRIO:
3945 mutex_lock(&priv->state_lock);
3946 err = mlx5e_setup_tc_mqprio(priv, type_data);
3947 mutex_unlock(&priv->state_lock);
3948 return err;
3949 case TC_SETUP_QDISC_HTB:
3950 mutex_lock(&priv->state_lock);
3951 err = mlx5e_htb_setup_tc(priv, type_data);
3952 mutex_unlock(&priv->state_lock);
3953 return err;
3954 default:
3955 return -EOPNOTSUPP;
3956 }
3957 }
3958
mlx5e_fold_sw_stats64(struct mlx5e_priv * priv,struct rtnl_link_stats64 * s)3959 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3960 {
3961 int i;
3962
3963 for (i = 0; i < priv->stats_nch; i++) {
3964 struct mlx5e_channel_stats *channel_stats = priv->channel_stats[i];
3965 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3966 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3967 int j;
3968
3969 s->rx_packets += rq_stats->packets + xskrq_stats->packets;
3970 s->rx_bytes += rq_stats->bytes + xskrq_stats->bytes;
3971 s->multicast += rq_stats->mcast_packets + xskrq_stats->mcast_packets;
3972
3973 for (j = 0; j < priv->max_opened_tc; j++) {
3974 struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3975
3976 s->tx_packets += sq_stats->packets;
3977 s->tx_bytes += sq_stats->bytes;
3978 s->tx_dropped += sq_stats->dropped;
3979 }
3980 }
3981 if (priv->tx_ptp_opened) {
3982 for (i = 0; i < priv->max_opened_tc; i++) {
3983 struct mlx5e_sq_stats *sq_stats = &priv->ptp_stats.sq[i];
3984
3985 s->tx_packets += sq_stats->packets;
3986 s->tx_bytes += sq_stats->bytes;
3987 s->tx_dropped += sq_stats->dropped;
3988 }
3989 }
3990 if (priv->rx_ptp_opened) {
3991 struct mlx5e_rq_stats *rq_stats = &priv->ptp_stats.rq;
3992
3993 s->rx_packets += rq_stats->packets;
3994 s->rx_bytes += rq_stats->bytes;
3995 s->multicast += rq_stats->mcast_packets;
3996 }
3997 }
3998
3999 void
mlx5e_get_stats(struct net_device * dev,struct rtnl_link_stats64 * stats)4000 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
4001 {
4002 struct mlx5e_priv *priv = netdev_priv(dev);
4003 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
4004
4005 if (!netif_device_present(dev))
4006 return;
4007
4008 /* In switchdev mode, monitor counters doesn't monitor
4009 * rx/tx stats of 802_3. The update stats mechanism
4010 * should keep the 802_3 layout counters updated
4011 */
4012 if (!mlx5e_monitor_counter_supported(priv) ||
4013 mlx5e_is_uplink_rep(priv)) {
4014 /* update HW stats in background for next time */
4015 mlx5e_queue_update_stats(priv);
4016 }
4017
4018 if (mlx5e_is_uplink_rep(priv)) {
4019 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
4020
4021 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
4022 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
4023 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
4024 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
4025
4026 /* vport multicast also counts packets that are dropped due to steering
4027 * or rx out of buffer
4028 */
4029 stats->multicast = VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
4030 } else {
4031 mlx5e_fold_sw_stats64(priv, stats);
4032 }
4033
4034 stats->rx_missed_errors = priv->stats.qcnt.rx_out_of_buffer;
4035 stats->rx_dropped = PPORT_2863_GET(pstats, if_in_discards);
4036
4037 stats->rx_length_errors =
4038 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
4039 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
4040 PPORT_802_3_GET(pstats, a_frame_too_long_errors) +
4041 VNIC_ENV_GET(&priv->stats.vnic, eth_wqe_too_small);
4042 stats->rx_crc_errors =
4043 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
4044 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
4045 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
4046 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
4047 stats->rx_frame_errors;
4048 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
4049 }
4050
mlx5e_nic_set_rx_mode(struct mlx5e_priv * priv)4051 static void mlx5e_nic_set_rx_mode(struct mlx5e_priv *priv)
4052 {
4053 if (mlx5e_is_uplink_rep(priv))
4054 return; /* no rx mode for uplink rep */
4055
4056 queue_work(priv->wq, &priv->set_rx_mode_work);
4057 }
4058
mlx5e_set_rx_mode(struct net_device * dev)4059 static void mlx5e_set_rx_mode(struct net_device *dev)
4060 {
4061 struct mlx5e_priv *priv = netdev_priv(dev);
4062
4063 mlx5e_nic_set_rx_mode(priv);
4064 }
4065
mlx5e_set_mac(struct net_device * netdev,void * addr)4066 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
4067 {
4068 struct mlx5e_priv *priv = netdev_priv(netdev);
4069 struct sockaddr *saddr = addr;
4070
4071 if (!is_valid_ether_addr(saddr->sa_data))
4072 return -EADDRNOTAVAIL;
4073
4074 netif_addr_lock_bh(netdev);
4075 eth_hw_addr_set(netdev, saddr->sa_data);
4076 netif_addr_unlock_bh(netdev);
4077
4078 mlx5e_nic_set_rx_mode(priv);
4079
4080 return 0;
4081 }
4082
4083 #define MLX5E_SET_FEATURE(features, feature, enable) \
4084 do { \
4085 if (enable) \
4086 *features |= feature; \
4087 else \
4088 *features &= ~feature; \
4089 } while (0)
4090
4091 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
4092
set_feature_lro(struct net_device * netdev,bool enable)4093 static int set_feature_lro(struct net_device *netdev, bool enable)
4094 {
4095 struct mlx5e_priv *priv = netdev_priv(netdev);
4096 struct mlx5_core_dev *mdev = priv->mdev;
4097 struct mlx5e_params *cur_params;
4098 struct mlx5e_params new_params;
4099 bool reset = true;
4100 int err = 0;
4101
4102 mutex_lock(&priv->state_lock);
4103
4104 cur_params = &priv->channels.params;
4105 new_params = *cur_params;
4106
4107 if (enable)
4108 new_params.packet_merge.type = MLX5E_PACKET_MERGE_LRO;
4109 else if (new_params.packet_merge.type == MLX5E_PACKET_MERGE_LRO)
4110 new_params.packet_merge.type = MLX5E_PACKET_MERGE_NONE;
4111 else
4112 goto out;
4113
4114 if (!(cur_params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO &&
4115 new_params.packet_merge.type == MLX5E_PACKET_MERGE_LRO)) {
4116 if (cur_params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4117 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, cur_params, NULL) ==
4118 mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_params, NULL))
4119 reset = false;
4120 }
4121 }
4122
4123 err = mlx5e_safe_switch_params(priv, &new_params,
4124 mlx5e_modify_tirs_packet_merge_ctx, NULL, reset);
4125 out:
4126 mutex_unlock(&priv->state_lock);
4127 return err;
4128 }
4129
set_feature_hw_gro(struct net_device * netdev,bool enable)4130 static int set_feature_hw_gro(struct net_device *netdev, bool enable)
4131 {
4132 struct mlx5e_priv *priv = netdev_priv(netdev);
4133 struct mlx5e_params new_params;
4134 bool reset = true;
4135 int err = 0;
4136
4137 mutex_lock(&priv->state_lock);
4138 new_params = priv->channels.params;
4139
4140 if (enable) {
4141 new_params.packet_merge.type = MLX5E_PACKET_MERGE_SHAMPO;
4142 } else if (new_params.packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) {
4143 new_params.packet_merge.type = MLX5E_PACKET_MERGE_NONE;
4144 } else {
4145 goto out;
4146 }
4147
4148 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
4149 out:
4150 mutex_unlock(&priv->state_lock);
4151 return err;
4152 }
4153
set_feature_cvlan_filter(struct net_device * netdev,bool enable)4154 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
4155 {
4156 struct mlx5e_priv *priv = netdev_priv(netdev);
4157
4158 if (enable)
4159 mlx5e_enable_cvlan_filter(priv->fs,
4160 !!(priv->netdev->flags & IFF_PROMISC));
4161 else
4162 mlx5e_disable_cvlan_filter(priv->fs,
4163 !!(priv->netdev->flags & IFF_PROMISC));
4164
4165 return 0;
4166 }
4167
set_feature_hw_tc(struct net_device * netdev,bool enable)4168 static int set_feature_hw_tc(struct net_device *netdev, bool enable)
4169 {
4170 struct mlx5e_priv *priv = netdev_priv(netdev);
4171 int err = 0;
4172
4173 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
4174 int tc_flag = mlx5e_is_uplink_rep(priv) ? MLX5_TC_FLAG(ESW_OFFLOAD) :
4175 MLX5_TC_FLAG(NIC_OFFLOAD);
4176 if (!enable && mlx5e_tc_num_filters(priv, tc_flag)) {
4177 netdev_err(netdev,
4178 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
4179 return -EINVAL;
4180 }
4181 #endif
4182
4183 mutex_lock(&priv->state_lock);
4184 if (!enable && mlx5e_selq_is_htb_enabled(&priv->selq)) {
4185 netdev_err(netdev, "Active HTB offload, can't turn hw_tc_offload off\n");
4186 err = -EINVAL;
4187 }
4188 mutex_unlock(&priv->state_lock);
4189
4190 return err;
4191 }
4192
set_feature_rx_all(struct net_device * netdev,bool enable)4193 static int set_feature_rx_all(struct net_device *netdev, bool enable)
4194 {
4195 struct mlx5e_priv *priv = netdev_priv(netdev);
4196 struct mlx5_core_dev *mdev = priv->mdev;
4197
4198 return mlx5_set_port_fcs(mdev, !enable);
4199 }
4200
mlx5e_get_def_rx_moderation(u8 cq_period_mode)4201 static struct dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4202 {
4203 return (struct dim_cq_moder) {
4204 .cq_period_mode = cq_period_mode,
4205 .pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS,
4206 .usec = cq_period_mode == DIM_CQ_PERIOD_MODE_START_FROM_CQE ?
4207 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
4208 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC,
4209 };
4210 }
4211
mlx5e_reset_rx_moderation(struct dim_cq_moder * cq_moder,u8 cq_period_mode,bool dim_enabled)4212 bool mlx5e_reset_rx_moderation(struct dim_cq_moder *cq_moder, u8 cq_period_mode,
4213 bool dim_enabled)
4214 {
4215 bool reset_needed = cq_moder->cq_period_mode != cq_period_mode;
4216
4217 if (dim_enabled)
4218 *cq_moder = net_dim_get_def_rx_moderation(cq_period_mode);
4219 else
4220 *cq_moder = mlx5e_get_def_rx_moderation(cq_period_mode);
4221
4222 return reset_needed;
4223 }
4224
mlx5e_reset_rx_channels_moderation(struct mlx5e_channels * chs,u8 cq_period_mode,bool dim_enabled,bool keep_dim_state)4225 bool mlx5e_reset_rx_channels_moderation(struct mlx5e_channels *chs, u8 cq_period_mode,
4226 bool dim_enabled, bool keep_dim_state)
4227 {
4228 bool reset = false;
4229 int i;
4230
4231 for (i = 0; i < chs->num; i++) {
4232 if (keep_dim_state)
4233 dim_enabled = !!chs->c[i]->rq.dim;
4234
4235 reset |= mlx5e_reset_rx_moderation(&chs->c[i]->rx_cq_moder,
4236 cq_period_mode, dim_enabled);
4237 }
4238
4239 return reset;
4240 }
4241
mlx5e_set_rx_port_ts(struct mlx5_core_dev * mdev,bool enable)4242 static int mlx5e_set_rx_port_ts(struct mlx5_core_dev *mdev, bool enable)
4243 {
4244 u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {};
4245 bool supported, curr_state;
4246 int err;
4247
4248 if (!MLX5_CAP_GEN(mdev, ports_check))
4249 return 0;
4250
4251 err = mlx5_query_ports_check(mdev, in, sizeof(in));
4252 if (err)
4253 return err;
4254
4255 supported = MLX5_GET(pcmr_reg, in, rx_ts_over_crc_cap);
4256 curr_state = MLX5_GET(pcmr_reg, in, rx_ts_over_crc);
4257
4258 if (!supported || enable == curr_state)
4259 return 0;
4260
4261 MLX5_SET(pcmr_reg, in, local_port, 1);
4262 MLX5_SET(pcmr_reg, in, rx_ts_over_crc, enable);
4263
4264 return mlx5_set_ports_check(mdev, in, sizeof(in));
4265 }
4266
mlx5e_set_rx_port_ts_wrap(struct mlx5e_priv * priv,void * ctx)4267 static int mlx5e_set_rx_port_ts_wrap(struct mlx5e_priv *priv, void *ctx)
4268 {
4269 struct mlx5_core_dev *mdev = priv->mdev;
4270 bool enable = *(bool *)ctx;
4271
4272 return mlx5e_set_rx_port_ts(mdev, enable);
4273 }
4274
set_feature_rx_fcs(struct net_device * netdev,bool enable)4275 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
4276 {
4277 struct mlx5e_priv *priv = netdev_priv(netdev);
4278 struct mlx5e_channels *chs = &priv->channels;
4279 struct mlx5e_params new_params;
4280 int err;
4281 bool rx_ts_over_crc = !enable;
4282
4283 mutex_lock(&priv->state_lock);
4284
4285 new_params = chs->params;
4286 new_params.scatter_fcs_en = enable;
4287 err = mlx5e_safe_switch_params(priv, &new_params, mlx5e_set_rx_port_ts_wrap,
4288 &rx_ts_over_crc, true);
4289 mutex_unlock(&priv->state_lock);
4290 return err;
4291 }
4292
set_feature_rx_vlan(struct net_device * netdev,bool enable)4293 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
4294 {
4295 struct mlx5e_priv *priv = netdev_priv(netdev);
4296 int err = 0;
4297
4298 mutex_lock(&priv->state_lock);
4299
4300 mlx5e_fs_set_vlan_strip_disable(priv->fs, !enable);
4301 priv->channels.params.vlan_strip_disable = !enable;
4302
4303 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4304 goto unlock;
4305
4306 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
4307 if (err) {
4308 mlx5e_fs_set_vlan_strip_disable(priv->fs, enable);
4309 priv->channels.params.vlan_strip_disable = enable;
4310 }
4311 unlock:
4312 mutex_unlock(&priv->state_lock);
4313
4314 return err;
4315 }
4316
mlx5e_vlan_rx_add_vid(struct net_device * dev,__be16 proto,u16 vid)4317 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
4318 {
4319 struct mlx5e_priv *priv = netdev_priv(dev);
4320 struct mlx5e_flow_steering *fs = priv->fs;
4321
4322 if (mlx5e_is_uplink_rep(priv))
4323 return 0; /* no vlan table for uplink rep */
4324
4325 return mlx5e_fs_vlan_rx_add_vid(fs, dev, proto, vid);
4326 }
4327
mlx5e_vlan_rx_kill_vid(struct net_device * dev,__be16 proto,u16 vid)4328 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
4329 {
4330 struct mlx5e_priv *priv = netdev_priv(dev);
4331 struct mlx5e_flow_steering *fs = priv->fs;
4332
4333 if (mlx5e_is_uplink_rep(priv))
4334 return 0; /* no vlan table for uplink rep */
4335
4336 return mlx5e_fs_vlan_rx_kill_vid(fs, dev, proto, vid);
4337 }
4338
4339 #ifdef CONFIG_MLX5_EN_ARFS
set_feature_arfs(struct net_device * netdev,bool enable)4340 static int set_feature_arfs(struct net_device *netdev, bool enable)
4341 {
4342 struct mlx5e_priv *priv = netdev_priv(netdev);
4343 int err;
4344
4345 if (enable)
4346 err = mlx5e_arfs_enable(priv->fs);
4347 else
4348 err = mlx5e_arfs_disable(priv->fs);
4349
4350 return err;
4351 }
4352 #endif
4353
mlx5e_handle_feature(struct net_device * netdev,netdev_features_t * features,netdev_features_t feature,mlx5e_feature_handler feature_handler)4354 static int mlx5e_handle_feature(struct net_device *netdev,
4355 netdev_features_t *features,
4356 netdev_features_t feature,
4357 mlx5e_feature_handler feature_handler)
4358 {
4359 netdev_features_t changes = *features ^ netdev->features;
4360 bool enable = !!(*features & feature);
4361 int err;
4362
4363 if (!(changes & feature))
4364 return 0;
4365
4366 err = feature_handler(netdev, enable);
4367 if (err) {
4368 MLX5E_SET_FEATURE(features, feature, !enable);
4369 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
4370 enable ? "Enable" : "Disable", &feature, err);
4371 return err;
4372 }
4373
4374 return 0;
4375 }
4376
mlx5e_set_xdp_feature(struct net_device * netdev)4377 void mlx5e_set_xdp_feature(struct net_device *netdev)
4378 {
4379 struct mlx5e_priv *priv = netdev_priv(netdev);
4380 struct mlx5e_params *params = &priv->channels.params;
4381 xdp_features_t val;
4382
4383 if (!netdev->netdev_ops->ndo_bpf ||
4384 params->packet_merge.type != MLX5E_PACKET_MERGE_NONE) {
4385 xdp_set_features_flag_locked(netdev, 0);
4386 return;
4387 }
4388
4389 val = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT |
4390 NETDEV_XDP_ACT_XSK_ZEROCOPY |
4391 NETDEV_XDP_ACT_RX_SG |
4392 NETDEV_XDP_ACT_NDO_XMIT |
4393 NETDEV_XDP_ACT_NDO_XMIT_SG;
4394 xdp_set_features_flag_locked(netdev, val);
4395 }
4396
mlx5e_set_features(struct net_device * netdev,netdev_features_t features)4397 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
4398 {
4399 netdev_features_t oper_features = features;
4400 int err = 0;
4401
4402 #define MLX5E_HANDLE_FEATURE(feature, handler) \
4403 mlx5e_handle_feature(netdev, &oper_features, feature, handler)
4404
4405 if (features & (NETIF_F_GRO_HW | NETIF_F_LRO)) {
4406 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
4407 err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
4408 err |= MLX5E_HANDLE_FEATURE(NETIF_F_GRO_HW, set_feature_hw_gro);
4409 } else {
4410 err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
4411 err |= MLX5E_HANDLE_FEATURE(NETIF_F_GRO_HW, set_feature_hw_gro);
4412 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
4413 }
4414 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
4415 set_feature_cvlan_filter);
4416 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_hw_tc);
4417 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
4418 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
4419 #ifdef CONFIG_MLX5_EN_ARFS
4420 err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
4421 #endif
4422 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TLS_RX, mlx5e_ktls_set_feature_rx);
4423
4424 if (err) {
4425 netdev->features = oper_features;
4426 return -EINVAL;
4427 }
4428
4429 /* update XDP supported features */
4430 mlx5e_set_xdp_feature(netdev);
4431
4432 return 0;
4433 }
4434
mlx5e_fix_uplink_rep_features(struct net_device * netdev,netdev_features_t features)4435 static netdev_features_t mlx5e_fix_uplink_rep_features(struct net_device *netdev,
4436 netdev_features_t features)
4437 {
4438 features &= ~NETIF_F_HW_TLS_RX;
4439 if (netdev->features & NETIF_F_HW_TLS_RX)
4440 netdev_warn(netdev, "Disabling hw_tls_rx, not supported in switchdev mode\n");
4441
4442 features &= ~NETIF_F_HW_TLS_TX;
4443 if (netdev->features & NETIF_F_HW_TLS_TX)
4444 netdev_warn(netdev, "Disabling hw_tls_tx, not supported in switchdev mode\n");
4445
4446 features &= ~NETIF_F_NTUPLE;
4447 if (netdev->features & NETIF_F_NTUPLE)
4448 netdev_warn(netdev, "Disabling ntuple, not supported in switchdev mode\n");
4449
4450 features &= ~NETIF_F_GRO_HW;
4451 if (netdev->features & NETIF_F_GRO_HW)
4452 netdev_warn(netdev, "Disabling HW_GRO, not supported in switchdev mode\n");
4453
4454 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4455 if (netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
4456 netdev_warn(netdev, "Disabling HW_VLAN CTAG FILTERING, not supported in switchdev mode\n");
4457
4458 features &= ~NETIF_F_HW_MACSEC;
4459 if (netdev->features & NETIF_F_HW_MACSEC)
4460 netdev_warn(netdev, "Disabling HW MACsec offload, not supported in switchdev mode\n");
4461
4462 return features;
4463 }
4464
mlx5e_fix_features(struct net_device * netdev,netdev_features_t features)4465 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
4466 netdev_features_t features)
4467 {
4468 struct netdev_config *cfg = netdev->cfg_pending;
4469 struct mlx5e_priv *priv = netdev_priv(netdev);
4470 struct mlx5e_vlan_table *vlan;
4471 struct mlx5e_params *params;
4472
4473 if (!netif_device_present(netdev))
4474 return features;
4475
4476 vlan = mlx5e_fs_get_vlan(priv->fs);
4477 mutex_lock(&priv->state_lock);
4478 params = &priv->channels.params;
4479 if (!vlan ||
4480 !bitmap_empty(mlx5e_vlan_get_active_svlans(vlan), VLAN_N_VID)) {
4481 /* HW strips the outer C-tag header, this is a problem
4482 * for S-tag traffic.
4483 */
4484 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
4485 if (!params->vlan_strip_disable)
4486 netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
4487 }
4488
4489 if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
4490 if (features & NETIF_F_LRO) {
4491 netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
4492 features &= ~NETIF_F_LRO;
4493 }
4494 if (features & NETIF_F_GRO_HW) {
4495 netdev_warn(netdev, "Disabling HW-GRO, not supported in legacy RQ\n");
4496 features &= ~NETIF_F_GRO_HW;
4497 }
4498 }
4499
4500 if (params->xdp_prog) {
4501 if (features & NETIF_F_LRO) {
4502 netdev_warn(netdev, "LRO is incompatible with XDP\n");
4503 features &= ~NETIF_F_LRO;
4504 }
4505 if (features & NETIF_F_GRO_HW) {
4506 netdev_warn(netdev, "HW GRO is incompatible with XDP\n");
4507 features &= ~NETIF_F_GRO_HW;
4508 }
4509 }
4510
4511 if (priv->xsk.refcnt) {
4512 if (features & NETIF_F_LRO) {
4513 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%u XSKs are active)\n",
4514 priv->xsk.refcnt);
4515 features &= ~NETIF_F_LRO;
4516 }
4517 if (features & NETIF_F_GRO_HW) {
4518 netdev_warn(netdev, "HW GRO is incompatible with AF_XDP (%u XSKs are active)\n",
4519 priv->xsk.refcnt);
4520 features &= ~NETIF_F_GRO_HW;
4521 }
4522 }
4523
4524 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
4525 features &= ~NETIF_F_RXHASH;
4526 if (netdev->features & NETIF_F_RXHASH)
4527 netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
4528
4529 if (features & NETIF_F_GRO_HW) {
4530 netdev_warn(netdev, "Disabling HW-GRO, not supported when CQE compress is active\n");
4531 features &= ~NETIF_F_GRO_HW;
4532 }
4533 }
4534
4535 /* The header-data split ring param requires HW GRO to stay enabled. */
4536 if (cfg && cfg->hds_config == ETHTOOL_TCP_DATA_SPLIT_ENABLED &&
4537 !(features & NETIF_F_GRO_HW)) {
4538 netdev_warn(netdev, "Keeping HW-GRO enabled, TCP header-data split depends on it\n");
4539 features |= NETIF_F_GRO_HW;
4540 }
4541
4542 if (mlx5e_is_uplink_rep(priv)) {
4543 features = mlx5e_fix_uplink_rep_features(netdev, features);
4544 netdev->netns_immutable = true;
4545 } else {
4546 netdev->netns_immutable = false;
4547 }
4548
4549 mutex_unlock(&priv->state_lock);
4550
4551 return features;
4552 }
4553
mlx5e_xsk_validate_mtu(struct net_device * netdev,struct mlx5e_channels * chs,struct mlx5e_params * new_params,struct mlx5_core_dev * mdev)4554 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
4555 struct mlx5e_channels *chs,
4556 struct mlx5e_params *new_params,
4557 struct mlx5_core_dev *mdev)
4558 {
4559 u16 ix;
4560
4561 for (ix = 0; ix < chs->params.num_channels; ix++) {
4562 struct xsk_buff_pool *xsk_pool =
4563 mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, ix);
4564 struct mlx5e_xsk_param xsk;
4565 int max_xdp_mtu;
4566
4567 if (!xsk_pool)
4568 continue;
4569
4570 mlx5e_build_xsk_param(xsk_pool, &xsk);
4571 max_xdp_mtu = mlx5e_xdp_max_mtu(new_params, &xsk);
4572
4573 /* Validate XSK params and XDP MTU in advance */
4574 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev) ||
4575 new_params->sw_mtu > max_xdp_mtu) {
4576 u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
4577 int max_mtu_frame, max_mtu_page, max_mtu;
4578
4579 /* Two criteria must be met:
4580 * 1. HW MTU + all headrooms <= XSK frame size.
4581 * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
4582 */
4583 max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
4584 max_mtu_page = MLX5E_HW2SW_MTU(new_params, SKB_MAX_HEAD(0));
4585 max_mtu = min3(max_mtu_frame, max_mtu_page, max_xdp_mtu);
4586
4587 netdev_err(netdev, "MTU %d is too big for an XSK running on channel %u or its redirection XDP program. Try MTU <= %d\n",
4588 new_params->sw_mtu, ix, max_mtu);
4589 return false;
4590 }
4591 }
4592
4593 return true;
4594 }
4595
mlx5e_params_validate_xdp(struct net_device * netdev,struct mlx5_core_dev * mdev,struct mlx5e_params * params)4596 static bool mlx5e_params_validate_xdp(struct net_device *netdev,
4597 struct mlx5_core_dev *mdev,
4598 struct mlx5e_params *params)
4599 {
4600 bool is_linear;
4601
4602 /* No XSK params: AF_XDP can't be enabled yet at the point of setting
4603 * the XDP program.
4604 */
4605 is_linear = params->rq_wq_type == MLX5_WQ_TYPE_CYCLIC ?
4606 mlx5e_rx_is_linear_skb(mdev, params, NULL) :
4607 mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL);
4608
4609 if (!is_linear) {
4610 if (!params->xdp_prog->aux->xdp_has_frags) {
4611 netdev_warn(netdev, "MTU(%d) > %d, too big for an XDP program not aware of multi buffer\n",
4612 params->sw_mtu,
4613 mlx5e_xdp_max_mtu(params, NULL));
4614 return false;
4615 }
4616 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
4617 !mlx5e_verify_params_rx_mpwqe_strides(mdev, params, NULL)) {
4618 netdev_warn(netdev, "XDP is not allowed with striding RQ and MTU(%d) > %d\n",
4619 params->sw_mtu,
4620 mlx5e_xdp_max_mtu(params, NULL));
4621 return false;
4622 }
4623 }
4624
4625 return true;
4626 }
4627
mlx5e_change_mtu(struct net_device * netdev,int new_mtu,mlx5e_fp_preactivate preactivate)4628 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
4629 mlx5e_fp_preactivate preactivate)
4630 {
4631 struct mlx5e_priv *priv = netdev_priv(netdev);
4632 struct mlx5e_params new_params;
4633 struct mlx5e_params *params;
4634 bool reset = true;
4635 int err = 0;
4636
4637 mutex_lock(&priv->state_lock);
4638
4639 params = &priv->channels.params;
4640
4641 new_params = *params;
4642 new_params.sw_mtu = new_mtu;
4643 err = mlx5e_validate_params(priv->mdev, &new_params);
4644 if (err)
4645 goto out;
4646
4647 if (new_params.xdp_prog && !mlx5e_params_validate_xdp(netdev, priv->mdev,
4648 &new_params)) {
4649 err = -EINVAL;
4650 goto out;
4651 }
4652
4653 if (priv->xsk.refcnt &&
4654 !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
4655 &new_params, priv->mdev)) {
4656 err = -EINVAL;
4657 goto out;
4658 }
4659
4660 if (params->packet_merge.type == MLX5E_PACKET_MERGE_LRO)
4661 reset = false;
4662
4663 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
4664 params->packet_merge.type != MLX5E_PACKET_MERGE_SHAMPO) {
4665 bool is_linear_old = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, params, NULL);
4666 bool is_linear_new = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
4667 &new_params, NULL);
4668 u8 sz_old = mlx5e_mpwqe_get_log_rq_size(priv->mdev, params, NULL);
4669 u8 sz_new = mlx5e_mpwqe_get_log_rq_size(priv->mdev, &new_params, NULL);
4670
4671 /* Always reset in linear mode - hw_mtu is used in data path.
4672 * Check that the mode was non-linear and didn't change.
4673 * If XSK is active, XSK RQs are linear.
4674 * Reset if the RQ size changed, even if it's non-linear.
4675 */
4676 if (!is_linear_old && !is_linear_new && !priv->xsk.refcnt &&
4677 sz_old == sz_new)
4678 reset = false;
4679 }
4680
4681 err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, reset);
4682
4683 out:
4684 WRITE_ONCE(netdev->mtu, params->sw_mtu);
4685 mutex_unlock(&priv->state_lock);
4686
4687 if (!err)
4688 netdev_update_features(netdev);
4689
4690 return err;
4691 }
4692
mlx5e_change_nic_mtu(struct net_device * netdev,int new_mtu)4693 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
4694 {
4695 return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu_ctx);
4696 }
4697
mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv * priv,void * ctx)4698 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx)
4699 {
4700 bool set = *(bool *)ctx;
4701
4702 return mlx5e_ptp_rx_manage_fs(priv, set);
4703 }
4704
mlx5e_hwstamp_config_no_ptp_rx(struct mlx5e_priv * priv,bool rx_filter)4705 static int mlx5e_hwstamp_config_no_ptp_rx(struct mlx5e_priv *priv, bool rx_filter)
4706 {
4707 bool rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
4708 int err;
4709
4710 if (!rx_filter)
4711 /* Reset CQE compression to Admin default */
4712 return mlx5e_modify_rx_cqe_compression_locked(priv, rx_cqe_compress_def, false);
4713
4714 if (!MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4715 return 0;
4716
4717 /* Disable CQE compression */
4718 netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
4719 err = mlx5e_modify_rx_cqe_compression_locked(priv, false, true);
4720 if (err)
4721 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
4722
4723 return err;
4724 }
4725
mlx5e_hwstamp_config_ptp_rx(struct mlx5e_priv * priv,bool ptp_rx)4726 static int mlx5e_hwstamp_config_ptp_rx(struct mlx5e_priv *priv, bool ptp_rx)
4727 {
4728 struct mlx5e_params new_params;
4729
4730 if (ptp_rx == priv->channels.params.ptp_rx)
4731 return 0;
4732
4733 new_params = priv->channels.params;
4734 new_params.ptp_rx = ptp_rx;
4735 return mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx,
4736 &new_params.ptp_rx, true);
4737 }
4738
mlx5e_hwstamp_set(struct mlx5e_priv * priv,struct ifreq * ifr)4739 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
4740 {
4741 struct hwtstamp_config config;
4742 bool rx_cqe_compress_def;
4743 bool ptp_rx;
4744 int err;
4745
4746 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
4747 (mlx5_clock_get_ptp_index(priv->mdev) == -1))
4748 return -EOPNOTSUPP;
4749
4750 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4751 return -EFAULT;
4752
4753 /* TX HW timestamp */
4754 switch (config.tx_type) {
4755 case HWTSTAMP_TX_OFF:
4756 case HWTSTAMP_TX_ON:
4757 break;
4758 default:
4759 return -ERANGE;
4760 }
4761
4762 mutex_lock(&priv->state_lock);
4763 rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
4764
4765 /* RX HW timestamp */
4766 switch (config.rx_filter) {
4767 case HWTSTAMP_FILTER_NONE:
4768 ptp_rx = false;
4769 break;
4770 case HWTSTAMP_FILTER_ALL:
4771 case HWTSTAMP_FILTER_SOME:
4772 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4773 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4774 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4775 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4776 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4777 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4778 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4779 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4780 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4781 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4782 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4783 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4784 case HWTSTAMP_FILTER_NTP_ALL:
4785 config.rx_filter = HWTSTAMP_FILTER_ALL;
4786 /* ptp_rx is set if both HW TS is set and CQE
4787 * compression is set
4788 */
4789 ptp_rx = rx_cqe_compress_def;
4790 break;
4791 default:
4792 err = -ERANGE;
4793 goto err_unlock;
4794 }
4795
4796 if (!mlx5e_profile_feature_cap(priv->profile, PTP_RX))
4797 err = mlx5e_hwstamp_config_no_ptp_rx(priv,
4798 config.rx_filter != HWTSTAMP_FILTER_NONE);
4799 else
4800 err = mlx5e_hwstamp_config_ptp_rx(priv, ptp_rx);
4801 if (err)
4802 goto err_unlock;
4803
4804 memcpy(&priv->tstamp, &config, sizeof(config));
4805 mutex_unlock(&priv->state_lock);
4806
4807 /* might need to fix some features */
4808 netdev_update_features(priv->netdev);
4809
4810 return copy_to_user(ifr->ifr_data, &config,
4811 sizeof(config)) ? -EFAULT : 0;
4812 err_unlock:
4813 mutex_unlock(&priv->state_lock);
4814 return err;
4815 }
4816
mlx5e_hwstamp_get(struct mlx5e_priv * priv,struct ifreq * ifr)4817 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
4818 {
4819 struct hwtstamp_config *cfg = &priv->tstamp;
4820
4821 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
4822 return -EOPNOTSUPP;
4823
4824 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
4825 }
4826
mlx5e_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)4827 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4828 {
4829 struct mlx5e_priv *priv = netdev_priv(dev);
4830
4831 switch (cmd) {
4832 case SIOCSHWTSTAMP:
4833 return mlx5e_hwstamp_set(priv, ifr);
4834 case SIOCGHWTSTAMP:
4835 return mlx5e_hwstamp_get(priv, ifr);
4836 default:
4837 return -EOPNOTSUPP;
4838 }
4839 }
4840
4841 #ifdef CONFIG_MLX5_ESWITCH
mlx5e_set_vf_mac(struct net_device * dev,int vf,u8 * mac)4842 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4843 {
4844 struct mlx5e_priv *priv = netdev_priv(dev);
4845 struct mlx5_core_dev *mdev = priv->mdev;
4846
4847 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4848 }
4849
mlx5e_set_vf_vlan(struct net_device * dev,int vf,u16 vlan,u8 qos,__be16 vlan_proto)4850 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4851 __be16 vlan_proto)
4852 {
4853 struct mlx5e_priv *priv = netdev_priv(dev);
4854 struct mlx5_core_dev *mdev = priv->mdev;
4855
4856 if (vlan_proto != htons(ETH_P_8021Q))
4857 return -EPROTONOSUPPORT;
4858
4859 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4860 vlan, qos);
4861 }
4862
mlx5e_set_vf_spoofchk(struct net_device * dev,int vf,bool setting)4863 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4864 {
4865 struct mlx5e_priv *priv = netdev_priv(dev);
4866 struct mlx5_core_dev *mdev = priv->mdev;
4867
4868 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4869 }
4870
mlx5e_set_vf_trust(struct net_device * dev,int vf,bool setting)4871 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4872 {
4873 struct mlx5e_priv *priv = netdev_priv(dev);
4874 struct mlx5_core_dev *mdev = priv->mdev;
4875
4876 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4877 }
4878
mlx5e_set_vf_rate(struct net_device * dev,int vf,int min_tx_rate,int max_tx_rate)4879 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4880 int max_tx_rate)
4881 {
4882 struct mlx5e_priv *priv = netdev_priv(dev);
4883 struct mlx5_core_dev *mdev = priv->mdev;
4884
4885 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4886 max_tx_rate, min_tx_rate);
4887 }
4888
mlx5_vport_link2ifla(u8 esw_link)4889 static int mlx5_vport_link2ifla(u8 esw_link)
4890 {
4891 switch (esw_link) {
4892 case MLX5_VPORT_ADMIN_STATE_DOWN:
4893 return IFLA_VF_LINK_STATE_DISABLE;
4894 case MLX5_VPORT_ADMIN_STATE_UP:
4895 return IFLA_VF_LINK_STATE_ENABLE;
4896 }
4897 return IFLA_VF_LINK_STATE_AUTO;
4898 }
4899
mlx5_ifla_link2vport(u8 ifla_link)4900 static int mlx5_ifla_link2vport(u8 ifla_link)
4901 {
4902 switch (ifla_link) {
4903 case IFLA_VF_LINK_STATE_DISABLE:
4904 return MLX5_VPORT_ADMIN_STATE_DOWN;
4905 case IFLA_VF_LINK_STATE_ENABLE:
4906 return MLX5_VPORT_ADMIN_STATE_UP;
4907 }
4908 return MLX5_VPORT_ADMIN_STATE_AUTO;
4909 }
4910
mlx5e_set_vf_link_state(struct net_device * dev,int vf,int link_state)4911 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4912 int link_state)
4913 {
4914 struct mlx5e_priv *priv = netdev_priv(dev);
4915 struct mlx5_core_dev *mdev = priv->mdev;
4916
4917 if (mlx5e_is_uplink_rep(priv))
4918 return -EOPNOTSUPP;
4919
4920 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4921 mlx5_ifla_link2vport(link_state));
4922 }
4923
mlx5e_get_vf_config(struct net_device * dev,int vf,struct ifla_vf_info * ivi)4924 int mlx5e_get_vf_config(struct net_device *dev,
4925 int vf, struct ifla_vf_info *ivi)
4926 {
4927 struct mlx5e_priv *priv = netdev_priv(dev);
4928 struct mlx5_core_dev *mdev = priv->mdev;
4929 int err;
4930
4931 if (!netif_device_present(dev))
4932 return -EOPNOTSUPP;
4933
4934 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4935 if (err)
4936 return err;
4937 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4938 return 0;
4939 }
4940
mlx5e_get_vf_stats(struct net_device * dev,int vf,struct ifla_vf_stats * vf_stats)4941 int mlx5e_get_vf_stats(struct net_device *dev,
4942 int vf, struct ifla_vf_stats *vf_stats)
4943 {
4944 struct mlx5e_priv *priv = netdev_priv(dev);
4945 struct mlx5_core_dev *mdev = priv->mdev;
4946
4947 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4948 vf_stats);
4949 }
4950
4951 static bool
mlx5e_has_offload_stats(const struct net_device * dev,int attr_id)4952 mlx5e_has_offload_stats(const struct net_device *dev, int attr_id)
4953 {
4954 struct mlx5e_priv *priv = netdev_priv(dev);
4955
4956 if (!netif_device_present(dev))
4957 return false;
4958
4959 if (!mlx5e_is_uplink_rep(priv))
4960 return false;
4961
4962 return mlx5e_rep_has_offload_stats(dev, attr_id);
4963 }
4964
4965 static int
mlx5e_get_offload_stats(int attr_id,const struct net_device * dev,void * sp)4966 mlx5e_get_offload_stats(int attr_id, const struct net_device *dev,
4967 void *sp)
4968 {
4969 struct mlx5e_priv *priv = netdev_priv(dev);
4970
4971 if (!mlx5e_is_uplink_rep(priv))
4972 return -EOPNOTSUPP;
4973
4974 return mlx5e_rep_get_offload_stats(attr_id, dev, sp);
4975 }
4976 #endif
4977
mlx5e_tunnel_proto_supported_tx(struct mlx5_core_dev * mdev,u8 proto_type)4978 static bool mlx5e_tunnel_proto_supported_tx(struct mlx5_core_dev *mdev, u8 proto_type)
4979 {
4980 switch (proto_type) {
4981 case IPPROTO_GRE:
4982 return MLX5_CAP_ETH(mdev, tunnel_stateless_gre);
4983 case IPPROTO_IPIP:
4984 case IPPROTO_IPV6:
4985 return (MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip) ||
4986 MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip_tx));
4987 default:
4988 return false;
4989 }
4990 }
4991
mlx5e_gre_tunnel_inner_proto_offload_supported(struct mlx5_core_dev * mdev,struct sk_buff * skb)4992 static bool mlx5e_gre_tunnel_inner_proto_offload_supported(struct mlx5_core_dev *mdev,
4993 struct sk_buff *skb)
4994 {
4995 switch (skb->inner_protocol) {
4996 case htons(ETH_P_IP):
4997 case htons(ETH_P_IPV6):
4998 case htons(ETH_P_TEB):
4999 return true;
5000 case htons(ETH_P_MPLS_UC):
5001 case htons(ETH_P_MPLS_MC):
5002 return MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre);
5003 }
5004 return false;
5005 }
5006
mlx5e_tunnel_features_check(struct mlx5e_priv * priv,struct sk_buff * skb,netdev_features_t features)5007 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
5008 struct sk_buff *skb,
5009 netdev_features_t features)
5010 {
5011 unsigned int offset = 0;
5012 struct udphdr *udph;
5013 u8 proto;
5014 u16 port;
5015
5016 switch (vlan_get_protocol(skb)) {
5017 case htons(ETH_P_IP):
5018 proto = ip_hdr(skb)->protocol;
5019 break;
5020 case htons(ETH_P_IPV6):
5021 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
5022 break;
5023 default:
5024 goto out;
5025 }
5026
5027 switch (proto) {
5028 case IPPROTO_GRE:
5029 if (mlx5e_gre_tunnel_inner_proto_offload_supported(priv->mdev, skb))
5030 return features;
5031 break;
5032 case IPPROTO_IPIP:
5033 case IPPROTO_IPV6:
5034 if (mlx5e_tunnel_proto_supported_tx(priv->mdev, IPPROTO_IPIP))
5035 return features;
5036 break;
5037 case IPPROTO_UDP:
5038 udph = udp_hdr(skb);
5039 port = be16_to_cpu(udph->dest);
5040
5041 /* Verify if UDP port is being offloaded by HW */
5042 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
5043 return vxlan_features_check(skb, features);
5044
5045 #if IS_ENABLED(CONFIG_GENEVE)
5046 /* Support Geneve offload for default UDP port */
5047 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
5048 return features;
5049 #endif
5050 break;
5051 #ifdef CONFIG_MLX5_EN_IPSEC
5052 case IPPROTO_ESP:
5053 return mlx5e_ipsec_feature_check(skb, features);
5054 #endif
5055 }
5056
5057 out:
5058 /* Disable CSUM and GSO if skb cannot be offloaded by HW */
5059 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
5060 }
5061
mlx5e_features_check(struct sk_buff * skb,struct net_device * netdev,netdev_features_t features)5062 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
5063 struct net_device *netdev,
5064 netdev_features_t features)
5065 {
5066 struct mlx5e_priv *priv = netdev_priv(netdev);
5067
5068 features = vlan_features_check(skb, features);
5069
5070 /* Validate if the tunneled packet is being offloaded by HW */
5071 if (skb->encapsulation &&
5072 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
5073 return mlx5e_tunnel_features_check(priv, skb, features);
5074
5075 return features;
5076 }
5077
mlx5e_tx_timeout_work(struct work_struct * work)5078 static void mlx5e_tx_timeout_work(struct work_struct *work)
5079 {
5080 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
5081 tx_timeout_work);
5082 struct net_device *netdev = priv->netdev;
5083 int i;
5084
5085 /* Recovering the TX queues implies re-enabling NAPI, which requires
5086 * the netdev instance lock.
5087 * However, channel closing flows have to wait for this work to finish
5088 * while holding the same lock. So either get the lock or find that
5089 * channels are being closed for other reason and this work is not
5090 * relevant anymore.
5091 */
5092 while (!netdev_trylock(netdev)) {
5093 if (!test_bit(MLX5E_STATE_CHANNELS_ACTIVE, &priv->state))
5094 return;
5095 msleep(20);
5096 }
5097
5098 for (i = 0; i < netdev->real_num_tx_queues; i++) {
5099 struct netdev_queue *dev_queue =
5100 netdev_get_tx_queue(netdev, i);
5101 struct mlx5e_txqsq *sq = priv->txq2sq[i];
5102
5103 if (!netif_xmit_stopped(dev_queue))
5104 continue;
5105
5106 if (mlx5e_reporter_tx_timeout(sq))
5107 /* break if tried to reopened channels */
5108 break;
5109 }
5110
5111 netdev_unlock(netdev);
5112 }
5113
mlx5e_tx_timeout(struct net_device * dev,unsigned int txqueue)5114 static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue)
5115 {
5116 struct mlx5e_priv *priv = netdev_priv(dev);
5117
5118 netdev_err(dev, "TX timeout detected\n");
5119 queue_work(priv->wq, &priv->tx_timeout_work);
5120 }
5121
mlx5e_xdp_allowed(struct net_device * netdev,struct mlx5_core_dev * mdev,struct mlx5e_params * params)5122 static int mlx5e_xdp_allowed(struct net_device *netdev, struct mlx5_core_dev *mdev,
5123 struct mlx5e_params *params)
5124 {
5125 if (params->packet_merge.type != MLX5E_PACKET_MERGE_NONE) {
5126 netdev_warn(netdev, "can't set XDP while HW-GRO/LRO is on, disable them first\n");
5127 return -EINVAL;
5128 }
5129
5130 if (!mlx5e_params_validate_xdp(netdev, mdev, params))
5131 return -EINVAL;
5132
5133 return 0;
5134 }
5135
mlx5e_rq_replace_xdp_prog(struct mlx5e_rq * rq,struct bpf_prog * prog)5136 static void mlx5e_rq_replace_xdp_prog(struct mlx5e_rq *rq, struct bpf_prog *prog)
5137 {
5138 struct bpf_prog *old_prog;
5139
5140 old_prog = rcu_replace_pointer(rq->xdp_prog, prog,
5141 lockdep_is_held(&rq->priv->state_lock));
5142 if (old_prog)
5143 bpf_prog_put(old_prog);
5144 }
5145
mlx5e_xdp_set(struct net_device * netdev,struct bpf_prog * prog)5146 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
5147 {
5148 struct mlx5e_priv *priv = netdev_priv(netdev);
5149 struct mlx5e_params new_params;
5150 struct bpf_prog *old_prog;
5151 int err = 0;
5152 bool reset;
5153 int i;
5154
5155 mutex_lock(&priv->state_lock);
5156
5157 new_params = priv->channels.params;
5158 new_params.xdp_prog = prog;
5159
5160 if (prog) {
5161 err = mlx5e_xdp_allowed(netdev, priv->mdev, &new_params);
5162 if (err)
5163 goto unlock;
5164 }
5165
5166 /* no need for full reset when exchanging programs */
5167 reset = (!priv->channels.params.xdp_prog || !prog);
5168
5169 old_prog = priv->channels.params.xdp_prog;
5170
5171 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
5172 if (err)
5173 goto unlock;
5174
5175 if (old_prog)
5176 bpf_prog_put(old_prog);
5177
5178 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
5179 goto unlock;
5180
5181 /* exchanging programs w/o reset, we update ref counts on behalf
5182 * of the channels RQs here.
5183 */
5184 bpf_prog_add(prog, priv->channels.num);
5185 for (i = 0; i < priv->channels.num; i++) {
5186 struct mlx5e_channel *c = priv->channels.c[i];
5187
5188 mlx5e_rq_replace_xdp_prog(&c->rq, prog);
5189 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) {
5190 bpf_prog_inc(prog);
5191 mlx5e_rq_replace_xdp_prog(&c->xskrq, prog);
5192 }
5193 }
5194
5195 unlock:
5196 mutex_unlock(&priv->state_lock);
5197
5198 /* Need to fix some features. */
5199 if (!err)
5200 netdev_update_features(netdev);
5201
5202 return err;
5203 }
5204
mlx5e_xdp(struct net_device * dev,struct netdev_bpf * xdp)5205 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
5206 {
5207 switch (xdp->command) {
5208 case XDP_SETUP_PROG:
5209 return mlx5e_xdp_set(dev, xdp->prog);
5210 case XDP_SETUP_XSK_POOL:
5211 return mlx5e_xsk_setup_pool(dev, xdp->xsk.pool,
5212 xdp->xsk.queue_id);
5213 default:
5214 return -EINVAL;
5215 }
5216 }
5217
5218 #ifdef CONFIG_MLX5_ESWITCH
mlx5e_bridge_getlink(struct sk_buff * skb,u32 pid,u32 seq,struct net_device * dev,u32 filter_mask,int nlflags)5219 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
5220 struct net_device *dev, u32 filter_mask,
5221 int nlflags)
5222 {
5223 struct mlx5e_priv *priv = netdev_priv(dev);
5224 struct mlx5_core_dev *mdev = priv->mdev;
5225 u8 mode, setting;
5226
5227 if (mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting))
5228 return -EOPNOTSUPP;
5229 mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
5230 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
5231 mode,
5232 0, 0, nlflags, filter_mask, NULL);
5233 }
5234
mlx5e_bridge_setlink(struct net_device * dev,struct nlmsghdr * nlh,u16 flags,struct netlink_ext_ack * extack)5235 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
5236 u16 flags, struct netlink_ext_ack *extack)
5237 {
5238 struct mlx5e_priv *priv = netdev_priv(dev);
5239 struct mlx5_core_dev *mdev = priv->mdev;
5240 struct nlattr *attr, *br_spec;
5241 u16 mode = BRIDGE_MODE_UNDEF;
5242 u8 setting;
5243 int rem;
5244
5245 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
5246 if (!br_spec)
5247 return -EINVAL;
5248
5249 nla_for_each_nested_type(attr, IFLA_BRIDGE_MODE, br_spec, rem) {
5250 mode = nla_get_u16(attr);
5251 if (mode > BRIDGE_MODE_VEPA)
5252 return -EINVAL;
5253
5254 break;
5255 }
5256
5257 if (mode == BRIDGE_MODE_UNDEF)
5258 return -EINVAL;
5259
5260 setting = (mode == BRIDGE_MODE_VEPA) ? 1 : 0;
5261 return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
5262 }
5263 #endif
5264
5265 const struct net_device_ops mlx5e_netdev_ops = {
5266 .ndo_open = mlx5e_open,
5267 .ndo_stop = mlx5e_close,
5268 .ndo_start_xmit = mlx5e_xmit,
5269 .ndo_setup_tc = mlx5e_setup_tc,
5270 .ndo_select_queue = mlx5e_select_queue,
5271 .ndo_get_stats64 = mlx5e_get_stats,
5272 .ndo_set_rx_mode = mlx5e_set_rx_mode,
5273 .ndo_set_mac_address = mlx5e_set_mac,
5274 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
5275 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
5276 .ndo_set_features = mlx5e_set_features,
5277 .ndo_fix_features = mlx5e_fix_features,
5278 .ndo_change_mtu = mlx5e_change_nic_mtu,
5279 .ndo_eth_ioctl = mlx5e_ioctl,
5280 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
5281 .ndo_features_check = mlx5e_features_check,
5282 .ndo_tx_timeout = mlx5e_tx_timeout,
5283 .ndo_bpf = mlx5e_xdp,
5284 .ndo_xdp_xmit = mlx5e_xdp_xmit,
5285 .ndo_xsk_wakeup = mlx5e_xsk_wakeup,
5286 #ifdef CONFIG_MLX5_EN_ARFS
5287 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
5288 #endif
5289 #ifdef CONFIG_MLX5_ESWITCH
5290 .ndo_bridge_setlink = mlx5e_bridge_setlink,
5291 .ndo_bridge_getlink = mlx5e_bridge_getlink,
5292
5293 /* SRIOV E-Switch NDOs */
5294 .ndo_set_vf_mac = mlx5e_set_vf_mac,
5295 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
5296 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
5297 .ndo_set_vf_trust = mlx5e_set_vf_trust,
5298 .ndo_set_vf_rate = mlx5e_set_vf_rate,
5299 .ndo_get_vf_config = mlx5e_get_vf_config,
5300 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
5301 .ndo_get_vf_stats = mlx5e_get_vf_stats,
5302 .ndo_has_offload_stats = mlx5e_has_offload_stats,
5303 .ndo_get_offload_stats = mlx5e_get_offload_stats,
5304 #endif
5305 };
5306
mlx5e_build_nic_params(struct mlx5e_priv * priv,struct mlx5e_xsk * xsk,u16 mtu)5307 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu)
5308 {
5309 struct mlx5e_params *params = &priv->channels.params;
5310 struct mlx5_core_dev *mdev = priv->mdev;
5311
5312 params->sw_mtu = mtu;
5313 params->hard_mtu = MLX5E_ETH_HARD_MTU;
5314 params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2,
5315 priv->max_nch);
5316 mlx5e_params_mqprio_reset(params);
5317
5318 /* SQ */
5319 params->log_sq_size = is_kdump_kernel() ?
5320 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
5321 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
5322 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
5323
5324 /* XDP SQ */
5325 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
5326
5327 /* set CQE compression */
5328 params->rx_cqe_compress_def = false;
5329 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
5330 MLX5_CAP_GEN(mdev, vport_group_manager))
5331 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
5332
5333 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
5334 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
5335
5336 /* RQ */
5337 mlx5e_build_rq_params(mdev, params);
5338
5339 params->terminate_lkey_be = mlx5_core_get_terminate_scatter_list_mkey(mdev);
5340
5341 params->packet_merge.timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
5342
5343 /* CQ moderation params */
5344 params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation) &&
5345 MLX5_CAP_GEN(mdev, cq_period_mode_modify);
5346 params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation) &&
5347 MLX5_CAP_GEN(mdev, cq_period_mode_modify);
5348 params->rx_moder_use_cqe_mode = !!MLX5_CAP_GEN(mdev, cq_period_start_from_cqe);
5349 params->tx_moder_use_cqe_mode = false;
5350 mlx5e_reset_rx_moderation(¶ms->rx_cq_moderation, params->rx_moder_use_cqe_mode,
5351 params->rx_dim_enabled);
5352 mlx5e_reset_tx_moderation(¶ms->tx_cq_moderation, params->tx_moder_use_cqe_mode,
5353 params->tx_dim_enabled);
5354
5355 /* TX inline */
5356 mlx5_query_min_inline(mdev, ¶ms->tx_min_inline_mode);
5357
5358 /* AF_XDP */
5359 params->xsk = xsk;
5360
5361 /* Do not update netdev->features directly in here
5362 * on mlx5e_attach_netdev() we will call mlx5e_update_features()
5363 * To update netdev->features please modify mlx5e_fix_features()
5364 */
5365 }
5366
mlx5e_set_netdev_dev_addr(struct net_device * netdev)5367 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
5368 {
5369 struct mlx5e_priv *priv = netdev_priv(netdev);
5370 u8 addr[ETH_ALEN];
5371
5372 mlx5_query_mac_address(priv->mdev, addr);
5373 if (is_zero_ether_addr(addr) &&
5374 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
5375 eth_hw_addr_random(netdev);
5376 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
5377 return;
5378 }
5379
5380 eth_hw_addr_set(netdev, addr);
5381 }
5382
mlx5e_vxlan_set_port(struct net_device * netdev,unsigned int table,unsigned int entry,struct udp_tunnel_info * ti)5383 static int mlx5e_vxlan_set_port(struct net_device *netdev, unsigned int table,
5384 unsigned int entry, struct udp_tunnel_info *ti)
5385 {
5386 struct mlx5e_priv *priv = netdev_priv(netdev);
5387
5388 return mlx5_vxlan_add_port(priv->mdev->vxlan, ntohs(ti->port));
5389 }
5390
mlx5e_vxlan_unset_port(struct net_device * netdev,unsigned int table,unsigned int entry,struct udp_tunnel_info * ti)5391 static int mlx5e_vxlan_unset_port(struct net_device *netdev, unsigned int table,
5392 unsigned int entry, struct udp_tunnel_info *ti)
5393 {
5394 struct mlx5e_priv *priv = netdev_priv(netdev);
5395
5396 return mlx5_vxlan_del_port(priv->mdev->vxlan, ntohs(ti->port));
5397 }
5398
mlx5e_vxlan_set_netdev_info(struct mlx5e_priv * priv)5399 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv)
5400 {
5401 if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
5402 return;
5403
5404 priv->nic_info.set_port = mlx5e_vxlan_set_port;
5405 priv->nic_info.unset_port = mlx5e_vxlan_unset_port;
5406 priv->nic_info.flags = UDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN;
5407 priv->nic_info.tables[0].tunnel_types = UDP_TUNNEL_TYPE_VXLAN;
5408 /* Don't count the space hard-coded to the IANA port */
5409 priv->nic_info.tables[0].n_entries =
5410 mlx5_vxlan_max_udp_ports(priv->mdev) - 1;
5411
5412 priv->netdev->udp_tunnel_nic_info = &priv->nic_info;
5413 }
5414
mlx5e_tunnel_any_tx_proto_supported(struct mlx5_core_dev * mdev)5415 static bool mlx5e_tunnel_any_tx_proto_supported(struct mlx5_core_dev *mdev)
5416 {
5417 int tt;
5418
5419 for (tt = 0; tt < MLX5_NUM_TUNNEL_TT; tt++) {
5420 if (mlx5e_tunnel_proto_supported_tx(mdev, mlx5_get_proto_by_tunnel_type(tt)))
5421 return true;
5422 }
5423 return (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev));
5424 }
5425
mlx5e_get_queue_stats_rx(struct net_device * dev,int i,struct netdev_queue_stats_rx * stats)5426 static void mlx5e_get_queue_stats_rx(struct net_device *dev, int i,
5427 struct netdev_queue_stats_rx *stats)
5428 {
5429 struct mlx5e_priv *priv = netdev_priv(dev);
5430 struct mlx5e_channel_stats *channel_stats;
5431 struct mlx5e_rq_stats *xskrq_stats;
5432 struct mlx5e_rq_stats *rq_stats;
5433
5434 if (mlx5e_is_uplink_rep(priv) || !priv->stats_nch)
5435 return;
5436
5437 channel_stats = priv->channel_stats[i];
5438 xskrq_stats = &channel_stats->xskrq;
5439 rq_stats = &channel_stats->rq;
5440
5441 stats->packets = rq_stats->packets + xskrq_stats->packets;
5442 stats->bytes = rq_stats->bytes + xskrq_stats->bytes;
5443 stats->alloc_fail = rq_stats->buff_alloc_err +
5444 xskrq_stats->buff_alloc_err;
5445 }
5446
mlx5e_get_queue_stats_tx(struct net_device * dev,int i,struct netdev_queue_stats_tx * stats)5447 static void mlx5e_get_queue_stats_tx(struct net_device *dev, int i,
5448 struct netdev_queue_stats_tx *stats)
5449 {
5450 struct mlx5e_priv *priv = netdev_priv(dev);
5451 struct mlx5e_sq_stats *sq_stats;
5452
5453 if (!priv->stats_nch)
5454 return;
5455
5456 /* no special case needed for ptp htb etc since txq2sq_stats is kept up
5457 * to date for active sq_stats, otherwise get_base_stats takes care of
5458 * inactive sqs.
5459 */
5460 sq_stats = priv->txq2sq_stats[i];
5461 stats->packets = sq_stats->packets;
5462 stats->bytes = sq_stats->bytes;
5463 }
5464
mlx5e_get_base_stats(struct net_device * dev,struct netdev_queue_stats_rx * rx,struct netdev_queue_stats_tx * tx)5465 static void mlx5e_get_base_stats(struct net_device *dev,
5466 struct netdev_queue_stats_rx *rx,
5467 struct netdev_queue_stats_tx *tx)
5468 {
5469 struct mlx5e_priv *priv = netdev_priv(dev);
5470 struct mlx5e_ptp *ptp_channel;
5471 int i, tc;
5472
5473 if (!mlx5e_is_uplink_rep(priv)) {
5474 rx->packets = 0;
5475 rx->bytes = 0;
5476 rx->alloc_fail = 0;
5477
5478 for (i = priv->channels.params.num_channels; i < priv->stats_nch; i++) {
5479 struct netdev_queue_stats_rx rx_i = {0};
5480
5481 mlx5e_get_queue_stats_rx(dev, i, &rx_i);
5482
5483 rx->packets += rx_i.packets;
5484 rx->bytes += rx_i.bytes;
5485 rx->alloc_fail += rx_i.alloc_fail;
5486 }
5487
5488 /* always report PTP RX stats from base as there is no
5489 * corresponding channel to report them under in
5490 * mlx5e_get_queue_stats_rx.
5491 */
5492 if (priv->rx_ptp_opened) {
5493 struct mlx5e_rq_stats *rq_stats = &priv->ptp_stats.rq;
5494
5495 rx->packets += rq_stats->packets;
5496 rx->bytes += rq_stats->bytes;
5497 }
5498 }
5499
5500 tx->packets = 0;
5501 tx->bytes = 0;
5502
5503 for (i = 0; i < priv->stats_nch; i++) {
5504 struct mlx5e_channel_stats *channel_stats = priv->channel_stats[i];
5505
5506 /* handle two cases:
5507 *
5508 * 1. channels which are active. In this case,
5509 * report only deactivated TCs on these channels.
5510 *
5511 * 2. channels which were deactivated
5512 * (i > priv->channels.params.num_channels)
5513 * must have all of their TCs [0 .. priv->max_opened_tc)
5514 * examined because deactivated channels will not be in the
5515 * range of [0..real_num_tx_queues) and will not have their
5516 * stats reported by mlx5e_get_queue_stats_tx.
5517 */
5518 if (i < priv->channels.params.num_channels)
5519 tc = mlx5e_get_dcb_num_tc(&priv->channels.params);
5520 else
5521 tc = 0;
5522
5523 for (; tc < priv->max_opened_tc; tc++) {
5524 struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[tc];
5525
5526 tx->packets += sq_stats->packets;
5527 tx->bytes += sq_stats->bytes;
5528 }
5529 }
5530
5531 /* if PTP TX was opened at some point and has since either:
5532 * - been shutdown and set to NULL, or
5533 * - simply disabled (bit unset)
5534 *
5535 * report stats directly from the ptp_stats structures as these queues
5536 * are now unavailable and there is no txq index to retrieve these
5537 * stats via calls to mlx5e_get_queue_stats_tx.
5538 */
5539 ptp_channel = priv->channels.ptp;
5540 if (priv->tx_ptp_opened && (!ptp_channel || !test_bit(MLX5E_PTP_STATE_TX, ptp_channel->state))) {
5541 for (tc = 0; tc < priv->max_opened_tc; tc++) {
5542 struct mlx5e_sq_stats *sq_stats = &priv->ptp_stats.sq[tc];
5543
5544 tx->packets += sq_stats->packets;
5545 tx->bytes += sq_stats->bytes;
5546 }
5547 }
5548 }
5549
5550 static const struct netdev_stat_ops mlx5e_stat_ops = {
5551 .get_queue_stats_rx = mlx5e_get_queue_stats_rx,
5552 .get_queue_stats_tx = mlx5e_get_queue_stats_tx,
5553 .get_base_stats = mlx5e_get_base_stats,
5554 };
5555
5556 struct mlx5_qmgmt_data {
5557 struct mlx5e_channel *c;
5558 struct mlx5e_channel_param cparam;
5559 };
5560
mlx5e_queue_mem_alloc(struct net_device * dev,void * newq,int queue_index)5561 static int mlx5e_queue_mem_alloc(struct net_device *dev, void *newq,
5562 int queue_index)
5563 {
5564 struct mlx5_qmgmt_data *new = (struct mlx5_qmgmt_data *)newq;
5565 struct mlx5e_priv *priv = netdev_priv(dev);
5566 struct mlx5e_channels *chs = &priv->channels;
5567 struct mlx5e_params params = chs->params;
5568 struct mlx5_core_dev *mdev;
5569 int err;
5570
5571 mutex_lock(&priv->state_lock);
5572 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
5573 err = -ENODEV;
5574 goto unlock;
5575 }
5576
5577 if (queue_index >= chs->num) {
5578 err = -ERANGE;
5579 goto unlock;
5580 }
5581
5582 if (MLX5E_GET_PFLAG(&chs->params, MLX5E_PFLAG_TX_PORT_TS) ||
5583 chs->params.ptp_rx ||
5584 chs->params.xdp_prog ||
5585 priv->htb) {
5586 netdev_err(priv->netdev,
5587 "Cloning channels with Port/rx PTP, XDP or HTB is not supported\n");
5588 err = -EOPNOTSUPP;
5589 goto unlock;
5590 }
5591
5592 mdev = mlx5_sd_ch_ix_get_dev(priv->mdev, queue_index);
5593 err = mlx5e_build_channel_param(mdev, ¶ms, &new->cparam);
5594 if (err)
5595 goto unlock;
5596
5597 err = mlx5e_open_channel(priv, queue_index, ¶ms, NULL, &new->c);
5598 unlock:
5599 mutex_unlock(&priv->state_lock);
5600 return err;
5601 }
5602
mlx5e_queue_mem_free(struct net_device * dev,void * mem)5603 static void mlx5e_queue_mem_free(struct net_device *dev, void *mem)
5604 {
5605 struct mlx5_qmgmt_data *data = (struct mlx5_qmgmt_data *)mem;
5606
5607 /* not supposed to happen since mlx5e_queue_start never fails
5608 * but this is how this should be implemented just in case
5609 */
5610 if (data->c)
5611 mlx5e_close_channel(data->c);
5612 }
5613
mlx5e_queue_stop(struct net_device * dev,void * oldq,int queue_index)5614 static int mlx5e_queue_stop(struct net_device *dev, void *oldq, int queue_index)
5615 {
5616 /* In mlx5 a txq cannot be simply stopped in isolation, only restarted.
5617 * mlx5e_queue_start does not fail, we stop the old queue there.
5618 * TODO: Improve this.
5619 */
5620 return 0;
5621 }
5622
mlx5e_queue_start(struct net_device * dev,void * newq,int queue_index)5623 static int mlx5e_queue_start(struct net_device *dev, void *newq,
5624 int queue_index)
5625 {
5626 struct mlx5_qmgmt_data *new = (struct mlx5_qmgmt_data *)newq;
5627 struct mlx5e_priv *priv = netdev_priv(dev);
5628 struct mlx5e_channel *old;
5629
5630 mutex_lock(&priv->state_lock);
5631
5632 /* stop and close the old */
5633 old = priv->channels.c[queue_index];
5634 mlx5e_deactivate_priv_channels(priv);
5635 /* close old before activating new, to avoid napi conflict */
5636 mlx5e_close_channel(old);
5637
5638 /* start the new */
5639 priv->channels.c[queue_index] = new->c;
5640 mlx5e_activate_priv_channels(priv);
5641 mutex_unlock(&priv->state_lock);
5642 return 0;
5643 }
5644
5645 static const struct netdev_queue_mgmt_ops mlx5e_queue_mgmt_ops = {
5646 .ndo_queue_mem_size = sizeof(struct mlx5_qmgmt_data),
5647 .ndo_queue_mem_alloc = mlx5e_queue_mem_alloc,
5648 .ndo_queue_mem_free = mlx5e_queue_mem_free,
5649 .ndo_queue_start = mlx5e_queue_start,
5650 .ndo_queue_stop = mlx5e_queue_stop,
5651 };
5652
mlx5e_build_nic_netdev(struct net_device * netdev)5653 static void mlx5e_build_nic_netdev(struct net_device *netdev)
5654 {
5655 struct mlx5e_priv *priv = netdev_priv(netdev);
5656 struct mlx5_core_dev *mdev = priv->mdev;
5657 bool fcs_supported;
5658 bool fcs_enabled;
5659
5660 SET_NETDEV_DEV(netdev, mdev->device);
5661
5662 netdev->netdev_ops = &mlx5e_netdev_ops;
5663 netdev->queue_mgmt_ops = &mlx5e_queue_mgmt_ops;
5664 netdev->xdp_metadata_ops = &mlx5e_xdp_metadata_ops;
5665 netdev->xsk_tx_metadata_ops = &mlx5e_xsk_tx_metadata_ops;
5666 netdev->request_ops_lock = true;
5667 netdev_lockdep_set_classes(netdev);
5668
5669 mlx5e_dcbnl_build_netdev(netdev);
5670
5671 netdev->watchdog_timeo = 15 * HZ;
5672
5673 netdev->stat_ops = &mlx5e_stat_ops;
5674 netdev->ethtool_ops = &mlx5e_ethtool_ops;
5675
5676 netdev->vlan_features |= NETIF_F_SG;
5677 netdev->vlan_features |= NETIF_F_HW_CSUM;
5678 netdev->vlan_features |= NETIF_F_HW_MACSEC;
5679 netdev->vlan_features |= NETIF_F_GRO;
5680 netdev->vlan_features |= NETIF_F_TSO;
5681 netdev->vlan_features |= NETIF_F_TSO6;
5682 netdev->vlan_features |= NETIF_F_RXCSUM;
5683 netdev->vlan_features |= NETIF_F_RXHASH;
5684 netdev->vlan_features |= NETIF_F_GSO_PARTIAL;
5685
5686 netdev->mpls_features |= NETIF_F_SG;
5687 netdev->mpls_features |= NETIF_F_HW_CSUM;
5688 netdev->mpls_features |= NETIF_F_TSO;
5689 netdev->mpls_features |= NETIF_F_TSO6;
5690
5691 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_TX;
5692 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_RX;
5693
5694 /* Tunneled LRO is not supported in the driver, and the same RQs are
5695 * shared between inner and outer TIRs, so the driver can't disable LRO
5696 * for inner TIRs while having it enabled for outer TIRs. Due to this,
5697 * block LRO altogether if the firmware declares tunneled LRO support.
5698 */
5699 if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
5700 !MLX5_CAP_ETH(mdev, tunnel_lro_vxlan) &&
5701 !MLX5_CAP_ETH(mdev, tunnel_lro_gre) &&
5702 mlx5e_check_fragmented_striding_rq_cap(mdev, PAGE_SHIFT,
5703 MLX5E_MPWRQ_UMR_MODE_ALIGNED))
5704 netdev->vlan_features |= NETIF_F_LRO;
5705
5706 if (mlx5e_hw_gro_supported(mdev) &&
5707 mlx5e_check_fragmented_striding_rq_cap(mdev, PAGE_SHIFT,
5708 MLX5E_MPWRQ_UMR_MODE_ALIGNED))
5709 netdev->vlan_features |= NETIF_F_GRO_HW;
5710
5711 netdev->hw_features = netdev->vlan_features;
5712 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
5713 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
5714 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
5715 netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
5716
5717 if (mlx5e_tunnel_any_tx_proto_supported(mdev)) {
5718 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
5719 netdev->hw_enc_features |= NETIF_F_TSO;
5720 netdev->hw_enc_features |= NETIF_F_TSO6;
5721 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
5722 }
5723
5724 if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
5725 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
5726 NETIF_F_GSO_UDP_TUNNEL_CSUM;
5727 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
5728 NETIF_F_GSO_UDP_TUNNEL_CSUM;
5729 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
5730 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL |
5731 NETIF_F_GSO_UDP_TUNNEL_CSUM;
5732 }
5733
5734 if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_GRE)) {
5735 netdev->hw_features |= NETIF_F_GSO_GRE |
5736 NETIF_F_GSO_GRE_CSUM;
5737 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
5738 NETIF_F_GSO_GRE_CSUM;
5739 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
5740 NETIF_F_GSO_GRE_CSUM;
5741 }
5742
5743 if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_IPIP)) {
5744 netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
5745 NETIF_F_GSO_IPXIP6;
5746 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
5747 NETIF_F_GSO_IPXIP6;
5748 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
5749 NETIF_F_GSO_IPXIP6;
5750 }
5751
5752 netdev->gso_partial_features |= NETIF_F_GSO_UDP_L4;
5753 netdev->hw_features |= NETIF_F_GSO_UDP_L4;
5754
5755 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
5756
5757 if (fcs_supported)
5758 netdev->hw_features |= NETIF_F_RXALL;
5759
5760 if (MLX5_CAP_ETH(mdev, scatter_fcs))
5761 netdev->hw_features |= NETIF_F_RXFCS;
5762
5763 if (mlx5_qos_is_supported(mdev))
5764 netdev->hw_features |= NETIF_F_HW_TC;
5765
5766 netdev->features = netdev->hw_features;
5767
5768 /* Defaults */
5769 if (fcs_enabled)
5770 netdev->features &= ~NETIF_F_RXALL;
5771 netdev->features &= ~NETIF_F_LRO;
5772 netdev->features &= ~NETIF_F_GRO_HW;
5773 netdev->features &= ~NETIF_F_RXFCS;
5774
5775 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
5776 if (FT_CAP(flow_modify_en) &&
5777 FT_CAP(modify_root) &&
5778 FT_CAP(identified_miss_table_mode) &&
5779 FT_CAP(flow_table_modify)) {
5780 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
5781 netdev->hw_features |= NETIF_F_HW_TC;
5782 #endif
5783 #if IS_ENABLED(CONFIG_MLX5_EN_ARFS)
5784 netdev->hw_features |= NETIF_F_NTUPLE;
5785 #elif IS_ENABLED(CONFIG_MLX5_EN_RXNFC)
5786 netdev->features |= NETIF_F_NTUPLE;
5787 #endif
5788 }
5789
5790 netdev->features |= NETIF_F_HIGHDMA;
5791 netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
5792
5793 netdev->priv_flags |= IFF_UNICAST_FLT;
5794
5795 netdev->netmem_tx = true;
5796
5797 netif_set_tso_max_size(netdev, GSO_MAX_SIZE);
5798 mlx5e_set_xdp_feature(netdev);
5799 mlx5e_set_netdev_dev_addr(netdev);
5800 mlx5e_macsec_build_netdev(priv);
5801 mlx5e_ipsec_build_netdev(priv);
5802 mlx5e_ktls_build_netdev(priv);
5803 }
5804
mlx5e_create_q_counters(struct mlx5e_priv * priv)5805 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
5806 {
5807 u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {};
5808 u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {};
5809 struct mlx5_core_dev *mdev = priv->mdev;
5810 struct mlx5_core_dev *pos;
5811 int err, i;
5812
5813 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
5814
5815 mlx5_sd_for_each_dev(i, mdev, pos) {
5816 err = mlx5_cmd_exec_inout(pos, alloc_q_counter, in, out);
5817 if (!err)
5818 priv->q_counter[i] =
5819 MLX5_GET(alloc_q_counter_out, out, counter_set_id);
5820 }
5821
5822 err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
5823 if (!err)
5824 priv->drop_rq_q_counter =
5825 MLX5_GET(alloc_q_counter_out, out, counter_set_id);
5826 }
5827
mlx5e_destroy_q_counters(struct mlx5e_priv * priv)5828 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
5829 {
5830 u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {};
5831 struct mlx5_core_dev *pos;
5832 int i;
5833
5834 MLX5_SET(dealloc_q_counter_in, in, opcode,
5835 MLX5_CMD_OP_DEALLOC_Q_COUNTER);
5836 mlx5_sd_for_each_dev(i, priv->mdev, pos) {
5837 if (priv->q_counter[i]) {
5838 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
5839 priv->q_counter[i]);
5840 mlx5_cmd_exec_in(pos, dealloc_q_counter, in);
5841 }
5842 }
5843
5844 if (priv->drop_rq_q_counter) {
5845 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
5846 priv->drop_rq_q_counter);
5847 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
5848 }
5849 }
5850
mlx5e_nic_init(struct mlx5_core_dev * mdev,struct net_device * netdev)5851 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
5852 struct net_device *netdev)
5853 {
5854 const bool take_rtnl = netdev->reg_state == NETREG_REGISTERED;
5855 struct mlx5e_priv *priv = netdev_priv(netdev);
5856 struct mlx5e_flow_steering *fs;
5857 int err;
5858
5859 mlx5e_build_nic_params(priv, &priv->xsk, netdev->mtu);
5860 mlx5e_vxlan_set_netdev_info(priv);
5861
5862 mlx5e_timestamp_init(priv);
5863
5864 priv->dfs_root = debugfs_create_dir("nic",
5865 mlx5_debugfs_get_dev_root(mdev));
5866
5867 fs = mlx5e_fs_init(priv->profile, mdev,
5868 !test_bit(MLX5E_STATE_DESTROYING, &priv->state),
5869 priv->dfs_root);
5870 if (!fs) {
5871 err = -ENOMEM;
5872 mlx5_core_err(mdev, "FS initialization failed, %d\n", err);
5873 debugfs_remove_recursive(priv->dfs_root);
5874 return err;
5875 }
5876 priv->fs = fs;
5877
5878 err = mlx5e_ktls_init(priv);
5879 if (err)
5880 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
5881
5882 mlx5e_health_create_reporters(priv);
5883
5884 /* If netdev is already registered (e.g. move from uplink to nic profile),
5885 * RTNL lock must be held before triggering netdev notifiers.
5886 */
5887 if (take_rtnl)
5888 rtnl_lock();
5889
5890 /* update XDP supported features */
5891 mlx5e_set_xdp_feature(netdev);
5892
5893 if (take_rtnl)
5894 rtnl_unlock();
5895
5896 return 0;
5897 }
5898
mlx5e_nic_cleanup(struct mlx5e_priv * priv)5899 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
5900 {
5901 mlx5e_health_destroy_reporters(priv);
5902 mlx5e_ktls_cleanup(priv);
5903 mlx5e_fs_cleanup(priv->fs);
5904 debugfs_remove_recursive(priv->dfs_root);
5905 priv->fs = NULL;
5906 }
5907
mlx5e_init_nic_rx(struct mlx5e_priv * priv)5908 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
5909 {
5910 struct mlx5_core_dev *mdev = priv->mdev;
5911 enum mlx5e_rx_res_features features;
5912 int err;
5913
5914 mlx5e_create_q_counters(priv);
5915
5916 err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
5917 if (err) {
5918 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
5919 goto err_destroy_q_counters;
5920 }
5921
5922 features = MLX5E_RX_RES_FEATURE_PTP;
5923 if (mlx5_tunnel_inner_ft_supported(mdev))
5924 features |= MLX5E_RX_RES_FEATURE_INNER_FT;
5925 if (mlx5_get_sd(priv->mdev))
5926 features |= MLX5E_RX_RES_FEATURE_MULTI_VHCA;
5927
5928 priv->rx_res = mlx5e_rx_res_create(priv->mdev, features, priv->max_nch, priv->drop_rq.rqn,
5929 &priv->channels.params.packet_merge,
5930 priv->channels.params.num_channels);
5931 if (IS_ERR(priv->rx_res)) {
5932 err = PTR_ERR(priv->rx_res);
5933 priv->rx_res = NULL;
5934 mlx5_core_err(mdev, "create rx resources failed, %d\n", err);
5935 goto err_close_drop_rq;
5936 }
5937
5938 err = mlx5e_create_flow_steering(priv->fs, priv->rx_res, priv->profile,
5939 priv->netdev);
5940 if (err) {
5941 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
5942 goto err_destroy_rx_res;
5943 }
5944
5945 err = mlx5e_tc_nic_init(priv);
5946 if (err)
5947 goto err_destroy_flow_steering;
5948
5949 err = mlx5e_accel_init_rx(priv);
5950 if (err)
5951 goto err_tc_nic_cleanup;
5952
5953 #ifdef CONFIG_MLX5_EN_ARFS
5954 priv->netdev->rx_cpu_rmap = mlx5_eq_table_get_rmap(priv->mdev);
5955 #endif
5956
5957 return 0;
5958
5959 err_tc_nic_cleanup:
5960 mlx5e_tc_nic_cleanup(priv);
5961 err_destroy_flow_steering:
5962 mlx5e_destroy_flow_steering(priv->fs, mlx5e_fs_has_arfs(priv->netdev),
5963 priv->profile);
5964 err_destroy_rx_res:
5965 mlx5e_rx_res_destroy(priv->rx_res);
5966 priv->rx_res = NULL;
5967 err_close_drop_rq:
5968 mlx5e_close_drop_rq(&priv->drop_rq);
5969 err_destroy_q_counters:
5970 mlx5e_destroy_q_counters(priv);
5971 return err;
5972 }
5973
mlx5e_cleanup_nic_rx(struct mlx5e_priv * priv)5974 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
5975 {
5976 mlx5e_accel_cleanup_rx(priv);
5977 mlx5e_tc_nic_cleanup(priv);
5978 mlx5e_destroy_flow_steering(priv->fs, mlx5e_fs_has_arfs(priv->netdev),
5979 priv->profile);
5980 mlx5e_rx_res_destroy(priv->rx_res);
5981 priv->rx_res = NULL;
5982 mlx5e_close_drop_rq(&priv->drop_rq);
5983 mlx5e_destroy_q_counters(priv);
5984 }
5985
mlx5e_set_mqprio_rl(struct mlx5e_priv * priv)5986 static void mlx5e_set_mqprio_rl(struct mlx5e_priv *priv)
5987 {
5988 struct mlx5e_params *params;
5989 struct mlx5e_mqprio_rl *rl;
5990
5991 params = &priv->channels.params;
5992 if (params->mqprio.mode != TC_MQPRIO_MODE_CHANNEL)
5993 return;
5994
5995 rl = mlx5e_mqprio_rl_create(priv->mdev, params->mqprio.num_tc,
5996 params->mqprio.channel.max_rate);
5997 if (IS_ERR(rl))
5998 rl = NULL;
5999 priv->mqprio_rl = rl;
6000 mlx5e_mqprio_rl_update_params(params, rl);
6001 }
6002
mlx5e_init_nic_tx(struct mlx5e_priv * priv)6003 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
6004 {
6005 int err;
6006
6007 err = mlx5e_accel_init_tx(priv);
6008 if (err)
6009 return err;
6010
6011 mlx5e_set_mqprio_rl(priv);
6012 mlx5e_dcbnl_initialize(priv);
6013 return 0;
6014 }
6015
mlx5e_nic_enable(struct mlx5e_priv * priv)6016 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
6017 {
6018 struct net_device *netdev = priv->netdev;
6019 struct mlx5_core_dev *mdev = priv->mdev;
6020 int err;
6021
6022 mlx5e_fs_init_l2_addr(priv->fs, netdev);
6023 mlx5e_ipsec_init(priv);
6024
6025 err = mlx5e_macsec_init(priv);
6026 if (err)
6027 mlx5_core_err(mdev, "MACsec initialization failed, %d\n", err);
6028
6029 /* Marking the link as currently not needed by the Driver */
6030 if (!netif_running(netdev))
6031 mlx5e_modify_admin_state(mdev, MLX5_PORT_DOWN);
6032
6033 mlx5e_set_netdev_mtu_boundaries(priv);
6034 mlx5e_set_dev_port_mtu(priv);
6035
6036 mlx5_lag_add_netdev(mdev, netdev);
6037
6038 mlx5e_enable_async_events(priv);
6039 mlx5e_enable_blocking_events(priv);
6040 if (mlx5e_monitor_counter_supported(priv))
6041 mlx5e_monitor_counter_init(priv);
6042
6043 mlx5e_pcie_cong_event_init(priv);
6044 mlx5e_hv_vhca_stats_create(priv);
6045 if (netdev->reg_state != NETREG_REGISTERED)
6046 return;
6047 mlx5e_dcbnl_init_app(priv);
6048
6049 mlx5e_nic_set_rx_mode(priv);
6050
6051 rtnl_lock();
6052 netdev_lock(netdev);
6053 if (netif_running(netdev))
6054 mlx5e_open(netdev);
6055 udp_tunnel_nic_reset_ntf(priv->netdev);
6056 netdev_unlock(netdev);
6057 netif_device_attach(netdev);
6058 rtnl_unlock();
6059 }
6060
mlx5e_nic_disable(struct mlx5e_priv * priv)6061 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
6062 {
6063 struct mlx5_core_dev *mdev = priv->mdev;
6064
6065 if (priv->netdev->reg_state == NETREG_REGISTERED)
6066 mlx5e_dcbnl_delete_app(priv);
6067
6068 rtnl_lock();
6069 netdev_lock(priv->netdev);
6070 if (netif_running(priv->netdev))
6071 mlx5e_close(priv->netdev);
6072 netif_device_detach(priv->netdev);
6073 if (priv->en_trap) {
6074 mlx5e_deactivate_trap(priv);
6075 mlx5e_close_trap(priv->en_trap);
6076 priv->en_trap = NULL;
6077 }
6078 netdev_unlock(priv->netdev);
6079 rtnl_unlock();
6080
6081 mlx5e_nic_set_rx_mode(priv);
6082
6083 mlx5e_pcie_cong_event_cleanup(priv);
6084 mlx5e_hv_vhca_stats_destroy(priv);
6085 if (mlx5e_monitor_counter_supported(priv))
6086 mlx5e_monitor_counter_cleanup(priv);
6087
6088 mlx5e_disable_blocking_events(priv);
6089 mlx5e_disable_async_events(priv);
6090 mlx5_lag_remove_netdev(mdev, priv->netdev);
6091 mlx5_vxlan_reset_to_default(mdev->vxlan);
6092 mlx5e_macsec_cleanup(priv);
6093 mlx5e_ipsec_cleanup(priv);
6094 }
6095
mlx5e_update_nic_rx(struct mlx5e_priv * priv)6096 static int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
6097 {
6098 return mlx5e_refresh_tirs(priv, false, false);
6099 }
6100
6101 static const struct mlx5e_profile mlx5e_nic_profile = {
6102 .init = mlx5e_nic_init,
6103 .cleanup = mlx5e_nic_cleanup,
6104 .init_rx = mlx5e_init_nic_rx,
6105 .cleanup_rx = mlx5e_cleanup_nic_rx,
6106 .init_tx = mlx5e_init_nic_tx,
6107 .cleanup_tx = mlx5e_cleanup_nic_tx,
6108 .enable = mlx5e_nic_enable,
6109 .disable = mlx5e_nic_disable,
6110 .update_rx = mlx5e_update_nic_rx,
6111 .update_stats = mlx5e_stats_update_ndo_stats,
6112 .update_carrier = mlx5e_update_carrier,
6113 .rx_handlers = &mlx5e_rx_handlers_nic,
6114 .max_tc = MLX5_MAX_NUM_TC,
6115 .stats_grps = mlx5e_nic_stats_grps,
6116 .stats_grps_num = mlx5e_nic_stats_grps_num,
6117 .features = BIT(MLX5E_PROFILE_FEATURE_PTP_RX) |
6118 BIT(MLX5E_PROFILE_FEATURE_PTP_TX) |
6119 BIT(MLX5E_PROFILE_FEATURE_QOS_HTB) |
6120 BIT(MLX5E_PROFILE_FEATURE_FS_VLAN) |
6121 BIT(MLX5E_PROFILE_FEATURE_FS_TC),
6122 };
6123
mlx5e_profile_max_num_channels(struct mlx5_core_dev * mdev,const struct mlx5e_profile * profile)6124 static int mlx5e_profile_max_num_channels(struct mlx5_core_dev *mdev,
6125 const struct mlx5e_profile *profile)
6126 {
6127 int nch;
6128
6129 nch = mlx5e_get_max_num_channels(mdev);
6130
6131 if (profile->max_nch_limit)
6132 nch = min_t(int, nch, profile->max_nch_limit(mdev));
6133 return nch;
6134 }
6135
6136 static unsigned int
mlx5e_calc_max_nch(struct mlx5_core_dev * mdev,struct net_device * netdev,const struct mlx5e_profile * profile)6137 mlx5e_calc_max_nch(struct mlx5_core_dev *mdev, struct net_device *netdev,
6138 const struct mlx5e_profile *profile)
6139
6140 {
6141 unsigned int max_nch, tmp;
6142
6143 /* core resources */
6144 max_nch = mlx5e_profile_max_num_channels(mdev, profile);
6145
6146 /* netdev rx queues */
6147 max_nch = min_t(unsigned int, max_nch, netdev->num_rx_queues);
6148
6149 /* netdev tx queues */
6150 tmp = netdev->num_tx_queues;
6151 if (mlx5_qos_is_supported(mdev))
6152 tmp -= mlx5e_qos_max_leaf_nodes(mdev);
6153 if (MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn))
6154 tmp -= profile->max_tc;
6155 tmp = tmp / profile->max_tc;
6156 max_nch = min_t(unsigned int, max_nch, tmp);
6157
6158 return max_nch;
6159 }
6160
mlx5e_get_pf_num_tirs(struct mlx5_core_dev * mdev)6161 int mlx5e_get_pf_num_tirs(struct mlx5_core_dev *mdev)
6162 {
6163 /* Indirect TIRS: 2 sets of TTCs (inner + outer steering)
6164 * and 1 set of direct TIRS
6165 */
6166 return 2 * MLX5E_NUM_INDIR_TIRS
6167 + mlx5e_profile_max_num_channels(mdev, &mlx5e_nic_profile);
6168 }
6169
mlx5e_set_rx_mode_work(struct work_struct * work)6170 void mlx5e_set_rx_mode_work(struct work_struct *work)
6171 {
6172 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
6173 set_rx_mode_work);
6174
6175 return mlx5e_fs_set_rx_mode_work(priv->fs, priv->netdev);
6176 }
6177
6178 /* mlx5e generic netdev management API (move to en_common.c) */
mlx5e_priv_init(struct mlx5e_priv * priv,const struct mlx5e_profile * profile,struct net_device * netdev,struct mlx5_core_dev * mdev)6179 int mlx5e_priv_init(struct mlx5e_priv *priv,
6180 const struct mlx5e_profile *profile,
6181 struct net_device *netdev,
6182 struct mlx5_core_dev *mdev)
6183 {
6184 int nch, num_txqs, node;
6185 int err;
6186
6187 num_txqs = netdev->num_tx_queues;
6188 nch = mlx5e_calc_max_nch(mdev, netdev, profile);
6189 node = dev_to_node(mlx5_core_dma_dev(mdev));
6190
6191 /* priv init */
6192 priv->mdev = mdev;
6193 priv->netdev = netdev;
6194 priv->max_nch = nch;
6195 priv->max_opened_tc = 1;
6196
6197 if (!alloc_cpumask_var(&priv->scratchpad.cpumask, GFP_KERNEL))
6198 return -ENOMEM;
6199
6200 mutex_init(&priv->state_lock);
6201
6202 err = mlx5e_selq_init(&priv->selq, &priv->state_lock);
6203 if (err)
6204 goto err_free_cpumask;
6205
6206 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
6207 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
6208 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
6209 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
6210
6211 priv->wq = create_singlethread_workqueue("mlx5e");
6212 if (!priv->wq)
6213 goto err_free_selq;
6214
6215 priv->txq2sq = kcalloc_node(num_txqs, sizeof(*priv->txq2sq), GFP_KERNEL, node);
6216 if (!priv->txq2sq)
6217 goto err_destroy_workqueue;
6218
6219 priv->txq2sq_stats = kcalloc_node(num_txqs, sizeof(*priv->txq2sq_stats), GFP_KERNEL, node);
6220 if (!priv->txq2sq_stats)
6221 goto err_free_txq2sq;
6222
6223 priv->tx_rates = kcalloc_node(num_txqs, sizeof(*priv->tx_rates), GFP_KERNEL, node);
6224 if (!priv->tx_rates)
6225 goto err_free_txq2sq_stats;
6226
6227 priv->channel_stats =
6228 kcalloc_node(nch, sizeof(*priv->channel_stats), GFP_KERNEL, node);
6229 if (!priv->channel_stats)
6230 goto err_free_tx_rates;
6231
6232 return 0;
6233
6234 err_free_tx_rates:
6235 kfree(priv->tx_rates);
6236 err_free_txq2sq_stats:
6237 kfree(priv->txq2sq_stats);
6238 err_free_txq2sq:
6239 kfree(priv->txq2sq);
6240 err_destroy_workqueue:
6241 destroy_workqueue(priv->wq);
6242 err_free_selq:
6243 mlx5e_selq_cleanup(&priv->selq);
6244 err_free_cpumask:
6245 free_cpumask_var(priv->scratchpad.cpumask);
6246 return -ENOMEM;
6247 }
6248
mlx5e_priv_cleanup(struct mlx5e_priv * priv)6249 void mlx5e_priv_cleanup(struct mlx5e_priv *priv)
6250 {
6251 int i;
6252
6253 /* bail if change profile failed and also rollback failed */
6254 if (!priv->mdev)
6255 return;
6256
6257 for (i = 0; i < priv->stats_nch; i++)
6258 kvfree(priv->channel_stats[i]);
6259 kfree(priv->channel_stats);
6260 kfree(priv->tx_rates);
6261 kfree(priv->txq2sq_stats);
6262 kfree(priv->txq2sq);
6263 destroy_workqueue(priv->wq);
6264 mlx5e_selq_cleanup(&priv->selq);
6265 free_cpumask_var(priv->scratchpad.cpumask);
6266
6267 for (i = 0; i < priv->htb_max_qos_sqs; i++)
6268 kfree(priv->htb_qos_sq_stats[i]);
6269 kvfree(priv->htb_qos_sq_stats);
6270
6271 if (priv->mqprio_rl) {
6272 mlx5e_mqprio_rl_cleanup(priv->mqprio_rl);
6273 mlx5e_mqprio_rl_free(priv->mqprio_rl);
6274 }
6275
6276 memset(priv, 0, sizeof(*priv));
6277 }
6278
mlx5e_get_max_num_txqs(struct mlx5_core_dev * mdev,const struct mlx5e_profile * profile)6279 static unsigned int mlx5e_get_max_num_txqs(struct mlx5_core_dev *mdev,
6280 const struct mlx5e_profile *profile)
6281 {
6282 unsigned int nch, ptp_txqs, qos_txqs;
6283
6284 nch = mlx5e_profile_max_num_channels(mdev, profile);
6285
6286 ptp_txqs = MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn) &&
6287 mlx5e_profile_feature_cap(profile, PTP_TX) ?
6288 profile->max_tc : 0;
6289
6290 qos_txqs = mlx5_qos_is_supported(mdev) &&
6291 mlx5e_profile_feature_cap(profile, QOS_HTB) ?
6292 mlx5e_qos_max_leaf_nodes(mdev) : 0;
6293
6294 return nch * profile->max_tc + ptp_txqs + qos_txqs;
6295 }
6296
mlx5e_get_max_num_rxqs(struct mlx5_core_dev * mdev,const struct mlx5e_profile * profile)6297 static unsigned int mlx5e_get_max_num_rxqs(struct mlx5_core_dev *mdev,
6298 const struct mlx5e_profile *profile)
6299 {
6300 return mlx5e_profile_max_num_channels(mdev, profile);
6301 }
6302
6303 struct net_device *
mlx5e_create_netdev(struct mlx5_core_dev * mdev,const struct mlx5e_profile * profile)6304 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile)
6305 {
6306 struct net_device *netdev;
6307 unsigned int txqs, rxqs;
6308 int err;
6309
6310 txqs = mlx5e_get_max_num_txqs(mdev, profile);
6311 rxqs = mlx5e_get_max_num_rxqs(mdev, profile);
6312
6313 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), txqs, rxqs);
6314 if (!netdev) {
6315 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
6316 return NULL;
6317 }
6318
6319 err = mlx5e_priv_init(netdev_priv(netdev), profile, netdev, mdev);
6320 if (err) {
6321 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
6322 goto err_free_netdev;
6323 }
6324
6325 netif_carrier_off(netdev);
6326 netif_tx_disable(netdev);
6327 dev_net_set(netdev, mlx5_core_net(mdev));
6328
6329 return netdev;
6330
6331 err_free_netdev:
6332 free_netdev(netdev);
6333
6334 return NULL;
6335 }
6336
mlx5e_update_features(struct net_device * netdev)6337 static void mlx5e_update_features(struct net_device *netdev)
6338 {
6339 if (netdev->reg_state != NETREG_REGISTERED)
6340 return; /* features will be updated on netdev registration */
6341
6342 rtnl_lock();
6343 netdev_lock(netdev);
6344 netdev_update_features(netdev);
6345 netdev_unlock(netdev);
6346 rtnl_unlock();
6347 }
6348
mlx5e_reset_channels(struct net_device * netdev)6349 static void mlx5e_reset_channels(struct net_device *netdev)
6350 {
6351 netdev_reset_tc(netdev);
6352 }
6353
mlx5e_attach_netdev(struct mlx5e_priv * priv)6354 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
6355 {
6356 const bool need_lock = priv->netdev->reg_state == NETREG_REGISTERED;
6357 const struct mlx5e_profile *profile = priv->profile;
6358 int max_nch;
6359 int err;
6360
6361 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
6362 if (priv->fs)
6363 mlx5e_fs_set_state_destroy(priv->fs,
6364 !test_bit(MLX5E_STATE_DESTROYING, &priv->state));
6365
6366 /* Validate the max_wqe_size_sq capability. */
6367 if (WARN_ON_ONCE(mlx5e_get_max_sq_wqebbs(priv->mdev) < MLX5E_MAX_TX_WQEBBS)) {
6368 mlx5_core_warn(priv->mdev, "MLX5E: Max SQ WQEBBs firmware capability: %u, needed %u\n",
6369 mlx5e_get_max_sq_wqebbs(priv->mdev), (unsigned int)MLX5E_MAX_TX_WQEBBS);
6370 return -EIO;
6371 }
6372
6373 /* max number of channels may have changed */
6374 max_nch = mlx5e_calc_max_nch(priv->mdev, priv->netdev, profile);
6375 if (priv->channels.params.num_channels > max_nch) {
6376 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
6377 /* Reducing the number of channels - RXFH has to be reset, and
6378 * mlx5e_num_channels_changed below will build the RQT.
6379 */
6380 priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED;
6381 priv->channels.params.num_channels = max_nch;
6382 if (priv->channels.params.mqprio.mode == TC_MQPRIO_MODE_CHANNEL) {
6383 mlx5_core_warn(priv->mdev, "MLX5E: Disabling MQPRIO channel mode\n");
6384 mlx5e_params_mqprio_reset(&priv->channels.params);
6385 }
6386 }
6387 if (max_nch != priv->max_nch) {
6388 mlx5_core_warn(priv->mdev,
6389 "MLX5E: Updating max number of channels from %u to %u\n",
6390 priv->max_nch, max_nch);
6391 priv->max_nch = max_nch;
6392 }
6393
6394 /* 1. Set the real number of queues in the kernel the first time.
6395 * 2. Set our default XPS cpumask.
6396 * 3. Build the RQT.
6397 *
6398 * Locking is required by netif_set_real_num_*_queues in case the
6399 * netdev has been registered by this point (if this function was called
6400 * in the reload or resume flow).
6401 */
6402 if (need_lock) {
6403 rtnl_lock();
6404 netdev_lock(priv->netdev);
6405 }
6406 err = mlx5e_num_channels_changed(priv);
6407 if (need_lock) {
6408 netdev_unlock(priv->netdev);
6409 rtnl_unlock();
6410 }
6411 if (err)
6412 goto out;
6413
6414 err = profile->init_tx(priv);
6415 if (err)
6416 goto out;
6417
6418 err = profile->init_rx(priv);
6419 if (err)
6420 goto err_cleanup_tx;
6421
6422 if (profile->enable)
6423 profile->enable(priv);
6424
6425 mlx5e_update_features(priv->netdev);
6426
6427 return 0;
6428
6429 err_cleanup_tx:
6430 profile->cleanup_tx(priv);
6431
6432 out:
6433 mlx5e_reset_channels(priv->netdev);
6434 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
6435 if (priv->fs)
6436 mlx5e_fs_set_state_destroy(priv->fs,
6437 !test_bit(MLX5E_STATE_DESTROYING, &priv->state));
6438 cancel_work_sync(&priv->update_stats_work);
6439 return err;
6440 }
6441
mlx5e_detach_netdev(struct mlx5e_priv * priv)6442 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
6443 {
6444 const struct mlx5e_profile *profile = priv->profile;
6445
6446 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
6447 if (priv->fs)
6448 mlx5e_fs_set_state_destroy(priv->fs,
6449 !test_bit(MLX5E_STATE_DESTROYING, &priv->state));
6450
6451 if (profile->disable)
6452 profile->disable(priv);
6453 flush_workqueue(priv->wq);
6454
6455 profile->cleanup_rx(priv);
6456 profile->cleanup_tx(priv);
6457 mlx5e_reset_channels(priv->netdev);
6458 cancel_work_sync(&priv->update_stats_work);
6459 }
6460
6461 static int
mlx5e_netdev_init_profile(struct net_device * netdev,struct mlx5_core_dev * mdev,const struct mlx5e_profile * new_profile,void * new_ppriv)6462 mlx5e_netdev_init_profile(struct net_device *netdev, struct mlx5_core_dev *mdev,
6463 const struct mlx5e_profile *new_profile, void *new_ppriv)
6464 {
6465 struct mlx5e_priv *priv = netdev_priv(netdev);
6466 int err;
6467
6468 err = mlx5e_priv_init(priv, new_profile, netdev, mdev);
6469 if (err) {
6470 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
6471 return err;
6472 }
6473 netif_carrier_off(netdev);
6474 priv->profile = new_profile;
6475 priv->ppriv = new_ppriv;
6476 err = new_profile->init(priv->mdev, priv->netdev);
6477 if (err)
6478 goto priv_cleanup;
6479
6480 return 0;
6481
6482 priv_cleanup:
6483 mlx5e_priv_cleanup(priv);
6484 return err;
6485 }
6486
6487 static int
mlx5e_netdev_attach_profile(struct net_device * netdev,struct mlx5_core_dev * mdev,const struct mlx5e_profile * new_profile,void * new_ppriv)6488 mlx5e_netdev_attach_profile(struct net_device *netdev, struct mlx5_core_dev *mdev,
6489 const struct mlx5e_profile *new_profile, void *new_ppriv)
6490 {
6491 struct mlx5e_priv *priv = netdev_priv(netdev);
6492 int err;
6493
6494 err = mlx5e_netdev_init_profile(netdev, mdev, new_profile, new_ppriv);
6495 if (err)
6496 return err;
6497
6498 err = mlx5e_attach_netdev(priv);
6499 if (err)
6500 goto profile_cleanup;
6501 return err;
6502
6503 profile_cleanup:
6504 new_profile->cleanup(priv);
6505 mlx5e_priv_cleanup(priv);
6506 return err;
6507 }
6508
mlx5e_netdev_change_profile(struct mlx5e_priv * priv,const struct mlx5e_profile * new_profile,void * new_ppriv)6509 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
6510 const struct mlx5e_profile *new_profile, void *new_ppriv)
6511 {
6512 const struct mlx5e_profile *orig_profile = priv->profile;
6513 struct net_device *netdev = priv->netdev;
6514 struct mlx5_core_dev *mdev = priv->mdev;
6515 void *orig_ppriv = priv->ppriv;
6516 int err, rollback_err;
6517
6518 /* cleanup old profile */
6519 mlx5e_detach_netdev(priv);
6520 priv->profile->cleanup(priv);
6521 mlx5e_priv_cleanup(priv);
6522
6523 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6524 mlx5e_netdev_init_profile(netdev, mdev, new_profile, new_ppriv);
6525 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
6526 return -EIO;
6527 }
6528
6529 err = mlx5e_netdev_attach_profile(netdev, mdev, new_profile, new_ppriv);
6530 if (err) { /* roll back to original profile */
6531 netdev_warn(netdev, "%s: new profile init failed, %d\n", __func__, err);
6532 goto rollback;
6533 }
6534
6535 return 0;
6536
6537 rollback:
6538 rollback_err = mlx5e_netdev_attach_profile(netdev, mdev, orig_profile, orig_ppriv);
6539 if (rollback_err)
6540 netdev_err(netdev, "%s: failed to rollback to orig profile, %d\n",
6541 __func__, rollback_err);
6542 return err;
6543 }
6544
mlx5e_netdev_attach_nic_profile(struct mlx5e_priv * priv)6545 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv)
6546 {
6547 mlx5e_netdev_change_profile(priv, &mlx5e_nic_profile, NULL);
6548 }
6549
mlx5e_destroy_netdev(struct mlx5e_priv * priv)6550 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
6551 {
6552 struct net_device *netdev = priv->netdev;
6553
6554 mlx5e_priv_cleanup(priv);
6555 free_netdev(netdev);
6556 }
6557
_mlx5e_resume(struct auxiliary_device * adev)6558 static int _mlx5e_resume(struct auxiliary_device *adev)
6559 {
6560 struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
6561 struct mlx5e_dev *mlx5e_dev = auxiliary_get_drvdata(adev);
6562 struct mlx5e_priv *priv = mlx5e_dev->priv;
6563 struct net_device *netdev = priv->netdev;
6564 struct mlx5_core_dev *mdev = edev->mdev;
6565 struct mlx5_core_dev *pos, *to;
6566 int err, i;
6567
6568 if (netif_device_present(netdev))
6569 return 0;
6570
6571 mlx5_sd_for_each_dev(i, mdev, pos) {
6572 err = mlx5e_create_mdev_resources(pos, true);
6573 if (err)
6574 goto err_destroy_mdev_res;
6575 }
6576
6577 err = mlx5e_attach_netdev(priv);
6578 if (err)
6579 goto err_destroy_mdev_res;
6580
6581 return 0;
6582
6583 err_destroy_mdev_res:
6584 to = pos;
6585 mlx5_sd_for_each_dev_to(i, mdev, to, pos)
6586 mlx5e_destroy_mdev_resources(pos);
6587 return err;
6588 }
6589
mlx5e_resume(struct auxiliary_device * adev)6590 static int mlx5e_resume(struct auxiliary_device *adev)
6591 {
6592 struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
6593 struct mlx5_core_dev *mdev = edev->mdev;
6594 struct auxiliary_device *actual_adev;
6595 int err;
6596
6597 err = mlx5_sd_init(mdev);
6598 if (err)
6599 return err;
6600
6601 actual_adev = mlx5_sd_get_adev(mdev, adev, edev->idx);
6602 if (actual_adev)
6603 return _mlx5e_resume(actual_adev);
6604 return 0;
6605 }
6606
_mlx5e_suspend(struct auxiliary_device * adev,bool pre_netdev_reg)6607 static int _mlx5e_suspend(struct auxiliary_device *adev, bool pre_netdev_reg)
6608 {
6609 struct mlx5e_dev *mlx5e_dev = auxiliary_get_drvdata(adev);
6610 struct mlx5e_priv *priv = mlx5e_dev->priv;
6611 struct net_device *netdev = priv->netdev;
6612 struct mlx5_core_dev *mdev = priv->mdev;
6613 struct mlx5_core_dev *pos;
6614 int i;
6615
6616 if (!pre_netdev_reg && !netif_device_present(netdev)) {
6617 if (test_bit(MLX5E_STATE_DESTROYING, &priv->state))
6618 mlx5_sd_for_each_dev(i, mdev, pos)
6619 mlx5e_destroy_mdev_resources(pos);
6620 return -ENODEV;
6621 }
6622
6623 mlx5e_detach_netdev(priv);
6624 mlx5_sd_for_each_dev(i, mdev, pos)
6625 mlx5e_destroy_mdev_resources(pos);
6626
6627 return 0;
6628 }
6629
mlx5e_suspend(struct auxiliary_device * adev,pm_message_t state)6630 static int mlx5e_suspend(struct auxiliary_device *adev, pm_message_t state)
6631 {
6632 struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
6633 struct mlx5_core_dev *mdev = edev->mdev;
6634 struct auxiliary_device *actual_adev;
6635 int err = 0;
6636
6637 actual_adev = mlx5_sd_get_adev(mdev, adev, edev->idx);
6638 if (actual_adev)
6639 err = _mlx5e_suspend(actual_adev, false);
6640
6641 mlx5_sd_cleanup(mdev);
6642 return err;
6643 }
6644
_mlx5e_probe(struct auxiliary_device * adev)6645 static int _mlx5e_probe(struct auxiliary_device *adev)
6646 {
6647 struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
6648 const struct mlx5e_profile *profile = &mlx5e_nic_profile;
6649 struct mlx5_core_dev *mdev = edev->mdev;
6650 struct mlx5e_dev *mlx5e_dev;
6651 struct net_device *netdev;
6652 struct mlx5e_priv *priv;
6653 int err;
6654
6655 mlx5e_dev = mlx5e_create_devlink(&adev->dev, mdev);
6656 if (IS_ERR(mlx5e_dev))
6657 return PTR_ERR(mlx5e_dev);
6658 auxiliary_set_drvdata(adev, mlx5e_dev);
6659
6660 err = mlx5e_devlink_port_register(mlx5e_dev, mdev);
6661 if (err) {
6662 mlx5_core_err(mdev, "mlx5e_devlink_port_register failed, %d\n", err);
6663 goto err_devlink_unregister;
6664 }
6665
6666 netdev = mlx5e_create_netdev(mdev, profile);
6667 if (!netdev) {
6668 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
6669 err = -ENOMEM;
6670 goto err_devlink_port_unregister;
6671 }
6672 SET_NETDEV_DEVLINK_PORT(netdev, &mlx5e_dev->dl_port);
6673
6674 mlx5e_build_nic_netdev(netdev);
6675
6676 priv = netdev_priv(netdev);
6677 mlx5e_dev->priv = priv;
6678
6679 priv->profile = profile;
6680 priv->ppriv = NULL;
6681
6682 err = profile->init(mdev, netdev);
6683 if (err) {
6684 mlx5_core_err(mdev, "mlx5e_nic_profile init failed, %d\n", err);
6685 goto err_destroy_netdev;
6686 }
6687
6688 err = _mlx5e_resume(adev);
6689 if (err) {
6690 mlx5_core_err(mdev, "_mlx5e_resume failed, %d\n", err);
6691 goto err_profile_cleanup;
6692 }
6693
6694 err = register_netdev(netdev);
6695 if (err) {
6696 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
6697 goto err_resume;
6698 }
6699
6700 mlx5e_dcbnl_init_app(priv);
6701 mlx5_core_uplink_netdev_set(mdev, netdev);
6702 mlx5e_params_print_info(mdev, &priv->channels.params);
6703 return 0;
6704
6705 err_resume:
6706 _mlx5e_suspend(adev, true);
6707 err_profile_cleanup:
6708 profile->cleanup(priv);
6709 err_destroy_netdev:
6710 mlx5e_destroy_netdev(priv);
6711 err_devlink_port_unregister:
6712 mlx5e_devlink_port_unregister(mlx5e_dev);
6713 err_devlink_unregister:
6714 mlx5e_destroy_devlink(mlx5e_dev);
6715 return err;
6716 }
6717
mlx5e_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)6718 static int mlx5e_probe(struct auxiliary_device *adev,
6719 const struct auxiliary_device_id *id)
6720 {
6721 struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
6722 struct mlx5_core_dev *mdev = edev->mdev;
6723 struct auxiliary_device *actual_adev;
6724 int err;
6725
6726 err = mlx5_sd_init(mdev);
6727 if (err)
6728 return err;
6729
6730 actual_adev = mlx5_sd_get_adev(mdev, adev, edev->idx);
6731 if (actual_adev)
6732 return _mlx5e_probe(actual_adev);
6733 return 0;
6734 }
6735
_mlx5e_remove(struct auxiliary_device * adev)6736 static void _mlx5e_remove(struct auxiliary_device *adev)
6737 {
6738 struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
6739 struct mlx5e_dev *mlx5e_dev = auxiliary_get_drvdata(adev);
6740 struct mlx5e_priv *priv = mlx5e_dev->priv;
6741 struct mlx5_core_dev *mdev = edev->mdev;
6742
6743 mlx5_core_uplink_netdev_set(mdev, NULL);
6744 mlx5e_dcbnl_delete_app(priv);
6745 /* When unload driver, the netdev is in registered state
6746 * if it's from legacy mode. If from switchdev mode, it
6747 * is already unregistered before changing to NIC profile.
6748 */
6749 if (priv->netdev->reg_state == NETREG_REGISTERED) {
6750 unregister_netdev(priv->netdev);
6751 _mlx5e_suspend(adev, false);
6752 } else {
6753 struct mlx5_core_dev *pos;
6754 int i;
6755
6756 if (test_bit(MLX5E_STATE_DESTROYING, &priv->state))
6757 mlx5_sd_for_each_dev(i, mdev, pos)
6758 mlx5e_destroy_mdev_resources(pos);
6759 else
6760 _mlx5e_suspend(adev, true);
6761 }
6762 /* Avoid cleanup if profile rollback failed. */
6763 if (priv->profile)
6764 priv->profile->cleanup(priv);
6765 mlx5e_destroy_netdev(priv);
6766 mlx5e_devlink_port_unregister(mlx5e_dev);
6767 mlx5e_destroy_devlink(mlx5e_dev);
6768 }
6769
mlx5e_remove(struct auxiliary_device * adev)6770 static void mlx5e_remove(struct auxiliary_device *adev)
6771 {
6772 struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
6773 struct mlx5_core_dev *mdev = edev->mdev;
6774 struct auxiliary_device *actual_adev;
6775
6776 actual_adev = mlx5_sd_get_adev(mdev, adev, edev->idx);
6777 if (actual_adev)
6778 _mlx5e_remove(actual_adev);
6779
6780 mlx5_sd_cleanup(mdev);
6781 }
6782
6783 static const struct auxiliary_device_id mlx5e_id_table[] = {
6784 { .name = MLX5_ADEV_NAME ".eth", },
6785 {},
6786 };
6787
6788 MODULE_DEVICE_TABLE(auxiliary, mlx5e_id_table);
6789
6790 static struct auxiliary_driver mlx5e_driver = {
6791 .name = "eth",
6792 .probe = mlx5e_probe,
6793 .remove = mlx5e_remove,
6794 .suspend = mlx5e_suspend,
6795 .resume = mlx5e_resume,
6796 .id_table = mlx5e_id_table,
6797 };
6798
mlx5e_init(void)6799 int mlx5e_init(void)
6800 {
6801 int ret;
6802
6803 mlx5e_build_ptys2ethtool_map();
6804 ret = auxiliary_driver_register(&mlx5e_driver);
6805 if (ret)
6806 return ret;
6807
6808 ret = mlx5e_rep_init();
6809 if (ret)
6810 auxiliary_driver_unregister(&mlx5e_driver);
6811 return ret;
6812 }
6813
mlx5e_cleanup(void)6814 void mlx5e_cleanup(void)
6815 {
6816 mlx5e_rep_cleanup();
6817 auxiliary_driver_unregister(&mlx5e_driver);
6818 }
6819