xref: /linux/drivers/net/ethernet/mellanox/mlx5/core/en.h (revision 8be4d31cb8aaeea27bde4b7ddb26e28a89062ebf)
1 /*
2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 #ifndef __MLX5_EN_H__
33 #define __MLX5_EN_H__
34 
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/crash_dump.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
46 #include <linux/mlx5/fs.h>
47 #include <linux/rhashtable.h>
48 #include <net/udp_tunnel.h>
49 #include <net/switchdev.h>
50 #include <net/xdp.h>
51 #include <linux/dim.h>
52 #include <linux/bits.h>
53 #include "wq.h"
54 #include "mlx5_core.h"
55 #include "en_stats.h"
56 #include "en/dcbnl.h"
57 #include "en/fs.h"
58 #include "en/qos.h"
59 #include "lib/hv_vhca.h"
60 #include "lib/clock.h"
61 #include "en/rx_res.h"
62 #include "en/selq.h"
63 #include "lib/sd.h"
64 
65 extern const struct net_device_ops mlx5e_netdev_ops;
66 struct page_pool;
67 
68 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4)
69 #define MLX5E_METADATA_ETHER_LEN 8
70 
71 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
72 
73 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu))
74 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu))
75 
76 #define MLX5E_MAX_NUM_MQPRIO_CH_TC TC_QOPT_MAX_QUEUE
77 
78 #define MLX5_RX_HEADROOM NET_SKB_PAD
79 #define MLX5_SKB_FRAG_SZ(len)	(SKB_DATA_ALIGN(len) +	\
80 				 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
81 
82 #define MLX5E_RX_MAX_HEAD (256)
83 #define MLX5E_SHAMPO_LOG_HEADER_ENTRY_SIZE (8)
84 #define MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE (9)
85 #define MLX5E_SHAMPO_WQ_HEADER_PER_PAGE (PAGE_SIZE >> MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE)
86 #define MLX5E_SHAMPO_LOG_WQ_HEADER_PER_PAGE (PAGE_SHIFT - MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE)
87 #define MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE_SHIFT (6)
88 #define MLX5E_SHAMPO_WQ_RESRV_SIZE_BASE_SHIFT (12)
89 #define MLX5E_SHAMPO_WQ_LOG_RESRV_SIZE (16)
90 #define MLX5E_SHAMPO_WQ_RESRV_SIZE BIT(MLX5E_SHAMPO_WQ_LOG_RESRV_SIZE)
91 
92 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
93 	(6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
94 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
95 	max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
96 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \
97 	MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD))
98 
99 /* Keep in sync with mlx5e_mpwrq_log_wqe_sz.
100  * These are theoretical maximums, which can be further restricted by
101  * capabilities. These values are used for static resource allocations and
102  * sanity checks.
103  * MLX5_SEND_WQE_MAX_SIZE is a bit bigger than the maximum cacheline-aligned WQE
104  * size actually used at runtime, but it's not a problem when calculating static
105  * array sizes.
106  */
107 #define MLX5_UMR_MAX_FLEX_SPACE \
108 	(ALIGN_DOWN(MLX5_SEND_WQE_MAX_SIZE - sizeof(struct mlx5e_umr_wqe), \
109 		    MLX5_UMR_FLEX_ALIGNMENT))
110 #define MLX5_MPWRQ_MAX_PAGES_PER_WQE \
111 	rounddown_pow_of_two(MLX5_UMR_MAX_FLEX_SPACE / sizeof(struct mlx5_mtt))
112 
113 #define MLX5E_MAX_RQ_NUM_MTTS	\
114 	(ALIGN_DOWN(U16_MAX, 4) * 2) /* Fits into u16 and aligned by WQEBB. */
115 #define MLX5E_MAX_RQ_NUM_KSMS (U16_MAX - 1) /* So that num_ksms fits into u16. */
116 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024))
117 
118 #define MLX5E_MIN_SKB_FRAG_SZ		(MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM))
119 #define MLX5E_LOG_MAX_RX_WQE_BULK	\
120 	(ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ)))
121 
122 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE                0x6
123 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE                0xa
124 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE                0xd
125 
126 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK)
127 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE                0xa
128 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE		0xd
129 
130 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW            0x2
131 
132 #define MLX5E_DEFAULT_LRO_TIMEOUT                       32
133 #define MLX5E_DEFAULT_SHAMPO_TIMEOUT			1024
134 
135 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC      0x10
136 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
137 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS      0x20
138 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC      0x10
139 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
140 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS      0x20
141 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES                0x80
142 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW            0x2
143 
144 #define MLX5E_MIN_NUM_CHANNELS         0x1
145 #define MLX5E_MAX_NUM_CHANNELS         256
146 #define MLX5E_TX_CQ_POLL_BUDGET        128
147 #define MLX5E_TX_XSK_POLL_BUDGET       64
148 #define MLX5E_SQ_RECOVER_MIN_INTERVAL  500 /* msecs */
149 
150 #define mlx5e_state_dereference(priv, p) \
151 	rcu_dereference_protected((p), lockdep_is_held(&(priv)->state_lock))
152 
153 enum mlx5e_devcom_events {
154 	MPV_DEVCOM_MASTER_UP,
155 	MPV_DEVCOM_MASTER_DOWN,
156 	MPV_DEVCOM_IPSEC_MASTER_UP,
157 	MPV_DEVCOM_IPSEC_MASTER_DOWN,
158 };
159 
mlx5e_get_num_lag_ports(struct mlx5_core_dev * mdev)160 static inline u8 mlx5e_get_num_lag_ports(struct mlx5_core_dev *mdev)
161 {
162 	if (mlx5_lag_is_lacp_owner(mdev))
163 		return 1;
164 
165 	return clamp_t(u8, MLX5_CAP_GEN(mdev, num_lag_ports), 1, MLX5_MAX_PORTS);
166 }
167 
mlx5_min_rx_wqes(int wq_type,u32 wq_size)168 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
169 {
170 	switch (wq_type) {
171 	case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
172 		return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
173 			     wq_size / 2);
174 	default:
175 		return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
176 			     wq_size / 2);
177 	}
178 }
179 
180 /* Use this function to get max num channels (rxqs/txqs) only to create netdev */
mlx5e_get_max_num_channels(struct mlx5_core_dev * mdev)181 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
182 {
183 	return is_kdump_kernel() ?
184 		MLX5E_MIN_NUM_CHANNELS :
185 		min3(mlx5_comp_vectors_max(mdev), (u32)MLX5E_MAX_NUM_CHANNELS,
186 		     (u32)(1 << MLX5_CAP_GEN(mdev, log_max_rqt_size)));
187 }
188 
189 /* The maximum WQE size can be retrieved by max_wqe_sz_sq in
190  * bytes units. Driver hardens the limitation to 1KB (16
191  * WQEBBs), unless firmware capability is stricter.
192  */
mlx5e_get_max_sq_wqebbs(struct mlx5_core_dev * mdev)193 static inline u8 mlx5e_get_max_sq_wqebbs(struct mlx5_core_dev *mdev)
194 {
195 	BUILD_BUG_ON(MLX5_SEND_WQE_MAX_WQEBBS > U8_MAX);
196 
197 	return (u8)min_t(u16, MLX5_SEND_WQE_MAX_WQEBBS,
198 			 MLX5_CAP_GEN(mdev, max_wqe_sz_sq) / MLX5_SEND_WQE_BB);
199 }
200 
mlx5e_get_max_sq_aligned_wqebbs(struct mlx5_core_dev * mdev)201 static inline u8 mlx5e_get_max_sq_aligned_wqebbs(struct mlx5_core_dev *mdev)
202 {
203 /* The return value will be multiplied by MLX5_SEND_WQEBB_NUM_DS.
204  * Since max_sq_wqebbs may be up to MLX5_SEND_WQE_MAX_WQEBBS == 16,
205  * see mlx5e_get_max_sq_wqebbs(), the multiplication (16 * 4 == 64)
206  * overflows the 6-bit DS field of Ctrl Segment. Use a bound lower
207  * than MLX5_SEND_WQE_MAX_WQEBBS to let a full-session WQE be
208  * cache-aligned.
209  */
210 	u8 wqebbs = mlx5e_get_max_sq_wqebbs(mdev);
211 
212 	wqebbs = min_t(u8, wqebbs, MLX5_SEND_WQE_MAX_WQEBBS - 1);
213 #if L1_CACHE_BYTES >= 128
214 	wqebbs = ALIGN_DOWN(wqebbs, 2);
215 #endif
216 	return wqebbs;
217 }
218 
219 struct mlx5e_tx_wqe {
220 	struct mlx5_wqe_ctrl_seg ctrl;
221 	struct mlx5_wqe_eth_seg  eth;
222 	struct mlx5_wqe_data_seg data[];
223 };
224 
225 struct mlx5e_rx_wqe_ll {
226 	struct mlx5_wqe_srq_next_seg  next;
227 	struct mlx5_wqe_data_seg      data[];
228 };
229 
230 struct mlx5e_rx_wqe_cyc {
231 	DECLARE_FLEX_ARRAY(struct mlx5_wqe_data_seg, data);
232 };
233 
234 struct mlx5e_umr_wqe_hdr {
235 	struct mlx5_wqe_ctrl_seg       ctrl;
236 	struct mlx5_wqe_umr_ctrl_seg   uctrl;
237 	struct mlx5_mkey_seg           mkc;
238 };
239 
240 struct mlx5e_umr_wqe {
241 	struct mlx5e_umr_wqe_hdr hdr;
242 	union {
243 		DECLARE_FLEX_ARRAY(struct mlx5_mtt, inline_mtts);
244 		DECLARE_FLEX_ARRAY(struct mlx5_klm, inline_klms);
245 		DECLARE_FLEX_ARRAY(struct mlx5_ksm, inline_ksms);
246 	};
247 };
248 static_assert(offsetof(struct mlx5e_umr_wqe, inline_mtts) == sizeof(struct mlx5e_umr_wqe_hdr),
249 	      "struct members should be included in struct mlx5e_umr_wqe_hdr, not in struct mlx5e_umr_wqe");
250 
251 enum mlx5e_priv_flag {
252 	MLX5E_PFLAG_RX_CQE_BASED_MODER,
253 	MLX5E_PFLAG_TX_CQE_BASED_MODER,
254 	MLX5E_PFLAG_RX_CQE_COMPRESS,
255 	MLX5E_PFLAG_RX_STRIDING_RQ,
256 	MLX5E_PFLAG_RX_NO_CSUM_COMPLETE,
257 	MLX5E_PFLAG_XDP_TX_MPWQE,
258 	MLX5E_PFLAG_SKB_TX_MPWQE,
259 	MLX5E_PFLAG_TX_PORT_TS,
260 	MLX5E_NUM_PFLAGS, /* Keep last */
261 };
262 
263 #define MLX5E_SET_PFLAG(params, pflag, enable)			\
264 	do {							\
265 		if (enable)					\
266 			(params)->pflags |= BIT(pflag);		\
267 		else						\
268 			(params)->pflags &= ~(BIT(pflag));	\
269 	} while (0)
270 
271 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag))))
272 
273 enum packet_merge {
274 	MLX5E_PACKET_MERGE_NONE,
275 	MLX5E_PACKET_MERGE_LRO,
276 	MLX5E_PACKET_MERGE_SHAMPO,
277 };
278 
279 struct mlx5e_packet_merge_param {
280 	enum packet_merge type;
281 	u32 timeout;
282 };
283 
284 struct mlx5e_params {
285 	u8  log_sq_size;
286 	u8  rq_wq_type;
287 	u8  log_rq_mtu_frames;
288 	u16 num_channels;
289 	struct {
290 		u16 mode;
291 		u8 num_tc;
292 		struct netdev_tc_txq tc_to_txq[TC_MAX_QUEUE];
293 		struct {
294 			u64 max_rate[TC_MAX_QUEUE];
295 			u32 hw_id[TC_MAX_QUEUE];
296 		} channel;
297 	} mqprio;
298 	bool rx_cqe_compress_def;
299 	struct dim_cq_moder rx_cq_moderation;
300 	struct dim_cq_moder tx_cq_moderation;
301 	struct mlx5e_packet_merge_param packet_merge;
302 	u8  tx_min_inline_mode;
303 	bool vlan_strip_disable;
304 	bool scatter_fcs_en;
305 	bool rx_dim_enabled;
306 	bool tx_dim_enabled;
307 	bool rx_moder_use_cqe_mode;
308 	bool tx_moder_use_cqe_mode;
309 	u32 pflags;
310 	struct bpf_prog *xdp_prog;
311 	struct mlx5e_xsk *xsk;
312 	unsigned int sw_mtu;
313 	int hard_mtu;
314 	bool ptp_rx;
315 	__be32 terminate_lkey_be;
316 };
317 
mlx5e_get_dcb_num_tc(struct mlx5e_params * params)318 static inline u8 mlx5e_get_dcb_num_tc(struct mlx5e_params *params)
319 {
320 	return params->mqprio.mode == TC_MQPRIO_MODE_DCB ?
321 		params->mqprio.num_tc : 1;
322 }
323 
324 /* Keep this enum consistent with the corresponding strings array
325  * declared in en/reporter_rx.c
326  */
327 enum {
328 	MLX5E_RQ_STATE_ENABLED = 0,
329 	MLX5E_RQ_STATE_RECOVERING,
330 	MLX5E_RQ_STATE_DIM,
331 	MLX5E_RQ_STATE_NO_CSUM_COMPLETE,
332 	MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */
333 	MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, /* set when mini_cqe_resp_stride_index cap is used */
334 	MLX5E_RQ_STATE_SHAMPO, /* set when SHAMPO cap is used */
335 	MLX5E_RQ_STATE_MINI_CQE_ENHANCED,  /* set when enhanced mini_cqe_cap is used */
336 	MLX5E_RQ_STATE_XSK, /* set to indicate an xsk rq */
337 	MLX5E_NUM_RQ_STATES, /* Must be kept last */
338 };
339 
340 struct mlx5e_cq {
341 	/* data path - accessed per cqe */
342 	struct mlx5_cqwq           wq;
343 
344 	/* data path - accessed per napi poll */
345 	u16                        event_ctr;
346 	struct napi_struct        *napi;
347 	struct mlx5_core_cq        mcq;
348 	struct mlx5e_ch_stats     *ch_stats;
349 
350 	/* control */
351 	struct net_device         *netdev;
352 	struct mlx5_core_dev      *mdev;
353 	struct workqueue_struct   *workqueue;
354 	struct mlx5_wq_ctrl        wq_ctrl;
355 } ____cacheline_aligned_in_smp;
356 
357 struct mlx5e_cq_decomp {
358 	/* cqe decompression */
359 	struct mlx5_cqe64          title;
360 	struct mlx5_mini_cqe8      mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
361 	u8                         mini_arr_idx;
362 	u16                        left;
363 	u16                        wqe_counter;
364 	bool                       last_cqe_title;
365 } ____cacheline_aligned_in_smp;
366 
367 enum mlx5e_dma_map_type {
368 	MLX5E_DMA_MAP_SINGLE,
369 	MLX5E_DMA_MAP_PAGE
370 };
371 
372 struct mlx5e_sq_dma {
373 	dma_addr_t              addr;
374 	u32                     size;
375 	enum mlx5e_dma_map_type type;
376 };
377 
378 /* Keep this enum consistent with the corresponding strings array
379  * declared in en/reporter_tx.c
380  */
381 enum {
382 	MLX5E_SQ_STATE_ENABLED = 0,
383 	MLX5E_SQ_STATE_MPWQE,
384 	MLX5E_SQ_STATE_RECOVERING,
385 	MLX5E_SQ_STATE_IPSEC,
386 	MLX5E_SQ_STATE_DIM,
387 	MLX5E_SQ_STATE_PENDING_XSK_TX,
388 	MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC,
389 	MLX5E_NUM_SQ_STATES, /* Must be kept last */
390 };
391 
392 struct mlx5e_tx_mpwqe {
393 	/* Current MPWQE session */
394 	struct mlx5e_tx_wqe *wqe;
395 	u32 bytes_count;
396 	u8 ds_count;
397 	u8 ds_count_max;
398 	u8 pkt_count;
399 	u8 inline_on;
400 };
401 
402 struct mlx5e_skb_fifo {
403 	struct sk_buff **fifo;
404 	u16 *pc;
405 	u16 *cc;
406 	u16 mask;
407 };
408 
409 struct mlx5e_ptpsq;
410 
411 struct mlx5e_txqsq {
412 	/* data path */
413 
414 	/* dirtied @completion */
415 	u16                        cc;
416 	u16                        skb_fifo_cc;
417 	u32                        dma_fifo_cc;
418 	struct dim                *dim; /* Adaptive Moderation */
419 
420 	/* dirtied @xmit */
421 	u16                        pc ____cacheline_aligned_in_smp;
422 	u16                        skb_fifo_pc;
423 	u32                        dma_fifo_pc;
424 	struct mlx5e_tx_mpwqe      mpwqe;
425 
426 	struct mlx5e_cq            cq;
427 
428 	/* read only */
429 	struct mlx5_wq_cyc         wq;
430 	u32                        dma_fifo_mask;
431 	struct mlx5e_sq_stats     *stats;
432 	struct {
433 		struct mlx5e_sq_dma       *dma_fifo;
434 		struct mlx5e_skb_fifo      skb_fifo;
435 		struct mlx5e_tx_wqe_info  *wqe_info;
436 	} db;
437 	void __iomem              *uar_map;
438 	struct netdev_queue       *txq;
439 	u32                        sqn;
440 	u16                        stop_room;
441 	u8                         max_sq_mpw_wqebbs;
442 	u8                         min_inline_mode;
443 	struct device             *pdev;
444 	__be32                     mkey_be;
445 	unsigned long              state;
446 	unsigned int               hw_mtu;
447 	struct mlx5_clock         *clock;
448 	struct net_device         *netdev;
449 	struct mlx5_core_dev      *mdev;
450 	struct mlx5e_channel      *channel;
451 	struct mlx5e_priv         *priv;
452 
453 	/* control path */
454 	struct mlx5_wq_ctrl        wq_ctrl;
455 	int                        ch_ix;
456 	int                        txq_ix;
457 	u32                        rate_limit;
458 	struct work_struct         recover_work;
459 	struct mlx5e_ptpsq        *ptpsq;
460 	cqe_ts_to_ns               ptp_cyc2time;
461 } ____cacheline_aligned_in_smp;
462 
463 struct mlx5e_xdp_info_fifo {
464 	union mlx5e_xdp_info *xi;
465 	u32 *cc;
466 	u32 *pc;
467 	u32 mask;
468 };
469 
470 struct mlx5e_xdpsq;
471 struct mlx5e_xmit_data;
472 struct xsk_tx_metadata;
473 typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *);
474 typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *,
475 					struct mlx5e_xmit_data *,
476 					int,
477 					struct xsk_tx_metadata *);
478 
479 struct mlx5e_xdpsq {
480 	/* data path */
481 
482 	/* dirtied @completion */
483 	u32                        xdpi_fifo_cc;
484 	u16                        cc;
485 
486 	/* dirtied @xmit */
487 	u32                        xdpi_fifo_pc ____cacheline_aligned_in_smp;
488 	u16                        pc;
489 	struct mlx5_wqe_ctrl_seg   *doorbell_cseg;
490 	struct mlx5e_tx_mpwqe      mpwqe;
491 
492 	struct mlx5e_cq            cq;
493 
494 	/* read only */
495 	struct xsk_buff_pool      *xsk_pool;
496 	struct mlx5_wq_cyc         wq;
497 	struct mlx5e_xdpsq_stats  *stats;
498 	mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check;
499 	mlx5e_fp_xmit_xdp_frame    xmit_xdp_frame;
500 	struct {
501 		struct mlx5e_xdp_wqe_info *wqe_info;
502 		struct mlx5e_xdp_info_fifo xdpi_fifo;
503 	} db;
504 	void __iomem              *uar_map;
505 	u32                        sqn;
506 	struct device             *pdev;
507 	__be32                     mkey_be;
508 	u16                        stop_room;
509 	u8                         max_sq_mpw_wqebbs;
510 	u8                         min_inline_mode;
511 	unsigned long              state;
512 	unsigned int               hw_mtu;
513 
514 	/* control path */
515 	struct mlx5_wq_ctrl        wq_ctrl;
516 	struct mlx5e_channel      *channel;
517 } ____cacheline_aligned_in_smp;
518 
519 struct mlx5e_xdp_buff {
520 	struct xdp_buff xdp;
521 	struct mlx5_cqe64 *cqe;
522 	struct mlx5e_rq *rq;
523 };
524 
525 struct mlx5e_ktls_resync_resp;
526 
527 struct mlx5e_icosq {
528 	/* data path */
529 	u16                        cc;
530 	u16                        pc;
531 
532 	struct mlx5_wqe_ctrl_seg  *doorbell_cseg;
533 	struct mlx5e_cq            cq;
534 
535 	/* write@xmit, read@completion */
536 	struct {
537 		struct mlx5e_icosq_wqe_info *wqe_info;
538 	} db;
539 
540 	/* read only */
541 	struct mlx5_wq_cyc         wq;
542 	void __iomem              *uar_map;
543 	u32                        sqn;
544 	u16                        reserved_room;
545 	unsigned long              state;
546 	struct mlx5e_ktls_resync_resp *ktls_resync;
547 
548 	/* control path */
549 	struct mlx5_wq_ctrl        wq_ctrl;
550 	struct mlx5e_channel      *channel;
551 
552 	struct work_struct         recover_work;
553 } ____cacheline_aligned_in_smp;
554 
555 struct mlx5e_frag_page {
556 	netmem_ref netmem;
557 	u16 frags;
558 };
559 
560 enum mlx5e_wqe_frag_flag {
561 	MLX5E_WQE_FRAG_LAST_IN_PAGE,
562 	MLX5E_WQE_FRAG_SKIP_RELEASE,
563 };
564 
565 struct mlx5e_wqe_frag_info {
566 	union {
567 		struct mlx5e_frag_page *frag_page;
568 		struct xdp_buff **xskp;
569 	};
570 	u32 offset;
571 	u8 flags;
572 };
573 
574 union mlx5e_alloc_units {
575 	DECLARE_FLEX_ARRAY(struct mlx5e_frag_page, frag_pages);
576 	DECLARE_FLEX_ARRAY(struct page *, pages);
577 	DECLARE_FLEX_ARRAY(struct xdp_buff *, xsk_buffs);
578 };
579 
580 struct mlx5e_mpw_info {
581 	u16 consumed_strides;
582 	DECLARE_BITMAP(skip_release_bitmap, MLX5_MPWRQ_MAX_PAGES_PER_WQE);
583 	struct mlx5e_frag_page linear_page;
584 	union mlx5e_alloc_units alloc_units;
585 };
586 
587 #define MLX5E_MAX_RX_FRAGS 4
588 
589 struct mlx5e_rq;
590 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
591 typedef struct sk_buff *
592 (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
593 			       struct mlx5_cqe64 *cqe, u16 cqe_bcnt,
594 			       u32 head_offset, u32 page_idx);
595 typedef struct sk_buff *
596 (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5e_wqe_frag_info *wi,
597 			 struct mlx5_cqe64 *cqe, u32 cqe_bcnt);
598 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq);
599 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
600 typedef void (*mlx5e_fp_shampo_dealloc_hd)(struct mlx5e_rq*, u16, u16, bool);
601 
602 int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool xsk);
603 void mlx5e_rq_set_trap_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params);
604 
605 enum mlx5e_rq_flag {
606 	MLX5E_RQ_FLAG_XDP_XMIT,
607 	MLX5E_RQ_FLAG_XDP_REDIRECT,
608 };
609 
610 struct mlx5e_rq_frag_info {
611 	int frag_size;
612 	int frag_stride;
613 };
614 
615 struct mlx5e_rq_frags_info {
616 	struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS];
617 	u8 num_frags;
618 	u8 log_num_frags;
619 	u16 wqe_bulk;
620 	u16 refill_unit;
621 	u8 wqe_index_mask;
622 };
623 
624 struct mlx5e_dma_info {
625 	dma_addr_t addr;
626 	union {
627 		struct mlx5e_frag_page *frag_page;
628 		struct page *page;
629 	};
630 };
631 
632 struct mlx5e_shampo_hd {
633 	struct mlx5e_frag_page *pages;
634 	u32 hd_per_wq;
635 	u16 hd_per_wqe;
636 	unsigned long *bitmap;
637 	u16 pi;
638 	u16 ci;
639 	__be32 mkey_be;
640 };
641 
642 struct mlx5e_hw_gro_data {
643 	struct sk_buff *skb;
644 	struct flow_keys fk;
645 	int second_ip_id;
646 };
647 
648 enum mlx5e_mpwrq_umr_mode {
649 	MLX5E_MPWRQ_UMR_MODE_ALIGNED,
650 	MLX5E_MPWRQ_UMR_MODE_UNALIGNED,
651 	MLX5E_MPWRQ_UMR_MODE_OVERSIZED,
652 	MLX5E_MPWRQ_UMR_MODE_TRIPLE,
653 };
654 
655 struct mlx5e_rq {
656 	/* data path */
657 	union {
658 		struct {
659 			struct mlx5_wq_cyc          wq;
660 			struct mlx5e_wqe_frag_info *frags;
661 			union mlx5e_alloc_units    *alloc_units;
662 			struct mlx5e_rq_frags_info  info;
663 			mlx5e_fp_skb_from_cqe       skb_from_cqe;
664 		} wqe;
665 		struct {
666 			struct mlx5_wq_ll      wq;
667 			struct mlx5e_umr_wqe_hdr umr_wqe;
668 			struct mlx5e_mpw_info *info;
669 			mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq;
670 			__be32                 umr_mkey_be;
671 			u16                    num_strides;
672 			u16                    actual_wq_head;
673 			u8                     log_stride_sz;
674 			u8                     umr_in_progress;
675 			u8                     umr_last_bulk;
676 			u8                     umr_completed;
677 			u8                     min_wqe_bulk;
678 			u8                     page_shift;
679 			u8                     pages_per_wqe;
680 			u8                     umr_wqebbs;
681 			u8                     mtts_per_wqe;
682 			u8                     umr_mode;
683 			struct mlx5e_shampo_hd *shampo;
684 		} mpwqe;
685 	};
686 	struct {
687 		u16            headroom;
688 		u32            frame0_sz;
689 		u8             map_dir;   /* dma map direction */
690 	} buff;
691 
692 	struct device         *pdev;
693 	struct net_device     *netdev;
694 	struct mlx5e_rq_stats *stats;
695 	struct mlx5e_cq        cq;
696 	struct mlx5e_cq_decomp cqd;
697 	struct hwtstamp_config *tstamp;
698 	struct mlx5_clock      *clock;
699 	struct mlx5e_icosq    *icosq;
700 	struct mlx5e_priv     *priv;
701 
702 	struct mlx5e_hw_gro_data *hw_gro_data;
703 
704 	mlx5e_fp_handle_rx_cqe handle_rx_cqe;
705 	mlx5e_fp_post_rx_wqes  post_wqes;
706 	mlx5e_fp_dealloc_wqe   dealloc_wqe;
707 
708 	unsigned long          state;
709 	int                    ix;
710 	unsigned int           hw_mtu;
711 
712 	struct dim            *dim; /* Dynamic Interrupt Moderation */
713 
714 	/* XDP */
715 	struct bpf_prog __rcu *xdp_prog;
716 	struct mlx5e_xdpsq    *xdpsq;
717 	DECLARE_BITMAP(flags, 8);
718 
719 	/* page pools */
720 	struct page_pool      *page_pool;
721 	struct page_pool      *hd_page_pool;
722 
723 	struct mlx5e_xdp_buff mxbuf;
724 
725 	/* AF_XDP zero-copy */
726 	struct xsk_buff_pool  *xsk_pool;
727 
728 	struct work_struct     recover_work;
729 	struct work_struct     rx_timeout_work;
730 
731 	/* control */
732 	struct mlx5_wq_ctrl    wq_ctrl;
733 	__be32                 mkey_be;
734 	u8                     wq_type;
735 	u32                    rqn;
736 	struct mlx5_core_dev  *mdev;
737 	struct mlx5e_channel  *channel;
738 	struct mlx5e_dma_info  wqe_overflow;
739 
740 	/* XDP read-mostly */
741 	struct xdp_rxq_info    xdp_rxq;
742 	cqe_ts_to_ns           ptp_cyc2time;
743 } ____cacheline_aligned_in_smp;
744 
745 enum mlx5e_channel_state {
746 	MLX5E_CHANNEL_STATE_XSK,
747 	MLX5E_CHANNEL_NUM_STATES
748 };
749 
750 struct mlx5e_channel {
751 	/* data path */
752 	struct mlx5e_rq            rq;
753 	struct mlx5e_xdpsq         rq_xdpsq;
754 	struct mlx5e_txqsq         sq[MLX5_MAX_NUM_TC];
755 	struct mlx5e_icosq         icosq;   /* internal control operations */
756 	struct mlx5e_txqsq __rcu * __rcu *qos_sqs;
757 	bool                       xdp;
758 	struct napi_struct         napi;
759 	struct device             *pdev;
760 	struct net_device         *netdev;
761 	__be32                     mkey_be;
762 	u16                        qos_sqs_size;
763 	u8                         num_tc;
764 	u8                         lag_port;
765 
766 	/* XDP_REDIRECT */
767 	struct mlx5e_xdpsq        *xdpsq;
768 
769 	/* AF_XDP zero-copy */
770 	struct mlx5e_rq            xskrq;
771 	struct mlx5e_xdpsq         xsksq;
772 
773 	/* Async ICOSQ */
774 	struct mlx5e_icosq         async_icosq;
775 	/* async_icosq can be accessed from any CPU - the spinlock protects it. */
776 	spinlock_t                 async_icosq_lock;
777 
778 	/* data path - accessed per napi poll */
779 	const struct cpumask	  *aff_mask;
780 	struct mlx5e_ch_stats     *stats;
781 
782 	/* control */
783 	struct mlx5e_priv         *priv;
784 	struct mlx5_core_dev      *mdev;
785 	struct hwtstamp_config    *tstamp;
786 	DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES);
787 	int                        ix;
788 	int                        vec_ix;
789 	int                        sd_ix;
790 	int                        cpu;
791 	/* Sync between icosq recovery and XSK enable/disable. */
792 	struct mutex               icosq_recovery_lock;
793 
794 	/* coalescing configuration */
795 	struct dim_cq_moder        rx_cq_moder;
796 	struct dim_cq_moder        tx_cq_moder;
797 };
798 
799 struct mlx5e_ptp;
800 
801 struct mlx5e_channels {
802 	struct mlx5e_channel **c;
803 	struct mlx5e_ptp      *ptp;
804 	unsigned int           num;
805 	struct mlx5e_params    params;
806 };
807 
808 struct mlx5e_channel_stats {
809 	struct mlx5e_ch_stats ch;
810 	struct mlx5e_sq_stats sq[MLX5_MAX_NUM_TC];
811 	struct mlx5e_rq_stats rq;
812 	struct mlx5e_rq_stats xskrq;
813 	struct mlx5e_xdpsq_stats rq_xdpsq;
814 	struct mlx5e_xdpsq_stats xdpsq;
815 	struct mlx5e_xdpsq_stats xsksq;
816 } ____cacheline_aligned_in_smp;
817 
818 struct mlx5e_ptp_stats {
819 	struct mlx5e_ch_stats ch;
820 	struct mlx5e_sq_stats sq[MLX5_MAX_NUM_TC];
821 	struct mlx5e_ptp_cq_stats cq[MLX5_MAX_NUM_TC];
822 	struct mlx5e_rq_stats rq;
823 } ____cacheline_aligned_in_smp;
824 
825 enum {
826 	MLX5E_STATE_OPENED,
827 	MLX5E_STATE_DESTROYING,
828 	MLX5E_STATE_XDP_TX_ENABLED,
829 	MLX5E_STATE_XDP_ACTIVE,
830 	MLX5E_STATE_CHANNELS_ACTIVE,
831 };
832 
833 struct mlx5e_modify_sq_param {
834 	int curr_state;
835 	int next_state;
836 	int rl_update;
837 	int rl_index;
838 	bool qos_update;
839 	u16 qos_queue_group_id;
840 };
841 
842 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
843 struct mlx5e_hv_vhca_stats_agent {
844 	struct mlx5_hv_vhca_agent *agent;
845 	struct delayed_work        work;
846 	u16                        delay;
847 	void                      *buf;
848 };
849 #endif
850 
851 struct mlx5e_xsk {
852 	/* XSK buffer pools are stored separately from channels,
853 	 * because we don't want to lose them when channels are
854 	 * recreated. The kernel also stores buffer pool, but it doesn't
855 	 * distinguish between zero-copy and non-zero-copy UMEMs, so
856 	 * rely on our mechanism.
857 	 */
858 	struct xsk_buff_pool **pools;
859 	u16 refcnt;
860 	bool ever_used;
861 };
862 
863 /* Temporary storage for variables that are allocated when struct mlx5e_priv is
864  * initialized, and used where we can't allocate them because that functions
865  * must not fail. Use with care and make sure the same variable is not used
866  * simultaneously by multiple users.
867  */
868 struct mlx5e_scratchpad {
869 	cpumask_var_t cpumask;
870 };
871 
872 struct mlx5e_trap;
873 struct mlx5e_htb;
874 
875 struct mlx5e_priv {
876 	/* priv data path fields - start */
877 	struct mlx5e_selq selq;
878 	struct mlx5e_txqsq **txq2sq;
879 	struct mlx5e_sq_stats **txq2sq_stats;
880 
881 #ifdef CONFIG_MLX5_CORE_EN_DCB
882 	struct mlx5e_dcbx_dp       dcbx_dp;
883 #endif
884 	/* priv data path fields - end */
885 
886 	unsigned long              state;
887 	struct mutex               state_lock; /* Protects Interface state */
888 	struct mlx5e_rq            drop_rq;
889 
890 	struct mlx5e_channels      channels;
891 	struct mlx5e_rx_res       *rx_res;
892 	u32                       *tx_rates;
893 
894 	struct mlx5e_flow_steering *fs;
895 
896 	struct workqueue_struct    *wq;
897 	struct work_struct         update_carrier_work;
898 	struct work_struct         set_rx_mode_work;
899 	struct work_struct         tx_timeout_work;
900 	struct work_struct         update_stats_work;
901 	struct work_struct         monitor_counters_work;
902 	struct mlx5_nb             monitor_counters_nb;
903 
904 	struct mlx5_core_dev      *mdev;
905 	struct net_device         *netdev;
906 	struct mlx5e_trap         *en_trap;
907 	struct mlx5e_stats         stats;
908 	struct mlx5e_channel_stats **channel_stats;
909 	struct mlx5e_channel_stats trap_stats;
910 	struct mlx5e_ptp_stats     ptp_stats;
911 	struct mlx5e_sq_stats      **htb_qos_sq_stats;
912 	u16                        htb_max_qos_sqs;
913 	u16                        stats_nch;
914 	u16                        max_nch;
915 	u8                         max_opened_tc;
916 	bool                       tx_ptp_opened;
917 	bool                       rx_ptp_opened;
918 	struct hwtstamp_config     tstamp;
919 	u16                        q_counter[MLX5_SD_MAX_GROUP_SZ];
920 	u16                        drop_rq_q_counter;
921 	struct notifier_block      events_nb;
922 	struct notifier_block      blocking_events_nb;
923 
924 	struct mlx5e_pcie_cong_event *cong_event;
925 
926 	struct udp_tunnel_nic_info nic_info;
927 #ifdef CONFIG_MLX5_CORE_EN_DCB
928 	struct mlx5e_dcbx          dcbx;
929 #endif
930 
931 	const struct mlx5e_profile *profile;
932 	void                      *ppriv;
933 #ifdef CONFIG_MLX5_MACSEC
934 	struct mlx5e_macsec       *macsec;
935 #endif
936 #ifdef CONFIG_MLX5_EN_IPSEC
937 	struct mlx5e_ipsec        *ipsec;
938 #endif
939 #ifdef CONFIG_MLX5_EN_TLS
940 	struct mlx5e_tls          *tls;
941 #endif
942 	struct devlink_health_reporter *tx_reporter;
943 	struct devlink_health_reporter *rx_reporter;
944 	struct mlx5e_xsk           xsk;
945 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
946 	struct mlx5e_hv_vhca_stats_agent stats_agent;
947 #endif
948 	struct mlx5e_scratchpad    scratchpad;
949 	struct mlx5e_htb          *htb;
950 	struct mlx5e_mqprio_rl    *mqprio_rl;
951 	struct dentry             *dfs_root;
952 	struct mlx5_devcom_comp_dev *devcom;
953 };
954 
955 struct mlx5e_dev {
956 	struct mlx5e_priv *priv;
957 	struct devlink_port dl_port;
958 };
959 
960 struct mlx5e_rx_handlers {
961 	mlx5e_fp_handle_rx_cqe handle_rx_cqe;
962 	mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
963 	mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe_shampo;
964 };
965 
966 extern const struct mlx5e_rx_handlers mlx5e_rx_handlers_nic;
967 
968 enum mlx5e_profile_feature {
969 	MLX5E_PROFILE_FEATURE_PTP_RX,
970 	MLX5E_PROFILE_FEATURE_PTP_TX,
971 	MLX5E_PROFILE_FEATURE_QOS_HTB,
972 	MLX5E_PROFILE_FEATURE_FS_VLAN,
973 	MLX5E_PROFILE_FEATURE_FS_TC,
974 };
975 
976 struct mlx5e_profile {
977 	int	(*init)(struct mlx5_core_dev *mdev,
978 			struct net_device *netdev);
979 	void	(*cleanup)(struct mlx5e_priv *priv);
980 	int	(*init_rx)(struct mlx5e_priv *priv);
981 	void	(*cleanup_rx)(struct mlx5e_priv *priv);
982 	int	(*init_tx)(struct mlx5e_priv *priv);
983 	void	(*cleanup_tx)(struct mlx5e_priv *priv);
984 	void	(*enable)(struct mlx5e_priv *priv);
985 	void	(*disable)(struct mlx5e_priv *priv);
986 	int	(*update_rx)(struct mlx5e_priv *priv);
987 	void	(*update_stats)(struct mlx5e_priv *priv);
988 	void	(*update_carrier)(struct mlx5e_priv *priv);
989 	int	(*max_nch_limit)(struct mlx5_core_dev *mdev);
990 	u32	(*get_tisn)(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv,
991 			    u8 lag_port, u8 tc);
992 	unsigned int (*stats_grps_num)(struct mlx5e_priv *priv);
993 	mlx5e_stats_grp_t *stats_grps;
994 	const struct mlx5e_rx_handlers *rx_handlers;
995 	int	max_tc;
996 	u32     features;
997 };
998 
999 u32 mlx5e_profile_get_tisn(struct mlx5_core_dev *mdev,
1000 			   struct mlx5e_priv *priv,
1001 			   const struct mlx5e_profile *profile,
1002 			   u8 lag_port, u8 tc);
1003 
1004 #define mlx5e_profile_feature_cap(profile, feature)	\
1005 	((profile)->features & BIT(MLX5E_PROFILE_FEATURE_##feature))
1006 
1007 void mlx5e_build_ptys2ethtool_map(void);
1008 
1009 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev, u8 page_shift,
1010 					    enum mlx5e_mpwrq_umr_mode umr_mode);
1011 
1012 void mlx5e_shampo_fill_umr(struct mlx5e_rq *rq, int len);
1013 void mlx5e_shampo_dealloc_hd(struct mlx5e_rq *rq);
1014 void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats);
1015 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s);
1016 
1017 int mlx5e_self_test_num(struct mlx5e_priv *priv);
1018 int mlx5e_self_test_fill_strings(struct mlx5e_priv *priv, u8 *data);
1019 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
1020 		     u64 *buf);
1021 void mlx5e_set_rx_mode_work(struct work_struct *work);
1022 
1023 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr);
1024 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr);
1025 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val, bool rx_filter);
1026 
1027 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
1028 			  u16 vid);
1029 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
1030 			   u16 vid);
1031 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
1032 
1033 struct mlx5e_xsk_param;
1034 
1035 struct mlx5e_rq_param;
1036 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
1037 		  struct mlx5e_xsk_param *xsk, int node, u16 q_counter,
1038 		  struct mlx5e_rq *rq);
1039 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
1040 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time);
1041 void mlx5e_close_rq(struct mlx5e_rq *rq);
1042 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param, u16 q_counter);
1043 void mlx5e_destroy_rq(struct mlx5e_rq *rq);
1044 
1045 bool mlx5e_reset_rx_moderation(struct dim_cq_moder *cq_moder, u8 cq_period_mode,
1046 			       bool dim_enabled);
1047 bool mlx5e_reset_rx_channels_moderation(struct mlx5e_channels *chs, u8 cq_period_mode,
1048 					bool dim_enabled, bool keep_dim_state);
1049 
1050 struct mlx5e_sq_param;
1051 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1052 		     struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
1053 		     struct mlx5e_xdpsq *sq, bool is_redirect);
1054 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq);
1055 
1056 struct mlx5e_create_cq_param {
1057 	struct net_device *netdev;
1058 	struct workqueue_struct *wq;
1059 	struct napi_struct *napi;
1060 	struct mlx5e_ch_stats *ch_stats;
1061 	int node;
1062 	int ix;
1063 };
1064 
1065 struct mlx5e_cq_param;
1066 int mlx5e_open_cq(struct mlx5_core_dev *mdev, struct dim_cq_moder moder,
1067 		  struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
1068 		  struct mlx5e_cq *cq);
1069 void mlx5e_close_cq(struct mlx5e_cq *cq);
1070 int mlx5e_modify_cq_period_mode(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
1071 				u8 cq_period_mode);
1072 int mlx5e_modify_cq_moderation(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
1073 			       u16 cq_period, u16 cq_max_count, u8 cq_period_mode);
1074 
1075 int mlx5e_open_locked(struct net_device *netdev);
1076 int mlx5e_close_locked(struct net_device *netdev);
1077 
1078 void mlx5e_trigger_napi_icosq(struct mlx5e_channel *c);
1079 void mlx5e_trigger_napi_sched(struct napi_struct *napi);
1080 
1081 int mlx5e_open_channels(struct mlx5e_priv *priv,
1082 			struct mlx5e_channels *chs);
1083 void mlx5e_close_channels(struct mlx5e_channels *chs);
1084 
1085 /* Function pointer to be used to modify HW or kernel settings while
1086  * switching channels
1087  */
1088 typedef int (*mlx5e_fp_preactivate)(struct mlx5e_priv *priv, void *context);
1089 #define MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(fn) \
1090 int fn##_ctx(struct mlx5e_priv *priv, void *context) \
1091 { \
1092 	return fn(priv); \
1093 }
1094 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv);
1095 int mlx5e_safe_switch_params(struct mlx5e_priv *priv,
1096 			     struct mlx5e_params *new_params,
1097 			     mlx5e_fp_preactivate preactivate,
1098 			     void *context, bool reset);
1099 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv);
1100 int mlx5e_num_channels_changed_ctx(struct mlx5e_priv *priv, void *context);
1101 int mlx5e_update_tc_and_tx_queues_ctx(struct mlx5e_priv *priv, void *context);
1102 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);
1103 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
1104 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx);
1105 
1106 int mlx5e_flush_rq(struct mlx5e_rq *rq, int curr_state);
1107 void mlx5e_activate_rq(struct mlx5e_rq *rq);
1108 void mlx5e_deactivate_rq(struct mlx5e_rq *rq);
1109 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq);
1110 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq);
1111 
1112 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1113 		    struct mlx5e_modify_sq_param *p);
1114 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1115 		     struct mlx5e_params *params, struct mlx5e_sq_param *param,
1116 		     struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id,
1117 		     struct mlx5e_sq_stats *sq_stats);
1118 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq);
1119 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq);
1120 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq);
1121 void mlx5e_tx_disable_queue(struct netdev_queue *txq);
1122 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa);
1123 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq);
1124 struct mlx5e_create_sq_param;
1125 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1126 			struct mlx5e_sq_param *param,
1127 			struct mlx5e_create_sq_param *csp,
1128 			u16 qos_queue_group_id,
1129 			u32 *sqn);
1130 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1131 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq);
1132 
1133 bool mlx5e_reset_tx_moderation(struct dim_cq_moder *cq_moder, u8 cq_period_mode,
1134 			       bool dim_enabled);
1135 bool mlx5e_reset_tx_channels_moderation(struct mlx5e_channels *chs, u8 cq_period_mode,
1136 					bool dim_enabled, bool keep_dim_state);
1137 
mlx5_tx_swp_supported(struct mlx5_core_dev * mdev)1138 static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev)
1139 {
1140 	return MLX5_CAP_ETH(mdev, swp) &&
1141 		MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso);
1142 }
1143 
1144 extern const struct ethtool_ops mlx5e_ethtool_ops;
1145 
1146 int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey);
1147 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev, bool create_tises);
1148 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
1149 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb,
1150 		       bool enable_mc_lb);
1151 void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc);
1152 
1153 /* common netdev helpers */
1154 void mlx5e_create_q_counters(struct mlx5e_priv *priv);
1155 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv);
1156 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
1157 		       struct mlx5e_rq *drop_rq);
1158 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq);
1159 
1160 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn);
1161 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
1162 
1163 void mlx5e_update_carrier(struct mlx5e_priv *priv);
1164 int mlx5e_close(struct net_device *netdev);
1165 int mlx5e_open(struct net_device *netdev);
1166 
1167 void mlx5e_queue_update_stats(struct mlx5e_priv *priv);
1168 
1169 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv);
1170 int mlx5e_set_dev_port_mtu_ctx(struct mlx5e_priv *priv, void *context);
1171 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
1172 		     mlx5e_fp_preactivate preactivate);
1173 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv);
1174 
1175 /* ethtool helpers */
1176 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
1177 			       struct ethtool_drvinfo *drvinfo);
1178 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
1179 			       u32 stringset, u8 *data);
1180 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);
1181 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
1182 				     struct ethtool_stats *stats, u64 *data);
1183 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
1184 				 struct ethtool_ringparam *param,
1185 				 struct kernel_ethtool_ringparam *kernel_param);
1186 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
1187 				struct ethtool_ringparam *param,
1188 				struct netlink_ext_ack *extack);
1189 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
1190 				struct ethtool_channels *ch);
1191 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
1192 			       struct ethtool_channels *ch);
1193 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
1194 			       struct ethtool_coalesce *coal,
1195 			       struct kernel_ethtool_coalesce *kernel_coal,
1196 			       struct netlink_ext_ack *extack);
1197 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
1198 			       struct ethtool_coalesce *coal,
1199 			       struct kernel_ethtool_coalesce *kernel_coal,
1200 			       struct netlink_ext_ack *extack);
1201 int mlx5e_get_per_queue_coalesce(struct net_device *dev, u32 queue,
1202 				 struct ethtool_coalesce *coal);
1203 int mlx5e_set_per_queue_coalesce(struct net_device *dev, u32 queue,
1204 				 struct ethtool_coalesce *coal);
1205 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv);
1206 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv);
1207 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1208 			      struct kernel_ethtool_ts_info *info);
1209 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1210 			       struct ethtool_flash *flash);
1211 
1212 /* mlx5e generic netdev management API */
1213 static inline bool
mlx5e_tx_mpwqe_supported(struct mlx5_core_dev * mdev)1214 mlx5e_tx_mpwqe_supported(struct mlx5_core_dev *mdev)
1215 {
1216 	return !is_kdump_kernel() &&
1217 		MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe);
1218 }
1219 
1220 int mlx5e_get_pf_num_tirs(struct mlx5_core_dev *mdev);
1221 int mlx5e_priv_init(struct mlx5e_priv *priv,
1222 		    const struct mlx5e_profile *profile,
1223 		    struct net_device *netdev,
1224 		    struct mlx5_core_dev *mdev);
1225 void mlx5e_priv_cleanup(struct mlx5e_priv *priv);
1226 struct net_device *
1227 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile);
1228 int mlx5e_attach_netdev(struct mlx5e_priv *priv);
1229 void mlx5e_detach_netdev(struct mlx5e_priv *priv);
1230 void mlx5e_destroy_netdev(struct mlx5e_priv *priv);
1231 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
1232 				const struct mlx5e_profile *new_profile, void *new_ppriv);
1233 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv);
1234 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv);
1235 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu);
1236 
1237 void mlx5e_set_xdp_feature(struct net_device *netdev);
1238 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
1239 				       struct net_device *netdev,
1240 				       netdev_features_t features);
1241 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features);
1242 #ifdef CONFIG_MLX5_ESWITCH
1243 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac);
1244 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate);
1245 int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi);
1246 int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats);
1247 #endif
1248 int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey);
1249 #endif /* __MLX5_EN_H__ */
1250