1 /*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/dim.h>
34 #include <linux/ethtool_netlink.h>
35 #include <net/netdev_queues.h>
36
37 #include "en.h"
38 #include "en/channels.h"
39 #include "en/dim.h"
40 #include "en/port.h"
41 #include "en/params.h"
42 #include "en/ptp.h"
43 #include "lib/clock.h"
44 #include "en/fs_ethtool.h"
45
46 #define LANES_UNKNOWN 0
47
mlx5e_ethtool_get_drvinfo(struct mlx5e_priv * priv,struct ethtool_drvinfo * drvinfo)48 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
49 struct ethtool_drvinfo *drvinfo)
50 {
51 struct mlx5_core_dev *mdev = priv->mdev;
52 int count;
53
54 strscpy(drvinfo->driver, KBUILD_MODNAME, sizeof(drvinfo->driver));
55 count = snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
56 "%d.%d.%04d (%.16s)", fw_rev_maj(mdev),
57 fw_rev_min(mdev), fw_rev_sub(mdev), mdev->board_id);
58 if (count >= sizeof(drvinfo->fw_version))
59 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
60 "%d.%d.%04d", fw_rev_maj(mdev),
61 fw_rev_min(mdev), fw_rev_sub(mdev));
62
63 strscpy(drvinfo->bus_info, dev_name(mdev->device),
64 sizeof(drvinfo->bus_info));
65 }
66
mlx5e_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * drvinfo)67 static void mlx5e_get_drvinfo(struct net_device *dev,
68 struct ethtool_drvinfo *drvinfo)
69 {
70 struct mlx5e_priv *priv = netdev_priv(dev);
71
72 mlx5e_ethtool_get_drvinfo(priv, drvinfo);
73 }
74
75 struct ptys2ethtool_config {
76 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
77 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
78 };
79
80 static
81 struct ptys2ethtool_config ptys2legacy_ethtool_table[MLX5E_LINK_MODES_NUMBER];
82 static
83 struct ptys2ethtool_config ptys2ext_ethtool_table[MLX5E_EXT_LINK_MODES_NUMBER];
84
85 #define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, table, ...) \
86 ({ \
87 struct ptys2ethtool_config *cfg; \
88 const unsigned int modes[] = { __VA_ARGS__ }; \
89 unsigned int i; \
90 cfg = &ptys2##table##_ethtool_table[reg_]; \
91 bitmap_zero(cfg->supported, \
92 __ETHTOOL_LINK_MODE_MASK_NBITS); \
93 bitmap_zero(cfg->advertised, \
94 __ETHTOOL_LINK_MODE_MASK_NBITS); \
95 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
96 bitmap_set(cfg->supported, modes[i], 1); \
97 bitmap_set(cfg->advertised, modes[i], 1); \
98 } \
99 })
100
mlx5e_build_ptys2ethtool_map(void)101 void mlx5e_build_ptys2ethtool_map(void)
102 {
103 memset(ptys2legacy_ethtool_table, 0, sizeof(ptys2legacy_ethtool_table));
104 memset(ptys2ext_ethtool_table, 0, sizeof(ptys2ext_ethtool_table));
105 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, legacy,
106 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
107 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, legacy,
108 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
109 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, legacy,
110 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
111 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, legacy,
112 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
113 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, legacy,
114 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
115 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, legacy,
116 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
117 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, legacy,
118 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
119 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, legacy,
120 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
121 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, legacy,
122 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
123 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, legacy,
124 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
125 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, legacy,
126 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
127 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, legacy,
128 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
129 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, legacy,
130 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
131 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, legacy,
132 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
133 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, legacy,
134 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
135 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, legacy,
136 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
137 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, legacy,
138 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
139 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, legacy,
140 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
141 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, legacy,
142 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
143 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100BASE_TX, legacy,
144 ETHTOOL_LINK_MODE_100baseT_Full_BIT);
145 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_T, legacy,
146 ETHTOOL_LINK_MODE_1000baseT_Full_BIT);
147 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, legacy,
148 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
149 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, legacy,
150 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
151 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, legacy,
152 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
153 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, legacy,
154 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
155 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, legacy,
156 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
157 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, legacy,
158 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
159 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_SGMII_100M, ext,
160 ETHTOOL_LINK_MODE_100baseT_Full_BIT);
161 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_X_SGMII, ext,
162 ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
163 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
164 ETHTOOL_LINK_MODE_1000baseX_Full_BIT);
165 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_5GBASE_R, ext,
166 ETHTOOL_LINK_MODE_5000baseT_Full_BIT);
167 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_XFI_XAUI_1, ext,
168 ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
169 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
170 ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
171 ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
172 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
173 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
174 ETHTOOL_LINK_MODE_10000baseER_Full_BIT);
175 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_XLAUI_4_XLPPI_4, ext,
176 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
177 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
178 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
179 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
180 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GAUI_1_25GBASE_CR_KR, ext,
181 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
182 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
183 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
184 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2,
185 ext,
186 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
187 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
188 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
189 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR, ext,
190 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
191 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
192 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
193 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
194 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT);
195 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_CAUI_4_100GBASE_CR4_KR4, ext,
196 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
197 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
198 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
199 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
200 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_2_100GBASE_CR2_KR2, ext,
201 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
202 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
203 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
204 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
205 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT);
206 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_4_200GBASE_CR4_KR4, ext,
207 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
208 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
209 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
210 ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,
211 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT);
212 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_8_400GBASE_CR8, ext,
213 ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT,
214 ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT,
215 ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT,
216 ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT,
217 ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT);
218 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_1_100GBASE_CR_KR, ext,
219 ETHTOOL_LINK_MODE_100000baseKR_Full_BIT,
220 ETHTOOL_LINK_MODE_100000baseSR_Full_BIT,
221 ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT,
222 ETHTOOL_LINK_MODE_100000baseDR_Full_BIT,
223 ETHTOOL_LINK_MODE_100000baseCR_Full_BIT);
224 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_2_200GBASE_CR2_KR2, ext,
225 ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT,
226 ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT,
227 ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT,
228 ETHTOOL_LINK_MODE_200000baseDR2_Full_BIT,
229 ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT);
230 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_4_400GBASE_CR4_KR4, ext,
231 ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT,
232 ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT,
233 ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT,
234 ETHTOOL_LINK_MODE_400000baseDR4_Full_BIT,
235 ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT);
236 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_800GAUI_8_800GBASE_CR8_KR8, ext,
237 ETHTOOL_LINK_MODE_800000baseCR8_Full_BIT,
238 ETHTOOL_LINK_MODE_800000baseKR8_Full_BIT,
239 ETHTOOL_LINK_MODE_800000baseDR8_Full_BIT,
240 ETHTOOL_LINK_MODE_800000baseDR8_2_Full_BIT,
241 ETHTOOL_LINK_MODE_800000baseSR8_Full_BIT,
242 ETHTOOL_LINK_MODE_800000baseVR8_Full_BIT);
243 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_1_200GBASE_CR1_KR1, ext,
244 ETHTOOL_LINK_MODE_200000baseCR_Full_BIT,
245 ETHTOOL_LINK_MODE_200000baseKR_Full_BIT,
246 ETHTOOL_LINK_MODE_200000baseDR_Full_BIT,
247 ETHTOOL_LINK_MODE_200000baseDR_2_Full_BIT,
248 ETHTOOL_LINK_MODE_200000baseSR_Full_BIT,
249 ETHTOOL_LINK_MODE_200000baseVR_Full_BIT);
250 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_2_400GBASE_CR2_KR2, ext,
251 ETHTOOL_LINK_MODE_400000baseCR2_Full_BIT,
252 ETHTOOL_LINK_MODE_400000baseKR2_Full_BIT,
253 ETHTOOL_LINK_MODE_400000baseDR2_Full_BIT,
254 ETHTOOL_LINK_MODE_400000baseDR2_2_Full_BIT,
255 ETHTOOL_LINK_MODE_400000baseSR2_Full_BIT,
256 ETHTOOL_LINK_MODE_400000baseVR2_Full_BIT);
257 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_800GAUI_4_800GBASE_CR4_KR4, ext,
258 ETHTOOL_LINK_MODE_800000baseCR4_Full_BIT,
259 ETHTOOL_LINK_MODE_800000baseKR4_Full_BIT,
260 ETHTOOL_LINK_MODE_800000baseDR4_Full_BIT,
261 ETHTOOL_LINK_MODE_800000baseDR4_2_Full_BIT,
262 ETHTOOL_LINK_MODE_800000baseSR4_Full_BIT,
263 ETHTOOL_LINK_MODE_800000baseVR4_Full_BIT);
264 }
265
mlx5e_ethtool_get_speed_arr(bool ext,struct ptys2ethtool_config ** arr,u32 * size)266 static void mlx5e_ethtool_get_speed_arr(bool ext,
267 struct ptys2ethtool_config **arr,
268 u32 *size)
269 {
270 *arr = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table;
271 *size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) :
272 ARRAY_SIZE(ptys2legacy_ethtool_table);
273 }
274
275 typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
276
277 struct pflag_desc {
278 char name[ETH_GSTRING_LEN];
279 mlx5e_pflag_handler handler;
280 };
281
282 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS];
283
mlx5e_ethtool_get_sset_count(struct mlx5e_priv * priv,int sset)284 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset)
285 {
286 switch (sset) {
287 case ETH_SS_STATS:
288 return mlx5e_stats_total_num(priv);
289 case ETH_SS_PRIV_FLAGS:
290 return MLX5E_NUM_PFLAGS;
291 case ETH_SS_TEST:
292 return mlx5e_self_test_num(priv);
293 default:
294 return -EOPNOTSUPP;
295 }
296 }
297
mlx5e_get_sset_count(struct net_device * dev,int sset)298 static int mlx5e_get_sset_count(struct net_device *dev, int sset)
299 {
300 struct mlx5e_priv *priv = netdev_priv(dev);
301
302 return mlx5e_ethtool_get_sset_count(priv, sset);
303 }
304
mlx5e_ethtool_get_strings(struct mlx5e_priv * priv,u32 stringset,u8 * data)305 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, u32 stringset, u8 *data)
306 {
307 int i;
308
309 switch (stringset) {
310 case ETH_SS_PRIV_FLAGS:
311 for (i = 0; i < MLX5E_NUM_PFLAGS; i++)
312 ethtool_puts(&data, mlx5e_priv_flags[i].name);
313 break;
314
315 case ETH_SS_TEST:
316 mlx5e_self_test_fill_strings(priv, data);
317 break;
318
319 case ETH_SS_STATS:
320 mlx5e_stats_fill_strings(priv, data);
321 break;
322 }
323 }
324
mlx5e_get_strings(struct net_device * dev,u32 stringset,u8 * data)325 static void mlx5e_get_strings(struct net_device *dev, u32 stringset, u8 *data)
326 {
327 struct mlx5e_priv *priv = netdev_priv(dev);
328
329 mlx5e_ethtool_get_strings(priv, stringset, data);
330 }
331
mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv * priv,struct ethtool_stats * stats,u64 * data)332 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
333 struct ethtool_stats *stats, u64 *data)
334 {
335 int idx = 0;
336
337 mutex_lock(&priv->state_lock);
338 mlx5e_stats_update(priv);
339 mutex_unlock(&priv->state_lock);
340
341 mlx5e_stats_fill(priv, data, idx);
342 }
343
mlx5e_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)344 static void mlx5e_get_ethtool_stats(struct net_device *dev,
345 struct ethtool_stats *stats,
346 u64 *data)
347 {
348 struct mlx5e_priv *priv = netdev_priv(dev);
349
350 mlx5e_ethtool_get_ethtool_stats(priv, stats, data);
351 }
352
mlx5e_ethtool_get_ringparam(struct mlx5e_priv * priv,struct ethtool_ringparam * param,struct kernel_ethtool_ringparam * kernel_param)353 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
354 struct ethtool_ringparam *param,
355 struct kernel_ethtool_ringparam *kernel_param)
356 {
357 /* Limitation for regular RQ. XSK RQ may clamp the queue length in
358 * mlx5e_mpwqe_get_log_rq_size.
359 */
360 u8 max_log_mpwrq_pkts = mlx5e_mpwrq_max_log_rq_pkts(priv->mdev,
361 PAGE_SHIFT,
362 MLX5E_MPWRQ_UMR_MODE_ALIGNED);
363
364 param->rx_max_pending = 1 << min_t(u8, MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE,
365 max_log_mpwrq_pkts);
366 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
367 param->rx_pending = 1 << priv->channels.params.log_rq_mtu_frames;
368 param->tx_pending = 1 << priv->channels.params.log_sq_size;
369 }
370
mlx5e_get_ringparam(struct net_device * dev,struct ethtool_ringparam * param,struct kernel_ethtool_ringparam * kernel_param,struct netlink_ext_ack * extack)371 static void mlx5e_get_ringparam(struct net_device *dev,
372 struct ethtool_ringparam *param,
373 struct kernel_ethtool_ringparam *kernel_param,
374 struct netlink_ext_ack *extack)
375 {
376 struct mlx5e_priv *priv = netdev_priv(dev);
377
378 mlx5e_ethtool_get_ringparam(priv, param, kernel_param);
379 }
380
mlx5e_ethtool_set_tcp_data_split(struct mlx5e_priv * priv,u8 tcp_data_split,struct netlink_ext_ack * extack)381 static bool mlx5e_ethtool_set_tcp_data_split(struct mlx5e_priv *priv,
382 u8 tcp_data_split,
383 struct netlink_ext_ack *extack)
384 {
385 struct net_device *dev = priv->netdev;
386
387 if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_ENABLED &&
388 !(dev->features & NETIF_F_GRO_HW)) {
389 NL_SET_ERR_MSG_MOD(extack,
390 "TCP-data-split is not supported when GRO HW is disabled");
391 return false;
392 }
393
394 /* Might need to disable HW-GRO if it was kept on due to hds. */
395 if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_DISABLED &&
396 dev->cfg->hds_config == ETHTOOL_TCP_DATA_SPLIT_ENABLED)
397 netdev_update_features(priv->netdev);
398
399 return true;
400 }
401
mlx5e_ethtool_set_ringparam(struct mlx5e_priv * priv,struct ethtool_ringparam * param,struct netlink_ext_ack * extack)402 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
403 struct ethtool_ringparam *param,
404 struct netlink_ext_ack *extack)
405 {
406 struct mlx5e_params new_params;
407 u8 log_rq_size;
408 u8 log_sq_size;
409 int err = 0;
410
411 if (param->rx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE)) {
412 NL_SET_ERR_MSG_FMT_MOD(extack, "rx (%d) < min (%d)",
413 param->rx_pending,
414 1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE);
415 return -EINVAL;
416 }
417
418 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
419 NL_SET_ERR_MSG_FMT_MOD(extack, "tx (%d) < min (%d)",
420 param->tx_pending,
421 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
422 return -EINVAL;
423 }
424
425 log_rq_size = order_base_2(param->rx_pending);
426 log_sq_size = order_base_2(param->tx_pending);
427
428 if (log_rq_size == priv->channels.params.log_rq_mtu_frames &&
429 log_sq_size == priv->channels.params.log_sq_size)
430 return 0;
431
432 mutex_lock(&priv->state_lock);
433
434 new_params = priv->channels.params;
435 new_params.log_rq_mtu_frames = log_rq_size;
436 new_params.log_sq_size = log_sq_size;
437
438 err = mlx5e_validate_params(priv->mdev, &new_params);
439 if (err)
440 goto unlock;
441
442 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true);
443
444 unlock:
445 mutex_unlock(&priv->state_lock);
446
447 if (!err)
448 netdev_update_features(priv->netdev);
449
450 return err;
451 }
452
mlx5e_set_ringparam(struct net_device * dev,struct ethtool_ringparam * param,struct kernel_ethtool_ringparam * kernel_param,struct netlink_ext_ack * extack)453 static int mlx5e_set_ringparam(struct net_device *dev,
454 struct ethtool_ringparam *param,
455 struct kernel_ethtool_ringparam *kernel_param,
456 struct netlink_ext_ack *extack)
457 {
458 struct mlx5e_priv *priv = netdev_priv(dev);
459
460 if (!mlx5e_ethtool_set_tcp_data_split(priv,
461 kernel_param->tcp_data_split,
462 extack))
463 return -EINVAL;
464
465 return mlx5e_ethtool_set_ringparam(priv, param, extack);
466 }
467
mlx5e_ethtool_get_channels(struct mlx5e_priv * priv,struct ethtool_channels * ch)468 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
469 struct ethtool_channels *ch)
470 {
471 mutex_lock(&priv->state_lock);
472 ch->max_combined = priv->max_nch;
473 ch->combined_count = priv->channels.params.num_channels;
474 mutex_unlock(&priv->state_lock);
475 }
476
mlx5e_get_channels(struct net_device * dev,struct ethtool_channels * ch)477 static void mlx5e_get_channels(struct net_device *dev,
478 struct ethtool_channels *ch)
479 {
480 struct mlx5e_priv *priv = netdev_priv(dev);
481
482 mlx5e_ethtool_get_channels(priv, ch);
483 }
484
mlx5e_ethtool_set_channels(struct mlx5e_priv * priv,struct ethtool_channels * ch)485 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
486 struct ethtool_channels *ch)
487 {
488 struct mlx5e_params *cur_params = &priv->channels.params;
489 unsigned int count = ch->combined_count;
490 struct mlx5e_params new_params;
491 bool arfs_enabled;
492 bool opened;
493 int err = 0;
494
495 if (!count) {
496 netdev_info(priv->netdev, "%s: combined_count=0 not supported\n",
497 __func__);
498 return -EINVAL;
499 }
500
501 if (cur_params->num_channels == count)
502 return 0;
503
504 mutex_lock(&priv->state_lock);
505
506 if (mlx5e_rx_res_get_current_hash(priv->rx_res).hfunc == ETH_RSS_HASH_XOR) {
507 unsigned int xor8_max_channels = mlx5e_rqt_max_num_channels_allowed_for_xor8();
508
509 if (count > xor8_max_channels) {
510 err = -EINVAL;
511 netdev_err(priv->netdev, "%s: Requested number of channels (%d) exceeds the maximum allowed by the XOR8 RSS hfunc (%d)\n",
512 __func__, count, xor8_max_channels);
513 goto out;
514 }
515 }
516
517 /* If RXFH is configured, changing the channels number is allowed only if
518 * it does not require resizing the RSS table. This is because the previous
519 * configuration may no longer be compatible with the new RSS table.
520 */
521 if (netif_is_rxfh_configured(priv->netdev)) {
522 int cur_rqt_size = mlx5e_rqt_size(priv->mdev, cur_params->num_channels);
523 int new_rqt_size = mlx5e_rqt_size(priv->mdev, count);
524
525 if (new_rqt_size != cur_rqt_size) {
526 err = -EINVAL;
527 netdev_err(priv->netdev,
528 "%s: RXFH is configured, block changing channels number that affects RSS table size (new: %d, current: %d)\n",
529 __func__, new_rqt_size, cur_rqt_size);
530 goto out;
531 }
532 }
533
534 /* Don't allow changing the number of channels if HTB offload is active,
535 * because the numeration of the QoS SQs will change, while per-queue
536 * qdiscs are attached.
537 */
538 if (mlx5e_selq_is_htb_enabled(&priv->selq)) {
539 err = -EINVAL;
540 netdev_err(priv->netdev, "%s: HTB offload is active, cannot change the number of channels\n",
541 __func__);
542 goto out;
543 }
544
545 /* Don't allow changing the number of channels if MQPRIO mode channel offload is active,
546 * because it defines a partition over the channels queues.
547 */
548 if (cur_params->mqprio.mode == TC_MQPRIO_MODE_CHANNEL) {
549 err = -EINVAL;
550 netdev_err(priv->netdev, "%s: MQPRIO mode channel offload is active, cannot change the number of channels\n",
551 __func__);
552 goto out;
553 }
554
555 new_params = *cur_params;
556 new_params.num_channels = count;
557
558 opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
559
560 arfs_enabled = opened && mlx5e_fs_want_arfs(priv->netdev);
561 if (arfs_enabled)
562 mlx5e_arfs_disable(priv->fs);
563
564 /* Switch to new channels, set new parameters and close old ones */
565 err = mlx5e_safe_switch_params(priv, &new_params,
566 mlx5e_num_channels_changed_ctx, NULL, true);
567
568 if (arfs_enabled) {
569 int err2 = mlx5e_arfs_enable(priv->fs);
570
571 if (err2)
572 netdev_err(priv->netdev, "%s: mlx5e_arfs_enable failed: %d\n",
573 __func__, err2);
574 }
575
576 out:
577 mutex_unlock(&priv->state_lock);
578
579 return err;
580 }
581
mlx5e_set_channels(struct net_device * dev,struct ethtool_channels * ch)582 static int mlx5e_set_channels(struct net_device *dev,
583 struct ethtool_channels *ch)
584 {
585 struct mlx5e_priv *priv = netdev_priv(dev);
586
587 return mlx5e_ethtool_set_channels(priv, ch);
588 }
589
mlx5e_ethtool_get_coalesce(struct mlx5e_priv * priv,struct ethtool_coalesce * coal,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)590 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
591 struct ethtool_coalesce *coal,
592 struct kernel_ethtool_coalesce *kernel_coal,
593 struct netlink_ext_ack *extack)
594 {
595 struct dim_cq_moder *rx_moder, *tx_moder;
596
597 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation)) {
598 NL_SET_ERR_MSG_MOD(extack, "CQ moderation not supported");
599 return -EOPNOTSUPP;
600 }
601
602 rx_moder = &priv->channels.params.rx_cq_moderation;
603 coal->rx_coalesce_usecs = rx_moder->usec;
604 coal->rx_max_coalesced_frames = rx_moder->pkts;
605 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_dim_enabled;
606 kernel_coal->use_cqe_mode_rx = priv->channels.params.rx_moder_use_cqe_mode;
607
608 tx_moder = &priv->channels.params.tx_cq_moderation;
609 coal->tx_coalesce_usecs = tx_moder->usec;
610 coal->tx_max_coalesced_frames = tx_moder->pkts;
611 coal->use_adaptive_tx_coalesce = priv->channels.params.tx_dim_enabled;
612 kernel_coal->use_cqe_mode_tx = priv->channels.params.tx_moder_use_cqe_mode;
613
614 return 0;
615 }
616
mlx5e_get_coalesce(struct net_device * netdev,struct ethtool_coalesce * coal,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)617 static int mlx5e_get_coalesce(struct net_device *netdev,
618 struct ethtool_coalesce *coal,
619 struct kernel_ethtool_coalesce *kernel_coal,
620 struct netlink_ext_ack *extack)
621 {
622 struct mlx5e_priv *priv = netdev_priv(netdev);
623
624 return mlx5e_ethtool_get_coalesce(priv, coal, kernel_coal, extack);
625 }
626
mlx5e_ethtool_get_per_queue_coalesce(struct mlx5e_priv * priv,u32 queue,struct ethtool_coalesce * coal)627 static int mlx5e_ethtool_get_per_queue_coalesce(struct mlx5e_priv *priv, u32 queue,
628 struct ethtool_coalesce *coal)
629 {
630 struct dim_cq_moder cur_moder;
631 struct mlx5e_channels *chs;
632 struct mlx5e_channel *c;
633
634 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
635 return -EOPNOTSUPP;
636
637 mutex_lock(&priv->state_lock);
638
639 chs = &priv->channels;
640 if (chs->num <= queue) {
641 mutex_unlock(&priv->state_lock);
642 return -EINVAL;
643 }
644
645 c = chs->c[queue];
646
647 coal->use_adaptive_rx_coalesce = !!c->rq.dim;
648 if (coal->use_adaptive_rx_coalesce) {
649 cur_moder = net_dim_get_rx_moderation(c->rq.dim->mode,
650 c->rq.dim->profile_ix);
651
652 coal->rx_coalesce_usecs = cur_moder.usec;
653 coal->rx_max_coalesced_frames = cur_moder.pkts;
654 } else {
655 coal->rx_coalesce_usecs = c->rx_cq_moder.usec;
656 coal->rx_max_coalesced_frames = c->rx_cq_moder.pkts;
657 }
658
659 coal->use_adaptive_tx_coalesce = !!c->sq[0].dim;
660 if (coal->use_adaptive_tx_coalesce) {
661 /* NOTE: Will only display DIM coalesce profile information of
662 * first channel. The current interface cannot display this
663 * information for all tc.
664 */
665 cur_moder = net_dim_get_tx_moderation(c->sq[0].dim->mode,
666 c->sq[0].dim->profile_ix);
667
668 coal->tx_coalesce_usecs = cur_moder.usec;
669 coal->tx_max_coalesced_frames = cur_moder.pkts;
670
671 } else {
672 coal->tx_coalesce_usecs = c->tx_cq_moder.usec;
673 coal->tx_max_coalesced_frames = c->tx_cq_moder.pkts;
674 }
675
676 mutex_unlock(&priv->state_lock);
677
678 return 0;
679 }
680
mlx5e_get_per_queue_coalesce(struct net_device * dev,u32 queue,struct ethtool_coalesce * coal)681 int mlx5e_get_per_queue_coalesce(struct net_device *dev, u32 queue,
682 struct ethtool_coalesce *coal)
683 {
684 struct mlx5e_priv *priv = netdev_priv(dev);
685
686 return mlx5e_ethtool_get_per_queue_coalesce(priv, queue, coal);
687 }
688
689 #define MLX5E_MAX_COAL_TIME MLX5_MAX_CQ_PERIOD
690 #define MLX5E_MAX_COAL_FRAMES MLX5_MAX_CQ_COUNT
691
692 static void
mlx5e_set_priv_channels_tx_coalesce(struct mlx5e_priv * priv,struct dim_cq_moder * moder)693 mlx5e_set_priv_channels_tx_coalesce(struct mlx5e_priv *priv, struct dim_cq_moder *moder)
694 {
695 int tc;
696 int i;
697
698 for (i = 0; i < priv->channels.num; ++i) {
699 struct mlx5e_channel *c = priv->channels.c[i];
700 struct mlx5_core_dev *mdev = c->mdev;
701 enum mlx5_cq_period_mode mode;
702
703 mode = mlx5e_cq_period_mode(moder->cq_period_mode);
704 c->tx_cq_moder = *moder;
705
706 for (tc = 0; tc < c->num_tc; tc++) {
707 mlx5e_modify_cq_moderation(mdev, &c->sq[tc].cq.mcq,
708 moder->usec, moder->pkts,
709 mode);
710 }
711 }
712 }
713
714 static void
mlx5e_set_priv_channels_rx_coalesce(struct mlx5e_priv * priv,struct dim_cq_moder * moder)715 mlx5e_set_priv_channels_rx_coalesce(struct mlx5e_priv *priv, struct dim_cq_moder *moder)
716 {
717 int i;
718
719 for (i = 0; i < priv->channels.num; ++i) {
720 struct mlx5e_channel *c = priv->channels.c[i];
721 struct mlx5_core_dev *mdev = c->mdev;
722 enum mlx5_cq_period_mode mode;
723
724 mode = mlx5e_cq_period_mode(moder->cq_period_mode);
725 c->rx_cq_moder = *moder;
726
727 mlx5e_modify_cq_moderation(mdev, &c->rq.cq.mcq, moder->usec, moder->pkts,
728 mode);
729 }
730 }
731
mlx5e_ethtool_set_coalesce(struct mlx5e_priv * priv,struct ethtool_coalesce * coal,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)732 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
733 struct ethtool_coalesce *coal,
734 struct kernel_ethtool_coalesce *kernel_coal,
735 struct netlink_ext_ack *extack)
736 {
737 struct dim_cq_moder *rx_moder, *tx_moder;
738 struct mlx5_core_dev *mdev = priv->mdev;
739 bool rx_dim_enabled, tx_dim_enabled;
740 struct mlx5e_params new_params;
741 bool reset_rx, reset_tx;
742 u8 cq_period_mode;
743 int err = 0;
744
745 if (!MLX5_CAP_GEN(mdev, cq_moderation) ||
746 !MLX5_CAP_GEN(mdev, cq_period_mode_modify)) {
747 NL_SET_ERR_MSG_MOD(extack, "CQ moderation not supported");
748 return -EOPNOTSUPP;
749 }
750
751 if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME ||
752 coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) {
753 NL_SET_ERR_MSG_FMT_MOD(
754 extack,
755 "Max coalesce time %lu usecs, tx-usecs (%u) rx-usecs (%u)",
756 MLX5E_MAX_COAL_TIME, coal->tx_coalesce_usecs,
757 coal->rx_coalesce_usecs);
758 return -ERANGE;
759 }
760
761 if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES ||
762 coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) {
763 NL_SET_ERR_MSG_FMT_MOD(
764 extack,
765 "Max coalesce frames %lu, tx-frames (%u) rx-frames (%u)",
766 MLX5E_MAX_COAL_FRAMES, coal->tx_max_coalesced_frames,
767 coal->rx_max_coalesced_frames);
768 return -ERANGE;
769 }
770
771 if ((kernel_coal->use_cqe_mode_rx || kernel_coal->use_cqe_mode_tx) &&
772 !MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) {
773 NL_SET_ERR_MSG_MOD(extack, "cqe-mode-rx/tx is not supported on this device");
774 return -EOPNOTSUPP;
775 }
776
777 rx_dim_enabled = !!coal->use_adaptive_rx_coalesce;
778 tx_dim_enabled = !!coal->use_adaptive_tx_coalesce;
779
780 mutex_lock(&priv->state_lock);
781 new_params = priv->channels.params;
782
783 cq_period_mode = mlx5e_dim_cq_period_mode(kernel_coal->use_cqe_mode_rx);
784 reset_rx = mlx5e_reset_rx_channels_moderation(&priv->channels, cq_period_mode,
785 rx_dim_enabled, false);
786 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_RX_CQE_BASED_MODER, cq_period_mode);
787
788 cq_period_mode = mlx5e_dim_cq_period_mode(kernel_coal->use_cqe_mode_tx);
789 reset_tx = mlx5e_reset_tx_channels_moderation(&priv->channels, cq_period_mode,
790 tx_dim_enabled, false);
791 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_TX_CQE_BASED_MODER, cq_period_mode);
792
793 reset_rx |= rx_dim_enabled != new_params.rx_dim_enabled;
794 reset_tx |= tx_dim_enabled != new_params.tx_dim_enabled;
795
796 /* Solely used for global ethtool get coalesce */
797 rx_moder = &new_params.rx_cq_moderation;
798 new_params.rx_dim_enabled = rx_dim_enabled;
799 new_params.rx_moder_use_cqe_mode = kernel_coal->use_cqe_mode_rx;
800
801 tx_moder = &new_params.tx_cq_moderation;
802 new_params.tx_dim_enabled = tx_dim_enabled;
803 new_params.tx_moder_use_cqe_mode = kernel_coal->use_cqe_mode_tx;
804
805 if (reset_rx) {
806 mlx5e_channels_rx_change_dim(&priv->channels, false);
807 mlx5e_reset_rx_moderation(rx_moder, new_params.rx_moder_use_cqe_mode,
808 rx_dim_enabled);
809
810 mlx5e_set_priv_channels_rx_coalesce(priv, rx_moder);
811 } else if (!rx_dim_enabled) {
812 rx_moder->usec = coal->rx_coalesce_usecs;
813 rx_moder->pkts = coal->rx_max_coalesced_frames;
814
815 mlx5e_set_priv_channels_rx_coalesce(priv, rx_moder);
816 }
817
818 if (reset_tx) {
819 mlx5e_channels_tx_change_dim(&priv->channels, false);
820 mlx5e_reset_tx_moderation(tx_moder, new_params.tx_moder_use_cqe_mode,
821 tx_dim_enabled);
822
823 mlx5e_set_priv_channels_tx_coalesce(priv, tx_moder);
824 } else if (!tx_dim_enabled) {
825 tx_moder->usec = coal->tx_coalesce_usecs;
826 tx_moder->pkts = coal->tx_max_coalesced_frames;
827
828 mlx5e_set_priv_channels_tx_coalesce(priv, tx_moder);
829 }
830
831 /* DIM enable/disable Rx and Tx channels */
832 err = mlx5e_channels_rx_change_dim(&priv->channels, rx_dim_enabled);
833 if (err)
834 goto state_unlock;
835 err = mlx5e_channels_tx_change_dim(&priv->channels, tx_dim_enabled);
836 if (err)
837 goto state_unlock;
838
839 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, false);
840 state_unlock:
841 mutex_unlock(&priv->state_lock);
842 return err;
843 }
844
mlx5e_set_coalesce(struct net_device * netdev,struct ethtool_coalesce * coal,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)845 static int mlx5e_set_coalesce(struct net_device *netdev,
846 struct ethtool_coalesce *coal,
847 struct kernel_ethtool_coalesce *kernel_coal,
848 struct netlink_ext_ack *extack)
849 {
850 struct mlx5e_priv *priv = netdev_priv(netdev);
851
852 return mlx5e_ethtool_set_coalesce(priv, coal, kernel_coal, extack);
853 }
854
mlx5e_ethtool_set_per_queue_coalesce(struct mlx5e_priv * priv,u32 queue,struct ethtool_coalesce * coal)855 static int mlx5e_ethtool_set_per_queue_coalesce(struct mlx5e_priv *priv, u32 queue,
856 struct ethtool_coalesce *coal)
857 {
858 struct mlx5_core_dev *mdev = priv->mdev;
859 bool rx_dim_enabled, tx_dim_enabled;
860 struct mlx5e_channels *chs;
861 struct mlx5e_channel *c;
862 int err = 0;
863 int tc;
864
865 if (!MLX5_CAP_GEN(mdev, cq_moderation))
866 return -EOPNOTSUPP;
867
868 if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME ||
869 coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) {
870 netdev_info(priv->netdev, "%s: maximum coalesce time supported is %lu usecs\n",
871 __func__, MLX5E_MAX_COAL_TIME);
872 return -ERANGE;
873 }
874
875 if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES ||
876 coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) {
877 netdev_info(priv->netdev, "%s: maximum coalesced frames supported is %lu\n",
878 __func__, MLX5E_MAX_COAL_FRAMES);
879 return -ERANGE;
880 }
881
882 rx_dim_enabled = !!coal->use_adaptive_rx_coalesce;
883 tx_dim_enabled = !!coal->use_adaptive_tx_coalesce;
884
885 mutex_lock(&priv->state_lock);
886
887 chs = &priv->channels;
888 if (chs->num <= queue) {
889 mutex_unlock(&priv->state_lock);
890 return -EINVAL;
891 }
892
893 c = chs->c[queue];
894
895 err = mlx5e_dim_rx_change(&c->rq, rx_dim_enabled);
896 if (err)
897 goto state_unlock;
898
899 for (tc = 0; tc < c->num_tc; tc++) {
900 err = mlx5e_dim_tx_change(&c->sq[tc], tx_dim_enabled);
901 if (err)
902 goto state_unlock;
903 }
904
905 if (!rx_dim_enabled) {
906 c->rx_cq_moder.usec = coal->rx_coalesce_usecs;
907 c->rx_cq_moder.pkts = coal->rx_max_coalesced_frames;
908
909 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
910 coal->rx_coalesce_usecs,
911 coal->rx_max_coalesced_frames);
912 }
913
914 if (!tx_dim_enabled) {
915 c->tx_cq_moder.usec = coal->tx_coalesce_usecs;
916 c->tx_cq_moder.pkts = coal->tx_max_coalesced_frames;
917
918 for (tc = 0; tc < c->num_tc; tc++)
919 mlx5_core_modify_cq_moderation(mdev, &c->sq[tc].cq.mcq,
920 coal->tx_coalesce_usecs,
921 coal->tx_max_coalesced_frames);
922 }
923
924 state_unlock:
925 mutex_unlock(&priv->state_lock);
926 return err;
927 }
928
mlx5e_set_per_queue_coalesce(struct net_device * dev,u32 queue,struct ethtool_coalesce * coal)929 int mlx5e_set_per_queue_coalesce(struct net_device *dev, u32 queue,
930 struct ethtool_coalesce *coal)
931 {
932 struct mlx5e_priv *priv = netdev_priv(dev);
933
934 return mlx5e_ethtool_set_per_queue_coalesce(priv, queue, coal);
935 }
936
ptys2ethtool_process_link(u32 eth_eproto,bool ext,bool advertised,unsigned long * modes)937 static void ptys2ethtool_process_link(u32 eth_eproto, bool ext, bool advertised,
938 unsigned long *modes)
939 {
940 unsigned long eproto = eth_eproto;
941 struct ptys2ethtool_config *table;
942 u32 max_size;
943 int proto;
944
945 mlx5e_ethtool_get_speed_arr(ext, &table, &max_size);
946 for_each_set_bit(proto, &eproto, max_size)
947 bitmap_or(modes, modes,
948 advertised ?
949 table[proto].advertised : table[proto].supported,
950 __ETHTOOL_LINK_MODE_MASK_NBITS);
951 }
952
953 static const u32 pplm_fec_2_ethtool[] = {
954 [MLX5E_FEC_NOFEC] = ETHTOOL_FEC_OFF,
955 [MLX5E_FEC_FIRECODE] = ETHTOOL_FEC_BASER,
956 [MLX5E_FEC_RS_528_514] = ETHTOOL_FEC_RS,
957 [MLX5E_FEC_RS_544_514] = ETHTOOL_FEC_RS,
958 [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_FEC_LLRS,
959 [MLX5E_FEC_RS_544_514_INTERLEAVED_QUAD] = ETHTOOL_FEC_RS,
960 };
961
pplm2ethtool_fec(u_long fec_mode,unsigned long size)962 static u32 pplm2ethtool_fec(u_long fec_mode, unsigned long size)
963 {
964 int mode = 0;
965
966 if (!fec_mode)
967 return ETHTOOL_FEC_AUTO;
968
969 mode = find_first_bit(&fec_mode, size);
970
971 if (mode < ARRAY_SIZE(pplm_fec_2_ethtool))
972 return pplm_fec_2_ethtool[mode];
973
974 return 0;
975 }
976
977 #define MLX5E_ADVERTISE_SUPPORTED_FEC(mlx5_fec, ethtool_fec) \
978 do { \
979 if (mlx5e_fec_in_caps(dev, 1 << (mlx5_fec))) \
980 __set_bit(ethtool_fec, \
981 link_ksettings->link_modes.supported);\
982 } while (0)
983
984 static const u32 pplm_fec_2_ethtool_linkmodes[] = {
985 [MLX5E_FEC_NOFEC] = ETHTOOL_LINK_MODE_FEC_NONE_BIT,
986 [MLX5E_FEC_FIRECODE] = ETHTOOL_LINK_MODE_FEC_BASER_BIT,
987 [MLX5E_FEC_RS_528_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT,
988 [MLX5E_FEC_RS_544_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT,
989 [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
990 };
991
get_fec_supported_advertised(struct mlx5_core_dev * dev,struct ethtool_link_ksettings * link_ksettings)992 static int get_fec_supported_advertised(struct mlx5_core_dev *dev,
993 struct ethtool_link_ksettings *link_ksettings)
994 {
995 unsigned long active_fec_long;
996 u32 active_fec;
997 u32 bitn;
998 int err;
999
1000 err = mlx5e_get_fec_mode(dev, &active_fec, NULL);
1001 if (err)
1002 return (err == -EOPNOTSUPP) ? 0 : err;
1003
1004 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_NOFEC,
1005 ETHTOOL_LINK_MODE_FEC_NONE_BIT);
1006 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_FIRECODE,
1007 ETHTOOL_LINK_MODE_FEC_BASER_BIT);
1008 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_RS_528_514,
1009 ETHTOOL_LINK_MODE_FEC_RS_BIT);
1010 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_LLRS_272_257_1,
1011 ETHTOOL_LINK_MODE_FEC_LLRS_BIT);
1012
1013 active_fec_long = active_fec;
1014 /* active fec is a bit set, find out which bit is set and
1015 * advertise the corresponding ethtool bit
1016 */
1017 bitn = find_first_bit(&active_fec_long, sizeof(active_fec_long) * BITS_PER_BYTE);
1018 if (bitn < ARRAY_SIZE(pplm_fec_2_ethtool_linkmodes))
1019 __set_bit(pplm_fec_2_ethtool_linkmodes[bitn],
1020 link_ksettings->link_modes.advertising);
1021
1022 return 0;
1023 }
1024
ptys2ethtool_supported_advertised_port(struct mlx5_core_dev * mdev,struct ethtool_link_ksettings * link_ksettings,u32 eth_proto_cap,u8 connector_type)1025 static void ptys2ethtool_supported_advertised_port(struct mlx5_core_dev *mdev,
1026 struct ethtool_link_ksettings *link_ksettings,
1027 u32 eth_proto_cap, u8 connector_type)
1028 {
1029 if (!MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type)) {
1030 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
1031 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
1032 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
1033 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
1034 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
1035 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
1036 ethtool_link_ksettings_add_link_mode(link_ksettings,
1037 supported,
1038 FIBRE);
1039 ethtool_link_ksettings_add_link_mode(link_ksettings,
1040 advertising,
1041 FIBRE);
1042 }
1043
1044 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
1045 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
1046 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
1047 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
1048 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
1049 ethtool_link_ksettings_add_link_mode(link_ksettings,
1050 supported,
1051 Backplane);
1052 ethtool_link_ksettings_add_link_mode(link_ksettings,
1053 advertising,
1054 Backplane);
1055 }
1056 return;
1057 }
1058
1059 switch (connector_type) {
1060 case MLX5E_PORT_TP:
1061 ethtool_link_ksettings_add_link_mode(link_ksettings,
1062 supported, TP);
1063 ethtool_link_ksettings_add_link_mode(link_ksettings,
1064 advertising, TP);
1065 break;
1066 case MLX5E_PORT_AUI:
1067 ethtool_link_ksettings_add_link_mode(link_ksettings,
1068 supported, AUI);
1069 ethtool_link_ksettings_add_link_mode(link_ksettings,
1070 advertising, AUI);
1071 break;
1072 case MLX5E_PORT_BNC:
1073 ethtool_link_ksettings_add_link_mode(link_ksettings,
1074 supported, BNC);
1075 ethtool_link_ksettings_add_link_mode(link_ksettings,
1076 advertising, BNC);
1077 break;
1078 case MLX5E_PORT_MII:
1079 ethtool_link_ksettings_add_link_mode(link_ksettings,
1080 supported, MII);
1081 ethtool_link_ksettings_add_link_mode(link_ksettings,
1082 advertising, MII);
1083 break;
1084 case MLX5E_PORT_FIBRE:
1085 ethtool_link_ksettings_add_link_mode(link_ksettings,
1086 supported, FIBRE);
1087 ethtool_link_ksettings_add_link_mode(link_ksettings,
1088 advertising, FIBRE);
1089 break;
1090 case MLX5E_PORT_DA:
1091 ethtool_link_ksettings_add_link_mode(link_ksettings,
1092 supported, Backplane);
1093 ethtool_link_ksettings_add_link_mode(link_ksettings,
1094 advertising, Backplane);
1095 break;
1096 case MLX5E_PORT_NONE:
1097 case MLX5E_PORT_OTHER:
1098 default:
1099 break;
1100 }
1101 }
1102
get_link_properties(struct net_device * netdev,u32 eth_proto_oper,bool force_legacy,u16 data_rate_oper,struct ethtool_link_ksettings * link_ksettings)1103 static void get_link_properties(struct net_device *netdev,
1104 u32 eth_proto_oper, bool force_legacy,
1105 u16 data_rate_oper,
1106 struct ethtool_link_ksettings *link_ksettings)
1107 {
1108 struct mlx5e_priv *priv = netdev_priv(netdev);
1109 const struct mlx5_link_info *info;
1110 u8 duplex = DUPLEX_UNKNOWN;
1111 u32 speed = SPEED_UNKNOWN;
1112 u32 lanes = LANES_UNKNOWN;
1113
1114 if (!netif_carrier_ok(netdev))
1115 goto out;
1116
1117 info = mlx5_port_ptys2info(priv->mdev, eth_proto_oper, force_legacy);
1118 if (info) {
1119 speed = info->speed;
1120 lanes = info->lanes;
1121 duplex = DUPLEX_FULL;
1122 } else if (data_rate_oper)
1123 speed = 100 * data_rate_oper;
1124
1125 out:
1126 link_ksettings->base.duplex = duplex;
1127 link_ksettings->base.speed = speed;
1128 link_ksettings->lanes = lanes;
1129 }
1130
get_supported(struct mlx5_core_dev * mdev,u32 eth_proto_cap,struct ethtool_link_ksettings * link_ksettings)1131 static void get_supported(struct mlx5_core_dev *mdev, u32 eth_proto_cap,
1132 struct ethtool_link_ksettings *link_ksettings)
1133 {
1134 unsigned long *supported = link_ksettings->link_modes.supported;
1135 bool ext = mlx5_ptys_ext_supported(mdev);
1136
1137 ptys2ethtool_process_link(eth_proto_cap, ext, false, supported);
1138
1139 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
1140 }
1141
get_advertising(u32 eth_proto_admin,u8 tx_pause,u8 rx_pause,struct ethtool_link_ksettings * link_ksettings,bool ext)1142 static void get_advertising(u32 eth_proto_admin, u8 tx_pause, u8 rx_pause,
1143 struct ethtool_link_ksettings *link_ksettings,
1144 bool ext)
1145 {
1146 unsigned long *advertising = link_ksettings->link_modes.advertising;
1147 ptys2ethtool_process_link(eth_proto_admin, ext, true, advertising);
1148 if (rx_pause)
1149 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
1150 if (tx_pause ^ rx_pause)
1151 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
1152 }
1153
1154 static int ptys2connector_type[MLX5E_CONNECTOR_TYPE_NUMBER] = {
1155 [MLX5E_PORT_UNKNOWN] = PORT_OTHER,
1156 [MLX5E_PORT_NONE] = PORT_NONE,
1157 [MLX5E_PORT_TP] = PORT_TP,
1158 [MLX5E_PORT_AUI] = PORT_AUI,
1159 [MLX5E_PORT_BNC] = PORT_BNC,
1160 [MLX5E_PORT_MII] = PORT_MII,
1161 [MLX5E_PORT_FIBRE] = PORT_FIBRE,
1162 [MLX5E_PORT_DA] = PORT_DA,
1163 [MLX5E_PORT_OTHER] = PORT_OTHER,
1164 };
1165
get_connector_port(struct mlx5_core_dev * mdev,u32 eth_proto,u8 connector_type)1166 static u8 get_connector_port(struct mlx5_core_dev *mdev, u32 eth_proto, u8 connector_type)
1167 {
1168 if (MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type))
1169 return ptys2connector_type[connector_type];
1170
1171 if (eth_proto &
1172 (MLX5E_PROT_MASK(MLX5E_10GBASE_SR) |
1173 MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) |
1174 MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) |
1175 MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
1176 return PORT_FIBRE;
1177 }
1178
1179 if (eth_proto &
1180 (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) |
1181 MLX5E_PROT_MASK(MLX5E_10GBASE_CR) |
1182 MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
1183 return PORT_DA;
1184 }
1185
1186 if (eth_proto &
1187 (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) |
1188 MLX5E_PROT_MASK(MLX5E_10GBASE_KR) |
1189 MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) |
1190 MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
1191 return PORT_NONE;
1192 }
1193
1194 return PORT_OTHER;
1195 }
1196
get_lp_advertising(struct mlx5_core_dev * mdev,u32 eth_proto_lp,struct ethtool_link_ksettings * link_ksettings)1197 static void get_lp_advertising(struct mlx5_core_dev *mdev, u32 eth_proto_lp,
1198 struct ethtool_link_ksettings *link_ksettings)
1199 {
1200 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
1201 bool ext = mlx5_ptys_ext_supported(mdev);
1202
1203 ptys2ethtool_process_link(eth_proto_lp, ext, true, lp_advertising);
1204 }
1205
mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv * priv,struct ethtool_link_ksettings * link_ksettings)1206 static int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
1207 struct ethtool_link_ksettings *link_ksettings)
1208 {
1209 struct mlx5_core_dev *mdev = priv->mdev;
1210 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {};
1211 u32 eth_proto_admin;
1212 u8 an_disable_admin;
1213 u16 data_rate_oper;
1214 u32 eth_proto_oper;
1215 u32 eth_proto_cap;
1216 u8 connector_type;
1217 u32 rx_pause = 0;
1218 u32 tx_pause = 0;
1219 u32 eth_proto_lp;
1220 bool admin_ext;
1221 u8 an_status;
1222 bool ext;
1223 int err;
1224
1225 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1, 0);
1226 if (err) {
1227 netdev_err(priv->netdev, "%s: query port ptys failed: %d\n",
1228 __func__, err);
1229 goto err_query_regs;
1230 }
1231 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability);
1232 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
1233 eth_proto_capability);
1234 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
1235 eth_proto_admin);
1236 /* Fields: eth_proto_admin and ext_eth_proto_admin are
1237 * mutually exclusive. Hence try reading legacy advertising
1238 * when extended advertising is zero.
1239 * admin_ext indicates which proto_admin (ext vs. legacy)
1240 * should be read and interpreted
1241 */
1242 admin_ext = ext;
1243 if (ext && !eth_proto_admin) {
1244 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, false,
1245 eth_proto_admin);
1246 admin_ext = false;
1247 }
1248
1249 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, admin_ext,
1250 eth_proto_oper);
1251 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
1252 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
1253 an_status = MLX5_GET(ptys_reg, out, an_status);
1254 connector_type = MLX5_GET(ptys_reg, out, connector_type);
1255 data_rate_oper = MLX5_GET(ptys_reg, out, data_rate_oper);
1256
1257 mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
1258
1259 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
1260 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
1261
1262 get_supported(mdev, eth_proto_cap, link_ksettings);
1263 get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings,
1264 admin_ext);
1265 get_link_properties(priv->netdev, eth_proto_oper, !admin_ext,
1266 data_rate_oper, link_ksettings);
1267
1268 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
1269 connector_type = connector_type < MLX5E_CONNECTOR_TYPE_NUMBER ?
1270 connector_type : MLX5E_PORT_UNKNOWN;
1271 link_ksettings->base.port = get_connector_port(mdev, eth_proto_oper, connector_type);
1272 ptys2ethtool_supported_advertised_port(mdev, link_ksettings, eth_proto_admin,
1273 connector_type);
1274 get_lp_advertising(mdev, eth_proto_lp, link_ksettings);
1275
1276 if (an_status == MLX5_AN_COMPLETE)
1277 ethtool_link_ksettings_add_link_mode(link_ksettings,
1278 lp_advertising, Autoneg);
1279
1280 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
1281 AUTONEG_ENABLE;
1282 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
1283 Autoneg);
1284
1285 err = get_fec_supported_advertised(mdev, link_ksettings);
1286 if (err) {
1287 netdev_dbg(priv->netdev, "%s: FEC caps query failed: %d\n",
1288 __func__, err);
1289 err = 0; /* don't fail caps query because of FEC error */
1290 }
1291
1292 if (!an_disable_admin)
1293 ethtool_link_ksettings_add_link_mode(link_ksettings,
1294 advertising, Autoneg);
1295
1296 err_query_regs:
1297 return err;
1298 }
1299
mlx5e_get_link_ksettings(struct net_device * netdev,struct ethtool_link_ksettings * link_ksettings)1300 static int mlx5e_get_link_ksettings(struct net_device *netdev,
1301 struct ethtool_link_ksettings *link_ksettings)
1302 {
1303 struct mlx5e_priv *priv = netdev_priv(netdev);
1304
1305 return mlx5e_ethtool_get_link_ksettings(priv, link_ksettings);
1306 }
1307
mlx5e_speed_validate(struct net_device * netdev,bool ext,const unsigned long link_modes,u8 autoneg)1308 static int mlx5e_speed_validate(struct net_device *netdev, bool ext,
1309 const unsigned long link_modes, u8 autoneg)
1310 {
1311 /* Extended link-mode has no speed limitations. */
1312 if (ext)
1313 return 0;
1314
1315 if ((link_modes & MLX5E_PROT_MASK(MLX5E_56GBASE_R4)) &&
1316 autoneg != AUTONEG_ENABLE) {
1317 netdev_err(netdev, "%s: 56G link speed requires autoneg enabled\n",
1318 __func__);
1319 return -EINVAL;
1320 }
1321 return 0;
1322 }
1323
mlx5e_ethtool2ptys_adver_link(const unsigned long * link_modes)1324 static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
1325 {
1326 u32 i, ptys_modes = 0;
1327
1328 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
1329 if (bitmap_empty(ptys2legacy_ethtool_table[i].advertised,
1330 __ETHTOOL_LINK_MODE_MASK_NBITS))
1331 continue;
1332 if (bitmap_intersects(ptys2legacy_ethtool_table[i].advertised,
1333 link_modes,
1334 __ETHTOOL_LINK_MODE_MASK_NBITS))
1335 ptys_modes |= MLX5E_PROT_MASK(i);
1336 }
1337
1338 return ptys_modes;
1339 }
1340
mlx5e_ethtool2ptys_ext_adver_link(const unsigned long * link_modes)1341 static u32 mlx5e_ethtool2ptys_ext_adver_link(const unsigned long *link_modes)
1342 {
1343 u32 i, ptys_modes = 0;
1344 __ETHTOOL_DECLARE_LINK_MODE_MASK(modes);
1345
1346 for (i = 0; i < MLX5E_EXT_LINK_MODES_NUMBER; ++i) {
1347 if (bitmap_empty(ptys2ext_ethtool_table[i].advertised,
1348 __ETHTOOL_LINK_MODE_MASK_NBITS))
1349 continue;
1350 bitmap_zero(modes, __ETHTOOL_LINK_MODE_MASK_NBITS);
1351 bitmap_and(modes, ptys2ext_ethtool_table[i].advertised,
1352 link_modes, __ETHTOOL_LINK_MODE_MASK_NBITS);
1353
1354 if (bitmap_equal(modes, ptys2ext_ethtool_table[i].advertised,
1355 __ETHTOOL_LINK_MODE_MASK_NBITS))
1356 ptys_modes |= MLX5E_PROT_MASK(i);
1357 }
1358 return ptys_modes;
1359 }
1360
ext_link_mode_requested(const unsigned long * adver)1361 static bool ext_link_mode_requested(const unsigned long *adver)
1362 {
1363 #define MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT ETHTOOL_LINK_MODE_50000baseKR_Full_BIT
1364 int size = __ETHTOOL_LINK_MODE_MASK_NBITS - MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT;
1365 __ETHTOOL_DECLARE_LINK_MODE_MASK(modes) = {0,};
1366
1367 bitmap_set(modes, MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT, size);
1368 return bitmap_intersects(modes, adver, __ETHTOOL_LINK_MODE_MASK_NBITS);
1369 }
1370
mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv * priv,const struct ethtool_link_ksettings * link_ksettings)1371 static int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
1372 const struct ethtool_link_ksettings *link_ksettings)
1373 {
1374 struct mlx5_core_dev *mdev = priv->mdev;
1375 struct mlx5_port_eth_proto eproto;
1376 struct mlx5_link_info info = {};
1377 const unsigned long *adver;
1378 bool an_changes = false;
1379 u8 an_disable_admin;
1380 bool ext_supported;
1381 bool ext_requested;
1382 u8 an_disable_cap;
1383 bool an_disable;
1384 u32 link_modes;
1385 u8 an_status;
1386 u8 autoneg;
1387 bool ext;
1388 int err;
1389
1390 u32 (*ethtool2ptys_adver_func)(const unsigned long *adver);
1391
1392 adver = link_ksettings->link_modes.advertising;
1393 autoneg = link_ksettings->base.autoneg;
1394 info.speed = link_ksettings->base.speed;
1395 info.lanes = link_ksettings->lanes;
1396
1397 ext_supported = mlx5_ptys_ext_supported(mdev);
1398 ext_requested = ext_link_mode_requested(adver);
1399 if (!ext_supported && ext_requested)
1400 return -EOPNOTSUPP;
1401
1402 ext = autoneg == AUTONEG_ENABLE ? ext_requested : ext_supported;
1403 ethtool2ptys_adver_func = ext ? mlx5e_ethtool2ptys_ext_adver_link :
1404 mlx5e_ethtool2ptys_adver_link;
1405 err = mlx5_port_query_eth_proto(mdev, 1, ext, &eproto);
1406 if (err) {
1407 netdev_err(priv->netdev, "%s: query port eth proto failed: %d\n",
1408 __func__, err);
1409 goto out;
1410 }
1411 link_modes = autoneg == AUTONEG_ENABLE ? ethtool2ptys_adver_func(adver) :
1412 mlx5_port_info2linkmodes(mdev, &info, !ext);
1413
1414 err = mlx5e_speed_validate(priv->netdev, ext, link_modes, autoneg);
1415 if (err)
1416 goto out;
1417
1418 link_modes = link_modes & eproto.cap;
1419 if (!link_modes) {
1420 netdev_err(priv->netdev, "%s: Not supported link mode(s) requested",
1421 __func__);
1422 err = -EINVAL;
1423 goto out;
1424 }
1425
1426 mlx5_port_query_eth_autoneg(mdev, &an_status, &an_disable_cap,
1427 &an_disable_admin);
1428
1429 an_disable = autoneg == AUTONEG_DISABLE;
1430 an_changes = ((!an_disable && an_disable_admin) ||
1431 (an_disable && !an_disable_admin));
1432
1433 if (!an_changes && link_modes == eproto.admin)
1434 goto out;
1435
1436 err = mlx5_port_set_eth_ptys(mdev, an_disable, link_modes, ext);
1437 if (err) {
1438 netdev_err(priv->netdev, "%s: failed to set ptys reg: %d\n", __func__, err);
1439 goto out;
1440 }
1441
1442 mlx5_toggle_port_link(mdev);
1443
1444 out:
1445 return err;
1446 }
1447
mlx5e_set_link_ksettings(struct net_device * netdev,const struct ethtool_link_ksettings * link_ksettings)1448 static int mlx5e_set_link_ksettings(struct net_device *netdev,
1449 const struct ethtool_link_ksettings *link_ksettings)
1450 {
1451 struct mlx5e_priv *priv = netdev_priv(netdev);
1452
1453 return mlx5e_ethtool_set_link_ksettings(priv, link_ksettings);
1454 }
1455
mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv * priv)1456 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv)
1457 {
1458 return sizeof_field(struct mlx5e_rss_params_hash, toeplitz_hash_key);
1459 }
1460
mlx5e_get_rxfh_key_size(struct net_device * netdev)1461 static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
1462 {
1463 struct mlx5e_priv *priv = netdev_priv(netdev);
1464
1465 return mlx5e_ethtool_get_rxfh_key_size(priv);
1466 }
1467
mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv * priv)1468 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv)
1469 {
1470 return mlx5e_rqt_size(priv->mdev, priv->channels.params.num_channels);
1471 }
1472
mlx5e_get_rxfh_indir_size(struct net_device * netdev)1473 static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
1474 {
1475 struct mlx5e_priv *priv = netdev_priv(netdev);
1476
1477 return mlx5e_ethtool_get_rxfh_indir_size(priv);
1478 }
1479
mlx5e_get_rxfh(struct net_device * netdev,struct ethtool_rxfh_param * rxfh)1480 static int mlx5e_get_rxfh(struct net_device *netdev, struct ethtool_rxfh_param *rxfh)
1481 {
1482 struct mlx5e_priv *priv = netdev_priv(netdev);
1483 bool symmetric;
1484
1485 mutex_lock(&priv->state_lock);
1486 mlx5e_rx_res_rss_get_rxfh(priv->rx_res, 0, rxfh->indir, rxfh->key,
1487 &rxfh->hfunc, &symmetric);
1488 mutex_unlock(&priv->state_lock);
1489
1490 if (symmetric)
1491 rxfh->input_xfrm = RXH_XFRM_SYM_OR_XOR;
1492
1493 return 0;
1494 }
1495
mlx5e_rxfh_hfunc_check(struct mlx5e_priv * priv,const struct ethtool_rxfh_param * rxfh,struct netlink_ext_ack * extack)1496 static int mlx5e_rxfh_hfunc_check(struct mlx5e_priv *priv,
1497 const struct ethtool_rxfh_param *rxfh,
1498 struct netlink_ext_ack *extack)
1499 {
1500 unsigned int count;
1501
1502 count = priv->channels.params.num_channels;
1503
1504 if (rxfh->hfunc == ETH_RSS_HASH_XOR) {
1505 unsigned int xor8_max_channels = mlx5e_rqt_max_num_channels_allowed_for_xor8();
1506
1507 if (count > xor8_max_channels) {
1508 NL_SET_ERR_MSG_FMT_MOD(
1509 extack,
1510 "Number of channels (%u) exceeds the max for XOR8 RSS (%u)",
1511 count, xor8_max_channels);
1512 return -EINVAL;
1513 }
1514 }
1515
1516 return 0;
1517 }
1518
mlx5e_set_rxfh(struct net_device * dev,struct ethtool_rxfh_param * rxfh,struct netlink_ext_ack * extack)1519 static int mlx5e_set_rxfh(struct net_device *dev,
1520 struct ethtool_rxfh_param *rxfh,
1521 struct netlink_ext_ack *extack)
1522 {
1523 bool symmetric = rxfh->input_xfrm == RXH_XFRM_SYM_OR_XOR;
1524 struct mlx5e_priv *priv = netdev_priv(dev);
1525 u8 hfunc = rxfh->hfunc;
1526 int err;
1527
1528 mutex_lock(&priv->state_lock);
1529
1530 err = mlx5e_rxfh_hfunc_check(priv, rxfh, extack);
1531 if (err)
1532 goto unlock;
1533
1534 err = mlx5e_rx_res_rss_set_rxfh(priv->rx_res, rxfh->rss_context,
1535 rxfh->indir, rxfh->key,
1536 hfunc == ETH_RSS_HASH_NO_CHANGE ? NULL : &hfunc,
1537 rxfh->input_xfrm == RXH_XFRM_NO_CHANGE ? NULL : &symmetric);
1538
1539 unlock:
1540 mutex_unlock(&priv->state_lock);
1541 return err;
1542 }
1543
mlx5e_create_rxfh_context(struct net_device * dev,struct ethtool_rxfh_context * ctx,const struct ethtool_rxfh_param * rxfh,struct netlink_ext_ack * extack)1544 static int mlx5e_create_rxfh_context(struct net_device *dev,
1545 struct ethtool_rxfh_context *ctx,
1546 const struct ethtool_rxfh_param *rxfh,
1547 struct netlink_ext_ack *extack)
1548 {
1549 bool symmetric = rxfh->input_xfrm == RXH_XFRM_SYM_OR_XOR;
1550 struct mlx5e_priv *priv = netdev_priv(dev);
1551 u8 hfunc = rxfh->hfunc;
1552 int err;
1553
1554 mutex_lock(&priv->state_lock);
1555
1556 err = mlx5e_rxfh_hfunc_check(priv, rxfh, extack);
1557 if (err)
1558 goto unlock;
1559
1560 err = mlx5e_rx_res_rss_init(priv->rx_res, rxfh->rss_context,
1561 priv->channels.params.num_channels);
1562 if (err)
1563 goto unlock;
1564
1565 err = mlx5e_rx_res_rss_set_rxfh(priv->rx_res, rxfh->rss_context,
1566 rxfh->indir, rxfh->key,
1567 hfunc == ETH_RSS_HASH_NO_CHANGE ? NULL : &hfunc,
1568 rxfh->input_xfrm == RXH_XFRM_NO_CHANGE ? NULL : &symmetric);
1569 if (err)
1570 goto unlock;
1571
1572 mlx5e_rx_res_rss_get_rxfh(priv->rx_res, rxfh->rss_context,
1573 ethtool_rxfh_context_indir(ctx),
1574 ethtool_rxfh_context_key(ctx),
1575 &ctx->hfunc, &symmetric);
1576 if (symmetric)
1577 ctx->input_xfrm = RXH_XFRM_SYM_OR_XOR;
1578
1579 unlock:
1580 mutex_unlock(&priv->state_lock);
1581 return err;
1582 }
1583
mlx5e_modify_rxfh_context(struct net_device * dev,struct ethtool_rxfh_context * ctx,const struct ethtool_rxfh_param * rxfh,struct netlink_ext_ack * extack)1584 static int mlx5e_modify_rxfh_context(struct net_device *dev,
1585 struct ethtool_rxfh_context *ctx,
1586 const struct ethtool_rxfh_param *rxfh,
1587 struct netlink_ext_ack *extack)
1588 {
1589 bool symmetric = rxfh->input_xfrm == RXH_XFRM_SYM_OR_XOR;
1590 struct mlx5e_priv *priv = netdev_priv(dev);
1591 u8 hfunc = rxfh->hfunc;
1592 int err;
1593
1594 mutex_lock(&priv->state_lock);
1595
1596 err = mlx5e_rxfh_hfunc_check(priv, rxfh, extack);
1597 if (err)
1598 goto unlock;
1599
1600 err = mlx5e_rx_res_rss_set_rxfh(priv->rx_res, rxfh->rss_context,
1601 rxfh->indir, rxfh->key,
1602 hfunc == ETH_RSS_HASH_NO_CHANGE ? NULL : &hfunc,
1603 rxfh->input_xfrm == RXH_XFRM_NO_CHANGE ? NULL : &symmetric);
1604
1605 unlock:
1606 mutex_unlock(&priv->state_lock);
1607 return err;
1608 }
1609
mlx5e_remove_rxfh_context(struct net_device * dev,struct ethtool_rxfh_context * ctx,u32 rss_context,struct netlink_ext_ack * extack)1610 static int mlx5e_remove_rxfh_context(struct net_device *dev,
1611 struct ethtool_rxfh_context *ctx,
1612 u32 rss_context,
1613 struct netlink_ext_ack *extack)
1614 {
1615 struct mlx5e_priv *priv = netdev_priv(dev);
1616 int err;
1617
1618 mutex_lock(&priv->state_lock);
1619 err = mlx5e_rx_res_rss_destroy(priv->rx_res, rss_context);
1620 mutex_unlock(&priv->state_lock);
1621 return err;
1622 }
1623
1624 #define MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC 100
1625 #define MLX5E_PFC_PREVEN_TOUT_MAX_MSEC 8000
1626 #define MLX5E_PFC_PREVEN_MINOR_PRECENT 85
1627 #define MLX5E_PFC_PREVEN_TOUT_MIN_MSEC 80
1628 #define MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout) \
1629 max_t(u16, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, \
1630 (critical_tout * MLX5E_PFC_PREVEN_MINOR_PRECENT) / 100)
1631
mlx5e_get_pfc_prevention_tout(struct net_device * netdev,u16 * pfc_prevention_tout)1632 static int mlx5e_get_pfc_prevention_tout(struct net_device *netdev,
1633 u16 *pfc_prevention_tout)
1634 {
1635 struct mlx5e_priv *priv = netdev_priv(netdev);
1636 struct mlx5_core_dev *mdev = priv->mdev;
1637
1638 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1639 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1640 return -EOPNOTSUPP;
1641
1642 return mlx5_query_port_stall_watermark(mdev, pfc_prevention_tout, NULL);
1643 }
1644
mlx5e_set_pfc_prevention_tout(struct net_device * netdev,u16 pfc_preven)1645 static int mlx5e_set_pfc_prevention_tout(struct net_device *netdev,
1646 u16 pfc_preven)
1647 {
1648 struct mlx5e_priv *priv = netdev_priv(netdev);
1649 struct mlx5_core_dev *mdev = priv->mdev;
1650 u16 critical_tout;
1651 u16 minor;
1652
1653 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1654 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1655 return -EOPNOTSUPP;
1656
1657 critical_tout = (pfc_preven == PFC_STORM_PREVENTION_AUTO) ?
1658 MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC :
1659 pfc_preven;
1660
1661 if (critical_tout != PFC_STORM_PREVENTION_DISABLE &&
1662 (critical_tout > MLX5E_PFC_PREVEN_TOUT_MAX_MSEC ||
1663 critical_tout < MLX5E_PFC_PREVEN_TOUT_MIN_MSEC)) {
1664 netdev_info(netdev, "%s: pfc prevention tout not in range (%d-%d)\n",
1665 __func__, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC,
1666 MLX5E_PFC_PREVEN_TOUT_MAX_MSEC);
1667 return -EINVAL;
1668 }
1669
1670 minor = MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout);
1671 return mlx5_set_port_stall_watermark(mdev, critical_tout,
1672 minor);
1673 }
1674
mlx5e_get_tunable(struct net_device * dev,const struct ethtool_tunable * tuna,void * data)1675 static int mlx5e_get_tunable(struct net_device *dev,
1676 const struct ethtool_tunable *tuna,
1677 void *data)
1678 {
1679 int err;
1680
1681 switch (tuna->id) {
1682 case ETHTOOL_PFC_PREVENTION_TOUT:
1683 err = mlx5e_get_pfc_prevention_tout(dev, data);
1684 break;
1685 default:
1686 err = -EINVAL;
1687 break;
1688 }
1689
1690 return err;
1691 }
1692
mlx5e_set_tunable(struct net_device * dev,const struct ethtool_tunable * tuna,const void * data)1693 static int mlx5e_set_tunable(struct net_device *dev,
1694 const struct ethtool_tunable *tuna,
1695 const void *data)
1696 {
1697 struct mlx5e_priv *priv = netdev_priv(dev);
1698 int err;
1699
1700 mutex_lock(&priv->state_lock);
1701
1702 switch (tuna->id) {
1703 case ETHTOOL_PFC_PREVENTION_TOUT:
1704 err = mlx5e_set_pfc_prevention_tout(dev, *(u16 *)data);
1705 break;
1706 default:
1707 err = -EINVAL;
1708 break;
1709 }
1710
1711 mutex_unlock(&priv->state_lock);
1712 return err;
1713 }
1714
mlx5e_get_pause_stats(struct net_device * netdev,struct ethtool_pause_stats * pause_stats)1715 static void mlx5e_get_pause_stats(struct net_device *netdev,
1716 struct ethtool_pause_stats *pause_stats)
1717 {
1718 struct mlx5e_priv *priv = netdev_priv(netdev);
1719
1720 mlx5e_stats_pause_get(priv, pause_stats);
1721 }
1722
mlx5e_ethtool_get_pauseparam(struct mlx5e_priv * priv,struct ethtool_pauseparam * pauseparam)1723 static void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1724 struct ethtool_pauseparam *pauseparam)
1725 {
1726 struct mlx5_core_dev *mdev = priv->mdev;
1727 int err;
1728
1729 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1730 &pauseparam->tx_pause);
1731 if (err) {
1732 netdev_err(priv->netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1733 __func__, err);
1734 }
1735 }
1736
mlx5e_get_pauseparam(struct net_device * netdev,struct ethtool_pauseparam * pauseparam)1737 static void mlx5e_get_pauseparam(struct net_device *netdev,
1738 struct ethtool_pauseparam *pauseparam)
1739 {
1740 struct mlx5e_priv *priv = netdev_priv(netdev);
1741
1742 mlx5e_ethtool_get_pauseparam(priv, pauseparam);
1743 }
1744
mlx5e_ethtool_set_pauseparam(struct mlx5e_priv * priv,struct ethtool_pauseparam * pauseparam)1745 static int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1746 struct ethtool_pauseparam *pauseparam)
1747 {
1748 struct mlx5_core_dev *mdev = priv->mdev;
1749 int err;
1750
1751 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
1752 return -EOPNOTSUPP;
1753
1754 if (pauseparam->autoneg)
1755 return -EINVAL;
1756
1757 err = mlx5_set_port_pause(mdev,
1758 pauseparam->rx_pause ? 1 : 0,
1759 pauseparam->tx_pause ? 1 : 0);
1760 if (err) {
1761 netdev_err(priv->netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1762 __func__, err);
1763 }
1764
1765 return err;
1766 }
1767
mlx5e_set_pauseparam(struct net_device * netdev,struct ethtool_pauseparam * pauseparam)1768 static int mlx5e_set_pauseparam(struct net_device *netdev,
1769 struct ethtool_pauseparam *pauseparam)
1770 {
1771 struct mlx5e_priv *priv = netdev_priv(netdev);
1772
1773 return mlx5e_ethtool_set_pauseparam(priv, pauseparam);
1774 }
1775
mlx5e_ethtool_get_ts_info(struct mlx5e_priv * priv,struct kernel_ethtool_ts_info * info)1776 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1777 struct kernel_ethtool_ts_info *info)
1778 {
1779 struct mlx5_core_dev *mdev = priv->mdev;
1780
1781 info->phc_index = mlx5_clock_get_ptp_index(mdev);
1782
1783 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
1784 info->phc_index == -1)
1785 return 0;
1786
1787 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
1788 SOF_TIMESTAMPING_TX_SOFTWARE |
1789 SOF_TIMESTAMPING_RX_HARDWARE |
1790 SOF_TIMESTAMPING_RAW_HARDWARE;
1791
1792 info->tx_types = BIT(HWTSTAMP_TX_OFF) |
1793 BIT(HWTSTAMP_TX_ON);
1794
1795 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
1796 BIT(HWTSTAMP_FILTER_ALL);
1797
1798 return 0;
1799 }
1800
mlx5e_get_ts_info(struct net_device * dev,struct kernel_ethtool_ts_info * info)1801 static int mlx5e_get_ts_info(struct net_device *dev,
1802 struct kernel_ethtool_ts_info *info)
1803 {
1804 struct mlx5e_priv *priv = netdev_priv(dev);
1805
1806 return mlx5e_ethtool_get_ts_info(priv, info);
1807 }
1808
mlx5e_get_wol_supported(struct mlx5_core_dev * mdev)1809 static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1810 {
1811 __u32 ret = 0;
1812
1813 if (MLX5_CAP_GEN(mdev, wol_g))
1814 ret |= WAKE_MAGIC;
1815
1816 if (MLX5_CAP_GEN(mdev, wol_s))
1817 ret |= WAKE_MAGICSECURE;
1818
1819 if (MLX5_CAP_GEN(mdev, wol_a))
1820 ret |= WAKE_ARP;
1821
1822 if (MLX5_CAP_GEN(mdev, wol_b))
1823 ret |= WAKE_BCAST;
1824
1825 if (MLX5_CAP_GEN(mdev, wol_m))
1826 ret |= WAKE_MCAST;
1827
1828 if (MLX5_CAP_GEN(mdev, wol_u))
1829 ret |= WAKE_UCAST;
1830
1831 if (MLX5_CAP_GEN(mdev, wol_p))
1832 ret |= WAKE_PHY;
1833
1834 return ret;
1835 }
1836
mlx5e_reformat_wol_mode_mlx5_to_linux(u8 mode)1837 static __u32 mlx5e_reformat_wol_mode_mlx5_to_linux(u8 mode)
1838 {
1839 __u32 ret = 0;
1840
1841 if (mode & MLX5_WOL_MAGIC)
1842 ret |= WAKE_MAGIC;
1843
1844 if (mode & MLX5_WOL_SECURED_MAGIC)
1845 ret |= WAKE_MAGICSECURE;
1846
1847 if (mode & MLX5_WOL_ARP)
1848 ret |= WAKE_ARP;
1849
1850 if (mode & MLX5_WOL_BROADCAST)
1851 ret |= WAKE_BCAST;
1852
1853 if (mode & MLX5_WOL_MULTICAST)
1854 ret |= WAKE_MCAST;
1855
1856 if (mode & MLX5_WOL_UNICAST)
1857 ret |= WAKE_UCAST;
1858
1859 if (mode & MLX5_WOL_PHY_ACTIVITY)
1860 ret |= WAKE_PHY;
1861
1862 return ret;
1863 }
1864
mlx5e_reformat_wol_mode_linux_to_mlx5(__u32 mode)1865 static u8 mlx5e_reformat_wol_mode_linux_to_mlx5(__u32 mode)
1866 {
1867 u8 ret = 0;
1868
1869 if (mode & WAKE_MAGIC)
1870 ret |= MLX5_WOL_MAGIC;
1871
1872 if (mode & WAKE_MAGICSECURE)
1873 ret |= MLX5_WOL_SECURED_MAGIC;
1874
1875 if (mode & WAKE_ARP)
1876 ret |= MLX5_WOL_ARP;
1877
1878 if (mode & WAKE_BCAST)
1879 ret |= MLX5_WOL_BROADCAST;
1880
1881 if (mode & WAKE_MCAST)
1882 ret |= MLX5_WOL_MULTICAST;
1883
1884 if (mode & WAKE_UCAST)
1885 ret |= MLX5_WOL_UNICAST;
1886
1887 if (mode & WAKE_PHY)
1888 ret |= MLX5_WOL_PHY_ACTIVITY;
1889
1890 return ret;
1891 }
1892
mlx5e_get_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)1893 static void mlx5e_get_wol(struct net_device *netdev,
1894 struct ethtool_wolinfo *wol)
1895 {
1896 struct mlx5e_priv *priv = netdev_priv(netdev);
1897 struct mlx5_core_dev *mdev = priv->mdev;
1898 u8 mlx5_wol_mode;
1899 int err;
1900
1901 memset(wol, 0, sizeof(*wol));
1902
1903 wol->supported = mlx5e_get_wol_supported(mdev);
1904 if (!wol->supported)
1905 return;
1906
1907 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1908 if (err)
1909 return;
1910
1911 wol->wolopts = mlx5e_reformat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1912 }
1913
mlx5e_set_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)1914 static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1915 {
1916 struct mlx5e_priv *priv = netdev_priv(netdev);
1917 struct mlx5_core_dev *mdev = priv->mdev;
1918 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1919 u32 mlx5_wol_mode;
1920
1921 if (!wol_supported)
1922 return -EOPNOTSUPP;
1923
1924 if (wol->wolopts & ~wol_supported)
1925 return -EINVAL;
1926
1927 mlx5_wol_mode = mlx5e_reformat_wol_mode_linux_to_mlx5(wol->wolopts);
1928
1929 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1930 }
1931
mlx5e_get_fec_stats(struct net_device * netdev,struct ethtool_fec_stats * fec_stats,struct ethtool_fec_hist * hist)1932 static void mlx5e_get_fec_stats(struct net_device *netdev,
1933 struct ethtool_fec_stats *fec_stats,
1934 struct ethtool_fec_hist *hist)
1935 {
1936 struct mlx5e_priv *priv = netdev_priv(netdev);
1937
1938 mlx5e_stats_fec_get(priv, fec_stats, hist);
1939 }
1940
mlx5e_get_fecparam(struct net_device * netdev,struct ethtool_fecparam * fecparam)1941 static int mlx5e_get_fecparam(struct net_device *netdev,
1942 struct ethtool_fecparam *fecparam)
1943 {
1944 struct mlx5e_priv *priv = netdev_priv(netdev);
1945 struct mlx5_core_dev *mdev = priv->mdev;
1946 u16 fec_configured;
1947 u32 fec_active;
1948 int err;
1949
1950 err = mlx5e_get_fec_mode(mdev, &fec_active, &fec_configured);
1951
1952 if (err)
1953 return err;
1954
1955 fecparam->active_fec = pplm2ethtool_fec((unsigned long)fec_active,
1956 sizeof(unsigned long) * BITS_PER_BYTE);
1957
1958 if (!fecparam->active_fec)
1959 return -EOPNOTSUPP;
1960
1961 fecparam->fec = pplm2ethtool_fec((unsigned long)fec_configured,
1962 sizeof(unsigned long) * BITS_PER_BYTE);
1963
1964 return 0;
1965 }
1966
mlx5e_set_fecparam(struct net_device * netdev,struct ethtool_fecparam * fecparam)1967 static int mlx5e_set_fecparam(struct net_device *netdev,
1968 struct ethtool_fecparam *fecparam)
1969 {
1970 struct mlx5e_priv *priv = netdev_priv(netdev);
1971 struct mlx5_core_dev *mdev = priv->mdev;
1972 unsigned long fec_bitmap;
1973 u16 fec_policy = 0;
1974 int mode;
1975 int err;
1976
1977 bitmap_from_arr32(&fec_bitmap, &fecparam->fec, sizeof(fecparam->fec) * BITS_PER_BYTE);
1978 if (bitmap_weight(&fec_bitmap, ETHTOOL_FEC_LLRS_BIT + 1) > 1)
1979 return -EOPNOTSUPP;
1980
1981 for (mode = 0; mode < ARRAY_SIZE(pplm_fec_2_ethtool); mode++) {
1982 if (!(pplm_fec_2_ethtool[mode] & fecparam->fec))
1983 continue;
1984 fec_policy |= (1 << mode);
1985 break;
1986 }
1987
1988 err = mlx5e_set_fec_mode(mdev, fec_policy);
1989
1990 if (err)
1991 return err;
1992
1993 mlx5_toggle_port_link(mdev);
1994
1995 return 0;
1996 }
1997
mlx5e_set_phys_id(struct net_device * dev,enum ethtool_phys_id_state state)1998 static int mlx5e_set_phys_id(struct net_device *dev,
1999 enum ethtool_phys_id_state state)
2000 {
2001 struct mlx5e_priv *priv = netdev_priv(dev);
2002 struct mlx5_core_dev *mdev = priv->mdev;
2003 u16 beacon_duration;
2004
2005 if (!MLX5_CAP_GEN(mdev, beacon_led))
2006 return -EOPNOTSUPP;
2007
2008 switch (state) {
2009 case ETHTOOL_ID_ACTIVE:
2010 beacon_duration = MLX5_BEACON_DURATION_INF;
2011 break;
2012 case ETHTOOL_ID_INACTIVE:
2013 beacon_duration = MLX5_BEACON_DURATION_OFF;
2014 break;
2015 default:
2016 return -EOPNOTSUPP;
2017 }
2018
2019 return mlx5_set_port_beacon(mdev, beacon_duration);
2020 }
2021
mlx5e_get_module_info(struct net_device * netdev,struct ethtool_modinfo * modinfo)2022 static int mlx5e_get_module_info(struct net_device *netdev,
2023 struct ethtool_modinfo *modinfo)
2024 {
2025 struct mlx5e_priv *priv = netdev_priv(netdev);
2026 struct mlx5_core_dev *dev = priv->mdev;
2027 int size_read = 0;
2028 u8 data[4] = {0};
2029
2030 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
2031 if (size_read < 2)
2032 return -EIO;
2033
2034 /* data[0] = identifier byte */
2035 switch (data[0]) {
2036 case MLX5_MODULE_ID_QSFP:
2037 modinfo->type = ETH_MODULE_SFF_8436;
2038 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
2039 break;
2040 case MLX5_MODULE_ID_QSFP_PLUS:
2041 case MLX5_MODULE_ID_QSFP28:
2042 /* data[1] = revision id */
2043 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
2044 modinfo->type = ETH_MODULE_SFF_8636;
2045 modinfo->eeprom_len = ETH_MODULE_SFF_8636_MAX_LEN;
2046 } else {
2047 modinfo->type = ETH_MODULE_SFF_8436;
2048 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
2049 }
2050 break;
2051 case MLX5_MODULE_ID_SFP:
2052 modinfo->type = ETH_MODULE_SFF_8472;
2053 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2054 break;
2055 default:
2056 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
2057 __func__, data[0]);
2058 return -EINVAL;
2059 }
2060
2061 return 0;
2062 }
2063
mlx5e_get_module_eeprom(struct net_device * netdev,struct ethtool_eeprom * ee,u8 * data)2064 static int mlx5e_get_module_eeprom(struct net_device *netdev,
2065 struct ethtool_eeprom *ee,
2066 u8 *data)
2067 {
2068 struct mlx5e_priv *priv = netdev_priv(netdev);
2069 struct mlx5_core_dev *mdev = priv->mdev;
2070 int offset = ee->offset;
2071 int size_read;
2072 int i = 0;
2073
2074 if (!ee->len)
2075 return -EINVAL;
2076
2077 memset(data, 0, ee->len);
2078
2079 while (i < ee->len) {
2080 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
2081 data + i);
2082
2083 if (!size_read)
2084 /* Done reading */
2085 return 0;
2086
2087 if (size_read < 0) {
2088 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
2089 __func__, size_read);
2090 return size_read;
2091 }
2092
2093 i += size_read;
2094 offset += size_read;
2095 }
2096
2097 return 0;
2098 }
2099
mlx5e_get_module_eeprom_by_page(struct net_device * netdev,const struct ethtool_module_eeprom * page_data,struct netlink_ext_ack * extack)2100 static int mlx5e_get_module_eeprom_by_page(struct net_device *netdev,
2101 const struct ethtool_module_eeprom *page_data,
2102 struct netlink_ext_ack *extack)
2103 {
2104 struct mlx5e_priv *priv = netdev_priv(netdev);
2105 struct mlx5_module_eeprom_query_params query;
2106 struct mlx5_core_dev *mdev = priv->mdev;
2107 u8 *data = page_data->data;
2108 int size_read;
2109 int i = 0;
2110
2111 if (!page_data->length)
2112 return -EINVAL;
2113
2114 memset(data, 0, page_data->length);
2115
2116 query.offset = page_data->offset;
2117 query.i2c_address = page_data->i2c_address;
2118 query.bank = page_data->bank;
2119 query.page = page_data->page;
2120 while (i < page_data->length) {
2121 query.size = page_data->length - i;
2122 size_read = mlx5_query_module_eeprom_by_page(mdev, &query, data + i);
2123
2124 /* Done reading, return how many bytes was read */
2125 if (!size_read)
2126 return i;
2127
2128 if (size_read < 0) {
2129 NL_SET_ERR_MSG_FMT_MOD(
2130 extack,
2131 "Query module eeprom by page failed, read %u bytes, err %d",
2132 i, size_read);
2133 return size_read;
2134 }
2135
2136 i += size_read;
2137 query.offset += size_read;
2138 }
2139
2140 return i;
2141 }
2142
mlx5e_ethtool_flash_device(struct mlx5e_priv * priv,struct ethtool_flash * flash)2143 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
2144 struct ethtool_flash *flash)
2145 {
2146 struct mlx5_core_dev *mdev = priv->mdev;
2147 struct net_device *dev = priv->netdev;
2148 const struct firmware *fw;
2149 int err;
2150
2151 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
2152 return -EOPNOTSUPP;
2153
2154 err = request_firmware_direct(&fw, flash->data, &dev->dev);
2155 if (err)
2156 return err;
2157
2158 err = mlx5_firmware_flash(mdev, fw, NULL);
2159 release_firmware(fw);
2160
2161 return err;
2162 }
2163
mlx5e_flash_device(struct net_device * dev,struct ethtool_flash * flash)2164 static int mlx5e_flash_device(struct net_device *dev,
2165 struct ethtool_flash *flash)
2166 {
2167 struct mlx5e_priv *priv = netdev_priv(dev);
2168
2169 return mlx5e_ethtool_flash_device(priv, flash);
2170 }
2171
set_pflag_cqe_based_moder(struct net_device * netdev,bool enable,bool is_rx_cq)2172 static int set_pflag_cqe_based_moder(struct net_device *netdev, bool enable,
2173 bool is_rx_cq)
2174 {
2175 struct mlx5e_priv *priv = netdev_priv(netdev);
2176 u8 cq_period_mode, current_cq_period_mode;
2177 struct mlx5e_params new_params;
2178
2179 if (enable && !MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2180 return -EOPNOTSUPP;
2181
2182 cq_period_mode = mlx5e_dim_cq_period_mode(enable);
2183
2184 current_cq_period_mode = is_rx_cq ?
2185 priv->channels.params.rx_cq_moderation.cq_period_mode :
2186 priv->channels.params.tx_cq_moderation.cq_period_mode;
2187
2188 if (cq_period_mode == current_cq_period_mode)
2189 return 0;
2190
2191 new_params = priv->channels.params;
2192 if (is_rx_cq) {
2193 mlx5e_reset_rx_channels_moderation(&priv->channels, cq_period_mode,
2194 false, true);
2195 mlx5e_channels_rx_toggle_dim(&priv->channels);
2196 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
2197 cq_period_mode);
2198 } else {
2199 mlx5e_reset_tx_channels_moderation(&priv->channels, cq_period_mode,
2200 false, true);
2201 mlx5e_channels_tx_toggle_dim(&priv->channels);
2202 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
2203 cq_period_mode);
2204 }
2205
2206 /* Update pflags of existing channels without resetting them */
2207 return mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, false);
2208 }
2209
set_pflag_tx_cqe_based_moder(struct net_device * netdev,bool enable)2210 static int set_pflag_tx_cqe_based_moder(struct net_device *netdev, bool enable)
2211 {
2212 return set_pflag_cqe_based_moder(netdev, enable, false);
2213 }
2214
set_pflag_rx_cqe_based_moder(struct net_device * netdev,bool enable)2215 static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
2216 {
2217 return set_pflag_cqe_based_moder(netdev, enable, true);
2218 }
2219
mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv * priv,bool new_val,bool rx_filter)2220 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val, bool rx_filter)
2221 {
2222 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS);
2223 struct mlx5e_params new_params;
2224 int err = 0;
2225
2226 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
2227 return new_val ? -EOPNOTSUPP : 0;
2228
2229 if (curr_val == new_val)
2230 return 0;
2231
2232 if (new_val && !mlx5e_profile_feature_cap(priv->profile, PTP_RX) && rx_filter) {
2233 netdev_err(priv->netdev,
2234 "Profile doesn't support enabling of CQE compression while hardware time-stamping is enabled.\n");
2235 return -EINVAL;
2236 }
2237
2238 if (priv->channels.params.packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) {
2239 netdev_warn(priv->netdev, "Can't set CQE compression with HW-GRO, disable it first.\n");
2240 return -EINVAL;
2241 }
2242
2243 new_params = priv->channels.params;
2244 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val);
2245 if (rx_filter)
2246 new_params.ptp_rx = new_val;
2247
2248 if (new_params.ptp_rx == priv->channels.params.ptp_rx)
2249 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true);
2250 else
2251 err = mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx,
2252 &new_params.ptp_rx, true);
2253 if (err)
2254 return err;
2255
2256 netdev_dbg(priv->netdev, "MLX5E: RxCqeCmprss was turned %s\n",
2257 MLX5E_GET_PFLAG(&priv->channels.params,
2258 MLX5E_PFLAG_RX_CQE_COMPRESS) ? "ON" : "OFF");
2259
2260 return 0;
2261 }
2262
set_pflag_rx_cqe_compress(struct net_device * netdev,bool enable)2263 static int set_pflag_rx_cqe_compress(struct net_device *netdev,
2264 bool enable)
2265 {
2266 struct mlx5e_priv *priv = netdev_priv(netdev);
2267 struct mlx5_core_dev *mdev = priv->mdev;
2268 bool rx_filter;
2269 int err;
2270
2271 if (!MLX5_CAP_GEN(mdev, cqe_compression))
2272 return -EOPNOTSUPP;
2273
2274 rx_filter = priv->tstamp.rx_filter != HWTSTAMP_FILTER_NONE;
2275 err = mlx5e_modify_rx_cqe_compression_locked(priv, enable, rx_filter);
2276 if (err)
2277 return err;
2278
2279 priv->channels.params.rx_cqe_compress_def = enable;
2280
2281 return 0;
2282 }
2283
set_pflag_rx_striding_rq(struct net_device * netdev,bool enable)2284 static int set_pflag_rx_striding_rq(struct net_device *netdev, bool enable)
2285 {
2286 struct mlx5e_priv *priv = netdev_priv(netdev);
2287 struct mlx5_core_dev *mdev = priv->mdev;
2288 struct mlx5e_params new_params;
2289 int err;
2290
2291 if (enable) {
2292 /* Checking the regular RQ here; mlx5e_validate_xsk_param called
2293 * from mlx5e_open_xsk will check for each XSK queue, and
2294 * mlx5e_safe_switch_params will be reverted if any check fails.
2295 */
2296 int err = mlx5e_mpwrq_validate_regular(mdev, &priv->channels.params);
2297
2298 if (err)
2299 return err;
2300 } else if (priv->channels.params.packet_merge.type != MLX5E_PACKET_MERGE_NONE) {
2301 netdev_warn(netdev, "Can't set legacy RQ with HW-GRO/LRO, disable them first\n");
2302 return -EINVAL;
2303 }
2304
2305 new_params = priv->channels.params;
2306
2307 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_RX_STRIDING_RQ, enable);
2308 mlx5e_set_rq_type(mdev, &new_params);
2309
2310 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true);
2311 if (err)
2312 return err;
2313
2314 /* update XDP supported features */
2315 mlx5e_set_xdp_feature(netdev);
2316
2317 return 0;
2318 }
2319
set_pflag_rx_no_csum_complete(struct net_device * netdev,bool enable)2320 static int set_pflag_rx_no_csum_complete(struct net_device *netdev, bool enable)
2321 {
2322 struct mlx5e_priv *priv = netdev_priv(netdev);
2323 struct mlx5e_channels *channels = &priv->channels;
2324 struct mlx5e_channel *c;
2325 int i;
2326
2327 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) ||
2328 priv->channels.params.xdp_prog)
2329 return 0;
2330
2331 for (i = 0; i < channels->num; i++) {
2332 c = channels->c[i];
2333 if (enable)
2334 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
2335 else
2336 __clear_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
2337 }
2338
2339 return 0;
2340 }
2341
set_pflag_tx_mpwqe_common(struct net_device * netdev,u32 flag,bool enable)2342 static int set_pflag_tx_mpwqe_common(struct net_device *netdev, u32 flag, bool enable)
2343 {
2344 struct mlx5e_priv *priv = netdev_priv(netdev);
2345 struct mlx5_core_dev *mdev = priv->mdev;
2346 struct mlx5e_params new_params;
2347
2348 if (enable && !mlx5e_tx_mpwqe_supported(mdev))
2349 return -EOPNOTSUPP;
2350
2351 new_params = priv->channels.params;
2352
2353 MLX5E_SET_PFLAG(&new_params, flag, enable);
2354
2355 return mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true);
2356 }
2357
set_pflag_xdp_tx_mpwqe(struct net_device * netdev,bool enable)2358 static int set_pflag_xdp_tx_mpwqe(struct net_device *netdev, bool enable)
2359 {
2360 return set_pflag_tx_mpwqe_common(netdev, MLX5E_PFLAG_XDP_TX_MPWQE, enable);
2361 }
2362
set_pflag_skb_tx_mpwqe(struct net_device * netdev,bool enable)2363 static int set_pflag_skb_tx_mpwqe(struct net_device *netdev, bool enable)
2364 {
2365 return set_pflag_tx_mpwqe_common(netdev, MLX5E_PFLAG_SKB_TX_MPWQE, enable);
2366 }
2367
set_pflag_tx_port_ts(struct net_device * netdev,bool enable)2368 static int set_pflag_tx_port_ts(struct net_device *netdev, bool enable)
2369 {
2370 struct mlx5e_priv *priv = netdev_priv(netdev);
2371 struct mlx5_core_dev *mdev = priv->mdev;
2372 struct mlx5e_params new_params;
2373 int err;
2374
2375 if (!MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn) ||
2376 !MLX5_CAP_GEN_2(mdev, ts_cqe_metadata_size2wqe_counter))
2377 return -EOPNOTSUPP;
2378
2379 /* Don't allow changing the PTP state if HTB offload is active, because
2380 * the numeration of the QoS SQs will change, while per-queue qdiscs are
2381 * attached.
2382 */
2383 if (mlx5e_selq_is_htb_enabled(&priv->selq)) {
2384 netdev_err(priv->netdev, "%s: HTB offload is active, cannot change the PTP state\n",
2385 __func__);
2386 return -EINVAL;
2387 }
2388
2389 new_params = priv->channels.params;
2390 /* Don't allow enabling TX-port-TS if MQPRIO mode channel offload is
2391 * active, since it defines explicitly which TC accepts the packet.
2392 * This conflicts with TX-port-TS hijacking the PTP traffic to a specific
2393 * HW TX-queue.
2394 */
2395 if (enable && new_params.mqprio.mode == TC_MQPRIO_MODE_CHANNEL) {
2396 netdev_err(priv->netdev,
2397 "%s: MQPRIO mode channel offload is active, cannot set the TX-port-TS\n",
2398 __func__);
2399 return -EINVAL;
2400 }
2401 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_TX_PORT_TS, enable);
2402 /* No need to verify SQ stop room as
2403 * ptpsq.txqsq.stop_room <= generic_sq->stop_room, and both
2404 * has the same log_sq_size.
2405 */
2406
2407 err = mlx5e_safe_switch_params(priv, &new_params,
2408 mlx5e_update_tc_and_tx_queues_ctx, NULL, true);
2409 if (!err)
2410 priv->tx_ptp_opened = true;
2411
2412 return err;
2413 }
2414
2415 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS] = {
2416 { "rx_cqe_moder", set_pflag_rx_cqe_based_moder },
2417 { "tx_cqe_moder", set_pflag_tx_cqe_based_moder },
2418 { "rx_cqe_compress", set_pflag_rx_cqe_compress },
2419 { "rx_striding_rq", set_pflag_rx_striding_rq },
2420 { "rx_no_csum_complete", set_pflag_rx_no_csum_complete },
2421 { "xdp_tx_mpwqe", set_pflag_xdp_tx_mpwqe },
2422 { "skb_tx_mpwqe", set_pflag_skb_tx_mpwqe },
2423 { "tx_port_ts", set_pflag_tx_port_ts },
2424 };
2425
mlx5e_handle_pflag(struct net_device * netdev,u32 wanted_flags,enum mlx5e_priv_flag flag)2426 static int mlx5e_handle_pflag(struct net_device *netdev,
2427 u32 wanted_flags,
2428 enum mlx5e_priv_flag flag)
2429 {
2430 struct mlx5e_priv *priv = netdev_priv(netdev);
2431 bool enable = !!(wanted_flags & BIT(flag));
2432 u32 changes = wanted_flags ^ priv->channels.params.pflags;
2433 int err;
2434
2435 if (!(changes & BIT(flag)))
2436 return 0;
2437
2438 err = mlx5e_priv_flags[flag].handler(netdev, enable);
2439 if (err) {
2440 netdev_err(netdev, "%s private flag '%s' failed err %d\n",
2441 enable ? "Enable" : "Disable", mlx5e_priv_flags[flag].name, err);
2442 return err;
2443 }
2444
2445 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable);
2446 return 0;
2447 }
2448
mlx5e_set_priv_flags(struct net_device * netdev,u32 pflags)2449 static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
2450 {
2451 struct mlx5e_priv *priv = netdev_priv(netdev);
2452 enum mlx5e_priv_flag pflag;
2453 int err;
2454
2455 mutex_lock(&priv->state_lock);
2456
2457 for (pflag = 0; pflag < MLX5E_NUM_PFLAGS; pflag++) {
2458 err = mlx5e_handle_pflag(netdev, pflags, pflag);
2459 if (err)
2460 break;
2461 }
2462
2463 mutex_unlock(&priv->state_lock);
2464
2465 /* Need to fix some features.. */
2466 netdev_update_features(netdev);
2467
2468 return err;
2469 }
2470
mlx5e_get_priv_flags(struct net_device * netdev)2471 static u32 mlx5e_get_priv_flags(struct net_device *netdev)
2472 {
2473 struct mlx5e_priv *priv = netdev_priv(netdev);
2474
2475 return priv->channels.params.pflags;
2476 }
2477
mlx5e_get_rxfh_fields(struct net_device * dev,struct ethtool_rxfh_fields * info)2478 static int mlx5e_get_rxfh_fields(struct net_device *dev,
2479 struct ethtool_rxfh_fields *info)
2480 {
2481 struct mlx5e_priv *priv = netdev_priv(dev);
2482
2483 return mlx5e_ethtool_get_rxfh_fields(priv, info);
2484 }
2485
mlx5e_set_rxfh_fields(struct net_device * dev,const struct ethtool_rxfh_fields * cmd,struct netlink_ext_ack * extack)2486 static int mlx5e_set_rxfh_fields(struct net_device *dev,
2487 const struct ethtool_rxfh_fields *cmd,
2488 struct netlink_ext_ack *extack)
2489 {
2490 struct mlx5e_priv *priv = netdev_priv(dev);
2491
2492 return mlx5e_ethtool_set_rxfh_fields(priv, cmd, extack);
2493 }
2494
mlx5e_get_rxnfc(struct net_device * dev,struct ethtool_rxnfc * info,u32 * rule_locs)2495 static int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2496 u32 *rule_locs)
2497 {
2498 struct mlx5e_priv *priv = netdev_priv(dev);
2499
2500 /* ETHTOOL_GRXRINGS is needed by ethtool -x which is not part
2501 * of rxnfc. We keep this logic out of mlx5e_ethtool_get_rxnfc,
2502 * to avoid breaking "ethtool -x" when mlx5e_ethtool_get_rxnfc
2503 * is compiled out via CONFIG_MLX5_EN_RXNFC=n.
2504 */
2505 if (info->cmd == ETHTOOL_GRXRINGS) {
2506 info->data = priv->channels.params.num_channels;
2507 return 0;
2508 }
2509
2510 return mlx5e_ethtool_get_rxnfc(priv, info, rule_locs);
2511 }
2512
mlx5e_set_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd)2513 static int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2514 {
2515 struct mlx5e_priv *priv = netdev_priv(dev);
2516
2517 return mlx5e_ethtool_set_rxnfc(priv, cmd);
2518 }
2519
query_port_status_opcode(struct mlx5_core_dev * mdev,u32 * status_opcode)2520 static int query_port_status_opcode(struct mlx5_core_dev *mdev, u32 *status_opcode)
2521 {
2522 struct mlx5_ifc_pddr_troubleshooting_page_bits *pddr_troubleshooting_page;
2523 u32 in[MLX5_ST_SZ_DW(pddr_reg)] = {};
2524 u32 out[MLX5_ST_SZ_DW(pddr_reg)];
2525 int err;
2526
2527 MLX5_SET(pddr_reg, in, local_port, 1);
2528 MLX5_SET(pddr_reg, in, page_select,
2529 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE);
2530
2531 pddr_troubleshooting_page = MLX5_ADDR_OF(pddr_reg, in, page_data);
2532 MLX5_SET(pddr_troubleshooting_page, pddr_troubleshooting_page,
2533 group_opcode, MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR);
2534 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
2535 sizeof(out), MLX5_REG_PDDR, 0, 0);
2536 if (err)
2537 return err;
2538
2539 pddr_troubleshooting_page = MLX5_ADDR_OF(pddr_reg, out, page_data);
2540 *status_opcode = MLX5_GET(pddr_troubleshooting_page, pddr_troubleshooting_page,
2541 status_opcode);
2542 return 0;
2543 }
2544
2545 struct mlx5e_ethtool_link_ext_state_opcode_mapping {
2546 u32 status_opcode;
2547 enum ethtool_link_ext_state link_ext_state;
2548 u8 link_ext_substate;
2549 };
2550
2551 static const struct mlx5e_ethtool_link_ext_state_opcode_mapping
2552 mlx5e_link_ext_state_opcode_map[] = {
2553 /* States relating to the autonegotiation or issues therein */
2554 {2, ETHTOOL_LINK_EXT_STATE_AUTONEG,
2555 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED},
2556 {3, ETHTOOL_LINK_EXT_STATE_AUTONEG,
2557 ETHTOOL_LINK_EXT_SUBSTATE_AN_ACK_NOT_RECEIVED},
2558 {4, ETHTOOL_LINK_EXT_STATE_AUTONEG,
2559 ETHTOOL_LINK_EXT_SUBSTATE_AN_NEXT_PAGE_EXCHANGE_FAILED},
2560 {36, ETHTOOL_LINK_EXT_STATE_AUTONEG,
2561 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED_FORCE_MODE},
2562 {38, ETHTOOL_LINK_EXT_STATE_AUTONEG,
2563 ETHTOOL_LINK_EXT_SUBSTATE_AN_FEC_MISMATCH_DURING_OVERRIDE},
2564 {39, ETHTOOL_LINK_EXT_STATE_AUTONEG,
2565 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_HCD},
2566
2567 /* Failure during link training */
2568 {5, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE,
2569 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_FRAME_LOCK_NOT_ACQUIRED},
2570 {6, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE,
2571 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_INHIBIT_TIMEOUT},
2572 {7, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE,
2573 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_PARTNER_DID_NOT_SET_RECEIVER_READY},
2574 {8, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE, 0},
2575 {14, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE,
2576 ETHTOOL_LINK_EXT_SUBSTATE_LT_REMOTE_FAULT},
2577
2578 /* Logical mismatch in physical coding sublayer or forward error correction sublayer */
2579 {9, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
2580 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_BLOCK_LOCK},
2581 {10, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
2582 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_AM_LOCK},
2583 {11, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
2584 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_GET_ALIGN_STATUS},
2585 {12, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
2586 ETHTOOL_LINK_EXT_SUBSTATE_LLM_FC_FEC_IS_NOT_LOCKED},
2587 {13, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
2588 ETHTOOL_LINK_EXT_SUBSTATE_LLM_RS_FEC_IS_NOT_LOCKED},
2589
2590 /* Signal integrity issues */
2591 {15, ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY, 0},
2592 {17, ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY,
2593 ETHTOOL_LINK_EXT_SUBSTATE_BSI_LARGE_NUMBER_OF_PHYSICAL_ERRORS},
2594 {42, ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY,
2595 ETHTOOL_LINK_EXT_SUBSTATE_BSI_UNSUPPORTED_RATE},
2596
2597 /* No cable connected */
2598 {1024, ETHTOOL_LINK_EXT_STATE_NO_CABLE, 0},
2599
2600 /* Failure is related to cable, e.g., unsupported cable */
2601 {16, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
2602 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
2603 {20, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
2604 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
2605 {29, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
2606 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
2607 {1025, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
2608 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
2609 {1029, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
2610 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
2611 {1031, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE, 0},
2612
2613 /* Failure is related to EEPROM, e.g., failure during reading or parsing the data */
2614 {1027, ETHTOOL_LINK_EXT_STATE_EEPROM_ISSUE, 0},
2615
2616 /* Failure during calibration algorithm */
2617 {23, ETHTOOL_LINK_EXT_STATE_CALIBRATION_FAILURE, 0},
2618
2619 /* The hardware is not able to provide the power required from cable or module */
2620 {1032, ETHTOOL_LINK_EXT_STATE_POWER_BUDGET_EXCEEDED, 0},
2621
2622 /* The module is overheated */
2623 {1030, ETHTOOL_LINK_EXT_STATE_OVERHEAT, 0},
2624 };
2625
2626 static void
mlx5e_set_link_ext_state(struct mlx5e_ethtool_link_ext_state_opcode_mapping link_ext_state_mapping,struct ethtool_link_ext_state_info * link_ext_state_info)2627 mlx5e_set_link_ext_state(struct mlx5e_ethtool_link_ext_state_opcode_mapping
2628 link_ext_state_mapping,
2629 struct ethtool_link_ext_state_info *link_ext_state_info)
2630 {
2631 switch (link_ext_state_mapping.link_ext_state) {
2632 case ETHTOOL_LINK_EXT_STATE_AUTONEG:
2633 link_ext_state_info->autoneg =
2634 link_ext_state_mapping.link_ext_substate;
2635 break;
2636 case ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE:
2637 link_ext_state_info->link_training =
2638 link_ext_state_mapping.link_ext_substate;
2639 break;
2640 case ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH:
2641 link_ext_state_info->link_logical_mismatch =
2642 link_ext_state_mapping.link_ext_substate;
2643 break;
2644 case ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY:
2645 link_ext_state_info->bad_signal_integrity =
2646 link_ext_state_mapping.link_ext_substate;
2647 break;
2648 case ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE:
2649 link_ext_state_info->cable_issue =
2650 link_ext_state_mapping.link_ext_substate;
2651 break;
2652 default:
2653 break;
2654 }
2655
2656 link_ext_state_info->link_ext_state = link_ext_state_mapping.link_ext_state;
2657 }
2658
2659 static int
mlx5e_get_link_ext_state(struct net_device * dev,struct ethtool_link_ext_state_info * link_ext_state_info)2660 mlx5e_get_link_ext_state(struct net_device *dev,
2661 struct ethtool_link_ext_state_info *link_ext_state_info)
2662 {
2663 struct mlx5e_ethtool_link_ext_state_opcode_mapping link_ext_state_mapping;
2664 struct mlx5e_priv *priv = netdev_priv(dev);
2665 u32 status_opcode = 0;
2666 int i;
2667
2668 /* Exit without data if the interface state is OK, since no extended data is
2669 * available in such case
2670 */
2671 if (netif_carrier_ok(dev))
2672 return -ENODATA;
2673
2674 if (query_port_status_opcode(priv->mdev, &status_opcode) ||
2675 !status_opcode)
2676 return -ENODATA;
2677
2678 for (i = 0; i < ARRAY_SIZE(mlx5e_link_ext_state_opcode_map); i++) {
2679 link_ext_state_mapping = mlx5e_link_ext_state_opcode_map[i];
2680 if (link_ext_state_mapping.status_opcode == status_opcode) {
2681 mlx5e_set_link_ext_state(link_ext_state_mapping,
2682 link_ext_state_info);
2683 return 0;
2684 }
2685 }
2686
2687 return -ENODATA;
2688 }
2689
mlx5e_get_eth_phy_stats(struct net_device * netdev,struct ethtool_eth_phy_stats * phy_stats)2690 static void mlx5e_get_eth_phy_stats(struct net_device *netdev,
2691 struct ethtool_eth_phy_stats *phy_stats)
2692 {
2693 struct mlx5e_priv *priv = netdev_priv(netdev);
2694
2695 mlx5e_stats_eth_phy_get(priv, phy_stats);
2696 }
2697
mlx5e_get_eth_mac_stats(struct net_device * netdev,struct ethtool_eth_mac_stats * mac_stats)2698 static void mlx5e_get_eth_mac_stats(struct net_device *netdev,
2699 struct ethtool_eth_mac_stats *mac_stats)
2700 {
2701 struct mlx5e_priv *priv = netdev_priv(netdev);
2702
2703 mlx5e_stats_eth_mac_get(priv, mac_stats);
2704 }
2705
mlx5e_get_eth_ctrl_stats(struct net_device * netdev,struct ethtool_eth_ctrl_stats * ctrl_stats)2706 static void mlx5e_get_eth_ctrl_stats(struct net_device *netdev,
2707 struct ethtool_eth_ctrl_stats *ctrl_stats)
2708 {
2709 struct mlx5e_priv *priv = netdev_priv(netdev);
2710
2711 mlx5e_stats_eth_ctrl_get(priv, ctrl_stats);
2712 }
2713
mlx5e_get_rmon_stats(struct net_device * netdev,struct ethtool_rmon_stats * rmon_stats,const struct ethtool_rmon_hist_range ** ranges)2714 static void mlx5e_get_rmon_stats(struct net_device *netdev,
2715 struct ethtool_rmon_stats *rmon_stats,
2716 const struct ethtool_rmon_hist_range **ranges)
2717 {
2718 struct mlx5e_priv *priv = netdev_priv(netdev);
2719
2720 mlx5e_stats_rmon_get(priv, rmon_stats, ranges);
2721 }
2722
mlx5e_get_ts_stats(struct net_device * netdev,struct ethtool_ts_stats * ts_stats)2723 static void mlx5e_get_ts_stats(struct net_device *netdev,
2724 struct ethtool_ts_stats *ts_stats)
2725 {
2726 struct mlx5e_priv *priv = netdev_priv(netdev);
2727
2728 mlx5e_stats_ts_get(priv, ts_stats);
2729 }
2730
2731 const struct ethtool_ops mlx5e_ethtool_ops = {
2732 .cap_link_lanes_supported = true,
2733 .rxfh_per_ctx_fields = true,
2734 .rxfh_per_ctx_key = true,
2735 .rxfh_max_num_contexts = MLX5E_MAX_NUM_RSS,
2736 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
2737 ETHTOOL_COALESCE_MAX_FRAMES |
2738 ETHTOOL_COALESCE_USE_ADAPTIVE |
2739 ETHTOOL_COALESCE_USE_CQE,
2740 .supported_input_xfrm = RXH_XFRM_SYM_OR_XOR,
2741 .supported_ring_params = ETHTOOL_RING_USE_TCP_DATA_SPLIT,
2742 .get_drvinfo = mlx5e_get_drvinfo,
2743 .get_link = ethtool_op_get_link,
2744 .get_link_ext_state = mlx5e_get_link_ext_state,
2745 .get_strings = mlx5e_get_strings,
2746 .get_sset_count = mlx5e_get_sset_count,
2747 .get_ethtool_stats = mlx5e_get_ethtool_stats,
2748 .get_ringparam = mlx5e_get_ringparam,
2749 .set_ringparam = mlx5e_set_ringparam,
2750 .get_channels = mlx5e_get_channels,
2751 .set_channels = mlx5e_set_channels,
2752 .get_coalesce = mlx5e_get_coalesce,
2753 .set_coalesce = mlx5e_set_coalesce,
2754 .get_per_queue_coalesce = mlx5e_get_per_queue_coalesce,
2755 .set_per_queue_coalesce = mlx5e_set_per_queue_coalesce,
2756 .get_link_ksettings = mlx5e_get_link_ksettings,
2757 .set_link_ksettings = mlx5e_set_link_ksettings,
2758 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
2759 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
2760 .get_rxfh = mlx5e_get_rxfh,
2761 .set_rxfh = mlx5e_set_rxfh,
2762 .get_rxfh_fields = mlx5e_get_rxfh_fields,
2763 .set_rxfh_fields = mlx5e_set_rxfh_fields,
2764 .create_rxfh_context = mlx5e_create_rxfh_context,
2765 .modify_rxfh_context = mlx5e_modify_rxfh_context,
2766 .remove_rxfh_context = mlx5e_remove_rxfh_context,
2767 .get_rxnfc = mlx5e_get_rxnfc,
2768 .set_rxnfc = mlx5e_set_rxnfc,
2769 .get_tunable = mlx5e_get_tunable,
2770 .set_tunable = mlx5e_set_tunable,
2771 .get_pause_stats = mlx5e_get_pause_stats,
2772 .get_pauseparam = mlx5e_get_pauseparam,
2773 .set_pauseparam = mlx5e_set_pauseparam,
2774 .get_ts_info = mlx5e_get_ts_info,
2775 .set_phys_id = mlx5e_set_phys_id,
2776 .get_wol = mlx5e_get_wol,
2777 .set_wol = mlx5e_set_wol,
2778 .get_module_info = mlx5e_get_module_info,
2779 .get_module_eeprom = mlx5e_get_module_eeprom,
2780 .get_module_eeprom_by_page = mlx5e_get_module_eeprom_by_page,
2781 .flash_device = mlx5e_flash_device,
2782 .get_priv_flags = mlx5e_get_priv_flags,
2783 .set_priv_flags = mlx5e_set_priv_flags,
2784 .self_test = mlx5e_self_test,
2785 .get_fec_stats = mlx5e_get_fec_stats,
2786 .get_fecparam = mlx5e_get_fecparam,
2787 .set_fecparam = mlx5e_set_fecparam,
2788 .get_eth_phy_stats = mlx5e_get_eth_phy_stats,
2789 .get_eth_mac_stats = mlx5e_get_eth_mac_stats,
2790 .get_eth_ctrl_stats = mlx5e_get_eth_ctrl_stats,
2791 .get_rmon_stats = mlx5e_get_rmon_stats,
2792 .get_ts_stats = mlx5e_get_ts_stats,
2793 .get_link_ext_stats = mlx5e_get_link_ext_stats
2794 };
2795