1 /*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/dim.h>
34 #include <linux/ethtool_netlink.h>
35
36 #include "en.h"
37 #include "en/channels.h"
38 #include "en/dim.h"
39 #include "en/port.h"
40 #include "en/params.h"
41 #include "en/ptp.h"
42 #include "lib/clock.h"
43 #include "en/fs_ethtool.h"
44
45 #define LANES_UNKNOWN 0
46
mlx5e_ethtool_get_drvinfo(struct mlx5e_priv * priv,struct ethtool_drvinfo * drvinfo)47 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
48 struct ethtool_drvinfo *drvinfo)
49 {
50 struct mlx5_core_dev *mdev = priv->mdev;
51 int count;
52
53 strscpy(drvinfo->driver, KBUILD_MODNAME, sizeof(drvinfo->driver));
54 count = snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
55 "%d.%d.%04d (%.16s)", fw_rev_maj(mdev),
56 fw_rev_min(mdev), fw_rev_sub(mdev), mdev->board_id);
57 if (count >= sizeof(drvinfo->fw_version))
58 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
59 "%d.%d.%04d", fw_rev_maj(mdev),
60 fw_rev_min(mdev), fw_rev_sub(mdev));
61
62 strscpy(drvinfo->bus_info, dev_name(mdev->device),
63 sizeof(drvinfo->bus_info));
64 }
65
mlx5e_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * drvinfo)66 static void mlx5e_get_drvinfo(struct net_device *dev,
67 struct ethtool_drvinfo *drvinfo)
68 {
69 struct mlx5e_priv *priv = netdev_priv(dev);
70
71 mlx5e_ethtool_get_drvinfo(priv, drvinfo);
72 }
73
74 struct ptys2ethtool_config {
75 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
76 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
77 };
78
79 static
80 struct ptys2ethtool_config ptys2legacy_ethtool_table[MLX5E_LINK_MODES_NUMBER];
81 static
82 struct ptys2ethtool_config ptys2ext_ethtool_table[MLX5E_EXT_LINK_MODES_NUMBER];
83
84 #define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, table, ...) \
85 ({ \
86 struct ptys2ethtool_config *cfg; \
87 const unsigned int modes[] = { __VA_ARGS__ }; \
88 unsigned int i; \
89 cfg = &ptys2##table##_ethtool_table[reg_]; \
90 bitmap_zero(cfg->supported, \
91 __ETHTOOL_LINK_MODE_MASK_NBITS); \
92 bitmap_zero(cfg->advertised, \
93 __ETHTOOL_LINK_MODE_MASK_NBITS); \
94 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
95 bitmap_set(cfg->supported, modes[i], 1); \
96 bitmap_set(cfg->advertised, modes[i], 1); \
97 } \
98 })
99
mlx5e_build_ptys2ethtool_map(void)100 void mlx5e_build_ptys2ethtool_map(void)
101 {
102 memset(ptys2legacy_ethtool_table, 0, sizeof(ptys2legacy_ethtool_table));
103 memset(ptys2ext_ethtool_table, 0, sizeof(ptys2ext_ethtool_table));
104 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, legacy,
105 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
106 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, legacy,
107 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
108 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, legacy,
109 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
110 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, legacy,
111 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
112 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, legacy,
113 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
114 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, legacy,
115 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
116 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, legacy,
117 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
118 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, legacy,
119 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
120 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, legacy,
121 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
122 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, legacy,
123 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
124 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, legacy,
125 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
126 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, legacy,
127 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
128 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, legacy,
129 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
130 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, legacy,
131 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
132 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, legacy,
133 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
134 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, legacy,
135 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
136 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, legacy,
137 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
138 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, legacy,
139 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
140 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, legacy,
141 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
142 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100BASE_TX, legacy,
143 ETHTOOL_LINK_MODE_100baseT_Full_BIT);
144 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_T, legacy,
145 ETHTOOL_LINK_MODE_1000baseT_Full_BIT);
146 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, legacy,
147 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
148 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, legacy,
149 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
150 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, legacy,
151 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
152 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, legacy,
153 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
154 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, legacy,
155 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
156 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, legacy,
157 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
158 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_SGMII_100M, ext,
159 ETHTOOL_LINK_MODE_100baseT_Full_BIT);
160 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_X_SGMII, ext,
161 ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
162 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
163 ETHTOOL_LINK_MODE_1000baseX_Full_BIT);
164 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_5GBASE_R, ext,
165 ETHTOOL_LINK_MODE_5000baseT_Full_BIT);
166 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_XFI_XAUI_1, ext,
167 ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
168 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
169 ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
170 ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
171 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
172 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
173 ETHTOOL_LINK_MODE_10000baseER_Full_BIT);
174 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_XLAUI_4_XLPPI_4, ext,
175 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
176 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
177 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
178 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
179 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GAUI_1_25GBASE_CR_KR, ext,
180 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
181 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
182 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
183 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2,
184 ext,
185 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
186 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
187 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
188 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR, ext,
189 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
190 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
191 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
192 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
193 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT);
194 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_CAUI_4_100GBASE_CR4_KR4, ext,
195 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
196 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
197 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
198 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
199 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_2_100GBASE_CR2_KR2, ext,
200 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
201 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
202 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
203 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
204 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT);
205 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_4_200GBASE_CR4_KR4, ext,
206 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
207 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
208 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
209 ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,
210 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT);
211 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_8_400GBASE_CR8, ext,
212 ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT,
213 ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT,
214 ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT,
215 ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT,
216 ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT);
217 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_1_100GBASE_CR_KR, ext,
218 ETHTOOL_LINK_MODE_100000baseKR_Full_BIT,
219 ETHTOOL_LINK_MODE_100000baseSR_Full_BIT,
220 ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT,
221 ETHTOOL_LINK_MODE_100000baseDR_Full_BIT,
222 ETHTOOL_LINK_MODE_100000baseCR_Full_BIT);
223 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_2_200GBASE_CR2_KR2, ext,
224 ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT,
225 ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT,
226 ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT,
227 ETHTOOL_LINK_MODE_200000baseDR2_Full_BIT,
228 ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT);
229 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_4_400GBASE_CR4_KR4, ext,
230 ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT,
231 ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT,
232 ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT,
233 ETHTOOL_LINK_MODE_400000baseDR4_Full_BIT,
234 ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT);
235 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_800GAUI_8_800GBASE_CR8_KR8, ext,
236 ETHTOOL_LINK_MODE_800000baseCR8_Full_BIT,
237 ETHTOOL_LINK_MODE_800000baseKR8_Full_BIT,
238 ETHTOOL_LINK_MODE_800000baseDR8_Full_BIT,
239 ETHTOOL_LINK_MODE_800000baseDR8_2_Full_BIT,
240 ETHTOOL_LINK_MODE_800000baseSR8_Full_BIT,
241 ETHTOOL_LINK_MODE_800000baseVR8_Full_BIT);
242 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_1_200GBASE_CR1_KR1, ext,
243 ETHTOOL_LINK_MODE_200000baseCR_Full_BIT,
244 ETHTOOL_LINK_MODE_200000baseKR_Full_BIT,
245 ETHTOOL_LINK_MODE_200000baseDR_Full_BIT,
246 ETHTOOL_LINK_MODE_200000baseDR_2_Full_BIT,
247 ETHTOOL_LINK_MODE_200000baseSR_Full_BIT,
248 ETHTOOL_LINK_MODE_200000baseVR_Full_BIT);
249 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_2_400GBASE_CR2_KR2, ext,
250 ETHTOOL_LINK_MODE_400000baseCR2_Full_BIT,
251 ETHTOOL_LINK_MODE_400000baseKR2_Full_BIT,
252 ETHTOOL_LINK_MODE_400000baseDR2_Full_BIT,
253 ETHTOOL_LINK_MODE_400000baseDR2_2_Full_BIT,
254 ETHTOOL_LINK_MODE_400000baseSR2_Full_BIT,
255 ETHTOOL_LINK_MODE_400000baseVR2_Full_BIT);
256 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_800GAUI_4_800GBASE_CR4_KR4, ext,
257 ETHTOOL_LINK_MODE_800000baseCR4_Full_BIT,
258 ETHTOOL_LINK_MODE_800000baseKR4_Full_BIT,
259 ETHTOOL_LINK_MODE_800000baseDR4_Full_BIT,
260 ETHTOOL_LINK_MODE_800000baseDR4_2_Full_BIT,
261 ETHTOOL_LINK_MODE_800000baseSR4_Full_BIT,
262 ETHTOOL_LINK_MODE_800000baseVR4_Full_BIT);
263 }
264
mlx5e_ethtool_get_speed_arr(bool ext,struct ptys2ethtool_config ** arr,u32 * size)265 static void mlx5e_ethtool_get_speed_arr(bool ext,
266 struct ptys2ethtool_config **arr,
267 u32 *size)
268 {
269 *arr = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table;
270 *size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) :
271 ARRAY_SIZE(ptys2legacy_ethtool_table);
272 }
273
274 typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
275
276 struct pflag_desc {
277 char name[ETH_GSTRING_LEN];
278 mlx5e_pflag_handler handler;
279 };
280
281 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS];
282
mlx5e_ethtool_get_sset_count(struct mlx5e_priv * priv,int sset)283 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset)
284 {
285 switch (sset) {
286 case ETH_SS_STATS:
287 return mlx5e_stats_total_num(priv);
288 case ETH_SS_PRIV_FLAGS:
289 return MLX5E_NUM_PFLAGS;
290 case ETH_SS_TEST:
291 return mlx5e_self_test_num(priv);
292 default:
293 return -EOPNOTSUPP;
294 }
295 }
296
mlx5e_get_sset_count(struct net_device * dev,int sset)297 static int mlx5e_get_sset_count(struct net_device *dev, int sset)
298 {
299 struct mlx5e_priv *priv = netdev_priv(dev);
300
301 return mlx5e_ethtool_get_sset_count(priv, sset);
302 }
303
mlx5e_ethtool_get_strings(struct mlx5e_priv * priv,u32 stringset,u8 * data)304 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, u32 stringset, u8 *data)
305 {
306 int i;
307
308 switch (stringset) {
309 case ETH_SS_PRIV_FLAGS:
310 for (i = 0; i < MLX5E_NUM_PFLAGS; i++)
311 ethtool_puts(&data, mlx5e_priv_flags[i].name);
312 break;
313
314 case ETH_SS_TEST:
315 mlx5e_self_test_fill_strings(priv, data);
316 break;
317
318 case ETH_SS_STATS:
319 mlx5e_stats_fill_strings(priv, data);
320 break;
321 }
322 }
323
mlx5e_get_strings(struct net_device * dev,u32 stringset,u8 * data)324 static void mlx5e_get_strings(struct net_device *dev, u32 stringset, u8 *data)
325 {
326 struct mlx5e_priv *priv = netdev_priv(dev);
327
328 mlx5e_ethtool_get_strings(priv, stringset, data);
329 }
330
mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv * priv,struct ethtool_stats * stats,u64 * data)331 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
332 struct ethtool_stats *stats, u64 *data)
333 {
334 int idx = 0;
335
336 mutex_lock(&priv->state_lock);
337 mlx5e_stats_update(priv);
338 mutex_unlock(&priv->state_lock);
339
340 mlx5e_stats_fill(priv, data, idx);
341 }
342
mlx5e_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)343 static void mlx5e_get_ethtool_stats(struct net_device *dev,
344 struct ethtool_stats *stats,
345 u64 *data)
346 {
347 struct mlx5e_priv *priv = netdev_priv(dev);
348
349 mlx5e_ethtool_get_ethtool_stats(priv, stats, data);
350 }
351
mlx5e_ethtool_get_ringparam(struct mlx5e_priv * priv,struct ethtool_ringparam * param,struct kernel_ethtool_ringparam * kernel_param)352 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
353 struct ethtool_ringparam *param,
354 struct kernel_ethtool_ringparam *kernel_param)
355 {
356 /* Limitation for regular RQ. XSK RQ may clamp the queue length in
357 * mlx5e_mpwqe_get_log_rq_size.
358 */
359 u8 max_log_mpwrq_pkts = mlx5e_mpwrq_max_log_rq_pkts(priv->mdev,
360 PAGE_SHIFT,
361 MLX5E_MPWRQ_UMR_MODE_ALIGNED);
362
363 param->rx_max_pending = 1 << min_t(u8, MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE,
364 max_log_mpwrq_pkts);
365 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
366 param->rx_pending = 1 << priv->channels.params.log_rq_mtu_frames;
367 param->tx_pending = 1 << priv->channels.params.log_sq_size;
368
369 kernel_param->tcp_data_split =
370 (priv->channels.params.packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) ?
371 ETHTOOL_TCP_DATA_SPLIT_ENABLED :
372 ETHTOOL_TCP_DATA_SPLIT_DISABLED;
373 }
374
mlx5e_get_ringparam(struct net_device * dev,struct ethtool_ringparam * param,struct kernel_ethtool_ringparam * kernel_param,struct netlink_ext_ack * extack)375 static void mlx5e_get_ringparam(struct net_device *dev,
376 struct ethtool_ringparam *param,
377 struct kernel_ethtool_ringparam *kernel_param,
378 struct netlink_ext_ack *extack)
379 {
380 struct mlx5e_priv *priv = netdev_priv(dev);
381
382 mlx5e_ethtool_get_ringparam(priv, param, kernel_param);
383 }
384
mlx5e_ethtool_set_ringparam(struct mlx5e_priv * priv,struct ethtool_ringparam * param,struct netlink_ext_ack * extack)385 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
386 struct ethtool_ringparam *param,
387 struct netlink_ext_ack *extack)
388 {
389 struct mlx5e_params new_params;
390 u8 log_rq_size;
391 u8 log_sq_size;
392 int err = 0;
393
394 if (param->rx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE)) {
395 NL_SET_ERR_MSG_FMT_MOD(extack, "rx (%d) < min (%d)",
396 param->rx_pending,
397 1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE);
398 return -EINVAL;
399 }
400
401 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
402 NL_SET_ERR_MSG_FMT_MOD(extack, "tx (%d) < min (%d)",
403 param->tx_pending,
404 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
405 return -EINVAL;
406 }
407
408 log_rq_size = order_base_2(param->rx_pending);
409 log_sq_size = order_base_2(param->tx_pending);
410
411 if (log_rq_size == priv->channels.params.log_rq_mtu_frames &&
412 log_sq_size == priv->channels.params.log_sq_size)
413 return 0;
414
415 mutex_lock(&priv->state_lock);
416
417 new_params = priv->channels.params;
418 new_params.log_rq_mtu_frames = log_rq_size;
419 new_params.log_sq_size = log_sq_size;
420
421 err = mlx5e_validate_params(priv->mdev, &new_params);
422 if (err)
423 goto unlock;
424
425 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true);
426
427 unlock:
428 mutex_unlock(&priv->state_lock);
429
430 if (!err)
431 netdev_update_features(priv->netdev);
432
433 return err;
434 }
435
mlx5e_set_ringparam(struct net_device * dev,struct ethtool_ringparam * param,struct kernel_ethtool_ringparam * kernel_param,struct netlink_ext_ack * extack)436 static int mlx5e_set_ringparam(struct net_device *dev,
437 struct ethtool_ringparam *param,
438 struct kernel_ethtool_ringparam *kernel_param,
439 struct netlink_ext_ack *extack)
440 {
441 struct mlx5e_priv *priv = netdev_priv(dev);
442
443 return mlx5e_ethtool_set_ringparam(priv, param, extack);
444 }
445
mlx5e_ethtool_get_channels(struct mlx5e_priv * priv,struct ethtool_channels * ch)446 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
447 struct ethtool_channels *ch)
448 {
449 mutex_lock(&priv->state_lock);
450 ch->max_combined = priv->max_nch;
451 ch->combined_count = priv->channels.params.num_channels;
452 mutex_unlock(&priv->state_lock);
453 }
454
mlx5e_get_channels(struct net_device * dev,struct ethtool_channels * ch)455 static void mlx5e_get_channels(struct net_device *dev,
456 struct ethtool_channels *ch)
457 {
458 struct mlx5e_priv *priv = netdev_priv(dev);
459
460 mlx5e_ethtool_get_channels(priv, ch);
461 }
462
mlx5e_ethtool_set_channels(struct mlx5e_priv * priv,struct ethtool_channels * ch)463 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
464 struct ethtool_channels *ch)
465 {
466 struct mlx5e_params *cur_params = &priv->channels.params;
467 unsigned int count = ch->combined_count;
468 struct mlx5e_params new_params;
469 bool arfs_enabled;
470 bool opened;
471 int err = 0;
472
473 if (!count) {
474 netdev_info(priv->netdev, "%s: combined_count=0 not supported\n",
475 __func__);
476 return -EINVAL;
477 }
478
479 if (cur_params->num_channels == count)
480 return 0;
481
482 mutex_lock(&priv->state_lock);
483
484 if (mlx5e_rx_res_get_current_hash(priv->rx_res).hfunc == ETH_RSS_HASH_XOR) {
485 unsigned int xor8_max_channels = mlx5e_rqt_max_num_channels_allowed_for_xor8();
486
487 if (count > xor8_max_channels) {
488 err = -EINVAL;
489 netdev_err(priv->netdev, "%s: Requested number of channels (%d) exceeds the maximum allowed by the XOR8 RSS hfunc (%d)\n",
490 __func__, count, xor8_max_channels);
491 goto out;
492 }
493 }
494
495 /* If RXFH is configured, changing the channels number is allowed only if
496 * it does not require resizing the RSS table. This is because the previous
497 * configuration may no longer be compatible with the new RSS table.
498 */
499 if (netif_is_rxfh_configured(priv->netdev)) {
500 int cur_rqt_size = mlx5e_rqt_size(priv->mdev, cur_params->num_channels);
501 int new_rqt_size = mlx5e_rqt_size(priv->mdev, count);
502
503 if (new_rqt_size != cur_rqt_size) {
504 err = -EINVAL;
505 netdev_err(priv->netdev,
506 "%s: RXFH is configured, block changing channels number that affects RSS table size (new: %d, current: %d)\n",
507 __func__, new_rqt_size, cur_rqt_size);
508 goto out;
509 }
510 }
511
512 /* Don't allow changing the number of channels if HTB offload is active,
513 * because the numeration of the QoS SQs will change, while per-queue
514 * qdiscs are attached.
515 */
516 if (mlx5e_selq_is_htb_enabled(&priv->selq)) {
517 err = -EINVAL;
518 netdev_err(priv->netdev, "%s: HTB offload is active, cannot change the number of channels\n",
519 __func__);
520 goto out;
521 }
522
523 /* Don't allow changing the number of channels if MQPRIO mode channel offload is active,
524 * because it defines a partition over the channels queues.
525 */
526 if (cur_params->mqprio.mode == TC_MQPRIO_MODE_CHANNEL) {
527 err = -EINVAL;
528 netdev_err(priv->netdev, "%s: MQPRIO mode channel offload is active, cannot change the number of channels\n",
529 __func__);
530 goto out;
531 }
532
533 new_params = *cur_params;
534 new_params.num_channels = count;
535
536 opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
537
538 arfs_enabled = opened && mlx5e_fs_want_arfs(priv->netdev);
539 if (arfs_enabled)
540 mlx5e_arfs_disable(priv->fs);
541
542 /* Switch to new channels, set new parameters and close old ones */
543 err = mlx5e_safe_switch_params(priv, &new_params,
544 mlx5e_num_channels_changed_ctx, NULL, true);
545
546 if (arfs_enabled) {
547 int err2 = mlx5e_arfs_enable(priv->fs);
548
549 if (err2)
550 netdev_err(priv->netdev, "%s: mlx5e_arfs_enable failed: %d\n",
551 __func__, err2);
552 }
553
554 out:
555 mutex_unlock(&priv->state_lock);
556
557 return err;
558 }
559
mlx5e_set_channels(struct net_device * dev,struct ethtool_channels * ch)560 static int mlx5e_set_channels(struct net_device *dev,
561 struct ethtool_channels *ch)
562 {
563 struct mlx5e_priv *priv = netdev_priv(dev);
564
565 return mlx5e_ethtool_set_channels(priv, ch);
566 }
567
mlx5e_ethtool_get_coalesce(struct mlx5e_priv * priv,struct ethtool_coalesce * coal,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)568 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
569 struct ethtool_coalesce *coal,
570 struct kernel_ethtool_coalesce *kernel_coal,
571 struct netlink_ext_ack *extack)
572 {
573 struct dim_cq_moder *rx_moder, *tx_moder;
574
575 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation)) {
576 NL_SET_ERR_MSG_MOD(extack, "CQ moderation not supported");
577 return -EOPNOTSUPP;
578 }
579
580 rx_moder = &priv->channels.params.rx_cq_moderation;
581 coal->rx_coalesce_usecs = rx_moder->usec;
582 coal->rx_max_coalesced_frames = rx_moder->pkts;
583 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_dim_enabled;
584 kernel_coal->use_cqe_mode_rx = priv->channels.params.rx_moder_use_cqe_mode;
585
586 tx_moder = &priv->channels.params.tx_cq_moderation;
587 coal->tx_coalesce_usecs = tx_moder->usec;
588 coal->tx_max_coalesced_frames = tx_moder->pkts;
589 coal->use_adaptive_tx_coalesce = priv->channels.params.tx_dim_enabled;
590 kernel_coal->use_cqe_mode_tx = priv->channels.params.tx_moder_use_cqe_mode;
591
592 return 0;
593 }
594
mlx5e_get_coalesce(struct net_device * netdev,struct ethtool_coalesce * coal,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)595 static int mlx5e_get_coalesce(struct net_device *netdev,
596 struct ethtool_coalesce *coal,
597 struct kernel_ethtool_coalesce *kernel_coal,
598 struct netlink_ext_ack *extack)
599 {
600 struct mlx5e_priv *priv = netdev_priv(netdev);
601
602 return mlx5e_ethtool_get_coalesce(priv, coal, kernel_coal, extack);
603 }
604
mlx5e_ethtool_get_per_queue_coalesce(struct mlx5e_priv * priv,u32 queue,struct ethtool_coalesce * coal)605 static int mlx5e_ethtool_get_per_queue_coalesce(struct mlx5e_priv *priv, u32 queue,
606 struct ethtool_coalesce *coal)
607 {
608 struct dim_cq_moder cur_moder;
609 struct mlx5e_channels *chs;
610 struct mlx5e_channel *c;
611
612 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
613 return -EOPNOTSUPP;
614
615 mutex_lock(&priv->state_lock);
616
617 chs = &priv->channels;
618 if (chs->num <= queue) {
619 mutex_unlock(&priv->state_lock);
620 return -EINVAL;
621 }
622
623 c = chs->c[queue];
624
625 coal->use_adaptive_rx_coalesce = !!c->rq.dim;
626 if (coal->use_adaptive_rx_coalesce) {
627 cur_moder = net_dim_get_rx_moderation(c->rq.dim->mode,
628 c->rq.dim->profile_ix);
629
630 coal->rx_coalesce_usecs = cur_moder.usec;
631 coal->rx_max_coalesced_frames = cur_moder.pkts;
632 } else {
633 coal->rx_coalesce_usecs = c->rx_cq_moder.usec;
634 coal->rx_max_coalesced_frames = c->rx_cq_moder.pkts;
635 }
636
637 coal->use_adaptive_tx_coalesce = !!c->sq[0].dim;
638 if (coal->use_adaptive_tx_coalesce) {
639 /* NOTE: Will only display DIM coalesce profile information of
640 * first channel. The current interface cannot display this
641 * information for all tc.
642 */
643 cur_moder = net_dim_get_tx_moderation(c->sq[0].dim->mode,
644 c->sq[0].dim->profile_ix);
645
646 coal->tx_coalesce_usecs = cur_moder.usec;
647 coal->tx_max_coalesced_frames = cur_moder.pkts;
648
649 } else {
650 coal->tx_coalesce_usecs = c->tx_cq_moder.usec;
651 coal->tx_max_coalesced_frames = c->tx_cq_moder.pkts;
652 }
653
654 mutex_unlock(&priv->state_lock);
655
656 return 0;
657 }
658
mlx5e_get_per_queue_coalesce(struct net_device * dev,u32 queue,struct ethtool_coalesce * coal)659 int mlx5e_get_per_queue_coalesce(struct net_device *dev, u32 queue,
660 struct ethtool_coalesce *coal)
661 {
662 struct mlx5e_priv *priv = netdev_priv(dev);
663
664 return mlx5e_ethtool_get_per_queue_coalesce(priv, queue, coal);
665 }
666
667 #define MLX5E_MAX_COAL_TIME MLX5_MAX_CQ_PERIOD
668 #define MLX5E_MAX_COAL_FRAMES MLX5_MAX_CQ_COUNT
669
670 static void
mlx5e_set_priv_channels_tx_coalesce(struct mlx5e_priv * priv,struct dim_cq_moder * moder)671 mlx5e_set_priv_channels_tx_coalesce(struct mlx5e_priv *priv, struct dim_cq_moder *moder)
672 {
673 int tc;
674 int i;
675
676 for (i = 0; i < priv->channels.num; ++i) {
677 struct mlx5e_channel *c = priv->channels.c[i];
678 struct mlx5_core_dev *mdev = c->mdev;
679 enum mlx5_cq_period_mode mode;
680
681 mode = mlx5e_cq_period_mode(moder->cq_period_mode);
682 c->tx_cq_moder = *moder;
683
684 for (tc = 0; tc < c->num_tc; tc++) {
685 mlx5e_modify_cq_moderation(mdev, &c->sq[tc].cq.mcq,
686 moder->usec, moder->pkts,
687 mode);
688 }
689 }
690 }
691
692 static void
mlx5e_set_priv_channels_rx_coalesce(struct mlx5e_priv * priv,struct dim_cq_moder * moder)693 mlx5e_set_priv_channels_rx_coalesce(struct mlx5e_priv *priv, struct dim_cq_moder *moder)
694 {
695 int i;
696
697 for (i = 0; i < priv->channels.num; ++i) {
698 struct mlx5e_channel *c = priv->channels.c[i];
699 struct mlx5_core_dev *mdev = c->mdev;
700 enum mlx5_cq_period_mode mode;
701
702 mode = mlx5e_cq_period_mode(moder->cq_period_mode);
703 c->rx_cq_moder = *moder;
704
705 mlx5e_modify_cq_moderation(mdev, &c->rq.cq.mcq, moder->usec, moder->pkts,
706 mode);
707 }
708 }
709
mlx5e_ethtool_set_coalesce(struct mlx5e_priv * priv,struct ethtool_coalesce * coal,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)710 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
711 struct ethtool_coalesce *coal,
712 struct kernel_ethtool_coalesce *kernel_coal,
713 struct netlink_ext_ack *extack)
714 {
715 struct dim_cq_moder *rx_moder, *tx_moder;
716 struct mlx5_core_dev *mdev = priv->mdev;
717 bool rx_dim_enabled, tx_dim_enabled;
718 struct mlx5e_params new_params;
719 bool reset_rx, reset_tx;
720 u8 cq_period_mode;
721 int err = 0;
722
723 if (!MLX5_CAP_GEN(mdev, cq_moderation) ||
724 !MLX5_CAP_GEN(mdev, cq_period_mode_modify)) {
725 NL_SET_ERR_MSG_MOD(extack, "CQ moderation not supported");
726 return -EOPNOTSUPP;
727 }
728
729 if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME ||
730 coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) {
731 NL_SET_ERR_MSG_FMT_MOD(
732 extack,
733 "Max coalesce time %lu usecs, tx-usecs (%u) rx-usecs (%u)",
734 MLX5E_MAX_COAL_TIME, coal->tx_coalesce_usecs,
735 coal->rx_coalesce_usecs);
736 return -ERANGE;
737 }
738
739 if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES ||
740 coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) {
741 NL_SET_ERR_MSG_FMT_MOD(
742 extack,
743 "Max coalesce frames %lu, tx-frames (%u) rx-frames (%u)",
744 MLX5E_MAX_COAL_FRAMES, coal->tx_max_coalesced_frames,
745 coal->rx_max_coalesced_frames);
746 return -ERANGE;
747 }
748
749 if ((kernel_coal->use_cqe_mode_rx || kernel_coal->use_cqe_mode_tx) &&
750 !MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) {
751 NL_SET_ERR_MSG_MOD(extack, "cqe-mode-rx/tx is not supported on this device");
752 return -EOPNOTSUPP;
753 }
754
755 rx_dim_enabled = !!coal->use_adaptive_rx_coalesce;
756 tx_dim_enabled = !!coal->use_adaptive_tx_coalesce;
757
758 mutex_lock(&priv->state_lock);
759 new_params = priv->channels.params;
760
761 cq_period_mode = mlx5e_dim_cq_period_mode(kernel_coal->use_cqe_mode_rx);
762 reset_rx = mlx5e_reset_rx_channels_moderation(&priv->channels, cq_period_mode,
763 rx_dim_enabled, false);
764 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_RX_CQE_BASED_MODER, cq_period_mode);
765
766 cq_period_mode = mlx5e_dim_cq_period_mode(kernel_coal->use_cqe_mode_tx);
767 reset_tx = mlx5e_reset_tx_channels_moderation(&priv->channels, cq_period_mode,
768 tx_dim_enabled, false);
769 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_TX_CQE_BASED_MODER, cq_period_mode);
770
771 reset_rx |= rx_dim_enabled != new_params.rx_dim_enabled;
772 reset_tx |= tx_dim_enabled != new_params.tx_dim_enabled;
773
774 /* Solely used for global ethtool get coalesce */
775 rx_moder = &new_params.rx_cq_moderation;
776 new_params.rx_dim_enabled = rx_dim_enabled;
777 new_params.rx_moder_use_cqe_mode = kernel_coal->use_cqe_mode_rx;
778
779 tx_moder = &new_params.tx_cq_moderation;
780 new_params.tx_dim_enabled = tx_dim_enabled;
781 new_params.tx_moder_use_cqe_mode = kernel_coal->use_cqe_mode_tx;
782
783 if (reset_rx) {
784 mlx5e_channels_rx_change_dim(&priv->channels, false);
785 mlx5e_reset_rx_moderation(rx_moder, new_params.rx_moder_use_cqe_mode,
786 rx_dim_enabled);
787
788 mlx5e_set_priv_channels_rx_coalesce(priv, rx_moder);
789 } else if (!rx_dim_enabled) {
790 rx_moder->usec = coal->rx_coalesce_usecs;
791 rx_moder->pkts = coal->rx_max_coalesced_frames;
792
793 mlx5e_set_priv_channels_rx_coalesce(priv, rx_moder);
794 }
795
796 if (reset_tx) {
797 mlx5e_channels_tx_change_dim(&priv->channels, false);
798 mlx5e_reset_tx_moderation(tx_moder, new_params.tx_moder_use_cqe_mode,
799 tx_dim_enabled);
800
801 mlx5e_set_priv_channels_tx_coalesce(priv, tx_moder);
802 } else if (!tx_dim_enabled) {
803 tx_moder->usec = coal->tx_coalesce_usecs;
804 tx_moder->pkts = coal->tx_max_coalesced_frames;
805
806 mlx5e_set_priv_channels_tx_coalesce(priv, tx_moder);
807 }
808
809 /* DIM enable/disable Rx and Tx channels */
810 err = mlx5e_channels_rx_change_dim(&priv->channels, rx_dim_enabled);
811 if (err)
812 goto state_unlock;
813 err = mlx5e_channels_tx_change_dim(&priv->channels, tx_dim_enabled);
814 if (err)
815 goto state_unlock;
816
817 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, false);
818 state_unlock:
819 mutex_unlock(&priv->state_lock);
820 return err;
821 }
822
mlx5e_set_coalesce(struct net_device * netdev,struct ethtool_coalesce * coal,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)823 static int mlx5e_set_coalesce(struct net_device *netdev,
824 struct ethtool_coalesce *coal,
825 struct kernel_ethtool_coalesce *kernel_coal,
826 struct netlink_ext_ack *extack)
827 {
828 struct mlx5e_priv *priv = netdev_priv(netdev);
829
830 return mlx5e_ethtool_set_coalesce(priv, coal, kernel_coal, extack);
831 }
832
mlx5e_ethtool_set_per_queue_coalesce(struct mlx5e_priv * priv,u32 queue,struct ethtool_coalesce * coal)833 static int mlx5e_ethtool_set_per_queue_coalesce(struct mlx5e_priv *priv, u32 queue,
834 struct ethtool_coalesce *coal)
835 {
836 struct mlx5_core_dev *mdev = priv->mdev;
837 bool rx_dim_enabled, tx_dim_enabled;
838 struct mlx5e_channels *chs;
839 struct mlx5e_channel *c;
840 int err = 0;
841 int tc;
842
843 if (!MLX5_CAP_GEN(mdev, cq_moderation))
844 return -EOPNOTSUPP;
845
846 if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME ||
847 coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) {
848 netdev_info(priv->netdev, "%s: maximum coalesce time supported is %lu usecs\n",
849 __func__, MLX5E_MAX_COAL_TIME);
850 return -ERANGE;
851 }
852
853 if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES ||
854 coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) {
855 netdev_info(priv->netdev, "%s: maximum coalesced frames supported is %lu\n",
856 __func__, MLX5E_MAX_COAL_FRAMES);
857 return -ERANGE;
858 }
859
860 rx_dim_enabled = !!coal->use_adaptive_rx_coalesce;
861 tx_dim_enabled = !!coal->use_adaptive_tx_coalesce;
862
863 mutex_lock(&priv->state_lock);
864
865 chs = &priv->channels;
866 if (chs->num <= queue) {
867 mutex_unlock(&priv->state_lock);
868 return -EINVAL;
869 }
870
871 c = chs->c[queue];
872
873 err = mlx5e_dim_rx_change(&c->rq, rx_dim_enabled);
874 if (err)
875 goto state_unlock;
876
877 for (tc = 0; tc < c->num_tc; tc++) {
878 err = mlx5e_dim_tx_change(&c->sq[tc], tx_dim_enabled);
879 if (err)
880 goto state_unlock;
881 }
882
883 if (!rx_dim_enabled) {
884 c->rx_cq_moder.usec = coal->rx_coalesce_usecs;
885 c->rx_cq_moder.pkts = coal->rx_max_coalesced_frames;
886
887 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
888 coal->rx_coalesce_usecs,
889 coal->rx_max_coalesced_frames);
890 }
891
892 if (!tx_dim_enabled) {
893 c->tx_cq_moder.usec = coal->tx_coalesce_usecs;
894 c->tx_cq_moder.pkts = coal->tx_max_coalesced_frames;
895
896 for (tc = 0; tc < c->num_tc; tc++)
897 mlx5_core_modify_cq_moderation(mdev, &c->sq[tc].cq.mcq,
898 coal->tx_coalesce_usecs,
899 coal->tx_max_coalesced_frames);
900 }
901
902 state_unlock:
903 mutex_unlock(&priv->state_lock);
904 return err;
905 }
906
mlx5e_set_per_queue_coalesce(struct net_device * dev,u32 queue,struct ethtool_coalesce * coal)907 int mlx5e_set_per_queue_coalesce(struct net_device *dev, u32 queue,
908 struct ethtool_coalesce *coal)
909 {
910 struct mlx5e_priv *priv = netdev_priv(dev);
911
912 return mlx5e_ethtool_set_per_queue_coalesce(priv, queue, coal);
913 }
914
ptys2ethtool_process_link(u32 eth_eproto,bool ext,bool advertised,unsigned long * modes)915 static void ptys2ethtool_process_link(u32 eth_eproto, bool ext, bool advertised,
916 unsigned long *modes)
917 {
918 unsigned long eproto = eth_eproto;
919 struct ptys2ethtool_config *table;
920 u32 max_size;
921 int proto;
922
923 mlx5e_ethtool_get_speed_arr(ext, &table, &max_size);
924 for_each_set_bit(proto, &eproto, max_size)
925 bitmap_or(modes, modes,
926 advertised ?
927 table[proto].advertised : table[proto].supported,
928 __ETHTOOL_LINK_MODE_MASK_NBITS);
929 }
930
931 static const u32 pplm_fec_2_ethtool[] = {
932 [MLX5E_FEC_NOFEC] = ETHTOOL_FEC_OFF,
933 [MLX5E_FEC_FIRECODE] = ETHTOOL_FEC_BASER,
934 [MLX5E_FEC_RS_528_514] = ETHTOOL_FEC_RS,
935 [MLX5E_FEC_RS_544_514] = ETHTOOL_FEC_RS,
936 [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_FEC_LLRS,
937 [MLX5E_FEC_RS_544_514_INTERLEAVED_QUAD] = ETHTOOL_FEC_RS,
938 };
939
pplm2ethtool_fec(u_long fec_mode,unsigned long size)940 static u32 pplm2ethtool_fec(u_long fec_mode, unsigned long size)
941 {
942 int mode = 0;
943
944 if (!fec_mode)
945 return ETHTOOL_FEC_AUTO;
946
947 mode = find_first_bit(&fec_mode, size);
948
949 if (mode < ARRAY_SIZE(pplm_fec_2_ethtool))
950 return pplm_fec_2_ethtool[mode];
951
952 return 0;
953 }
954
955 #define MLX5E_ADVERTISE_SUPPORTED_FEC(mlx5_fec, ethtool_fec) \
956 do { \
957 if (mlx5e_fec_in_caps(dev, 1 << (mlx5_fec))) \
958 __set_bit(ethtool_fec, \
959 link_ksettings->link_modes.supported);\
960 } while (0)
961
962 static const u32 pplm_fec_2_ethtool_linkmodes[] = {
963 [MLX5E_FEC_NOFEC] = ETHTOOL_LINK_MODE_FEC_NONE_BIT,
964 [MLX5E_FEC_FIRECODE] = ETHTOOL_LINK_MODE_FEC_BASER_BIT,
965 [MLX5E_FEC_RS_528_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT,
966 [MLX5E_FEC_RS_544_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT,
967 [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
968 };
969
get_fec_supported_advertised(struct mlx5_core_dev * dev,struct ethtool_link_ksettings * link_ksettings)970 static int get_fec_supported_advertised(struct mlx5_core_dev *dev,
971 struct ethtool_link_ksettings *link_ksettings)
972 {
973 unsigned long active_fec_long;
974 u32 active_fec;
975 u32 bitn;
976 int err;
977
978 err = mlx5e_get_fec_mode(dev, &active_fec, NULL);
979 if (err)
980 return (err == -EOPNOTSUPP) ? 0 : err;
981
982 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_NOFEC,
983 ETHTOOL_LINK_MODE_FEC_NONE_BIT);
984 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_FIRECODE,
985 ETHTOOL_LINK_MODE_FEC_BASER_BIT);
986 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_RS_528_514,
987 ETHTOOL_LINK_MODE_FEC_RS_BIT);
988 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_LLRS_272_257_1,
989 ETHTOOL_LINK_MODE_FEC_LLRS_BIT);
990
991 active_fec_long = active_fec;
992 /* active fec is a bit set, find out which bit is set and
993 * advertise the corresponding ethtool bit
994 */
995 bitn = find_first_bit(&active_fec_long, sizeof(active_fec_long) * BITS_PER_BYTE);
996 if (bitn < ARRAY_SIZE(pplm_fec_2_ethtool_linkmodes))
997 __set_bit(pplm_fec_2_ethtool_linkmodes[bitn],
998 link_ksettings->link_modes.advertising);
999
1000 return 0;
1001 }
1002
ptys2ethtool_supported_advertised_port(struct mlx5_core_dev * mdev,struct ethtool_link_ksettings * link_ksettings,u32 eth_proto_cap,u8 connector_type)1003 static void ptys2ethtool_supported_advertised_port(struct mlx5_core_dev *mdev,
1004 struct ethtool_link_ksettings *link_ksettings,
1005 u32 eth_proto_cap, u8 connector_type)
1006 {
1007 if (!MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type)) {
1008 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
1009 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
1010 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
1011 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
1012 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
1013 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
1014 ethtool_link_ksettings_add_link_mode(link_ksettings,
1015 supported,
1016 FIBRE);
1017 ethtool_link_ksettings_add_link_mode(link_ksettings,
1018 advertising,
1019 FIBRE);
1020 }
1021
1022 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
1023 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
1024 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
1025 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
1026 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
1027 ethtool_link_ksettings_add_link_mode(link_ksettings,
1028 supported,
1029 Backplane);
1030 ethtool_link_ksettings_add_link_mode(link_ksettings,
1031 advertising,
1032 Backplane);
1033 }
1034 return;
1035 }
1036
1037 switch (connector_type) {
1038 case MLX5E_PORT_TP:
1039 ethtool_link_ksettings_add_link_mode(link_ksettings,
1040 supported, TP);
1041 ethtool_link_ksettings_add_link_mode(link_ksettings,
1042 advertising, TP);
1043 break;
1044 case MLX5E_PORT_AUI:
1045 ethtool_link_ksettings_add_link_mode(link_ksettings,
1046 supported, AUI);
1047 ethtool_link_ksettings_add_link_mode(link_ksettings,
1048 advertising, AUI);
1049 break;
1050 case MLX5E_PORT_BNC:
1051 ethtool_link_ksettings_add_link_mode(link_ksettings,
1052 supported, BNC);
1053 ethtool_link_ksettings_add_link_mode(link_ksettings,
1054 advertising, BNC);
1055 break;
1056 case MLX5E_PORT_MII:
1057 ethtool_link_ksettings_add_link_mode(link_ksettings,
1058 supported, MII);
1059 ethtool_link_ksettings_add_link_mode(link_ksettings,
1060 advertising, MII);
1061 break;
1062 case MLX5E_PORT_FIBRE:
1063 ethtool_link_ksettings_add_link_mode(link_ksettings,
1064 supported, FIBRE);
1065 ethtool_link_ksettings_add_link_mode(link_ksettings,
1066 advertising, FIBRE);
1067 break;
1068 case MLX5E_PORT_DA:
1069 ethtool_link_ksettings_add_link_mode(link_ksettings,
1070 supported, Backplane);
1071 ethtool_link_ksettings_add_link_mode(link_ksettings,
1072 advertising, Backplane);
1073 break;
1074 case MLX5E_PORT_NONE:
1075 case MLX5E_PORT_OTHER:
1076 default:
1077 break;
1078 }
1079 }
1080
get_link_properties(struct net_device * netdev,u32 eth_proto_oper,bool force_legacy,u16 data_rate_oper,struct ethtool_link_ksettings * link_ksettings)1081 static void get_link_properties(struct net_device *netdev,
1082 u32 eth_proto_oper, bool force_legacy,
1083 u16 data_rate_oper,
1084 struct ethtool_link_ksettings *link_ksettings)
1085 {
1086 struct mlx5e_priv *priv = netdev_priv(netdev);
1087 const struct mlx5_link_info *info;
1088 u8 duplex = DUPLEX_UNKNOWN;
1089 u32 speed = SPEED_UNKNOWN;
1090 u32 lanes = LANES_UNKNOWN;
1091
1092 if (!netif_carrier_ok(netdev))
1093 goto out;
1094
1095 info = mlx5_port_ptys2info(priv->mdev, eth_proto_oper, force_legacy);
1096 if (info) {
1097 speed = info->speed;
1098 lanes = info->lanes;
1099 duplex = DUPLEX_FULL;
1100 } else if (data_rate_oper)
1101 speed = 100 * data_rate_oper;
1102
1103 out:
1104 link_ksettings->base.duplex = duplex;
1105 link_ksettings->base.speed = speed;
1106 link_ksettings->lanes = lanes;
1107 }
1108
get_supported(struct mlx5_core_dev * mdev,u32 eth_proto_cap,struct ethtool_link_ksettings * link_ksettings)1109 static void get_supported(struct mlx5_core_dev *mdev, u32 eth_proto_cap,
1110 struct ethtool_link_ksettings *link_ksettings)
1111 {
1112 unsigned long *supported = link_ksettings->link_modes.supported;
1113 bool ext = mlx5_ptys_ext_supported(mdev);
1114
1115 ptys2ethtool_process_link(eth_proto_cap, ext, false, supported);
1116
1117 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
1118 }
1119
get_advertising(u32 eth_proto_admin,u8 tx_pause,u8 rx_pause,struct ethtool_link_ksettings * link_ksettings,bool ext)1120 static void get_advertising(u32 eth_proto_admin, u8 tx_pause, u8 rx_pause,
1121 struct ethtool_link_ksettings *link_ksettings,
1122 bool ext)
1123 {
1124 unsigned long *advertising = link_ksettings->link_modes.advertising;
1125 ptys2ethtool_process_link(eth_proto_admin, ext, true, advertising);
1126 if (rx_pause)
1127 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
1128 if (tx_pause ^ rx_pause)
1129 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
1130 }
1131
1132 static int ptys2connector_type[MLX5E_CONNECTOR_TYPE_NUMBER] = {
1133 [MLX5E_PORT_UNKNOWN] = PORT_OTHER,
1134 [MLX5E_PORT_NONE] = PORT_NONE,
1135 [MLX5E_PORT_TP] = PORT_TP,
1136 [MLX5E_PORT_AUI] = PORT_AUI,
1137 [MLX5E_PORT_BNC] = PORT_BNC,
1138 [MLX5E_PORT_MII] = PORT_MII,
1139 [MLX5E_PORT_FIBRE] = PORT_FIBRE,
1140 [MLX5E_PORT_DA] = PORT_DA,
1141 [MLX5E_PORT_OTHER] = PORT_OTHER,
1142 };
1143
get_connector_port(struct mlx5_core_dev * mdev,u32 eth_proto,u8 connector_type)1144 static u8 get_connector_port(struct mlx5_core_dev *mdev, u32 eth_proto, u8 connector_type)
1145 {
1146 if (MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type))
1147 return ptys2connector_type[connector_type];
1148
1149 if (eth_proto &
1150 (MLX5E_PROT_MASK(MLX5E_10GBASE_SR) |
1151 MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) |
1152 MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) |
1153 MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
1154 return PORT_FIBRE;
1155 }
1156
1157 if (eth_proto &
1158 (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) |
1159 MLX5E_PROT_MASK(MLX5E_10GBASE_CR) |
1160 MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
1161 return PORT_DA;
1162 }
1163
1164 if (eth_proto &
1165 (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) |
1166 MLX5E_PROT_MASK(MLX5E_10GBASE_KR) |
1167 MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) |
1168 MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
1169 return PORT_NONE;
1170 }
1171
1172 return PORT_OTHER;
1173 }
1174
get_lp_advertising(struct mlx5_core_dev * mdev,u32 eth_proto_lp,struct ethtool_link_ksettings * link_ksettings)1175 static void get_lp_advertising(struct mlx5_core_dev *mdev, u32 eth_proto_lp,
1176 struct ethtool_link_ksettings *link_ksettings)
1177 {
1178 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
1179 bool ext = mlx5_ptys_ext_supported(mdev);
1180
1181 ptys2ethtool_process_link(eth_proto_lp, ext, true, lp_advertising);
1182 }
1183
mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv * priv,struct ethtool_link_ksettings * link_ksettings)1184 static int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
1185 struct ethtool_link_ksettings *link_ksettings)
1186 {
1187 struct mlx5_core_dev *mdev = priv->mdev;
1188 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {};
1189 u32 eth_proto_admin;
1190 u8 an_disable_admin;
1191 u16 data_rate_oper;
1192 u32 eth_proto_oper;
1193 u32 eth_proto_cap;
1194 u8 connector_type;
1195 u32 rx_pause = 0;
1196 u32 tx_pause = 0;
1197 u32 eth_proto_lp;
1198 bool admin_ext;
1199 u8 an_status;
1200 bool ext;
1201 int err;
1202
1203 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1, 0);
1204 if (err) {
1205 netdev_err(priv->netdev, "%s: query port ptys failed: %d\n",
1206 __func__, err);
1207 goto err_query_regs;
1208 }
1209 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability);
1210 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
1211 eth_proto_capability);
1212 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
1213 eth_proto_admin);
1214 /* Fields: eth_proto_admin and ext_eth_proto_admin are
1215 * mutually exclusive. Hence try reading legacy advertising
1216 * when extended advertising is zero.
1217 * admin_ext indicates which proto_admin (ext vs. legacy)
1218 * should be read and interpreted
1219 */
1220 admin_ext = ext;
1221 if (ext && !eth_proto_admin) {
1222 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, false,
1223 eth_proto_admin);
1224 admin_ext = false;
1225 }
1226
1227 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, admin_ext,
1228 eth_proto_oper);
1229 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
1230 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
1231 an_status = MLX5_GET(ptys_reg, out, an_status);
1232 connector_type = MLX5_GET(ptys_reg, out, connector_type);
1233 data_rate_oper = MLX5_GET(ptys_reg, out, data_rate_oper);
1234
1235 mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
1236
1237 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
1238 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
1239
1240 get_supported(mdev, eth_proto_cap, link_ksettings);
1241 get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings,
1242 admin_ext);
1243 get_link_properties(priv->netdev, eth_proto_oper, !admin_ext,
1244 data_rate_oper, link_ksettings);
1245
1246 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
1247 connector_type = connector_type < MLX5E_CONNECTOR_TYPE_NUMBER ?
1248 connector_type : MLX5E_PORT_UNKNOWN;
1249 link_ksettings->base.port = get_connector_port(mdev, eth_proto_oper, connector_type);
1250 ptys2ethtool_supported_advertised_port(mdev, link_ksettings, eth_proto_admin,
1251 connector_type);
1252 get_lp_advertising(mdev, eth_proto_lp, link_ksettings);
1253
1254 if (an_status == MLX5_AN_COMPLETE)
1255 ethtool_link_ksettings_add_link_mode(link_ksettings,
1256 lp_advertising, Autoneg);
1257
1258 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
1259 AUTONEG_ENABLE;
1260 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
1261 Autoneg);
1262
1263 err = get_fec_supported_advertised(mdev, link_ksettings);
1264 if (err) {
1265 netdev_dbg(priv->netdev, "%s: FEC caps query failed: %d\n",
1266 __func__, err);
1267 err = 0; /* don't fail caps query because of FEC error */
1268 }
1269
1270 if (!an_disable_admin)
1271 ethtool_link_ksettings_add_link_mode(link_ksettings,
1272 advertising, Autoneg);
1273
1274 err_query_regs:
1275 return err;
1276 }
1277
mlx5e_get_link_ksettings(struct net_device * netdev,struct ethtool_link_ksettings * link_ksettings)1278 static int mlx5e_get_link_ksettings(struct net_device *netdev,
1279 struct ethtool_link_ksettings *link_ksettings)
1280 {
1281 struct mlx5e_priv *priv = netdev_priv(netdev);
1282
1283 return mlx5e_ethtool_get_link_ksettings(priv, link_ksettings);
1284 }
1285
mlx5e_speed_validate(struct net_device * netdev,bool ext,const unsigned long link_modes,u8 autoneg)1286 static int mlx5e_speed_validate(struct net_device *netdev, bool ext,
1287 const unsigned long link_modes, u8 autoneg)
1288 {
1289 /* Extended link-mode has no speed limitations. */
1290 if (ext)
1291 return 0;
1292
1293 if ((link_modes & MLX5E_PROT_MASK(MLX5E_56GBASE_R4)) &&
1294 autoneg != AUTONEG_ENABLE) {
1295 netdev_err(netdev, "%s: 56G link speed requires autoneg enabled\n",
1296 __func__);
1297 return -EINVAL;
1298 }
1299 return 0;
1300 }
1301
mlx5e_ethtool2ptys_adver_link(const unsigned long * link_modes)1302 static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
1303 {
1304 u32 i, ptys_modes = 0;
1305
1306 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
1307 if (bitmap_empty(ptys2legacy_ethtool_table[i].advertised,
1308 __ETHTOOL_LINK_MODE_MASK_NBITS))
1309 continue;
1310 if (bitmap_intersects(ptys2legacy_ethtool_table[i].advertised,
1311 link_modes,
1312 __ETHTOOL_LINK_MODE_MASK_NBITS))
1313 ptys_modes |= MLX5E_PROT_MASK(i);
1314 }
1315
1316 return ptys_modes;
1317 }
1318
mlx5e_ethtool2ptys_ext_adver_link(const unsigned long * link_modes)1319 static u32 mlx5e_ethtool2ptys_ext_adver_link(const unsigned long *link_modes)
1320 {
1321 u32 i, ptys_modes = 0;
1322 __ETHTOOL_DECLARE_LINK_MODE_MASK(modes);
1323
1324 for (i = 0; i < MLX5E_EXT_LINK_MODES_NUMBER; ++i) {
1325 if (bitmap_empty(ptys2ext_ethtool_table[i].advertised,
1326 __ETHTOOL_LINK_MODE_MASK_NBITS))
1327 continue;
1328 bitmap_zero(modes, __ETHTOOL_LINK_MODE_MASK_NBITS);
1329 bitmap_and(modes, ptys2ext_ethtool_table[i].advertised,
1330 link_modes, __ETHTOOL_LINK_MODE_MASK_NBITS);
1331
1332 if (bitmap_equal(modes, ptys2ext_ethtool_table[i].advertised,
1333 __ETHTOOL_LINK_MODE_MASK_NBITS))
1334 ptys_modes |= MLX5E_PROT_MASK(i);
1335 }
1336 return ptys_modes;
1337 }
1338
ext_link_mode_requested(const unsigned long * adver)1339 static bool ext_link_mode_requested(const unsigned long *adver)
1340 {
1341 #define MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT ETHTOOL_LINK_MODE_50000baseKR_Full_BIT
1342 int size = __ETHTOOL_LINK_MODE_MASK_NBITS - MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT;
1343 __ETHTOOL_DECLARE_LINK_MODE_MASK(modes) = {0,};
1344
1345 bitmap_set(modes, MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT, size);
1346 return bitmap_intersects(modes, adver, __ETHTOOL_LINK_MODE_MASK_NBITS);
1347 }
1348
mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv * priv,const struct ethtool_link_ksettings * link_ksettings)1349 static int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
1350 const struct ethtool_link_ksettings *link_ksettings)
1351 {
1352 struct mlx5_core_dev *mdev = priv->mdev;
1353 struct mlx5_port_eth_proto eproto;
1354 struct mlx5_link_info info = {};
1355 const unsigned long *adver;
1356 bool an_changes = false;
1357 u8 an_disable_admin;
1358 bool ext_supported;
1359 bool ext_requested;
1360 u8 an_disable_cap;
1361 bool an_disable;
1362 u32 link_modes;
1363 u8 an_status;
1364 u8 autoneg;
1365 bool ext;
1366 int err;
1367
1368 u32 (*ethtool2ptys_adver_func)(const unsigned long *adver);
1369
1370 adver = link_ksettings->link_modes.advertising;
1371 autoneg = link_ksettings->base.autoneg;
1372 info.speed = link_ksettings->base.speed;
1373 info.lanes = link_ksettings->lanes;
1374
1375 ext_supported = mlx5_ptys_ext_supported(mdev);
1376 ext_requested = ext_link_mode_requested(adver);
1377 if (!ext_supported && ext_requested)
1378 return -EOPNOTSUPP;
1379
1380 ext = autoneg == AUTONEG_ENABLE ? ext_requested : ext_supported;
1381 ethtool2ptys_adver_func = ext ? mlx5e_ethtool2ptys_ext_adver_link :
1382 mlx5e_ethtool2ptys_adver_link;
1383 err = mlx5_port_query_eth_proto(mdev, 1, ext, &eproto);
1384 if (err) {
1385 netdev_err(priv->netdev, "%s: query port eth proto failed: %d\n",
1386 __func__, err);
1387 goto out;
1388 }
1389 link_modes = autoneg == AUTONEG_ENABLE ? ethtool2ptys_adver_func(adver) :
1390 mlx5_port_info2linkmodes(mdev, &info, !ext);
1391
1392 err = mlx5e_speed_validate(priv->netdev, ext, link_modes, autoneg);
1393 if (err)
1394 goto out;
1395
1396 link_modes = link_modes & eproto.cap;
1397 if (!link_modes) {
1398 netdev_err(priv->netdev, "%s: Not supported link mode(s) requested",
1399 __func__);
1400 err = -EINVAL;
1401 goto out;
1402 }
1403
1404 mlx5_port_query_eth_autoneg(mdev, &an_status, &an_disable_cap,
1405 &an_disable_admin);
1406
1407 an_disable = autoneg == AUTONEG_DISABLE;
1408 an_changes = ((!an_disable && an_disable_admin) ||
1409 (an_disable && !an_disable_admin));
1410
1411 if (!an_changes && link_modes == eproto.admin)
1412 goto out;
1413
1414 err = mlx5_port_set_eth_ptys(mdev, an_disable, link_modes, ext);
1415 if (err) {
1416 netdev_err(priv->netdev, "%s: failed to set ptys reg: %d\n", __func__, err);
1417 goto out;
1418 }
1419
1420 mlx5_toggle_port_link(mdev);
1421
1422 out:
1423 return err;
1424 }
1425
mlx5e_set_link_ksettings(struct net_device * netdev,const struct ethtool_link_ksettings * link_ksettings)1426 static int mlx5e_set_link_ksettings(struct net_device *netdev,
1427 const struct ethtool_link_ksettings *link_ksettings)
1428 {
1429 struct mlx5e_priv *priv = netdev_priv(netdev);
1430
1431 return mlx5e_ethtool_set_link_ksettings(priv, link_ksettings);
1432 }
1433
mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv * priv)1434 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv)
1435 {
1436 return sizeof_field(struct mlx5e_rss_params_hash, toeplitz_hash_key);
1437 }
1438
mlx5e_get_rxfh_key_size(struct net_device * netdev)1439 static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
1440 {
1441 struct mlx5e_priv *priv = netdev_priv(netdev);
1442
1443 return mlx5e_ethtool_get_rxfh_key_size(priv);
1444 }
1445
mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv * priv)1446 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv)
1447 {
1448 return mlx5e_rqt_size(priv->mdev, priv->channels.params.num_channels);
1449 }
1450
mlx5e_get_rxfh_indir_size(struct net_device * netdev)1451 static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
1452 {
1453 struct mlx5e_priv *priv = netdev_priv(netdev);
1454
1455 return mlx5e_ethtool_get_rxfh_indir_size(priv);
1456 }
1457
mlx5e_get_rxfh(struct net_device * netdev,struct ethtool_rxfh_param * rxfh)1458 static int mlx5e_get_rxfh(struct net_device *netdev, struct ethtool_rxfh_param *rxfh)
1459 {
1460 struct mlx5e_priv *priv = netdev_priv(netdev);
1461 u32 rss_context = rxfh->rss_context;
1462 bool symmetric;
1463 int err;
1464
1465 mutex_lock(&priv->state_lock);
1466 err = mlx5e_rx_res_rss_get_rxfh(priv->rx_res, rss_context,
1467 rxfh->indir, rxfh->key, &rxfh->hfunc, &symmetric);
1468 mutex_unlock(&priv->state_lock);
1469
1470 if (err)
1471 return err;
1472
1473 if (symmetric)
1474 rxfh->input_xfrm = RXH_XFRM_SYM_OR_XOR;
1475
1476 return 0;
1477 }
1478
mlx5e_set_rxfh(struct net_device * dev,struct ethtool_rxfh_param * rxfh,struct netlink_ext_ack * extack)1479 static int mlx5e_set_rxfh(struct net_device *dev, struct ethtool_rxfh_param *rxfh,
1480 struct netlink_ext_ack *extack)
1481 {
1482 bool symmetric = rxfh->input_xfrm == RXH_XFRM_SYM_OR_XOR;
1483 struct mlx5e_priv *priv = netdev_priv(dev);
1484 u32 *rss_context = &rxfh->rss_context;
1485 u8 hfunc = rxfh->hfunc;
1486 unsigned int count;
1487 int err;
1488
1489 mutex_lock(&priv->state_lock);
1490
1491 count = priv->channels.params.num_channels;
1492
1493 if (hfunc == ETH_RSS_HASH_XOR) {
1494 unsigned int xor8_max_channels = mlx5e_rqt_max_num_channels_allowed_for_xor8();
1495
1496 if (count > xor8_max_channels) {
1497 err = -EINVAL;
1498 netdev_err(priv->netdev, "%s: Cannot set RSS hash function to XOR, current number of channels (%d) exceeds the maximum allowed for XOR8 RSS hfunc (%d)\n",
1499 __func__, count, xor8_max_channels);
1500 goto unlock;
1501 }
1502 }
1503
1504 if (*rss_context && rxfh->rss_delete) {
1505 err = mlx5e_rx_res_rss_destroy(priv->rx_res, *rss_context);
1506 goto unlock;
1507 }
1508
1509 if (*rss_context == ETH_RXFH_CONTEXT_ALLOC) {
1510 err = mlx5e_rx_res_rss_init(priv->rx_res, rss_context, count);
1511 if (err)
1512 goto unlock;
1513 }
1514
1515 err = mlx5e_rx_res_rss_set_rxfh(priv->rx_res, *rss_context,
1516 rxfh->indir, rxfh->key,
1517 hfunc == ETH_RSS_HASH_NO_CHANGE ? NULL : &hfunc,
1518 rxfh->input_xfrm == RXH_XFRM_NO_CHANGE ? NULL : &symmetric);
1519
1520 unlock:
1521 mutex_unlock(&priv->state_lock);
1522 return err;
1523 }
1524
1525 #define MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC 100
1526 #define MLX5E_PFC_PREVEN_TOUT_MAX_MSEC 8000
1527 #define MLX5E_PFC_PREVEN_MINOR_PRECENT 85
1528 #define MLX5E_PFC_PREVEN_TOUT_MIN_MSEC 80
1529 #define MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout) \
1530 max_t(u16, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, \
1531 (critical_tout * MLX5E_PFC_PREVEN_MINOR_PRECENT) / 100)
1532
mlx5e_get_pfc_prevention_tout(struct net_device * netdev,u16 * pfc_prevention_tout)1533 static int mlx5e_get_pfc_prevention_tout(struct net_device *netdev,
1534 u16 *pfc_prevention_tout)
1535 {
1536 struct mlx5e_priv *priv = netdev_priv(netdev);
1537 struct mlx5_core_dev *mdev = priv->mdev;
1538
1539 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1540 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1541 return -EOPNOTSUPP;
1542
1543 return mlx5_query_port_stall_watermark(mdev, pfc_prevention_tout, NULL);
1544 }
1545
mlx5e_set_pfc_prevention_tout(struct net_device * netdev,u16 pfc_preven)1546 static int mlx5e_set_pfc_prevention_tout(struct net_device *netdev,
1547 u16 pfc_preven)
1548 {
1549 struct mlx5e_priv *priv = netdev_priv(netdev);
1550 struct mlx5_core_dev *mdev = priv->mdev;
1551 u16 critical_tout;
1552 u16 minor;
1553
1554 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1555 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1556 return -EOPNOTSUPP;
1557
1558 critical_tout = (pfc_preven == PFC_STORM_PREVENTION_AUTO) ?
1559 MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC :
1560 pfc_preven;
1561
1562 if (critical_tout != PFC_STORM_PREVENTION_DISABLE &&
1563 (critical_tout > MLX5E_PFC_PREVEN_TOUT_MAX_MSEC ||
1564 critical_tout < MLX5E_PFC_PREVEN_TOUT_MIN_MSEC)) {
1565 netdev_info(netdev, "%s: pfc prevention tout not in range (%d-%d)\n",
1566 __func__, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC,
1567 MLX5E_PFC_PREVEN_TOUT_MAX_MSEC);
1568 return -EINVAL;
1569 }
1570
1571 minor = MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout);
1572 return mlx5_set_port_stall_watermark(mdev, critical_tout,
1573 minor);
1574 }
1575
mlx5e_get_tunable(struct net_device * dev,const struct ethtool_tunable * tuna,void * data)1576 static int mlx5e_get_tunable(struct net_device *dev,
1577 const struct ethtool_tunable *tuna,
1578 void *data)
1579 {
1580 int err;
1581
1582 switch (tuna->id) {
1583 case ETHTOOL_PFC_PREVENTION_TOUT:
1584 err = mlx5e_get_pfc_prevention_tout(dev, data);
1585 break;
1586 default:
1587 err = -EINVAL;
1588 break;
1589 }
1590
1591 return err;
1592 }
1593
mlx5e_set_tunable(struct net_device * dev,const struct ethtool_tunable * tuna,const void * data)1594 static int mlx5e_set_tunable(struct net_device *dev,
1595 const struct ethtool_tunable *tuna,
1596 const void *data)
1597 {
1598 struct mlx5e_priv *priv = netdev_priv(dev);
1599 int err;
1600
1601 mutex_lock(&priv->state_lock);
1602
1603 switch (tuna->id) {
1604 case ETHTOOL_PFC_PREVENTION_TOUT:
1605 err = mlx5e_set_pfc_prevention_tout(dev, *(u16 *)data);
1606 break;
1607 default:
1608 err = -EINVAL;
1609 break;
1610 }
1611
1612 mutex_unlock(&priv->state_lock);
1613 return err;
1614 }
1615
mlx5e_get_pause_stats(struct net_device * netdev,struct ethtool_pause_stats * pause_stats)1616 static void mlx5e_get_pause_stats(struct net_device *netdev,
1617 struct ethtool_pause_stats *pause_stats)
1618 {
1619 struct mlx5e_priv *priv = netdev_priv(netdev);
1620
1621 mlx5e_stats_pause_get(priv, pause_stats);
1622 }
1623
mlx5e_ethtool_get_pauseparam(struct mlx5e_priv * priv,struct ethtool_pauseparam * pauseparam)1624 static void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1625 struct ethtool_pauseparam *pauseparam)
1626 {
1627 struct mlx5_core_dev *mdev = priv->mdev;
1628 int err;
1629
1630 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1631 &pauseparam->tx_pause);
1632 if (err) {
1633 netdev_err(priv->netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1634 __func__, err);
1635 }
1636 }
1637
mlx5e_get_pauseparam(struct net_device * netdev,struct ethtool_pauseparam * pauseparam)1638 static void mlx5e_get_pauseparam(struct net_device *netdev,
1639 struct ethtool_pauseparam *pauseparam)
1640 {
1641 struct mlx5e_priv *priv = netdev_priv(netdev);
1642
1643 mlx5e_ethtool_get_pauseparam(priv, pauseparam);
1644 }
1645
mlx5e_ethtool_set_pauseparam(struct mlx5e_priv * priv,struct ethtool_pauseparam * pauseparam)1646 static int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1647 struct ethtool_pauseparam *pauseparam)
1648 {
1649 struct mlx5_core_dev *mdev = priv->mdev;
1650 int err;
1651
1652 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
1653 return -EOPNOTSUPP;
1654
1655 if (pauseparam->autoneg)
1656 return -EINVAL;
1657
1658 err = mlx5_set_port_pause(mdev,
1659 pauseparam->rx_pause ? 1 : 0,
1660 pauseparam->tx_pause ? 1 : 0);
1661 if (err) {
1662 netdev_err(priv->netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1663 __func__, err);
1664 }
1665
1666 return err;
1667 }
1668
mlx5e_set_pauseparam(struct net_device * netdev,struct ethtool_pauseparam * pauseparam)1669 static int mlx5e_set_pauseparam(struct net_device *netdev,
1670 struct ethtool_pauseparam *pauseparam)
1671 {
1672 struct mlx5e_priv *priv = netdev_priv(netdev);
1673
1674 return mlx5e_ethtool_set_pauseparam(priv, pauseparam);
1675 }
1676
mlx5e_ethtool_get_ts_info(struct mlx5e_priv * priv,struct kernel_ethtool_ts_info * info)1677 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1678 struct kernel_ethtool_ts_info *info)
1679 {
1680 struct mlx5_core_dev *mdev = priv->mdev;
1681
1682 info->phc_index = mlx5_clock_get_ptp_index(mdev);
1683
1684 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
1685 info->phc_index == -1)
1686 return 0;
1687
1688 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
1689 SOF_TIMESTAMPING_TX_SOFTWARE |
1690 SOF_TIMESTAMPING_RX_HARDWARE |
1691 SOF_TIMESTAMPING_RAW_HARDWARE;
1692
1693 info->tx_types = BIT(HWTSTAMP_TX_OFF) |
1694 BIT(HWTSTAMP_TX_ON);
1695
1696 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
1697 BIT(HWTSTAMP_FILTER_ALL);
1698
1699 return 0;
1700 }
1701
mlx5e_get_ts_info(struct net_device * dev,struct kernel_ethtool_ts_info * info)1702 static int mlx5e_get_ts_info(struct net_device *dev,
1703 struct kernel_ethtool_ts_info *info)
1704 {
1705 struct mlx5e_priv *priv = netdev_priv(dev);
1706
1707 return mlx5e_ethtool_get_ts_info(priv, info);
1708 }
1709
mlx5e_get_wol_supported(struct mlx5_core_dev * mdev)1710 static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1711 {
1712 __u32 ret = 0;
1713
1714 if (MLX5_CAP_GEN(mdev, wol_g))
1715 ret |= WAKE_MAGIC;
1716
1717 if (MLX5_CAP_GEN(mdev, wol_s))
1718 ret |= WAKE_MAGICSECURE;
1719
1720 if (MLX5_CAP_GEN(mdev, wol_a))
1721 ret |= WAKE_ARP;
1722
1723 if (MLX5_CAP_GEN(mdev, wol_b))
1724 ret |= WAKE_BCAST;
1725
1726 if (MLX5_CAP_GEN(mdev, wol_m))
1727 ret |= WAKE_MCAST;
1728
1729 if (MLX5_CAP_GEN(mdev, wol_u))
1730 ret |= WAKE_UCAST;
1731
1732 if (MLX5_CAP_GEN(mdev, wol_p))
1733 ret |= WAKE_PHY;
1734
1735 return ret;
1736 }
1737
mlx5e_reformat_wol_mode_mlx5_to_linux(u8 mode)1738 static __u32 mlx5e_reformat_wol_mode_mlx5_to_linux(u8 mode)
1739 {
1740 __u32 ret = 0;
1741
1742 if (mode & MLX5_WOL_MAGIC)
1743 ret |= WAKE_MAGIC;
1744
1745 if (mode & MLX5_WOL_SECURED_MAGIC)
1746 ret |= WAKE_MAGICSECURE;
1747
1748 if (mode & MLX5_WOL_ARP)
1749 ret |= WAKE_ARP;
1750
1751 if (mode & MLX5_WOL_BROADCAST)
1752 ret |= WAKE_BCAST;
1753
1754 if (mode & MLX5_WOL_MULTICAST)
1755 ret |= WAKE_MCAST;
1756
1757 if (mode & MLX5_WOL_UNICAST)
1758 ret |= WAKE_UCAST;
1759
1760 if (mode & MLX5_WOL_PHY_ACTIVITY)
1761 ret |= WAKE_PHY;
1762
1763 return ret;
1764 }
1765
mlx5e_reformat_wol_mode_linux_to_mlx5(__u32 mode)1766 static u8 mlx5e_reformat_wol_mode_linux_to_mlx5(__u32 mode)
1767 {
1768 u8 ret = 0;
1769
1770 if (mode & WAKE_MAGIC)
1771 ret |= MLX5_WOL_MAGIC;
1772
1773 if (mode & WAKE_MAGICSECURE)
1774 ret |= MLX5_WOL_SECURED_MAGIC;
1775
1776 if (mode & WAKE_ARP)
1777 ret |= MLX5_WOL_ARP;
1778
1779 if (mode & WAKE_BCAST)
1780 ret |= MLX5_WOL_BROADCAST;
1781
1782 if (mode & WAKE_MCAST)
1783 ret |= MLX5_WOL_MULTICAST;
1784
1785 if (mode & WAKE_UCAST)
1786 ret |= MLX5_WOL_UNICAST;
1787
1788 if (mode & WAKE_PHY)
1789 ret |= MLX5_WOL_PHY_ACTIVITY;
1790
1791 return ret;
1792 }
1793
mlx5e_get_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)1794 static void mlx5e_get_wol(struct net_device *netdev,
1795 struct ethtool_wolinfo *wol)
1796 {
1797 struct mlx5e_priv *priv = netdev_priv(netdev);
1798 struct mlx5_core_dev *mdev = priv->mdev;
1799 u8 mlx5_wol_mode;
1800 int err;
1801
1802 memset(wol, 0, sizeof(*wol));
1803
1804 wol->supported = mlx5e_get_wol_supported(mdev);
1805 if (!wol->supported)
1806 return;
1807
1808 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1809 if (err)
1810 return;
1811
1812 wol->wolopts = mlx5e_reformat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1813 }
1814
mlx5e_set_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)1815 static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1816 {
1817 struct mlx5e_priv *priv = netdev_priv(netdev);
1818 struct mlx5_core_dev *mdev = priv->mdev;
1819 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1820 u32 mlx5_wol_mode;
1821
1822 if (!wol_supported)
1823 return -EOPNOTSUPP;
1824
1825 if (wol->wolopts & ~wol_supported)
1826 return -EINVAL;
1827
1828 mlx5_wol_mode = mlx5e_reformat_wol_mode_linux_to_mlx5(wol->wolopts);
1829
1830 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1831 }
1832
mlx5e_get_fec_stats(struct net_device * netdev,struct ethtool_fec_stats * fec_stats)1833 static void mlx5e_get_fec_stats(struct net_device *netdev,
1834 struct ethtool_fec_stats *fec_stats)
1835 {
1836 struct mlx5e_priv *priv = netdev_priv(netdev);
1837
1838 mlx5e_stats_fec_get(priv, fec_stats);
1839 }
1840
mlx5e_get_fecparam(struct net_device * netdev,struct ethtool_fecparam * fecparam)1841 static int mlx5e_get_fecparam(struct net_device *netdev,
1842 struct ethtool_fecparam *fecparam)
1843 {
1844 struct mlx5e_priv *priv = netdev_priv(netdev);
1845 struct mlx5_core_dev *mdev = priv->mdev;
1846 u16 fec_configured;
1847 u32 fec_active;
1848 int err;
1849
1850 err = mlx5e_get_fec_mode(mdev, &fec_active, &fec_configured);
1851
1852 if (err)
1853 return err;
1854
1855 fecparam->active_fec = pplm2ethtool_fec((unsigned long)fec_active,
1856 sizeof(unsigned long) * BITS_PER_BYTE);
1857
1858 if (!fecparam->active_fec)
1859 return -EOPNOTSUPP;
1860
1861 fecparam->fec = pplm2ethtool_fec((unsigned long)fec_configured,
1862 sizeof(unsigned long) * BITS_PER_BYTE);
1863
1864 return 0;
1865 }
1866
mlx5e_set_fecparam(struct net_device * netdev,struct ethtool_fecparam * fecparam)1867 static int mlx5e_set_fecparam(struct net_device *netdev,
1868 struct ethtool_fecparam *fecparam)
1869 {
1870 struct mlx5e_priv *priv = netdev_priv(netdev);
1871 struct mlx5_core_dev *mdev = priv->mdev;
1872 unsigned long fec_bitmap;
1873 u16 fec_policy = 0;
1874 int mode;
1875 int err;
1876
1877 bitmap_from_arr32(&fec_bitmap, &fecparam->fec, sizeof(fecparam->fec) * BITS_PER_BYTE);
1878 if (bitmap_weight(&fec_bitmap, ETHTOOL_FEC_LLRS_BIT + 1) > 1)
1879 return -EOPNOTSUPP;
1880
1881 for (mode = 0; mode < ARRAY_SIZE(pplm_fec_2_ethtool); mode++) {
1882 if (!(pplm_fec_2_ethtool[mode] & fecparam->fec))
1883 continue;
1884 fec_policy |= (1 << mode);
1885 break;
1886 }
1887
1888 err = mlx5e_set_fec_mode(mdev, fec_policy);
1889
1890 if (err)
1891 return err;
1892
1893 mlx5_toggle_port_link(mdev);
1894
1895 return 0;
1896 }
1897
mlx5e_set_phys_id(struct net_device * dev,enum ethtool_phys_id_state state)1898 static int mlx5e_set_phys_id(struct net_device *dev,
1899 enum ethtool_phys_id_state state)
1900 {
1901 struct mlx5e_priv *priv = netdev_priv(dev);
1902 struct mlx5_core_dev *mdev = priv->mdev;
1903 u16 beacon_duration;
1904
1905 if (!MLX5_CAP_GEN(mdev, beacon_led))
1906 return -EOPNOTSUPP;
1907
1908 switch (state) {
1909 case ETHTOOL_ID_ACTIVE:
1910 beacon_duration = MLX5_BEACON_DURATION_INF;
1911 break;
1912 case ETHTOOL_ID_INACTIVE:
1913 beacon_duration = MLX5_BEACON_DURATION_OFF;
1914 break;
1915 default:
1916 return -EOPNOTSUPP;
1917 }
1918
1919 return mlx5_set_port_beacon(mdev, beacon_duration);
1920 }
1921
mlx5e_get_module_info(struct net_device * netdev,struct ethtool_modinfo * modinfo)1922 static int mlx5e_get_module_info(struct net_device *netdev,
1923 struct ethtool_modinfo *modinfo)
1924 {
1925 struct mlx5e_priv *priv = netdev_priv(netdev);
1926 struct mlx5_core_dev *dev = priv->mdev;
1927 int size_read = 0;
1928 u8 data[4] = {0};
1929
1930 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1931 if (size_read < 2)
1932 return -EIO;
1933
1934 /* data[0] = identifier byte */
1935 switch (data[0]) {
1936 case MLX5_MODULE_ID_QSFP:
1937 modinfo->type = ETH_MODULE_SFF_8436;
1938 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
1939 break;
1940 case MLX5_MODULE_ID_QSFP_PLUS:
1941 case MLX5_MODULE_ID_QSFP28:
1942 /* data[1] = revision id */
1943 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1944 modinfo->type = ETH_MODULE_SFF_8636;
1945 modinfo->eeprom_len = ETH_MODULE_SFF_8636_MAX_LEN;
1946 } else {
1947 modinfo->type = ETH_MODULE_SFF_8436;
1948 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
1949 }
1950 break;
1951 case MLX5_MODULE_ID_SFP:
1952 modinfo->type = ETH_MODULE_SFF_8472;
1953 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1954 break;
1955 default:
1956 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1957 __func__, data[0]);
1958 return -EINVAL;
1959 }
1960
1961 return 0;
1962 }
1963
mlx5e_get_module_eeprom(struct net_device * netdev,struct ethtool_eeprom * ee,u8 * data)1964 static int mlx5e_get_module_eeprom(struct net_device *netdev,
1965 struct ethtool_eeprom *ee,
1966 u8 *data)
1967 {
1968 struct mlx5e_priv *priv = netdev_priv(netdev);
1969 struct mlx5_core_dev *mdev = priv->mdev;
1970 int offset = ee->offset;
1971 int size_read;
1972 int i = 0;
1973
1974 if (!ee->len)
1975 return -EINVAL;
1976
1977 memset(data, 0, ee->len);
1978
1979 while (i < ee->len) {
1980 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1981 data + i);
1982
1983 if (!size_read)
1984 /* Done reading */
1985 return 0;
1986
1987 if (size_read < 0) {
1988 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1989 __func__, size_read);
1990 return size_read;
1991 }
1992
1993 i += size_read;
1994 offset += size_read;
1995 }
1996
1997 return 0;
1998 }
1999
mlx5e_get_module_eeprom_by_page(struct net_device * netdev,const struct ethtool_module_eeprom * page_data,struct netlink_ext_ack * extack)2000 static int mlx5e_get_module_eeprom_by_page(struct net_device *netdev,
2001 const struct ethtool_module_eeprom *page_data,
2002 struct netlink_ext_ack *extack)
2003 {
2004 struct mlx5e_priv *priv = netdev_priv(netdev);
2005 struct mlx5_module_eeprom_query_params query;
2006 struct mlx5_core_dev *mdev = priv->mdev;
2007 u8 *data = page_data->data;
2008 int size_read;
2009 int i = 0;
2010
2011 if (!page_data->length)
2012 return -EINVAL;
2013
2014 memset(data, 0, page_data->length);
2015
2016 query.offset = page_data->offset;
2017 query.i2c_address = page_data->i2c_address;
2018 query.bank = page_data->bank;
2019 query.page = page_data->page;
2020 while (i < page_data->length) {
2021 query.size = page_data->length - i;
2022 size_read = mlx5_query_module_eeprom_by_page(mdev, &query, data + i);
2023
2024 /* Done reading, return how many bytes was read */
2025 if (!size_read)
2026 return i;
2027
2028 if (size_read == -EINVAL)
2029 return -EINVAL;
2030 if (size_read < 0) {
2031 NL_SET_ERR_MSG_FMT_MOD(
2032 extack,
2033 "Query module eeprom by page failed, read %u bytes, err %d",
2034 i, size_read);
2035 return i;
2036 }
2037
2038 i += size_read;
2039 query.offset += size_read;
2040 }
2041
2042 return i;
2043 }
2044
mlx5e_ethtool_flash_device(struct mlx5e_priv * priv,struct ethtool_flash * flash)2045 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
2046 struct ethtool_flash *flash)
2047 {
2048 struct mlx5_core_dev *mdev = priv->mdev;
2049 struct net_device *dev = priv->netdev;
2050 const struct firmware *fw;
2051 int err;
2052
2053 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
2054 return -EOPNOTSUPP;
2055
2056 err = request_firmware_direct(&fw, flash->data, &dev->dev);
2057 if (err)
2058 return err;
2059
2060 err = mlx5_firmware_flash(mdev, fw, NULL);
2061 release_firmware(fw);
2062
2063 return err;
2064 }
2065
mlx5e_flash_device(struct net_device * dev,struct ethtool_flash * flash)2066 static int mlx5e_flash_device(struct net_device *dev,
2067 struct ethtool_flash *flash)
2068 {
2069 struct mlx5e_priv *priv = netdev_priv(dev);
2070
2071 return mlx5e_ethtool_flash_device(priv, flash);
2072 }
2073
set_pflag_cqe_based_moder(struct net_device * netdev,bool enable,bool is_rx_cq)2074 static int set_pflag_cqe_based_moder(struct net_device *netdev, bool enable,
2075 bool is_rx_cq)
2076 {
2077 struct mlx5e_priv *priv = netdev_priv(netdev);
2078 u8 cq_period_mode, current_cq_period_mode;
2079 struct mlx5e_params new_params;
2080
2081 if (enable && !MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2082 return -EOPNOTSUPP;
2083
2084 cq_period_mode = mlx5e_dim_cq_period_mode(enable);
2085
2086 current_cq_period_mode = is_rx_cq ?
2087 priv->channels.params.rx_cq_moderation.cq_period_mode :
2088 priv->channels.params.tx_cq_moderation.cq_period_mode;
2089
2090 if (cq_period_mode == current_cq_period_mode)
2091 return 0;
2092
2093 new_params = priv->channels.params;
2094 if (is_rx_cq) {
2095 mlx5e_reset_rx_channels_moderation(&priv->channels, cq_period_mode,
2096 false, true);
2097 mlx5e_channels_rx_toggle_dim(&priv->channels);
2098 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
2099 cq_period_mode);
2100 } else {
2101 mlx5e_reset_tx_channels_moderation(&priv->channels, cq_period_mode,
2102 false, true);
2103 mlx5e_channels_tx_toggle_dim(&priv->channels);
2104 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
2105 cq_period_mode);
2106 }
2107
2108 /* Update pflags of existing channels without resetting them */
2109 return mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, false);
2110 }
2111
set_pflag_tx_cqe_based_moder(struct net_device * netdev,bool enable)2112 static int set_pflag_tx_cqe_based_moder(struct net_device *netdev, bool enable)
2113 {
2114 return set_pflag_cqe_based_moder(netdev, enable, false);
2115 }
2116
set_pflag_rx_cqe_based_moder(struct net_device * netdev,bool enable)2117 static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
2118 {
2119 return set_pflag_cqe_based_moder(netdev, enable, true);
2120 }
2121
mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv * priv,bool new_val,bool rx_filter)2122 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val, bool rx_filter)
2123 {
2124 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS);
2125 struct mlx5e_params new_params;
2126 int err = 0;
2127
2128 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
2129 return new_val ? -EOPNOTSUPP : 0;
2130
2131 if (curr_val == new_val)
2132 return 0;
2133
2134 if (new_val && !mlx5e_profile_feature_cap(priv->profile, PTP_RX) && rx_filter) {
2135 netdev_err(priv->netdev,
2136 "Profile doesn't support enabling of CQE compression while hardware time-stamping is enabled.\n");
2137 return -EINVAL;
2138 }
2139
2140 if (priv->channels.params.packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) {
2141 netdev_warn(priv->netdev, "Can't set CQE compression with HW-GRO, disable it first.\n");
2142 return -EINVAL;
2143 }
2144
2145 new_params = priv->channels.params;
2146 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val);
2147 if (rx_filter)
2148 new_params.ptp_rx = new_val;
2149
2150 if (new_params.ptp_rx == priv->channels.params.ptp_rx)
2151 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true);
2152 else
2153 err = mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx,
2154 &new_params.ptp_rx, true);
2155 if (err)
2156 return err;
2157
2158 netdev_dbg(priv->netdev, "MLX5E: RxCqeCmprss was turned %s\n",
2159 MLX5E_GET_PFLAG(&priv->channels.params,
2160 MLX5E_PFLAG_RX_CQE_COMPRESS) ? "ON" : "OFF");
2161
2162 return 0;
2163 }
2164
set_pflag_rx_cqe_compress(struct net_device * netdev,bool enable)2165 static int set_pflag_rx_cqe_compress(struct net_device *netdev,
2166 bool enable)
2167 {
2168 struct mlx5e_priv *priv = netdev_priv(netdev);
2169 struct mlx5_core_dev *mdev = priv->mdev;
2170 bool rx_filter;
2171 int err;
2172
2173 if (!MLX5_CAP_GEN(mdev, cqe_compression))
2174 return -EOPNOTSUPP;
2175
2176 rx_filter = priv->tstamp.rx_filter != HWTSTAMP_FILTER_NONE;
2177 err = mlx5e_modify_rx_cqe_compression_locked(priv, enable, rx_filter);
2178 if (err)
2179 return err;
2180
2181 priv->channels.params.rx_cqe_compress_def = enable;
2182
2183 return 0;
2184 }
2185
set_pflag_rx_striding_rq(struct net_device * netdev,bool enable)2186 static int set_pflag_rx_striding_rq(struct net_device *netdev, bool enable)
2187 {
2188 struct mlx5e_priv *priv = netdev_priv(netdev);
2189 struct mlx5_core_dev *mdev = priv->mdev;
2190 struct mlx5e_params new_params;
2191 int err;
2192
2193 if (enable) {
2194 /* Checking the regular RQ here; mlx5e_validate_xsk_param called
2195 * from mlx5e_open_xsk will check for each XSK queue, and
2196 * mlx5e_safe_switch_params will be reverted if any check fails.
2197 */
2198 int err = mlx5e_mpwrq_validate_regular(mdev, &priv->channels.params);
2199
2200 if (err)
2201 return err;
2202 } else if (priv->channels.params.packet_merge.type != MLX5E_PACKET_MERGE_NONE) {
2203 netdev_warn(netdev, "Can't set legacy RQ with HW-GRO/LRO, disable them first\n");
2204 return -EINVAL;
2205 }
2206
2207 new_params = priv->channels.params;
2208
2209 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_RX_STRIDING_RQ, enable);
2210 mlx5e_set_rq_type(mdev, &new_params);
2211
2212 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true);
2213 if (err)
2214 return err;
2215
2216 /* update XDP supported features */
2217 mlx5e_set_xdp_feature(netdev);
2218
2219 return 0;
2220 }
2221
set_pflag_rx_no_csum_complete(struct net_device * netdev,bool enable)2222 static int set_pflag_rx_no_csum_complete(struct net_device *netdev, bool enable)
2223 {
2224 struct mlx5e_priv *priv = netdev_priv(netdev);
2225 struct mlx5e_channels *channels = &priv->channels;
2226 struct mlx5e_channel *c;
2227 int i;
2228
2229 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) ||
2230 priv->channels.params.xdp_prog)
2231 return 0;
2232
2233 for (i = 0; i < channels->num; i++) {
2234 c = channels->c[i];
2235 if (enable)
2236 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
2237 else
2238 __clear_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
2239 }
2240
2241 return 0;
2242 }
2243
set_pflag_tx_mpwqe_common(struct net_device * netdev,u32 flag,bool enable)2244 static int set_pflag_tx_mpwqe_common(struct net_device *netdev, u32 flag, bool enable)
2245 {
2246 struct mlx5e_priv *priv = netdev_priv(netdev);
2247 struct mlx5_core_dev *mdev = priv->mdev;
2248 struct mlx5e_params new_params;
2249
2250 if (enable && !mlx5e_tx_mpwqe_supported(mdev))
2251 return -EOPNOTSUPP;
2252
2253 new_params = priv->channels.params;
2254
2255 MLX5E_SET_PFLAG(&new_params, flag, enable);
2256
2257 return mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true);
2258 }
2259
set_pflag_xdp_tx_mpwqe(struct net_device * netdev,bool enable)2260 static int set_pflag_xdp_tx_mpwqe(struct net_device *netdev, bool enable)
2261 {
2262 return set_pflag_tx_mpwqe_common(netdev, MLX5E_PFLAG_XDP_TX_MPWQE, enable);
2263 }
2264
set_pflag_skb_tx_mpwqe(struct net_device * netdev,bool enable)2265 static int set_pflag_skb_tx_mpwqe(struct net_device *netdev, bool enable)
2266 {
2267 return set_pflag_tx_mpwqe_common(netdev, MLX5E_PFLAG_SKB_TX_MPWQE, enable);
2268 }
2269
set_pflag_tx_port_ts(struct net_device * netdev,bool enable)2270 static int set_pflag_tx_port_ts(struct net_device *netdev, bool enable)
2271 {
2272 struct mlx5e_priv *priv = netdev_priv(netdev);
2273 struct mlx5_core_dev *mdev = priv->mdev;
2274 struct mlx5e_params new_params;
2275 int err;
2276
2277 if (!MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn) ||
2278 !MLX5_CAP_GEN_2(mdev, ts_cqe_metadata_size2wqe_counter))
2279 return -EOPNOTSUPP;
2280
2281 /* Don't allow changing the PTP state if HTB offload is active, because
2282 * the numeration of the QoS SQs will change, while per-queue qdiscs are
2283 * attached.
2284 */
2285 if (mlx5e_selq_is_htb_enabled(&priv->selq)) {
2286 netdev_err(priv->netdev, "%s: HTB offload is active, cannot change the PTP state\n",
2287 __func__);
2288 return -EINVAL;
2289 }
2290
2291 new_params = priv->channels.params;
2292 /* Don't allow enabling TX-port-TS if MQPRIO mode channel offload is
2293 * active, since it defines explicitly which TC accepts the packet.
2294 * This conflicts with TX-port-TS hijacking the PTP traffic to a specific
2295 * HW TX-queue.
2296 */
2297 if (enable && new_params.mqprio.mode == TC_MQPRIO_MODE_CHANNEL) {
2298 netdev_err(priv->netdev,
2299 "%s: MQPRIO mode channel offload is active, cannot set the TX-port-TS\n",
2300 __func__);
2301 return -EINVAL;
2302 }
2303 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_TX_PORT_TS, enable);
2304 /* No need to verify SQ stop room as
2305 * ptpsq.txqsq.stop_room <= generic_sq->stop_room, and both
2306 * has the same log_sq_size.
2307 */
2308
2309 err = mlx5e_safe_switch_params(priv, &new_params,
2310 mlx5e_update_tc_and_tx_queues_ctx, NULL, true);
2311 if (!err)
2312 priv->tx_ptp_opened = true;
2313
2314 return err;
2315 }
2316
2317 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS] = {
2318 { "rx_cqe_moder", set_pflag_rx_cqe_based_moder },
2319 { "tx_cqe_moder", set_pflag_tx_cqe_based_moder },
2320 { "rx_cqe_compress", set_pflag_rx_cqe_compress },
2321 { "rx_striding_rq", set_pflag_rx_striding_rq },
2322 { "rx_no_csum_complete", set_pflag_rx_no_csum_complete },
2323 { "xdp_tx_mpwqe", set_pflag_xdp_tx_mpwqe },
2324 { "skb_tx_mpwqe", set_pflag_skb_tx_mpwqe },
2325 { "tx_port_ts", set_pflag_tx_port_ts },
2326 };
2327
mlx5e_handle_pflag(struct net_device * netdev,u32 wanted_flags,enum mlx5e_priv_flag flag)2328 static int mlx5e_handle_pflag(struct net_device *netdev,
2329 u32 wanted_flags,
2330 enum mlx5e_priv_flag flag)
2331 {
2332 struct mlx5e_priv *priv = netdev_priv(netdev);
2333 bool enable = !!(wanted_flags & BIT(flag));
2334 u32 changes = wanted_flags ^ priv->channels.params.pflags;
2335 int err;
2336
2337 if (!(changes & BIT(flag)))
2338 return 0;
2339
2340 err = mlx5e_priv_flags[flag].handler(netdev, enable);
2341 if (err) {
2342 netdev_err(netdev, "%s private flag '%s' failed err %d\n",
2343 enable ? "Enable" : "Disable", mlx5e_priv_flags[flag].name, err);
2344 return err;
2345 }
2346
2347 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable);
2348 return 0;
2349 }
2350
mlx5e_set_priv_flags(struct net_device * netdev,u32 pflags)2351 static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
2352 {
2353 struct mlx5e_priv *priv = netdev_priv(netdev);
2354 enum mlx5e_priv_flag pflag;
2355 int err;
2356
2357 mutex_lock(&priv->state_lock);
2358
2359 for (pflag = 0; pflag < MLX5E_NUM_PFLAGS; pflag++) {
2360 err = mlx5e_handle_pflag(netdev, pflags, pflag);
2361 if (err)
2362 break;
2363 }
2364
2365 mutex_unlock(&priv->state_lock);
2366
2367 /* Need to fix some features.. */
2368 netdev_update_features(netdev);
2369
2370 return err;
2371 }
2372
mlx5e_get_priv_flags(struct net_device * netdev)2373 static u32 mlx5e_get_priv_flags(struct net_device *netdev)
2374 {
2375 struct mlx5e_priv *priv = netdev_priv(netdev);
2376
2377 return priv->channels.params.pflags;
2378 }
2379
mlx5e_get_rxnfc(struct net_device * dev,struct ethtool_rxnfc * info,u32 * rule_locs)2380 static int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2381 u32 *rule_locs)
2382 {
2383 struct mlx5e_priv *priv = netdev_priv(dev);
2384
2385 /* ETHTOOL_GRXRINGS is needed by ethtool -x which is not part
2386 * of rxnfc. We keep this logic out of mlx5e_ethtool_get_rxnfc,
2387 * to avoid breaking "ethtool -x" when mlx5e_ethtool_get_rxnfc
2388 * is compiled out via CONFIG_MLX5_EN_RXNFC=n.
2389 */
2390 if (info->cmd == ETHTOOL_GRXRINGS) {
2391 info->data = priv->channels.params.num_channels;
2392 return 0;
2393 }
2394
2395 return mlx5e_ethtool_get_rxnfc(priv, info, rule_locs);
2396 }
2397
mlx5e_set_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd)2398 static int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2399 {
2400 struct mlx5e_priv *priv = netdev_priv(dev);
2401
2402 return mlx5e_ethtool_set_rxnfc(priv, cmd);
2403 }
2404
query_port_status_opcode(struct mlx5_core_dev * mdev,u32 * status_opcode)2405 static int query_port_status_opcode(struct mlx5_core_dev *mdev, u32 *status_opcode)
2406 {
2407 struct mlx5_ifc_pddr_troubleshooting_page_bits *pddr_troubleshooting_page;
2408 u32 in[MLX5_ST_SZ_DW(pddr_reg)] = {};
2409 u32 out[MLX5_ST_SZ_DW(pddr_reg)];
2410 int err;
2411
2412 MLX5_SET(pddr_reg, in, local_port, 1);
2413 MLX5_SET(pddr_reg, in, page_select,
2414 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE);
2415
2416 pddr_troubleshooting_page = MLX5_ADDR_OF(pddr_reg, in, page_data);
2417 MLX5_SET(pddr_troubleshooting_page, pddr_troubleshooting_page,
2418 group_opcode, MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR);
2419 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
2420 sizeof(out), MLX5_REG_PDDR, 0, 0);
2421 if (err)
2422 return err;
2423
2424 pddr_troubleshooting_page = MLX5_ADDR_OF(pddr_reg, out, page_data);
2425 *status_opcode = MLX5_GET(pddr_troubleshooting_page, pddr_troubleshooting_page,
2426 status_opcode);
2427 return 0;
2428 }
2429
2430 struct mlx5e_ethtool_link_ext_state_opcode_mapping {
2431 u32 status_opcode;
2432 enum ethtool_link_ext_state link_ext_state;
2433 u8 link_ext_substate;
2434 };
2435
2436 static const struct mlx5e_ethtool_link_ext_state_opcode_mapping
2437 mlx5e_link_ext_state_opcode_map[] = {
2438 /* States relating to the autonegotiation or issues therein */
2439 {2, ETHTOOL_LINK_EXT_STATE_AUTONEG,
2440 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED},
2441 {3, ETHTOOL_LINK_EXT_STATE_AUTONEG,
2442 ETHTOOL_LINK_EXT_SUBSTATE_AN_ACK_NOT_RECEIVED},
2443 {4, ETHTOOL_LINK_EXT_STATE_AUTONEG,
2444 ETHTOOL_LINK_EXT_SUBSTATE_AN_NEXT_PAGE_EXCHANGE_FAILED},
2445 {36, ETHTOOL_LINK_EXT_STATE_AUTONEG,
2446 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED_FORCE_MODE},
2447 {38, ETHTOOL_LINK_EXT_STATE_AUTONEG,
2448 ETHTOOL_LINK_EXT_SUBSTATE_AN_FEC_MISMATCH_DURING_OVERRIDE},
2449 {39, ETHTOOL_LINK_EXT_STATE_AUTONEG,
2450 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_HCD},
2451
2452 /* Failure during link training */
2453 {5, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE,
2454 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_FRAME_LOCK_NOT_ACQUIRED},
2455 {6, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE,
2456 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_INHIBIT_TIMEOUT},
2457 {7, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE,
2458 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_PARTNER_DID_NOT_SET_RECEIVER_READY},
2459 {8, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE, 0},
2460 {14, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE,
2461 ETHTOOL_LINK_EXT_SUBSTATE_LT_REMOTE_FAULT},
2462
2463 /* Logical mismatch in physical coding sublayer or forward error correction sublayer */
2464 {9, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
2465 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_BLOCK_LOCK},
2466 {10, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
2467 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_AM_LOCK},
2468 {11, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
2469 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_GET_ALIGN_STATUS},
2470 {12, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
2471 ETHTOOL_LINK_EXT_SUBSTATE_LLM_FC_FEC_IS_NOT_LOCKED},
2472 {13, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
2473 ETHTOOL_LINK_EXT_SUBSTATE_LLM_RS_FEC_IS_NOT_LOCKED},
2474
2475 /* Signal integrity issues */
2476 {15, ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY, 0},
2477 {17, ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY,
2478 ETHTOOL_LINK_EXT_SUBSTATE_BSI_LARGE_NUMBER_OF_PHYSICAL_ERRORS},
2479 {42, ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY,
2480 ETHTOOL_LINK_EXT_SUBSTATE_BSI_UNSUPPORTED_RATE},
2481
2482 /* No cable connected */
2483 {1024, ETHTOOL_LINK_EXT_STATE_NO_CABLE, 0},
2484
2485 /* Failure is related to cable, e.g., unsupported cable */
2486 {16, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
2487 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
2488 {20, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
2489 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
2490 {29, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
2491 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
2492 {1025, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
2493 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
2494 {1029, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
2495 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
2496 {1031, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE, 0},
2497
2498 /* Failure is related to EEPROM, e.g., failure during reading or parsing the data */
2499 {1027, ETHTOOL_LINK_EXT_STATE_EEPROM_ISSUE, 0},
2500
2501 /* Failure during calibration algorithm */
2502 {23, ETHTOOL_LINK_EXT_STATE_CALIBRATION_FAILURE, 0},
2503
2504 /* The hardware is not able to provide the power required from cable or module */
2505 {1032, ETHTOOL_LINK_EXT_STATE_POWER_BUDGET_EXCEEDED, 0},
2506
2507 /* The module is overheated */
2508 {1030, ETHTOOL_LINK_EXT_STATE_OVERHEAT, 0},
2509 };
2510
2511 static void
mlx5e_set_link_ext_state(struct mlx5e_ethtool_link_ext_state_opcode_mapping link_ext_state_mapping,struct ethtool_link_ext_state_info * link_ext_state_info)2512 mlx5e_set_link_ext_state(struct mlx5e_ethtool_link_ext_state_opcode_mapping
2513 link_ext_state_mapping,
2514 struct ethtool_link_ext_state_info *link_ext_state_info)
2515 {
2516 switch (link_ext_state_mapping.link_ext_state) {
2517 case ETHTOOL_LINK_EXT_STATE_AUTONEG:
2518 link_ext_state_info->autoneg =
2519 link_ext_state_mapping.link_ext_substate;
2520 break;
2521 case ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE:
2522 link_ext_state_info->link_training =
2523 link_ext_state_mapping.link_ext_substate;
2524 break;
2525 case ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH:
2526 link_ext_state_info->link_logical_mismatch =
2527 link_ext_state_mapping.link_ext_substate;
2528 break;
2529 case ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY:
2530 link_ext_state_info->bad_signal_integrity =
2531 link_ext_state_mapping.link_ext_substate;
2532 break;
2533 case ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE:
2534 link_ext_state_info->cable_issue =
2535 link_ext_state_mapping.link_ext_substate;
2536 break;
2537 default:
2538 break;
2539 }
2540
2541 link_ext_state_info->link_ext_state = link_ext_state_mapping.link_ext_state;
2542 }
2543
2544 static int
mlx5e_get_link_ext_state(struct net_device * dev,struct ethtool_link_ext_state_info * link_ext_state_info)2545 mlx5e_get_link_ext_state(struct net_device *dev,
2546 struct ethtool_link_ext_state_info *link_ext_state_info)
2547 {
2548 struct mlx5e_ethtool_link_ext_state_opcode_mapping link_ext_state_mapping;
2549 struct mlx5e_priv *priv = netdev_priv(dev);
2550 u32 status_opcode = 0;
2551 int i;
2552
2553 /* Exit without data if the interface state is OK, since no extended data is
2554 * available in such case
2555 */
2556 if (netif_carrier_ok(dev))
2557 return -ENODATA;
2558
2559 if (query_port_status_opcode(priv->mdev, &status_opcode) ||
2560 !status_opcode)
2561 return -ENODATA;
2562
2563 for (i = 0; i < ARRAY_SIZE(mlx5e_link_ext_state_opcode_map); i++) {
2564 link_ext_state_mapping = mlx5e_link_ext_state_opcode_map[i];
2565 if (link_ext_state_mapping.status_opcode == status_opcode) {
2566 mlx5e_set_link_ext_state(link_ext_state_mapping,
2567 link_ext_state_info);
2568 return 0;
2569 }
2570 }
2571
2572 return -ENODATA;
2573 }
2574
mlx5e_get_eth_phy_stats(struct net_device * netdev,struct ethtool_eth_phy_stats * phy_stats)2575 static void mlx5e_get_eth_phy_stats(struct net_device *netdev,
2576 struct ethtool_eth_phy_stats *phy_stats)
2577 {
2578 struct mlx5e_priv *priv = netdev_priv(netdev);
2579
2580 mlx5e_stats_eth_phy_get(priv, phy_stats);
2581 }
2582
mlx5e_get_eth_mac_stats(struct net_device * netdev,struct ethtool_eth_mac_stats * mac_stats)2583 static void mlx5e_get_eth_mac_stats(struct net_device *netdev,
2584 struct ethtool_eth_mac_stats *mac_stats)
2585 {
2586 struct mlx5e_priv *priv = netdev_priv(netdev);
2587
2588 mlx5e_stats_eth_mac_get(priv, mac_stats);
2589 }
2590
mlx5e_get_eth_ctrl_stats(struct net_device * netdev,struct ethtool_eth_ctrl_stats * ctrl_stats)2591 static void mlx5e_get_eth_ctrl_stats(struct net_device *netdev,
2592 struct ethtool_eth_ctrl_stats *ctrl_stats)
2593 {
2594 struct mlx5e_priv *priv = netdev_priv(netdev);
2595
2596 mlx5e_stats_eth_ctrl_get(priv, ctrl_stats);
2597 }
2598
mlx5e_get_rmon_stats(struct net_device * netdev,struct ethtool_rmon_stats * rmon_stats,const struct ethtool_rmon_hist_range ** ranges)2599 static void mlx5e_get_rmon_stats(struct net_device *netdev,
2600 struct ethtool_rmon_stats *rmon_stats,
2601 const struct ethtool_rmon_hist_range **ranges)
2602 {
2603 struct mlx5e_priv *priv = netdev_priv(netdev);
2604
2605 mlx5e_stats_rmon_get(priv, rmon_stats, ranges);
2606 }
2607
mlx5e_get_ts_stats(struct net_device * netdev,struct ethtool_ts_stats * ts_stats)2608 static void mlx5e_get_ts_stats(struct net_device *netdev,
2609 struct ethtool_ts_stats *ts_stats)
2610 {
2611 struct mlx5e_priv *priv = netdev_priv(netdev);
2612
2613 mlx5e_stats_ts_get(priv, ts_stats);
2614 }
2615
2616 const struct ethtool_ops mlx5e_ethtool_ops = {
2617 .cap_link_lanes_supported = true,
2618 .cap_rss_ctx_supported = true,
2619 .rxfh_per_ctx_key = true,
2620 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
2621 ETHTOOL_COALESCE_MAX_FRAMES |
2622 ETHTOOL_COALESCE_USE_ADAPTIVE |
2623 ETHTOOL_COALESCE_USE_CQE,
2624 .supported_input_xfrm = RXH_XFRM_SYM_OR_XOR,
2625 .get_drvinfo = mlx5e_get_drvinfo,
2626 .get_link = ethtool_op_get_link,
2627 .get_link_ext_state = mlx5e_get_link_ext_state,
2628 .get_strings = mlx5e_get_strings,
2629 .get_sset_count = mlx5e_get_sset_count,
2630 .get_ethtool_stats = mlx5e_get_ethtool_stats,
2631 .get_ringparam = mlx5e_get_ringparam,
2632 .set_ringparam = mlx5e_set_ringparam,
2633 .get_channels = mlx5e_get_channels,
2634 .set_channels = mlx5e_set_channels,
2635 .get_coalesce = mlx5e_get_coalesce,
2636 .set_coalesce = mlx5e_set_coalesce,
2637 .get_per_queue_coalesce = mlx5e_get_per_queue_coalesce,
2638 .set_per_queue_coalesce = mlx5e_set_per_queue_coalesce,
2639 .get_link_ksettings = mlx5e_get_link_ksettings,
2640 .set_link_ksettings = mlx5e_set_link_ksettings,
2641 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
2642 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
2643 .get_rxfh = mlx5e_get_rxfh,
2644 .set_rxfh = mlx5e_set_rxfh,
2645 .get_rxnfc = mlx5e_get_rxnfc,
2646 .set_rxnfc = mlx5e_set_rxnfc,
2647 .get_tunable = mlx5e_get_tunable,
2648 .set_tunable = mlx5e_set_tunable,
2649 .get_pause_stats = mlx5e_get_pause_stats,
2650 .get_pauseparam = mlx5e_get_pauseparam,
2651 .set_pauseparam = mlx5e_set_pauseparam,
2652 .get_ts_info = mlx5e_get_ts_info,
2653 .set_phys_id = mlx5e_set_phys_id,
2654 .get_wol = mlx5e_get_wol,
2655 .set_wol = mlx5e_set_wol,
2656 .get_module_info = mlx5e_get_module_info,
2657 .get_module_eeprom = mlx5e_get_module_eeprom,
2658 .get_module_eeprom_by_page = mlx5e_get_module_eeprom_by_page,
2659 .flash_device = mlx5e_flash_device,
2660 .get_priv_flags = mlx5e_get_priv_flags,
2661 .set_priv_flags = mlx5e_set_priv_flags,
2662 .self_test = mlx5e_self_test,
2663 .get_fec_stats = mlx5e_get_fec_stats,
2664 .get_fecparam = mlx5e_get_fecparam,
2665 .set_fecparam = mlx5e_set_fecparam,
2666 .get_eth_phy_stats = mlx5e_get_eth_phy_stats,
2667 .get_eth_mac_stats = mlx5e_get_eth_mac_stats,
2668 .get_eth_ctrl_stats = mlx5e_get_eth_ctrl_stats,
2669 .get_rmon_stats = mlx5e_get_rmon_stats,
2670 .get_ts_stats = mlx5e_get_ts_stats,
2671 .get_link_ext_stats = mlx5e_get_link_ext_stats
2672 };
2673