1 /* 2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/dim.h> 34 #include <linux/ethtool_netlink.h> 35 #include <net/netdev_queues.h> 36 37 #include "en.h" 38 #include "en/channels.h" 39 #include "en/dim.h" 40 #include "en/port.h" 41 #include "en/params.h" 42 #include "en/ptp.h" 43 #include "lib/clock.h" 44 #include "en/fs_ethtool.h" 45 46 #define LANES_UNKNOWN 0 47 48 #define MLX5E_MAX_INDIR_RQT_SIZE \ 49 roundup_pow_of_two(MLX5E_MAX_NUM_CHANNELS * \ 50 MLX5E_UNIFORM_SPREAD_RQT_FACTOR) 51 52 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv, 53 struct ethtool_drvinfo *drvinfo) 54 { 55 struct mlx5_core_dev *mdev = priv->mdev; 56 int count; 57 58 strscpy(drvinfo->driver, KBUILD_MODNAME, sizeof(drvinfo->driver)); 59 count = snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), 60 "%d.%d.%04d (%.16s)", fw_rev_maj(mdev), 61 fw_rev_min(mdev), fw_rev_sub(mdev), mdev->board_id); 62 if (count >= sizeof(drvinfo->fw_version)) 63 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), 64 "%d.%d.%04d", fw_rev_maj(mdev), 65 fw_rev_min(mdev), fw_rev_sub(mdev)); 66 67 strscpy(drvinfo->bus_info, dev_name(mdev->device), 68 sizeof(drvinfo->bus_info)); 69 } 70 71 static void mlx5e_get_drvinfo(struct net_device *dev, 72 struct ethtool_drvinfo *drvinfo) 73 { 74 struct mlx5e_priv *priv = netdev_priv(dev); 75 76 mlx5e_ethtool_get_drvinfo(priv, drvinfo); 77 } 78 79 struct ptys2ethtool_config { 80 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); 81 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised); 82 }; 83 84 static 85 struct ptys2ethtool_config ptys2legacy_ethtool_table[MLX5E_LINK_MODES_NUMBER]; 86 static 87 struct ptys2ethtool_config ptys2ext_ethtool_table[MLX5E_EXT_LINK_MODES_NUMBER]; 88 89 #define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, table, ...) \ 90 ({ \ 91 struct ptys2ethtool_config *cfg; \ 92 const unsigned int modes[] = { __VA_ARGS__ }; \ 93 unsigned int i; \ 94 cfg = &ptys2##table##_ethtool_table[reg_]; \ 95 bitmap_zero(cfg->supported, \ 96 __ETHTOOL_LINK_MODE_MASK_NBITS); \ 97 bitmap_zero(cfg->advertised, \ 98 __ETHTOOL_LINK_MODE_MASK_NBITS); \ 99 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \ 100 bitmap_set(cfg->supported, modes[i], 1); \ 101 bitmap_set(cfg->advertised, modes[i], 1); \ 102 } \ 103 }) 104 105 void mlx5e_build_ptys2ethtool_map(void) 106 { 107 memset(ptys2legacy_ethtool_table, 0, sizeof(ptys2legacy_ethtool_table)); 108 memset(ptys2ext_ethtool_table, 0, sizeof(ptys2ext_ethtool_table)); 109 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, legacy, 110 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT); 111 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, legacy, 112 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT); 113 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, legacy, 114 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT); 115 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, legacy, 116 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT); 117 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, legacy, 118 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); 119 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, legacy, 120 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT); 121 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, legacy, 122 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT); 123 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, legacy, 124 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT); 125 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, legacy, 126 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT); 127 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, legacy, 128 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); 129 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, legacy, 130 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); 131 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, legacy, 132 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); 133 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, legacy, 134 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT); 135 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, legacy, 136 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT); 137 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, legacy, 138 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT); 139 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, legacy, 140 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT); 141 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, legacy, 142 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT); 143 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, legacy, 144 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT); 145 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, legacy, 146 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT); 147 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100BASE_TX, legacy, 148 ETHTOOL_LINK_MODE_100baseT_Full_BIT); 149 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_T, legacy, 150 ETHTOOL_LINK_MODE_1000baseT_Full_BIT); 151 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, legacy, 152 ETHTOOL_LINK_MODE_10000baseT_Full_BIT); 153 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, legacy, 154 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT); 155 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, legacy, 156 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT); 157 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, legacy, 158 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT); 159 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, legacy, 160 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT); 161 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, legacy, 162 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT); 163 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_SGMII_100M, ext, 164 ETHTOOL_LINK_MODE_100baseT_Full_BIT); 165 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_X_SGMII, ext, 166 ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 167 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 168 ETHTOOL_LINK_MODE_1000baseX_Full_BIT); 169 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_5GBASE_R, ext, 170 ETHTOOL_LINK_MODE_5000baseT_Full_BIT); 171 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_XFI_XAUI_1, ext, 172 ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 173 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 174 ETHTOOL_LINK_MODE_10000baseR_FEC_BIT, 175 ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, 176 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 177 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 178 ETHTOOL_LINK_MODE_10000baseER_Full_BIT); 179 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_XLAUI_4_XLPPI_4, ext, 180 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 181 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 182 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 183 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT); 184 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GAUI_1_25GBASE_CR_KR, ext, 185 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 186 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 187 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT); 188 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2, 189 ext, 190 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 191 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 192 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT); 193 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR, ext, 194 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, 195 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, 196 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, 197 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 198 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT); 199 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_CAUI_4_100GBASE_CR4_KR4, ext, 200 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 201 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 202 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 203 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT); 204 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_2_100GBASE_CR2_KR2, ext, 205 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT, 206 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT, 207 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT, 208 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT, 209 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT); 210 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_4_200GBASE_CR4_KR4, ext, 211 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT, 212 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT, 213 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT, 214 ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT, 215 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT); 216 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_8_400GBASE_CR8, ext, 217 ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT, 218 ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT, 219 ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT, 220 ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT, 221 ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT); 222 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_1_100GBASE_CR_KR, ext, 223 ETHTOOL_LINK_MODE_100000baseKR_Full_BIT, 224 ETHTOOL_LINK_MODE_100000baseSR_Full_BIT, 225 ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT, 226 ETHTOOL_LINK_MODE_100000baseDR_Full_BIT, 227 ETHTOOL_LINK_MODE_100000baseCR_Full_BIT); 228 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_2_200GBASE_CR2_KR2, ext, 229 ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT, 230 ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT, 231 ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT, 232 ETHTOOL_LINK_MODE_200000baseDR2_Full_BIT, 233 ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT); 234 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_4_400GBASE_CR4_KR4, ext, 235 ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT, 236 ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT, 237 ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT, 238 ETHTOOL_LINK_MODE_400000baseDR4_Full_BIT, 239 ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT); 240 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_800GAUI_8_800GBASE_CR8_KR8, ext, 241 ETHTOOL_LINK_MODE_800000baseCR8_Full_BIT, 242 ETHTOOL_LINK_MODE_800000baseKR8_Full_BIT, 243 ETHTOOL_LINK_MODE_800000baseDR8_Full_BIT, 244 ETHTOOL_LINK_MODE_800000baseDR8_2_Full_BIT, 245 ETHTOOL_LINK_MODE_800000baseSR8_Full_BIT, 246 ETHTOOL_LINK_MODE_800000baseVR8_Full_BIT); 247 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_1_200GBASE_CR1_KR1, ext, 248 ETHTOOL_LINK_MODE_200000baseCR_Full_BIT, 249 ETHTOOL_LINK_MODE_200000baseKR_Full_BIT, 250 ETHTOOL_LINK_MODE_200000baseDR_Full_BIT, 251 ETHTOOL_LINK_MODE_200000baseDR_2_Full_BIT, 252 ETHTOOL_LINK_MODE_200000baseSR_Full_BIT, 253 ETHTOOL_LINK_MODE_200000baseVR_Full_BIT); 254 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_2_400GBASE_CR2_KR2, ext, 255 ETHTOOL_LINK_MODE_400000baseCR2_Full_BIT, 256 ETHTOOL_LINK_MODE_400000baseKR2_Full_BIT, 257 ETHTOOL_LINK_MODE_400000baseDR2_Full_BIT, 258 ETHTOOL_LINK_MODE_400000baseDR2_2_Full_BIT, 259 ETHTOOL_LINK_MODE_400000baseSR2_Full_BIT, 260 ETHTOOL_LINK_MODE_400000baseVR2_Full_BIT); 261 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_800GAUI_4_800GBASE_CR4_KR4, ext, 262 ETHTOOL_LINK_MODE_800000baseCR4_Full_BIT, 263 ETHTOOL_LINK_MODE_800000baseKR4_Full_BIT, 264 ETHTOOL_LINK_MODE_800000baseDR4_Full_BIT, 265 ETHTOOL_LINK_MODE_800000baseDR4_2_Full_BIT, 266 ETHTOOL_LINK_MODE_800000baseSR4_Full_BIT, 267 ETHTOOL_LINK_MODE_800000baseVR4_Full_BIT); 268 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1600GAUI_8_1600GBASE_CR8_KR8, ext, 269 ETHTOOL_LINK_MODE_1600000baseCR8_Full_BIT, 270 ETHTOOL_LINK_MODE_1600000baseKR8_Full_BIT, 271 ETHTOOL_LINK_MODE_1600000baseDR8_Full_BIT, 272 ETHTOOL_LINK_MODE_1600000baseDR8_2_Full_BIT); 273 } 274 275 static void mlx5e_ethtool_get_speed_arr(bool ext, 276 struct ptys2ethtool_config **arr, 277 u32 *size) 278 { 279 *arr = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table; 280 *size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) : 281 ARRAY_SIZE(ptys2legacy_ethtool_table); 282 } 283 284 typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable); 285 286 struct pflag_desc { 287 char name[ETH_GSTRING_LEN]; 288 mlx5e_pflag_handler handler; 289 }; 290 291 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS]; 292 293 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset) 294 { 295 switch (sset) { 296 case ETH_SS_STATS: 297 return mlx5e_stats_total_num(priv); 298 case ETH_SS_PRIV_FLAGS: 299 return MLX5E_NUM_PFLAGS; 300 case ETH_SS_TEST: 301 return mlx5e_self_test_num(priv); 302 default: 303 return -EOPNOTSUPP; 304 } 305 } 306 307 static int mlx5e_get_sset_count(struct net_device *dev, int sset) 308 { 309 struct mlx5e_priv *priv = netdev_priv(dev); 310 311 return mlx5e_ethtool_get_sset_count(priv, sset); 312 } 313 314 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, u32 stringset, u8 *data) 315 { 316 int i; 317 318 switch (stringset) { 319 case ETH_SS_PRIV_FLAGS: 320 for (i = 0; i < MLX5E_NUM_PFLAGS; i++) 321 ethtool_puts(&data, mlx5e_priv_flags[i].name); 322 break; 323 324 case ETH_SS_TEST: 325 mlx5e_self_test_fill_strings(priv, data); 326 break; 327 328 case ETH_SS_STATS: 329 mlx5e_stats_fill_strings(priv, data); 330 break; 331 } 332 } 333 334 static void mlx5e_get_strings(struct net_device *dev, u32 stringset, u8 *data) 335 { 336 struct mlx5e_priv *priv = netdev_priv(dev); 337 338 mlx5e_ethtool_get_strings(priv, stringset, data); 339 } 340 341 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv, 342 struct ethtool_stats *stats, u64 *data) 343 { 344 int idx = 0; 345 346 mutex_lock(&priv->state_lock); 347 mlx5e_stats_update(priv); 348 mutex_unlock(&priv->state_lock); 349 350 mlx5e_stats_fill(priv, data, idx); 351 } 352 353 static void mlx5e_get_ethtool_stats(struct net_device *dev, 354 struct ethtool_stats *stats, 355 u64 *data) 356 { 357 struct mlx5e_priv *priv = netdev_priv(dev); 358 359 mlx5e_ethtool_get_ethtool_stats(priv, stats, data); 360 } 361 362 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv, 363 struct ethtool_ringparam *param, 364 struct kernel_ethtool_ringparam *kernel_param) 365 { 366 /* Limitation for regular RQ. XSK RQ may clamp the queue length in 367 * mlx5e_mpwqe_get_log_rq_size. 368 */ 369 u8 max_log_mpwrq_pkts = mlx5e_mpwrq_max_log_rq_pkts(priv->mdev, 370 PAGE_SHIFT, 371 MLX5E_MPWRQ_UMR_MODE_ALIGNED); 372 373 param->rx_max_pending = 1 << min_t(u8, MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE, 374 max_log_mpwrq_pkts); 375 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE; 376 param->rx_pending = 1 << priv->channels.params.log_rq_mtu_frames; 377 param->tx_pending = 1 << priv->channels.params.log_sq_size; 378 379 kernel_param->hds_thresh = 0; 380 kernel_param->hds_thresh_max = 0; 381 } 382 383 static void mlx5e_get_ringparam(struct net_device *dev, 384 struct ethtool_ringparam *param, 385 struct kernel_ethtool_ringparam *kernel_param, 386 struct netlink_ext_ack *extack) 387 { 388 struct mlx5e_priv *priv = netdev_priv(dev); 389 390 mlx5e_ethtool_get_ringparam(priv, param, kernel_param); 391 } 392 393 static bool mlx5e_ethtool_set_tcp_data_split(struct mlx5e_priv *priv, 394 u8 tcp_data_split, 395 struct netlink_ext_ack *extack) 396 { 397 struct net_device *dev = priv->netdev; 398 399 if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_ENABLED && 400 !(dev->features & NETIF_F_GRO_HW)) { 401 NL_SET_ERR_MSG_MOD(extack, 402 "TCP-data-split is not supported when GRO HW is disabled"); 403 return false; 404 } 405 406 return true; 407 } 408 409 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv, 410 struct ethtool_ringparam *param, 411 struct netlink_ext_ack *extack) 412 { 413 struct mlx5e_params new_params; 414 u8 log_rq_size; 415 u8 log_sq_size; 416 int err = 0; 417 418 if (param->rx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE)) { 419 NL_SET_ERR_MSG_FMT_MOD(extack, "rx (%d) < min (%d)", 420 param->rx_pending, 421 1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE); 422 return -EINVAL; 423 } 424 425 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) { 426 NL_SET_ERR_MSG_FMT_MOD(extack, "tx (%d) < min (%d)", 427 param->tx_pending, 428 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE); 429 return -EINVAL; 430 } 431 432 log_rq_size = order_base_2(param->rx_pending); 433 log_sq_size = order_base_2(param->tx_pending); 434 435 if (log_rq_size == priv->channels.params.log_rq_mtu_frames && 436 log_sq_size == priv->channels.params.log_sq_size) 437 return 0; 438 439 mutex_lock(&priv->state_lock); 440 441 new_params = priv->channels.params; 442 new_params.log_rq_mtu_frames = log_rq_size; 443 new_params.log_sq_size = log_sq_size; 444 445 err = mlx5e_validate_params(priv->mdev, &new_params); 446 if (err) 447 goto unlock; 448 449 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true); 450 451 unlock: 452 mutex_unlock(&priv->state_lock); 453 454 if (!err) 455 netdev_update_features(priv->netdev); 456 457 return err; 458 } 459 460 static int mlx5e_set_ringparam(struct net_device *dev, 461 struct ethtool_ringparam *param, 462 struct kernel_ethtool_ringparam *kernel_param, 463 struct netlink_ext_ack *extack) 464 { 465 struct mlx5e_priv *priv = netdev_priv(dev); 466 int err; 467 468 if (!mlx5e_ethtool_set_tcp_data_split(priv, 469 kernel_param->tcp_data_split, 470 extack)) 471 return -EINVAL; 472 473 err = mlx5e_ethtool_set_ringparam(priv, param, extack); 474 if (err) 475 return err; 476 477 /* Might need to disable HW-GRO if it was kept on due to hds. */ 478 if (kernel_param->tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_DISABLED && 479 dev->cfg->hds_config == ETHTOOL_TCP_DATA_SPLIT_ENABLED) 480 netdev_update_features(priv->netdev); 481 482 return 0; 483 } 484 485 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv, 486 struct ethtool_channels *ch) 487 { 488 mutex_lock(&priv->state_lock); 489 ch->max_combined = priv->max_nch; 490 ch->combined_count = priv->channels.params.num_channels; 491 mutex_unlock(&priv->state_lock); 492 } 493 494 static void mlx5e_get_channels(struct net_device *dev, 495 struct ethtool_channels *ch) 496 { 497 struct mlx5e_priv *priv = netdev_priv(dev); 498 499 mlx5e_ethtool_get_channels(priv, ch); 500 } 501 502 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv, 503 struct ethtool_channels *ch) 504 { 505 struct mlx5e_params *cur_params = &priv->channels.params; 506 unsigned int count = ch->combined_count; 507 int new_rqt_size, cur_rqt_size; 508 struct mlx5e_params new_params; 509 struct mlx5e_rss *rss0; 510 bool arfs_enabled; 511 bool has_rss_ctxs; 512 bool opened; 513 int err = 0; 514 515 ASSERT_RTNL(); 516 517 if (!count) { 518 netdev_info(priv->netdev, "%s: combined_count=0 not supported\n", 519 __func__); 520 return -EINVAL; 521 } 522 523 if (cur_params->num_channels == count) 524 return 0; 525 526 new_rqt_size = mlx5e_rqt_size(priv->mdev, count); 527 /* Validate that all non-default RSS contexts can be resized before 528 * committing to the channel count change. 529 * ethtool_rxfh_ctxs_can_resize() acquires rss_lock internally and 530 * cannot be called under state_lock (rss_lock -> state_lock ordering). 531 */ 532 has_rss_ctxs = priv->rx_res && mlx5e_rx_res_rss_cnt(priv->rx_res) > 1; 533 if (has_rss_ctxs) { 534 err = ethtool_rxfh_ctxs_can_resize(priv->netdev, new_rqt_size); 535 if (err) 536 return err; 537 } 538 539 mutex_lock(&priv->state_lock); 540 541 if (!priv->rx_res) { 542 err = -EINVAL; 543 goto out; 544 } 545 546 cur_rqt_size = mlx5e_rqt_size(priv->mdev, cur_params->num_channels); 547 rss0 = mlx5e_rx_res_rss_get(priv->rx_res, 0); 548 549 if (!ethtool_rxfh_indir_can_resize(priv->netdev, 550 mlx5e_rss_get_indir_table(rss0), 551 cur_rqt_size, new_rqt_size)) { 552 netdev_err(priv->netdev, 553 "%s: cannot resize RSS table (%u -> %u); reset indirection table to allow this change\n", 554 __func__, cur_rqt_size, new_rqt_size); 555 err = -EINVAL; 556 goto out; 557 } 558 559 /* Don't allow changing the number of channels if HTB offload is active, 560 * because the numeration of the QoS SQs will change, while per-queue 561 * qdiscs are attached. 562 */ 563 if (mlx5e_selq_is_htb_enabled(&priv->selq)) { 564 err = -EINVAL; 565 netdev_err(priv->netdev, "%s: HTB offload is active, cannot change the number of channels\n", 566 __func__); 567 goto out; 568 } 569 570 /* Don't allow changing the number of channels if MQPRIO mode channel offload is active, 571 * because it defines a partition over the channels queues. 572 */ 573 if (cur_params->mqprio.mode == TC_MQPRIO_MODE_CHANNEL) { 574 err = -EINVAL; 575 netdev_err(priv->netdev, "%s: MQPRIO mode channel offload is active, cannot change the number of channels\n", 576 __func__); 577 goto out; 578 } 579 580 new_params = *cur_params; 581 new_params.num_channels = count; 582 583 opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 584 585 arfs_enabled = opened && mlx5e_fs_want_arfs(priv->netdev); 586 if (arfs_enabled) 587 mlx5e_arfs_disable(priv->fs); 588 589 /* Switch to new channels, set new parameters and close old ones */ 590 err = mlx5e_safe_switch_params(priv, &new_params, 591 mlx5e_num_channels_changed_ctx, NULL, true); 592 593 if (arfs_enabled) { 594 int err2 = mlx5e_arfs_enable(priv->fs); 595 596 if (err2) 597 netdev_err(priv->netdev, "%s: mlx5e_arfs_enable failed: %d\n", 598 __func__, err2); 599 } 600 601 out: 602 mutex_unlock(&priv->state_lock); 603 604 /* After a successful channel count change that altered the RQT size, 605 * fold or unfold the indirection tables of all non-default RSS 606 * contexts. Must run after state_lock is released because 607 * ethtool_rxfh_ctxs_resize() acquires rss_lock internally. 608 */ 609 if (!err && cur_rqt_size != new_rqt_size && has_rss_ctxs) 610 ethtool_rxfh_ctxs_resize(priv->netdev, new_rqt_size); 611 612 return err; 613 } 614 615 static int mlx5e_set_channels(struct net_device *dev, 616 struct ethtool_channels *ch) 617 { 618 struct mlx5e_priv *priv = netdev_priv(dev); 619 620 return mlx5e_ethtool_set_channels(priv, ch); 621 } 622 623 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv, 624 struct ethtool_coalesce *coal, 625 struct kernel_ethtool_coalesce *kernel_coal, 626 struct netlink_ext_ack *extack) 627 { 628 struct dim_cq_moder *rx_moder, *tx_moder; 629 630 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation)) { 631 NL_SET_ERR_MSG_MOD(extack, "CQ moderation not supported"); 632 return -EOPNOTSUPP; 633 } 634 635 rx_moder = &priv->channels.params.rx_cq_moderation; 636 coal->rx_coalesce_usecs = rx_moder->usec; 637 coal->rx_max_coalesced_frames = rx_moder->pkts; 638 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_dim_enabled; 639 kernel_coal->use_cqe_mode_rx = priv->channels.params.rx_moder_use_cqe_mode; 640 641 tx_moder = &priv->channels.params.tx_cq_moderation; 642 coal->tx_coalesce_usecs = tx_moder->usec; 643 coal->tx_max_coalesced_frames = tx_moder->pkts; 644 coal->use_adaptive_tx_coalesce = priv->channels.params.tx_dim_enabled; 645 kernel_coal->use_cqe_mode_tx = priv->channels.params.tx_moder_use_cqe_mode; 646 647 return 0; 648 } 649 650 static int mlx5e_get_coalesce(struct net_device *netdev, 651 struct ethtool_coalesce *coal, 652 struct kernel_ethtool_coalesce *kernel_coal, 653 struct netlink_ext_ack *extack) 654 { 655 struct mlx5e_priv *priv = netdev_priv(netdev); 656 657 return mlx5e_ethtool_get_coalesce(priv, coal, kernel_coal, extack); 658 } 659 660 static int mlx5e_ethtool_get_per_queue_coalesce(struct mlx5e_priv *priv, u32 queue, 661 struct ethtool_coalesce *coal) 662 { 663 struct dim_cq_moder cur_moder; 664 struct mlx5e_channels *chs; 665 struct mlx5e_channel *c; 666 667 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation)) 668 return -EOPNOTSUPP; 669 670 mutex_lock(&priv->state_lock); 671 672 chs = &priv->channels; 673 if (chs->num <= queue) { 674 mutex_unlock(&priv->state_lock); 675 return -EINVAL; 676 } 677 678 c = chs->c[queue]; 679 680 coal->use_adaptive_rx_coalesce = !!c->rq.dim; 681 if (coal->use_adaptive_rx_coalesce) { 682 cur_moder = net_dim_get_rx_moderation(c->rq.dim->mode, 683 c->rq.dim->profile_ix); 684 685 coal->rx_coalesce_usecs = cur_moder.usec; 686 coal->rx_max_coalesced_frames = cur_moder.pkts; 687 } else { 688 coal->rx_coalesce_usecs = c->rx_cq_moder.usec; 689 coal->rx_max_coalesced_frames = c->rx_cq_moder.pkts; 690 } 691 692 coal->use_adaptive_tx_coalesce = !!c->sq[0].dim; 693 if (coal->use_adaptive_tx_coalesce) { 694 /* NOTE: Will only display DIM coalesce profile information of 695 * first channel. The current interface cannot display this 696 * information for all tc. 697 */ 698 cur_moder = net_dim_get_tx_moderation(c->sq[0].dim->mode, 699 c->sq[0].dim->profile_ix); 700 701 coal->tx_coalesce_usecs = cur_moder.usec; 702 coal->tx_max_coalesced_frames = cur_moder.pkts; 703 704 } else { 705 coal->tx_coalesce_usecs = c->tx_cq_moder.usec; 706 coal->tx_max_coalesced_frames = c->tx_cq_moder.pkts; 707 } 708 709 mutex_unlock(&priv->state_lock); 710 711 return 0; 712 } 713 714 int mlx5e_get_per_queue_coalesce(struct net_device *dev, u32 queue, 715 struct ethtool_coalesce *coal) 716 { 717 struct mlx5e_priv *priv = netdev_priv(dev); 718 719 return mlx5e_ethtool_get_per_queue_coalesce(priv, queue, coal); 720 } 721 722 #define MLX5E_MAX_COAL_TIME MLX5_MAX_CQ_PERIOD 723 #define MLX5E_MAX_COAL_FRAMES MLX5_MAX_CQ_COUNT 724 725 static void 726 mlx5e_set_priv_channels_tx_coalesce(struct mlx5e_priv *priv, struct dim_cq_moder *moder) 727 { 728 int tc; 729 int i; 730 731 for (i = 0; i < priv->channels.num; ++i) { 732 struct mlx5e_channel *c = priv->channels.c[i]; 733 struct mlx5_core_dev *mdev = c->mdev; 734 enum mlx5_cq_period_mode mode; 735 736 mode = mlx5e_cq_period_mode(moder->cq_period_mode); 737 c->tx_cq_moder = *moder; 738 739 for (tc = 0; tc < c->num_tc; tc++) { 740 mlx5e_modify_cq_moderation(mdev, &c->sq[tc].cq.mcq, 741 moder->usec, moder->pkts, 742 mode); 743 } 744 } 745 } 746 747 static void 748 mlx5e_set_priv_channels_rx_coalesce(struct mlx5e_priv *priv, struct dim_cq_moder *moder) 749 { 750 int i; 751 752 for (i = 0; i < priv->channels.num; ++i) { 753 struct mlx5e_channel *c = priv->channels.c[i]; 754 struct mlx5_core_dev *mdev = c->mdev; 755 enum mlx5_cq_period_mode mode; 756 757 mode = mlx5e_cq_period_mode(moder->cq_period_mode); 758 c->rx_cq_moder = *moder; 759 760 mlx5e_modify_cq_moderation(mdev, &c->rq.cq.mcq, moder->usec, moder->pkts, 761 mode); 762 } 763 } 764 765 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv, 766 struct ethtool_coalesce *coal, 767 struct kernel_ethtool_coalesce *kernel_coal, 768 struct netlink_ext_ack *extack) 769 { 770 struct dim_cq_moder *rx_moder, *tx_moder; 771 struct mlx5_core_dev *mdev = priv->mdev; 772 bool rx_dim_enabled, tx_dim_enabled; 773 struct mlx5e_params new_params; 774 bool reset_rx, reset_tx; 775 u8 cq_period_mode; 776 int err = 0; 777 778 if (!MLX5_CAP_GEN(mdev, cq_moderation) || 779 !MLX5_CAP_GEN(mdev, cq_period_mode_modify)) { 780 NL_SET_ERR_MSG_MOD(extack, "CQ moderation not supported"); 781 return -EOPNOTSUPP; 782 } 783 784 if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME || 785 coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) { 786 NL_SET_ERR_MSG_FMT_MOD( 787 extack, 788 "Max coalesce time %lu usecs, tx-usecs (%u) rx-usecs (%u)", 789 MLX5E_MAX_COAL_TIME, coal->tx_coalesce_usecs, 790 coal->rx_coalesce_usecs); 791 return -ERANGE; 792 } 793 794 if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES || 795 coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) { 796 NL_SET_ERR_MSG_FMT_MOD( 797 extack, 798 "Max coalesce frames %lu, tx-frames (%u) rx-frames (%u)", 799 MLX5E_MAX_COAL_FRAMES, coal->tx_max_coalesced_frames, 800 coal->rx_max_coalesced_frames); 801 return -ERANGE; 802 } 803 804 if ((kernel_coal->use_cqe_mode_rx || kernel_coal->use_cqe_mode_tx) && 805 !MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) { 806 NL_SET_ERR_MSG_MOD(extack, "cqe-mode-rx/tx is not supported on this device"); 807 return -EOPNOTSUPP; 808 } 809 810 rx_dim_enabled = !!coal->use_adaptive_rx_coalesce; 811 tx_dim_enabled = !!coal->use_adaptive_tx_coalesce; 812 813 mutex_lock(&priv->state_lock); 814 new_params = priv->channels.params; 815 816 cq_period_mode = mlx5e_dim_cq_period_mode(kernel_coal->use_cqe_mode_rx); 817 reset_rx = mlx5e_reset_rx_channels_moderation(&priv->channels, cq_period_mode, 818 rx_dim_enabled, false); 819 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_RX_CQE_BASED_MODER, cq_period_mode); 820 821 cq_period_mode = mlx5e_dim_cq_period_mode(kernel_coal->use_cqe_mode_tx); 822 reset_tx = mlx5e_reset_tx_channels_moderation(&priv->channels, cq_period_mode, 823 tx_dim_enabled, false); 824 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_TX_CQE_BASED_MODER, cq_period_mode); 825 826 reset_rx |= rx_dim_enabled != new_params.rx_dim_enabled; 827 reset_tx |= tx_dim_enabled != new_params.tx_dim_enabled; 828 829 /* Solely used for global ethtool get coalesce */ 830 rx_moder = &new_params.rx_cq_moderation; 831 new_params.rx_dim_enabled = rx_dim_enabled; 832 new_params.rx_moder_use_cqe_mode = kernel_coal->use_cqe_mode_rx; 833 834 tx_moder = &new_params.tx_cq_moderation; 835 new_params.tx_dim_enabled = tx_dim_enabled; 836 new_params.tx_moder_use_cqe_mode = kernel_coal->use_cqe_mode_tx; 837 838 if (reset_rx) { 839 mlx5e_channels_rx_change_dim(&priv->channels, false); 840 mlx5e_reset_rx_moderation(rx_moder, new_params.rx_moder_use_cqe_mode, 841 rx_dim_enabled); 842 843 mlx5e_set_priv_channels_rx_coalesce(priv, rx_moder); 844 } else if (!rx_dim_enabled) { 845 rx_moder->usec = coal->rx_coalesce_usecs; 846 rx_moder->pkts = coal->rx_max_coalesced_frames; 847 848 mlx5e_set_priv_channels_rx_coalesce(priv, rx_moder); 849 } 850 851 if (reset_tx) { 852 mlx5e_channels_tx_change_dim(&priv->channels, false); 853 mlx5e_reset_tx_moderation(tx_moder, new_params.tx_moder_use_cqe_mode, 854 tx_dim_enabled); 855 856 mlx5e_set_priv_channels_tx_coalesce(priv, tx_moder); 857 } else if (!tx_dim_enabled) { 858 tx_moder->usec = coal->tx_coalesce_usecs; 859 tx_moder->pkts = coal->tx_max_coalesced_frames; 860 861 mlx5e_set_priv_channels_tx_coalesce(priv, tx_moder); 862 } 863 864 /* DIM enable/disable Rx and Tx channels */ 865 err = mlx5e_channels_rx_change_dim(&priv->channels, rx_dim_enabled); 866 if (err) 867 goto state_unlock; 868 err = mlx5e_channels_tx_change_dim(&priv->channels, tx_dim_enabled); 869 if (err) 870 goto state_unlock; 871 872 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, false); 873 state_unlock: 874 mutex_unlock(&priv->state_lock); 875 return err; 876 } 877 878 static int mlx5e_set_coalesce(struct net_device *netdev, 879 struct ethtool_coalesce *coal, 880 struct kernel_ethtool_coalesce *kernel_coal, 881 struct netlink_ext_ack *extack) 882 { 883 struct mlx5e_priv *priv = netdev_priv(netdev); 884 885 return mlx5e_ethtool_set_coalesce(priv, coal, kernel_coal, extack); 886 } 887 888 static int mlx5e_ethtool_set_per_queue_coalesce(struct mlx5e_priv *priv, u32 queue, 889 struct ethtool_coalesce *coal) 890 { 891 struct mlx5_core_dev *mdev = priv->mdev; 892 bool rx_dim_enabled, tx_dim_enabled; 893 struct mlx5e_channels *chs; 894 struct mlx5e_channel *c; 895 int err = 0; 896 int tc; 897 898 if (!MLX5_CAP_GEN(mdev, cq_moderation)) 899 return -EOPNOTSUPP; 900 901 if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME || 902 coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) { 903 netdev_info(priv->netdev, "%s: maximum coalesce time supported is %lu usecs\n", 904 __func__, MLX5E_MAX_COAL_TIME); 905 return -ERANGE; 906 } 907 908 if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES || 909 coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) { 910 netdev_info(priv->netdev, "%s: maximum coalesced frames supported is %lu\n", 911 __func__, MLX5E_MAX_COAL_FRAMES); 912 return -ERANGE; 913 } 914 915 rx_dim_enabled = !!coal->use_adaptive_rx_coalesce; 916 tx_dim_enabled = !!coal->use_adaptive_tx_coalesce; 917 918 mutex_lock(&priv->state_lock); 919 920 chs = &priv->channels; 921 if (chs->num <= queue) { 922 mutex_unlock(&priv->state_lock); 923 return -EINVAL; 924 } 925 926 c = chs->c[queue]; 927 928 err = mlx5e_dim_rx_change(&c->rq, rx_dim_enabled); 929 if (err) 930 goto state_unlock; 931 932 for (tc = 0; tc < c->num_tc; tc++) { 933 err = mlx5e_dim_tx_change(&c->sq[tc], tx_dim_enabled); 934 if (err) 935 goto state_unlock; 936 } 937 938 if (!rx_dim_enabled) { 939 c->rx_cq_moder.usec = coal->rx_coalesce_usecs; 940 c->rx_cq_moder.pkts = coal->rx_max_coalesced_frames; 941 942 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq, 943 coal->rx_coalesce_usecs, 944 coal->rx_max_coalesced_frames); 945 } 946 947 if (!tx_dim_enabled) { 948 c->tx_cq_moder.usec = coal->tx_coalesce_usecs; 949 c->tx_cq_moder.pkts = coal->tx_max_coalesced_frames; 950 951 for (tc = 0; tc < c->num_tc; tc++) 952 mlx5_core_modify_cq_moderation(mdev, &c->sq[tc].cq.mcq, 953 coal->tx_coalesce_usecs, 954 coal->tx_max_coalesced_frames); 955 } 956 957 state_unlock: 958 mutex_unlock(&priv->state_lock); 959 return err; 960 } 961 962 int mlx5e_set_per_queue_coalesce(struct net_device *dev, u32 queue, 963 struct ethtool_coalesce *coal) 964 { 965 struct mlx5e_priv *priv = netdev_priv(dev); 966 967 return mlx5e_ethtool_set_per_queue_coalesce(priv, queue, coal); 968 } 969 970 static void ptys2ethtool_process_link(u32 eth_eproto, bool ext, bool advertised, 971 unsigned long *modes) 972 { 973 unsigned long eproto = eth_eproto; 974 struct ptys2ethtool_config *table; 975 u32 max_size; 976 int proto; 977 978 mlx5e_ethtool_get_speed_arr(ext, &table, &max_size); 979 for_each_set_bit(proto, &eproto, max_size) 980 bitmap_or(modes, modes, 981 advertised ? 982 table[proto].advertised : table[proto].supported, 983 __ETHTOOL_LINK_MODE_MASK_NBITS); 984 } 985 986 static const u32 pplm_fec_2_ethtool[] = { 987 [MLX5E_FEC_NOFEC] = ETHTOOL_FEC_OFF, 988 [MLX5E_FEC_FIRECODE] = ETHTOOL_FEC_BASER, 989 [MLX5E_FEC_RS_528_514] = ETHTOOL_FEC_RS, 990 [MLX5E_FEC_RS_544_514] = ETHTOOL_FEC_RS, 991 [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_FEC_LLRS, 992 [MLX5E_FEC_RS_544_514_INTERLEAVED_QUAD] = ETHTOOL_FEC_RS, 993 }; 994 995 static u32 pplm2ethtool_fec(u_long fec_mode, unsigned long size) 996 { 997 int mode = 0; 998 999 if (!fec_mode) 1000 return ETHTOOL_FEC_AUTO; 1001 1002 mode = find_first_bit(&fec_mode, size); 1003 1004 if (mode < ARRAY_SIZE(pplm_fec_2_ethtool)) 1005 return pplm_fec_2_ethtool[mode]; 1006 1007 return 0; 1008 } 1009 1010 #define MLX5E_ADVERTISE_SUPPORTED_FEC(fec_mask, ethtool_fec) \ 1011 do { \ 1012 if (mlx5e_fec_in_caps(dev, fec_mask)) \ 1013 __set_bit(ethtool_fec, \ 1014 link_ksettings->link_modes.supported);\ 1015 } while (0) 1016 1017 static const u32 pplm_fec_2_ethtool_linkmodes[] = { 1018 [MLX5E_FEC_NOFEC] = ETHTOOL_LINK_MODE_FEC_NONE_BIT, 1019 [MLX5E_FEC_FIRECODE] = ETHTOOL_LINK_MODE_FEC_BASER_BIT, 1020 [MLX5E_FEC_RS_528_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT, 1021 [MLX5E_FEC_RS_544_514_INTERLEAVED_QUAD] = ETHTOOL_LINK_MODE_FEC_RS_BIT, 1022 [MLX5E_FEC_RS_544_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT, 1023 [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 1024 }; 1025 1026 static int get_fec_supported_advertised(struct mlx5_core_dev *dev, 1027 struct ethtool_link_ksettings *link_ksettings) 1028 { 1029 unsigned long active_fec_long; 1030 u32 active_fec; 1031 u32 bitn; 1032 int err; 1033 1034 err = mlx5e_get_fec_mode(dev, &active_fec, NULL); 1035 if (err) 1036 return (err == -EOPNOTSUPP) ? 0 : err; 1037 1038 MLX5E_ADVERTISE_SUPPORTED_FEC(BIT(MLX5E_FEC_NOFEC), 1039 ETHTOOL_LINK_MODE_FEC_NONE_BIT); 1040 MLX5E_ADVERTISE_SUPPORTED_FEC(BIT(MLX5E_FEC_FIRECODE), 1041 ETHTOOL_LINK_MODE_FEC_BASER_BIT); 1042 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_RS_MASK, 1043 ETHTOOL_LINK_MODE_FEC_RS_BIT); 1044 MLX5E_ADVERTISE_SUPPORTED_FEC(BIT(MLX5E_FEC_LLRS_272_257_1), 1045 ETHTOOL_LINK_MODE_FEC_LLRS_BIT); 1046 1047 active_fec_long = active_fec; 1048 /* active fec is a bit set, find out which bit is set and 1049 * advertise the corresponding ethtool bit 1050 */ 1051 bitn = find_first_bit(&active_fec_long, sizeof(active_fec_long) * BITS_PER_BYTE); 1052 if (bitn < ARRAY_SIZE(pplm_fec_2_ethtool_linkmodes)) 1053 __set_bit(pplm_fec_2_ethtool_linkmodes[bitn], 1054 link_ksettings->link_modes.advertising); 1055 1056 return 0; 1057 } 1058 1059 static void ptys2ethtool_supported_advertised_port(struct mlx5_core_dev *mdev, 1060 struct ethtool_link_ksettings *link_ksettings, 1061 u32 eth_proto_cap, u8 connector_type) 1062 { 1063 if (!MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type)) { 1064 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR) 1065 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR) 1066 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) 1067 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) 1068 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) 1069 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) { 1070 ethtool_link_ksettings_add_link_mode(link_ksettings, 1071 supported, 1072 FIBRE); 1073 ethtool_link_ksettings_add_link_mode(link_ksettings, 1074 advertising, 1075 FIBRE); 1076 } 1077 1078 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4) 1079 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) 1080 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR) 1081 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) 1082 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) { 1083 ethtool_link_ksettings_add_link_mode(link_ksettings, 1084 supported, 1085 Backplane); 1086 ethtool_link_ksettings_add_link_mode(link_ksettings, 1087 advertising, 1088 Backplane); 1089 } 1090 return; 1091 } 1092 1093 switch (connector_type) { 1094 case MLX5E_PORT_TP: 1095 ethtool_link_ksettings_add_link_mode(link_ksettings, 1096 supported, TP); 1097 ethtool_link_ksettings_add_link_mode(link_ksettings, 1098 advertising, TP); 1099 break; 1100 case MLX5E_PORT_AUI: 1101 ethtool_link_ksettings_add_link_mode(link_ksettings, 1102 supported, AUI); 1103 ethtool_link_ksettings_add_link_mode(link_ksettings, 1104 advertising, AUI); 1105 break; 1106 case MLX5E_PORT_BNC: 1107 ethtool_link_ksettings_add_link_mode(link_ksettings, 1108 supported, BNC); 1109 ethtool_link_ksettings_add_link_mode(link_ksettings, 1110 advertising, BNC); 1111 break; 1112 case MLX5E_PORT_MII: 1113 ethtool_link_ksettings_add_link_mode(link_ksettings, 1114 supported, MII); 1115 ethtool_link_ksettings_add_link_mode(link_ksettings, 1116 advertising, MII); 1117 break; 1118 case MLX5E_PORT_FIBRE: 1119 ethtool_link_ksettings_add_link_mode(link_ksettings, 1120 supported, FIBRE); 1121 ethtool_link_ksettings_add_link_mode(link_ksettings, 1122 advertising, FIBRE); 1123 break; 1124 case MLX5E_PORT_DA: 1125 ethtool_link_ksettings_add_link_mode(link_ksettings, 1126 supported, Backplane); 1127 ethtool_link_ksettings_add_link_mode(link_ksettings, 1128 advertising, Backplane); 1129 break; 1130 case MLX5E_PORT_NONE: 1131 case MLX5E_PORT_OTHER: 1132 default: 1133 break; 1134 } 1135 } 1136 1137 static void get_link_properties(struct net_device *netdev, 1138 u32 eth_proto_oper, bool force_legacy, 1139 u16 data_rate_oper, 1140 struct ethtool_link_ksettings *link_ksettings) 1141 { 1142 struct mlx5e_priv *priv = netdev_priv(netdev); 1143 const struct mlx5_link_info *info; 1144 u8 duplex = DUPLEX_UNKNOWN; 1145 u32 speed = SPEED_UNKNOWN; 1146 u32 lanes = LANES_UNKNOWN; 1147 1148 if (!netif_carrier_ok(netdev)) 1149 goto out; 1150 1151 info = mlx5_port_ptys2info(priv->mdev, eth_proto_oper, force_legacy); 1152 if (info) { 1153 speed = info->speed; 1154 lanes = info->lanes; 1155 duplex = DUPLEX_FULL; 1156 } else if (data_rate_oper) 1157 speed = 100 * data_rate_oper; 1158 1159 out: 1160 link_ksettings->base.duplex = duplex; 1161 link_ksettings->base.speed = speed; 1162 link_ksettings->lanes = lanes; 1163 } 1164 1165 static void get_supported(struct mlx5_core_dev *mdev, u32 eth_proto_cap, 1166 struct ethtool_link_ksettings *link_ksettings) 1167 { 1168 unsigned long *supported = link_ksettings->link_modes.supported; 1169 bool ext = mlx5_ptys_ext_supported(mdev); 1170 1171 ptys2ethtool_process_link(eth_proto_cap, ext, false, supported); 1172 1173 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause); 1174 } 1175 1176 static void get_advertising(u32 eth_proto_admin, u8 tx_pause, u8 rx_pause, 1177 struct ethtool_link_ksettings *link_ksettings, 1178 bool ext) 1179 { 1180 unsigned long *advertising = link_ksettings->link_modes.advertising; 1181 ptys2ethtool_process_link(eth_proto_admin, ext, true, advertising); 1182 if (rx_pause) 1183 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause); 1184 if (tx_pause ^ rx_pause) 1185 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause); 1186 } 1187 1188 static int ptys2connector_type[MLX5E_CONNECTOR_TYPE_NUMBER] = { 1189 [MLX5E_PORT_UNKNOWN] = PORT_OTHER, 1190 [MLX5E_PORT_NONE] = PORT_NONE, 1191 [MLX5E_PORT_TP] = PORT_TP, 1192 [MLX5E_PORT_AUI] = PORT_AUI, 1193 [MLX5E_PORT_BNC] = PORT_BNC, 1194 [MLX5E_PORT_MII] = PORT_MII, 1195 [MLX5E_PORT_FIBRE] = PORT_FIBRE, 1196 [MLX5E_PORT_DA] = PORT_DA, 1197 [MLX5E_PORT_OTHER] = PORT_OTHER, 1198 }; 1199 1200 static u8 get_connector_port(struct mlx5_core_dev *mdev, u32 eth_proto, u8 connector_type) 1201 { 1202 if (MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type)) 1203 return ptys2connector_type[connector_type]; 1204 1205 if (eth_proto & 1206 (MLX5E_PROT_MASK(MLX5E_10GBASE_SR) | 1207 MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) | 1208 MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) | 1209 MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) { 1210 return PORT_FIBRE; 1211 } 1212 1213 if (eth_proto & 1214 (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) | 1215 MLX5E_PROT_MASK(MLX5E_10GBASE_CR) | 1216 MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) { 1217 return PORT_DA; 1218 } 1219 1220 if (eth_proto & 1221 (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) | 1222 MLX5E_PROT_MASK(MLX5E_10GBASE_KR) | 1223 MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) | 1224 MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) { 1225 return PORT_NONE; 1226 } 1227 1228 return PORT_OTHER; 1229 } 1230 1231 static void get_lp_advertising(struct mlx5_core_dev *mdev, u32 eth_proto_lp, 1232 struct ethtool_link_ksettings *link_ksettings) 1233 { 1234 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising; 1235 bool ext = mlx5_ptys_ext_supported(mdev); 1236 1237 ptys2ethtool_process_link(eth_proto_lp, ext, true, lp_advertising); 1238 } 1239 1240 static int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv, 1241 struct ethtool_link_ksettings *link_ksettings) 1242 { 1243 struct mlx5_core_dev *mdev = priv->mdev; 1244 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {}; 1245 u32 eth_proto_admin; 1246 u8 an_disable_admin; 1247 u16 data_rate_oper; 1248 u32 eth_proto_oper; 1249 u32 eth_proto_cap; 1250 u8 connector_type; 1251 u32 rx_pause = 0; 1252 u32 tx_pause = 0; 1253 u32 eth_proto_lp; 1254 bool admin_ext; 1255 u8 an_status; 1256 bool ext; 1257 int err; 1258 1259 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1, 0); 1260 if (err) { 1261 netdev_err(priv->netdev, "%s: query port ptys failed: %d\n", 1262 __func__, err); 1263 goto err_query_regs; 1264 } 1265 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability); 1266 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 1267 eth_proto_capability); 1268 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 1269 eth_proto_admin); 1270 /* Fields: eth_proto_admin and ext_eth_proto_admin are 1271 * mutually exclusive. Hence try reading legacy advertising 1272 * when extended advertising is zero. 1273 * admin_ext indicates which proto_admin (ext vs. legacy) 1274 * should be read and interpreted 1275 */ 1276 admin_ext = ext; 1277 if (ext && !eth_proto_admin) { 1278 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, false, 1279 eth_proto_admin); 1280 admin_ext = false; 1281 } 1282 1283 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, admin_ext, 1284 eth_proto_oper); 1285 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise); 1286 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin); 1287 an_status = MLX5_GET(ptys_reg, out, an_status); 1288 connector_type = MLX5_GET(ptys_reg, out, connector_type); 1289 data_rate_oper = MLX5_GET(ptys_reg, out, data_rate_oper); 1290 1291 mlx5_query_port_pause(mdev, &rx_pause, &tx_pause); 1292 1293 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported); 1294 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising); 1295 1296 get_supported(mdev, eth_proto_cap, link_ksettings); 1297 get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings, 1298 admin_ext); 1299 get_link_properties(priv->netdev, eth_proto_oper, !admin_ext, 1300 data_rate_oper, link_ksettings); 1301 1302 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap; 1303 connector_type = connector_type < MLX5E_CONNECTOR_TYPE_NUMBER ? 1304 connector_type : MLX5E_PORT_UNKNOWN; 1305 link_ksettings->base.port = get_connector_port(mdev, eth_proto_oper, connector_type); 1306 ptys2ethtool_supported_advertised_port(mdev, link_ksettings, eth_proto_admin, 1307 connector_type); 1308 get_lp_advertising(mdev, eth_proto_lp, link_ksettings); 1309 1310 if (an_status == MLX5_AN_COMPLETE) 1311 ethtool_link_ksettings_add_link_mode(link_ksettings, 1312 lp_advertising, Autoneg); 1313 1314 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE : 1315 AUTONEG_ENABLE; 1316 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, 1317 Autoneg); 1318 1319 err = get_fec_supported_advertised(mdev, link_ksettings); 1320 if (err) { 1321 netdev_dbg(priv->netdev, "%s: FEC caps query failed: %d\n", 1322 __func__, err); 1323 err = 0; /* don't fail caps query because of FEC error */ 1324 } 1325 1326 if (!an_disable_admin) 1327 ethtool_link_ksettings_add_link_mode(link_ksettings, 1328 advertising, Autoneg); 1329 1330 err_query_regs: 1331 return err; 1332 } 1333 1334 static int mlx5e_get_link_ksettings(struct net_device *netdev, 1335 struct ethtool_link_ksettings *link_ksettings) 1336 { 1337 struct mlx5e_priv *priv = netdev_priv(netdev); 1338 1339 return mlx5e_ethtool_get_link_ksettings(priv, link_ksettings); 1340 } 1341 1342 static int mlx5e_speed_validate(struct net_device *netdev, bool ext, 1343 const unsigned long link_modes, u8 autoneg) 1344 { 1345 /* Extended link-mode has no speed limitations. */ 1346 if (ext) 1347 return 0; 1348 1349 if ((link_modes & MLX5E_PROT_MASK(MLX5E_56GBASE_R4)) && 1350 autoneg != AUTONEG_ENABLE) { 1351 netdev_err(netdev, "%s: 56G link speed requires autoneg enabled\n", 1352 __func__); 1353 return -EINVAL; 1354 } 1355 return 0; 1356 } 1357 1358 static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes) 1359 { 1360 u32 i, ptys_modes = 0; 1361 1362 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) { 1363 if (bitmap_empty(ptys2legacy_ethtool_table[i].advertised, 1364 __ETHTOOL_LINK_MODE_MASK_NBITS)) 1365 continue; 1366 if (bitmap_intersects(ptys2legacy_ethtool_table[i].advertised, 1367 link_modes, 1368 __ETHTOOL_LINK_MODE_MASK_NBITS)) 1369 ptys_modes |= MLX5E_PROT_MASK(i); 1370 } 1371 1372 return ptys_modes; 1373 } 1374 1375 static u32 mlx5e_ethtool2ptys_ext_adver_link(const unsigned long *link_modes) 1376 { 1377 u32 i, ptys_modes = 0; 1378 __ETHTOOL_DECLARE_LINK_MODE_MASK(modes); 1379 1380 for (i = 0; i < MLX5E_EXT_LINK_MODES_NUMBER; ++i) { 1381 if (bitmap_empty(ptys2ext_ethtool_table[i].advertised, 1382 __ETHTOOL_LINK_MODE_MASK_NBITS)) 1383 continue; 1384 bitmap_zero(modes, __ETHTOOL_LINK_MODE_MASK_NBITS); 1385 bitmap_and(modes, ptys2ext_ethtool_table[i].advertised, 1386 link_modes, __ETHTOOL_LINK_MODE_MASK_NBITS); 1387 1388 if (bitmap_equal(modes, ptys2ext_ethtool_table[i].advertised, 1389 __ETHTOOL_LINK_MODE_MASK_NBITS)) 1390 ptys_modes |= MLX5E_PROT_MASK(i); 1391 } 1392 return ptys_modes; 1393 } 1394 1395 static bool ext_link_mode_requested(const unsigned long *adver) 1396 { 1397 #define MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT ETHTOOL_LINK_MODE_50000baseKR_Full_BIT 1398 int size = __ETHTOOL_LINK_MODE_MASK_NBITS - MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT; 1399 __ETHTOOL_DECLARE_LINK_MODE_MASK(modes) = {0,}; 1400 1401 bitmap_set(modes, MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT, size); 1402 return bitmap_intersects(modes, adver, __ETHTOOL_LINK_MODE_MASK_NBITS); 1403 } 1404 1405 static int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv, 1406 const struct ethtool_link_ksettings *link_ksettings) 1407 { 1408 struct mlx5_core_dev *mdev = priv->mdev; 1409 struct mlx5_port_eth_proto eproto; 1410 struct mlx5_link_info info = {}; 1411 const unsigned long *adver; 1412 bool an_changes = false; 1413 u8 an_disable_admin; 1414 bool ext_supported; 1415 bool ext_requested; 1416 u8 an_disable_cap; 1417 bool an_disable; 1418 u32 link_modes; 1419 u8 an_status; 1420 u8 autoneg; 1421 bool ext; 1422 int err; 1423 1424 u32 (*ethtool2ptys_adver_func)(const unsigned long *adver); 1425 1426 adver = link_ksettings->link_modes.advertising; 1427 autoneg = link_ksettings->base.autoneg; 1428 info.speed = link_ksettings->base.speed; 1429 info.lanes = link_ksettings->lanes; 1430 1431 ext_supported = mlx5_ptys_ext_supported(mdev); 1432 ext_requested = ext_link_mode_requested(adver); 1433 if (!ext_supported && ext_requested) 1434 return -EOPNOTSUPP; 1435 1436 ext = autoneg == AUTONEG_ENABLE ? ext_requested : ext_supported; 1437 ethtool2ptys_adver_func = ext ? mlx5e_ethtool2ptys_ext_adver_link : 1438 mlx5e_ethtool2ptys_adver_link; 1439 err = mlx5_port_query_eth_proto(mdev, 1, ext, &eproto); 1440 if (err) { 1441 netdev_err(priv->netdev, "%s: query port eth proto failed: %d\n", 1442 __func__, err); 1443 goto out; 1444 } 1445 link_modes = autoneg == AUTONEG_ENABLE ? ethtool2ptys_adver_func(adver) : 1446 mlx5_port_info2linkmodes(mdev, &info, !ext); 1447 1448 err = mlx5e_speed_validate(priv->netdev, ext, link_modes, autoneg); 1449 if (err) 1450 goto out; 1451 1452 link_modes = link_modes & eproto.cap; 1453 if (!link_modes) { 1454 netdev_err(priv->netdev, "%s: Not supported link mode(s) requested", 1455 __func__); 1456 err = -EINVAL; 1457 goto out; 1458 } 1459 1460 mlx5_port_query_eth_autoneg(mdev, &an_status, &an_disable_cap, 1461 &an_disable_admin); 1462 1463 an_disable = autoneg == AUTONEG_DISABLE; 1464 an_changes = ((!an_disable && an_disable_admin) || 1465 (an_disable && !an_disable_admin)); 1466 1467 if (!an_changes && link_modes == eproto.admin) 1468 goto out; 1469 1470 err = mlx5_port_set_eth_ptys(mdev, an_disable, link_modes, ext); 1471 if (err) { 1472 netdev_err(priv->netdev, "%s: failed to set ptys reg: %d\n", __func__, err); 1473 goto out; 1474 } 1475 1476 mlx5_toggle_port_link(mdev); 1477 1478 out: 1479 return err; 1480 } 1481 1482 static int mlx5e_set_link_ksettings(struct net_device *netdev, 1483 const struct ethtool_link_ksettings *link_ksettings) 1484 { 1485 struct mlx5e_priv *priv = netdev_priv(netdev); 1486 1487 return mlx5e_ethtool_set_link_ksettings(priv, link_ksettings); 1488 } 1489 1490 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv) 1491 { 1492 return sizeof_field(struct mlx5e_rss_params_hash, toeplitz_hash_key); 1493 } 1494 1495 static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev) 1496 { 1497 struct mlx5e_priv *priv = netdev_priv(netdev); 1498 1499 return mlx5e_ethtool_get_rxfh_key_size(priv); 1500 } 1501 1502 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv) 1503 { 1504 return mlx5e_rqt_size(priv->mdev, priv->channels.params.num_channels); 1505 } 1506 1507 static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev) 1508 { 1509 struct mlx5e_priv *priv = netdev_priv(netdev); 1510 1511 return mlx5e_ethtool_get_rxfh_indir_size(priv); 1512 } 1513 1514 static int mlx5e_get_rxfh(struct net_device *netdev, struct ethtool_rxfh_param *rxfh) 1515 { 1516 struct mlx5e_priv *priv = netdev_priv(netdev); 1517 bool symmetric; 1518 1519 mutex_lock(&priv->state_lock); 1520 mlx5e_rx_res_rss_get_rxfh(priv->rx_res, 0, rxfh->indir, rxfh->key, 1521 &rxfh->hfunc, &symmetric); 1522 mutex_unlock(&priv->state_lock); 1523 1524 if (symmetric) 1525 rxfh->input_xfrm = RXH_XFRM_SYM_OR_XOR; 1526 1527 return 0; 1528 } 1529 1530 static int mlx5e_set_rxfh(struct net_device *dev, 1531 struct ethtool_rxfh_param *rxfh, 1532 struct netlink_ext_ack *extack) 1533 { 1534 bool symmetric = rxfh->input_xfrm == RXH_XFRM_SYM_OR_XOR; 1535 struct mlx5e_priv *priv = netdev_priv(dev); 1536 u8 hfunc = rxfh->hfunc; 1537 int err; 1538 1539 mutex_lock(&priv->state_lock); 1540 1541 err = mlx5e_rx_res_rss_set_rxfh(priv->rx_res, rxfh->rss_context, 1542 rxfh->indir, rxfh->key, 1543 hfunc == ETH_RSS_HASH_NO_CHANGE ? NULL : &hfunc, 1544 rxfh->input_xfrm == RXH_XFRM_NO_CHANGE ? NULL : &symmetric); 1545 1546 mutex_unlock(&priv->state_lock); 1547 return err; 1548 } 1549 1550 static int mlx5e_create_rxfh_context(struct net_device *dev, 1551 struct ethtool_rxfh_context *ctx, 1552 const struct ethtool_rxfh_param *rxfh, 1553 struct netlink_ext_ack *extack) 1554 { 1555 bool symmetric = rxfh->input_xfrm == RXH_XFRM_SYM_OR_XOR; 1556 struct mlx5e_priv *priv = netdev_priv(dev); 1557 u8 hfunc = rxfh->hfunc; 1558 int err; 1559 1560 mutex_lock(&priv->state_lock); 1561 1562 err = mlx5e_rx_res_rss_init(priv->rx_res, rxfh->rss_context, 1563 priv->channels.params.num_channels); 1564 if (err) 1565 goto unlock; 1566 1567 err = mlx5e_rx_res_rss_set_rxfh(priv->rx_res, rxfh->rss_context, 1568 rxfh->indir, rxfh->key, 1569 hfunc == ETH_RSS_HASH_NO_CHANGE ? NULL : &hfunc, 1570 rxfh->input_xfrm == RXH_XFRM_NO_CHANGE ? NULL : &symmetric); 1571 if (err) { 1572 WARN_ON(mlx5e_rx_res_rss_destroy(priv->rx_res, 1573 rxfh->rss_context)); 1574 goto unlock; 1575 } 1576 1577 mlx5e_rx_res_rss_get_rxfh(priv->rx_res, rxfh->rss_context, 1578 ethtool_rxfh_context_indir(ctx), 1579 ethtool_rxfh_context_key(ctx), 1580 &ctx->hfunc, &symmetric); 1581 if (symmetric) 1582 ctx->input_xfrm = RXH_XFRM_SYM_OR_XOR; 1583 1584 unlock: 1585 mutex_unlock(&priv->state_lock); 1586 return err; 1587 } 1588 1589 static int mlx5e_modify_rxfh_context(struct net_device *dev, 1590 struct ethtool_rxfh_context *ctx, 1591 const struct ethtool_rxfh_param *rxfh, 1592 struct netlink_ext_ack *extack) 1593 { 1594 bool symmetric = rxfh->input_xfrm == RXH_XFRM_SYM_OR_XOR; 1595 struct mlx5e_priv *priv = netdev_priv(dev); 1596 u8 hfunc = rxfh->hfunc; 1597 int err; 1598 1599 mutex_lock(&priv->state_lock); 1600 1601 err = mlx5e_rx_res_rss_set_rxfh(priv->rx_res, rxfh->rss_context, 1602 rxfh->indir, rxfh->key, 1603 hfunc == ETH_RSS_HASH_NO_CHANGE ? NULL : &hfunc, 1604 rxfh->input_xfrm == RXH_XFRM_NO_CHANGE ? NULL : &symmetric); 1605 1606 mutex_unlock(&priv->state_lock); 1607 return err; 1608 } 1609 1610 static int mlx5e_remove_rxfh_context(struct net_device *dev, 1611 struct ethtool_rxfh_context *ctx, 1612 u32 rss_context, 1613 struct netlink_ext_ack *extack) 1614 { 1615 struct mlx5e_priv *priv = netdev_priv(dev); 1616 int err; 1617 1618 mutex_lock(&priv->state_lock); 1619 err = mlx5e_rx_res_rss_destroy(priv->rx_res, rss_context); 1620 mutex_unlock(&priv->state_lock); 1621 return err; 1622 } 1623 1624 #define MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC 100 1625 #define MLX5E_PFC_PREVEN_TOUT_MAX_MSEC 8000 1626 #define MLX5E_PFC_PREVEN_MINOR_PRECENT 85 1627 #define MLX5E_PFC_PREVEN_TOUT_MIN_MSEC 80 1628 #define MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout) \ 1629 max_t(u16, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, \ 1630 (critical_tout * MLX5E_PFC_PREVEN_MINOR_PRECENT) / 100) 1631 1632 static int mlx5e_get_pfc_prevention_tout(struct net_device *netdev, 1633 u16 *pfc_prevention_tout) 1634 { 1635 struct mlx5e_priv *priv = netdev_priv(netdev); 1636 struct mlx5_core_dev *mdev = priv->mdev; 1637 1638 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) || 1639 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect)) 1640 return -EOPNOTSUPP; 1641 1642 return mlx5_query_port_stall_watermark(mdev, pfc_prevention_tout, NULL); 1643 } 1644 1645 static int mlx5e_set_pfc_prevention_tout(struct net_device *netdev, 1646 u16 pfc_preven) 1647 { 1648 struct mlx5e_priv *priv = netdev_priv(netdev); 1649 struct mlx5_core_dev *mdev = priv->mdev; 1650 u16 critical_tout; 1651 u16 minor; 1652 1653 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) || 1654 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect)) 1655 return -EOPNOTSUPP; 1656 1657 critical_tout = (pfc_preven == PFC_STORM_PREVENTION_AUTO) ? 1658 MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC : 1659 pfc_preven; 1660 1661 if (critical_tout != PFC_STORM_PREVENTION_DISABLE && 1662 (critical_tout > MLX5E_PFC_PREVEN_TOUT_MAX_MSEC || 1663 critical_tout < MLX5E_PFC_PREVEN_TOUT_MIN_MSEC)) { 1664 netdev_info(netdev, "%s: pfc prevention tout not in range (%d-%d)\n", 1665 __func__, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, 1666 MLX5E_PFC_PREVEN_TOUT_MAX_MSEC); 1667 return -EINVAL; 1668 } 1669 1670 minor = MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout); 1671 return mlx5_set_port_stall_watermark(mdev, critical_tout, 1672 minor); 1673 } 1674 1675 static int mlx5e_get_tunable(struct net_device *dev, 1676 const struct ethtool_tunable *tuna, 1677 void *data) 1678 { 1679 int err; 1680 1681 switch (tuna->id) { 1682 case ETHTOOL_PFC_PREVENTION_TOUT: 1683 err = mlx5e_get_pfc_prevention_tout(dev, data); 1684 break; 1685 default: 1686 err = -EINVAL; 1687 break; 1688 } 1689 1690 return err; 1691 } 1692 1693 static int mlx5e_set_tunable(struct net_device *dev, 1694 const struct ethtool_tunable *tuna, 1695 const void *data) 1696 { 1697 struct mlx5e_priv *priv = netdev_priv(dev); 1698 int err; 1699 1700 mutex_lock(&priv->state_lock); 1701 1702 switch (tuna->id) { 1703 case ETHTOOL_PFC_PREVENTION_TOUT: 1704 err = mlx5e_set_pfc_prevention_tout(dev, *(u16 *)data); 1705 break; 1706 default: 1707 err = -EINVAL; 1708 break; 1709 } 1710 1711 mutex_unlock(&priv->state_lock); 1712 return err; 1713 } 1714 1715 static void mlx5e_get_pause_stats(struct net_device *netdev, 1716 struct ethtool_pause_stats *pause_stats) 1717 { 1718 struct mlx5e_priv *priv = netdev_priv(netdev); 1719 1720 mlx5e_stats_pause_get(priv, pause_stats); 1721 } 1722 1723 static void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv, 1724 struct ethtool_pauseparam *pauseparam) 1725 { 1726 struct mlx5_core_dev *mdev = priv->mdev; 1727 int err; 1728 1729 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause, 1730 &pauseparam->tx_pause); 1731 if (err) { 1732 netdev_err(priv->netdev, "%s: mlx5_query_port_pause failed:0x%x\n", 1733 __func__, err); 1734 } 1735 } 1736 1737 static void mlx5e_get_pauseparam(struct net_device *netdev, 1738 struct ethtool_pauseparam *pauseparam) 1739 { 1740 struct mlx5e_priv *priv = netdev_priv(netdev); 1741 1742 mlx5e_ethtool_get_pauseparam(priv, pauseparam); 1743 } 1744 1745 static int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv, 1746 struct ethtool_pauseparam *pauseparam) 1747 { 1748 struct mlx5_core_dev *mdev = priv->mdev; 1749 int err; 1750 1751 if (!MLX5_CAP_GEN(mdev, vport_group_manager)) 1752 return -EOPNOTSUPP; 1753 1754 if (pauseparam->autoneg) 1755 return -EINVAL; 1756 1757 err = mlx5_set_port_pause(mdev, 1758 pauseparam->rx_pause ? 1 : 0, 1759 pauseparam->tx_pause ? 1 : 0); 1760 if (err) { 1761 netdev_err(priv->netdev, "%s: mlx5_set_port_pause failed:0x%x\n", 1762 __func__, err); 1763 } 1764 1765 return err; 1766 } 1767 1768 static int mlx5e_set_pauseparam(struct net_device *netdev, 1769 struct ethtool_pauseparam *pauseparam) 1770 { 1771 struct mlx5e_priv *priv = netdev_priv(netdev); 1772 1773 return mlx5e_ethtool_set_pauseparam(priv, pauseparam); 1774 } 1775 1776 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv, 1777 struct kernel_ethtool_ts_info *info) 1778 { 1779 struct mlx5_core_dev *mdev = priv->mdev; 1780 1781 info->phc_index = mlx5_clock_get_ptp_index(mdev); 1782 1783 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) || 1784 info->phc_index == -1) 1785 return 0; 1786 1787 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE | 1788 SOF_TIMESTAMPING_TX_SOFTWARE | 1789 SOF_TIMESTAMPING_RX_HARDWARE | 1790 SOF_TIMESTAMPING_RAW_HARDWARE; 1791 1792 info->tx_types = BIT(HWTSTAMP_TX_OFF) | 1793 BIT(HWTSTAMP_TX_ON); 1794 1795 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | 1796 BIT(HWTSTAMP_FILTER_ALL); 1797 1798 return 0; 1799 } 1800 1801 static int mlx5e_get_ts_info(struct net_device *dev, 1802 struct kernel_ethtool_ts_info *info) 1803 { 1804 struct mlx5e_priv *priv = netdev_priv(dev); 1805 1806 return mlx5e_ethtool_get_ts_info(priv, info); 1807 } 1808 1809 static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev) 1810 { 1811 __u32 ret = 0; 1812 1813 if (MLX5_CAP_GEN(mdev, wol_g)) 1814 ret |= WAKE_MAGIC; 1815 1816 if (MLX5_CAP_GEN(mdev, wol_s)) 1817 ret |= WAKE_MAGICSECURE; 1818 1819 if (MLX5_CAP_GEN(mdev, wol_a)) 1820 ret |= WAKE_ARP; 1821 1822 if (MLX5_CAP_GEN(mdev, wol_b)) 1823 ret |= WAKE_BCAST; 1824 1825 if (MLX5_CAP_GEN(mdev, wol_m)) 1826 ret |= WAKE_MCAST; 1827 1828 if (MLX5_CAP_GEN(mdev, wol_u)) 1829 ret |= WAKE_UCAST; 1830 1831 if (MLX5_CAP_GEN(mdev, wol_p)) 1832 ret |= WAKE_PHY; 1833 1834 return ret; 1835 } 1836 1837 static __u32 mlx5e_reformat_wol_mode_mlx5_to_linux(u8 mode) 1838 { 1839 __u32 ret = 0; 1840 1841 if (mode & MLX5_WOL_MAGIC) 1842 ret |= WAKE_MAGIC; 1843 1844 if (mode & MLX5_WOL_SECURED_MAGIC) 1845 ret |= WAKE_MAGICSECURE; 1846 1847 if (mode & MLX5_WOL_ARP) 1848 ret |= WAKE_ARP; 1849 1850 if (mode & MLX5_WOL_BROADCAST) 1851 ret |= WAKE_BCAST; 1852 1853 if (mode & MLX5_WOL_MULTICAST) 1854 ret |= WAKE_MCAST; 1855 1856 if (mode & MLX5_WOL_UNICAST) 1857 ret |= WAKE_UCAST; 1858 1859 if (mode & MLX5_WOL_PHY_ACTIVITY) 1860 ret |= WAKE_PHY; 1861 1862 return ret; 1863 } 1864 1865 static u8 mlx5e_reformat_wol_mode_linux_to_mlx5(__u32 mode) 1866 { 1867 u8 ret = 0; 1868 1869 if (mode & WAKE_MAGIC) 1870 ret |= MLX5_WOL_MAGIC; 1871 1872 if (mode & WAKE_MAGICSECURE) 1873 ret |= MLX5_WOL_SECURED_MAGIC; 1874 1875 if (mode & WAKE_ARP) 1876 ret |= MLX5_WOL_ARP; 1877 1878 if (mode & WAKE_BCAST) 1879 ret |= MLX5_WOL_BROADCAST; 1880 1881 if (mode & WAKE_MCAST) 1882 ret |= MLX5_WOL_MULTICAST; 1883 1884 if (mode & WAKE_UCAST) 1885 ret |= MLX5_WOL_UNICAST; 1886 1887 if (mode & WAKE_PHY) 1888 ret |= MLX5_WOL_PHY_ACTIVITY; 1889 1890 return ret; 1891 } 1892 1893 static void mlx5e_get_wol(struct net_device *netdev, 1894 struct ethtool_wolinfo *wol) 1895 { 1896 struct mlx5e_priv *priv = netdev_priv(netdev); 1897 struct mlx5_core_dev *mdev = priv->mdev; 1898 u8 mlx5_wol_mode; 1899 int err; 1900 1901 memset(wol, 0, sizeof(*wol)); 1902 1903 wol->supported = mlx5e_get_wol_supported(mdev); 1904 if (!wol->supported) 1905 return; 1906 1907 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode); 1908 if (err) 1909 return; 1910 1911 wol->wolopts = mlx5e_reformat_wol_mode_mlx5_to_linux(mlx5_wol_mode); 1912 } 1913 1914 static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 1915 { 1916 struct mlx5e_priv *priv = netdev_priv(netdev); 1917 struct mlx5_core_dev *mdev = priv->mdev; 1918 __u32 wol_supported = mlx5e_get_wol_supported(mdev); 1919 u32 mlx5_wol_mode; 1920 1921 if (!wol_supported) 1922 return -EOPNOTSUPP; 1923 1924 if (wol->wolopts & ~wol_supported) 1925 return -EINVAL; 1926 1927 mlx5_wol_mode = mlx5e_reformat_wol_mode_linux_to_mlx5(wol->wolopts); 1928 1929 return mlx5_set_port_wol(mdev, mlx5_wol_mode); 1930 } 1931 1932 static void mlx5e_get_fec_stats(struct net_device *netdev, 1933 struct ethtool_fec_stats *fec_stats, 1934 struct ethtool_fec_hist *hist) 1935 { 1936 struct mlx5e_priv *priv = netdev_priv(netdev); 1937 1938 mlx5e_stats_fec_get(priv, fec_stats, hist); 1939 } 1940 1941 static int mlx5e_get_fecparam(struct net_device *netdev, 1942 struct ethtool_fecparam *fecparam) 1943 { 1944 struct mlx5e_priv *priv = netdev_priv(netdev); 1945 struct mlx5_core_dev *mdev = priv->mdev; 1946 u16 fec_configured; 1947 u32 fec_active; 1948 int err; 1949 1950 err = mlx5e_get_fec_mode(mdev, &fec_active, &fec_configured); 1951 1952 if (err) 1953 return err; 1954 1955 fecparam->active_fec = pplm2ethtool_fec((unsigned long)fec_active, 1956 sizeof(unsigned long) * BITS_PER_BYTE); 1957 1958 if (!fecparam->active_fec) 1959 return -EOPNOTSUPP; 1960 1961 fecparam->fec = pplm2ethtool_fec((unsigned long)fec_configured, 1962 sizeof(unsigned long) * BITS_PER_BYTE); 1963 1964 return 0; 1965 } 1966 1967 static int mlx5e_set_fecparam(struct net_device *netdev, 1968 struct ethtool_fecparam *fecparam) 1969 { 1970 struct mlx5e_priv *priv = netdev_priv(netdev); 1971 struct mlx5_core_dev *mdev = priv->mdev; 1972 unsigned long fec_bitmap; 1973 u16 fec_policy = 0; 1974 int mode; 1975 int err; 1976 1977 bitmap_from_arr32(&fec_bitmap, &fecparam->fec, sizeof(fecparam->fec) * BITS_PER_BYTE); 1978 if (bitmap_weight(&fec_bitmap, ETHTOOL_FEC_LLRS_BIT + 1) > 1) 1979 return -EOPNOTSUPP; 1980 1981 for (mode = 0; mode < ARRAY_SIZE(pplm_fec_2_ethtool); mode++) { 1982 if (!(pplm_fec_2_ethtool[mode] & fecparam->fec)) 1983 continue; 1984 fec_policy |= (1 << mode); 1985 break; 1986 } 1987 1988 err = mlx5e_set_fec_mode(mdev, fec_policy); 1989 1990 if (err) 1991 return err; 1992 1993 mlx5_toggle_port_link(mdev); 1994 1995 return 0; 1996 } 1997 1998 static int mlx5e_set_phys_id(struct net_device *dev, 1999 enum ethtool_phys_id_state state) 2000 { 2001 struct mlx5e_priv *priv = netdev_priv(dev); 2002 struct mlx5_core_dev *mdev = priv->mdev; 2003 u16 beacon_duration; 2004 2005 if (!MLX5_CAP_GEN(mdev, beacon_led)) 2006 return -EOPNOTSUPP; 2007 2008 switch (state) { 2009 case ETHTOOL_ID_ACTIVE: 2010 beacon_duration = MLX5_BEACON_DURATION_INF; 2011 break; 2012 case ETHTOOL_ID_INACTIVE: 2013 beacon_duration = MLX5_BEACON_DURATION_OFF; 2014 break; 2015 default: 2016 return -EOPNOTSUPP; 2017 } 2018 2019 return mlx5_set_port_beacon(mdev, beacon_duration); 2020 } 2021 2022 static int mlx5e_get_module_info(struct net_device *netdev, 2023 struct ethtool_modinfo *modinfo) 2024 { 2025 struct mlx5e_priv *priv = netdev_priv(netdev); 2026 struct mlx5_core_dev *dev = priv->mdev; 2027 int size_read = 0; 2028 u8 data[4] = {0}; 2029 2030 size_read = mlx5_query_module_eeprom(dev, 0, 2, data, NULL); 2031 if (size_read < 2) 2032 return -EIO; 2033 2034 /* data[0] = identifier byte */ 2035 switch (data[0]) { 2036 case MLX5_MODULE_ID_QSFP: 2037 modinfo->type = ETH_MODULE_SFF_8436; 2038 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN; 2039 break; 2040 case MLX5_MODULE_ID_QSFP_PLUS: 2041 case MLX5_MODULE_ID_QSFP28: 2042 /* data[1] = revision id */ 2043 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) { 2044 modinfo->type = ETH_MODULE_SFF_8636; 2045 modinfo->eeprom_len = ETH_MODULE_SFF_8636_MAX_LEN; 2046 } else { 2047 modinfo->type = ETH_MODULE_SFF_8436; 2048 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN; 2049 } 2050 break; 2051 case MLX5_MODULE_ID_SFP: 2052 modinfo->type = ETH_MODULE_SFF_8472; 2053 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 2054 break; 2055 default: 2056 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n", 2057 __func__, data[0]); 2058 return -EINVAL; 2059 } 2060 2061 return 0; 2062 } 2063 2064 static int mlx5e_get_module_eeprom(struct net_device *netdev, 2065 struct ethtool_eeprom *ee, 2066 u8 *data) 2067 { 2068 struct mlx5e_priv *priv = netdev_priv(netdev); 2069 struct mlx5_core_dev *mdev = priv->mdev; 2070 int offset = ee->offset; 2071 int size_read; 2072 u8 status = 0; 2073 int i = 0; 2074 2075 if (!ee->len) 2076 return -EINVAL; 2077 2078 memset(data, 0, ee->len); 2079 2080 while (i < ee->len) { 2081 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i, 2082 data + i, &status); 2083 if (!size_read) 2084 /* Done reading */ 2085 return 0; 2086 2087 if (size_read < 0) { 2088 netdev_err(netdev, 2089 "%s: mlx5_query_eeprom failed:0x%x, status %u\n", 2090 __func__, size_read, status); 2091 return size_read; 2092 } 2093 2094 i += size_read; 2095 offset += size_read; 2096 } 2097 2098 return 0; 2099 } 2100 2101 static int mlx5e_get_module_eeprom_by_page(struct net_device *netdev, 2102 const struct ethtool_module_eeprom *page_data, 2103 struct netlink_ext_ack *extack) 2104 { 2105 struct mlx5e_priv *priv = netdev_priv(netdev); 2106 struct mlx5_module_eeprom_query_params query; 2107 struct mlx5_core_dev *mdev = priv->mdev; 2108 u8 *data = page_data->data; 2109 int size_read; 2110 u8 status = 0; 2111 int i = 0; 2112 2113 if (!page_data->length) 2114 return -EINVAL; 2115 2116 memset(data, 0, page_data->length); 2117 2118 query.offset = page_data->offset; 2119 query.i2c_address = page_data->i2c_address; 2120 query.bank = page_data->bank; 2121 query.page = page_data->page; 2122 while (i < page_data->length) { 2123 query.size = page_data->length - i; 2124 size_read = mlx5_query_module_eeprom_by_page(mdev, &query, 2125 data + i, &status); 2126 2127 /* Done reading, return how many bytes was read */ 2128 if (!size_read) 2129 return i; 2130 2131 if (size_read < 0) { 2132 NL_SET_ERR_MSG_FMT_MOD( 2133 extack, 2134 "Query module eeprom by page failed, read %u bytes, err %d, status %u", 2135 i, size_read, status); 2136 return size_read; 2137 } 2138 2139 i += size_read; 2140 query.offset += size_read; 2141 } 2142 2143 return i; 2144 } 2145 2146 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv, 2147 struct ethtool_flash *flash) 2148 { 2149 struct mlx5_core_dev *mdev = priv->mdev; 2150 struct net_device *dev = priv->netdev; 2151 const struct firmware *fw; 2152 int err; 2153 2154 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS) 2155 return -EOPNOTSUPP; 2156 2157 err = request_firmware_direct(&fw, flash->data, &dev->dev); 2158 if (err) 2159 return err; 2160 2161 err = mlx5_firmware_flash(mdev, fw, NULL); 2162 release_firmware(fw); 2163 2164 return err; 2165 } 2166 2167 static int mlx5e_flash_device(struct net_device *dev, 2168 struct ethtool_flash *flash) 2169 { 2170 struct mlx5e_priv *priv = netdev_priv(dev); 2171 2172 return mlx5e_ethtool_flash_device(priv, flash); 2173 } 2174 2175 static int set_pflag_cqe_based_moder(struct net_device *netdev, bool enable, 2176 bool is_rx_cq) 2177 { 2178 struct mlx5e_priv *priv = netdev_priv(netdev); 2179 u8 cq_period_mode, current_cq_period_mode; 2180 struct mlx5e_params new_params; 2181 2182 if (enable && !MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2183 return -EOPNOTSUPP; 2184 2185 cq_period_mode = mlx5e_dim_cq_period_mode(enable); 2186 2187 current_cq_period_mode = is_rx_cq ? 2188 priv->channels.params.rx_cq_moderation.cq_period_mode : 2189 priv->channels.params.tx_cq_moderation.cq_period_mode; 2190 2191 if (cq_period_mode == current_cq_period_mode) 2192 return 0; 2193 2194 new_params = priv->channels.params; 2195 if (is_rx_cq) { 2196 mlx5e_reset_rx_channels_moderation(&priv->channels, cq_period_mode, 2197 false, true); 2198 mlx5e_channels_rx_toggle_dim(&priv->channels); 2199 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_RX_CQE_BASED_MODER, 2200 cq_period_mode); 2201 } else { 2202 mlx5e_reset_tx_channels_moderation(&priv->channels, cq_period_mode, 2203 false, true); 2204 mlx5e_channels_tx_toggle_dim(&priv->channels); 2205 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_TX_CQE_BASED_MODER, 2206 cq_period_mode); 2207 } 2208 2209 /* Update pflags of existing channels without resetting them */ 2210 return mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, false); 2211 } 2212 2213 static int set_pflag_tx_cqe_based_moder(struct net_device *netdev, bool enable) 2214 { 2215 return set_pflag_cqe_based_moder(netdev, enable, false); 2216 } 2217 2218 static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable) 2219 { 2220 return set_pflag_cqe_based_moder(netdev, enable, true); 2221 } 2222 2223 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val, bool rx_filter) 2224 { 2225 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS); 2226 struct mlx5e_params new_params; 2227 int err = 0; 2228 2229 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression)) 2230 return new_val ? -EOPNOTSUPP : 0; 2231 2232 if (curr_val == new_val) 2233 return 0; 2234 2235 if (new_val && !mlx5e_profile_feature_cap(priv->profile, PTP_RX) && rx_filter) { 2236 netdev_err(priv->netdev, 2237 "Profile doesn't support enabling of CQE compression while hardware time-stamping is enabled.\n"); 2238 return -EINVAL; 2239 } 2240 2241 if (priv->channels.params.packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) { 2242 netdev_warn(priv->netdev, "Can't set CQE compression with HW-GRO, disable it first.\n"); 2243 return -EINVAL; 2244 } 2245 2246 new_params = priv->channels.params; 2247 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val); 2248 if (rx_filter) 2249 new_params.ptp_rx = new_val; 2250 2251 if (new_params.ptp_rx == priv->channels.params.ptp_rx) 2252 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true); 2253 else 2254 err = mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx, 2255 &new_params.ptp_rx, true); 2256 if (err) 2257 return err; 2258 2259 netdev_dbg(priv->netdev, "MLX5E: RxCqeCmprss was turned %s\n", 2260 MLX5E_GET_PFLAG(&priv->channels.params, 2261 MLX5E_PFLAG_RX_CQE_COMPRESS) ? "ON" : "OFF"); 2262 2263 return 0; 2264 } 2265 2266 static int set_pflag_rx_cqe_compress(struct net_device *netdev, 2267 bool enable) 2268 { 2269 struct mlx5e_priv *priv = netdev_priv(netdev); 2270 struct mlx5_core_dev *mdev = priv->mdev; 2271 bool rx_filter; 2272 int err; 2273 2274 if (!MLX5_CAP_GEN(mdev, cqe_compression)) 2275 return -EOPNOTSUPP; 2276 2277 rx_filter = priv->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE; 2278 err = mlx5e_modify_rx_cqe_compression_locked(priv, enable, rx_filter); 2279 if (err) 2280 return err; 2281 2282 priv->channels.params.rx_cqe_compress_def = enable; 2283 2284 return 0; 2285 } 2286 2287 static int set_pflag_rx_striding_rq(struct net_device *netdev, bool enable) 2288 { 2289 struct mlx5e_priv *priv = netdev_priv(netdev); 2290 struct mlx5_core_dev *mdev = priv->mdev; 2291 struct mlx5e_params new_params; 2292 2293 if (enable) { 2294 /* Checking the regular RQ here; mlx5e_validate_xsk_param called 2295 * from mlx5e_open_xsk will check for each XSK queue, and 2296 * mlx5e_safe_switch_params will be reverted if any check fails. 2297 */ 2298 int err = mlx5e_mpwrq_validate_regular(mdev, &priv->channels.params); 2299 2300 if (err) 2301 return err; 2302 } else if (priv->channels.params.packet_merge.type != MLX5E_PACKET_MERGE_NONE) { 2303 netdev_warn(netdev, "Can't set legacy RQ with HW-GRO/LRO, disable them first\n"); 2304 return -EINVAL; 2305 } 2306 2307 new_params = priv->channels.params; 2308 2309 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_RX_STRIDING_RQ, enable); 2310 mlx5e_set_rq_type(mdev, &new_params); 2311 2312 return mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true); 2313 } 2314 2315 static int set_pflag_rx_no_csum_complete(struct net_device *netdev, bool enable) 2316 { 2317 struct mlx5e_priv *priv = netdev_priv(netdev); 2318 struct mlx5e_channels *channels = &priv->channels; 2319 struct mlx5e_channel *c; 2320 int i; 2321 2322 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || 2323 priv->channels.params.xdp_prog) 2324 return 0; 2325 2326 for (i = 0; i < channels->num; i++) { 2327 c = channels->c[i]; 2328 __assign_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state, 2329 enable); 2330 } 2331 2332 return 0; 2333 } 2334 2335 static int set_pflag_tx_mpwqe_common(struct net_device *netdev, u32 flag, bool enable) 2336 { 2337 struct mlx5e_priv *priv = netdev_priv(netdev); 2338 struct mlx5_core_dev *mdev = priv->mdev; 2339 struct mlx5e_params new_params; 2340 2341 if (enable && !mlx5e_tx_mpwqe_supported(mdev)) 2342 return -EOPNOTSUPP; 2343 2344 new_params = priv->channels.params; 2345 2346 MLX5E_SET_PFLAG(&new_params, flag, enable); 2347 2348 return mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true); 2349 } 2350 2351 static int set_pflag_xdp_tx_mpwqe(struct net_device *netdev, bool enable) 2352 { 2353 return set_pflag_tx_mpwqe_common(netdev, MLX5E_PFLAG_XDP_TX_MPWQE, enable); 2354 } 2355 2356 static int set_pflag_skb_tx_mpwqe(struct net_device *netdev, bool enable) 2357 { 2358 return set_pflag_tx_mpwqe_common(netdev, MLX5E_PFLAG_SKB_TX_MPWQE, enable); 2359 } 2360 2361 static int set_pflag_tx_port_ts(struct net_device *netdev, bool enable) 2362 { 2363 struct mlx5e_priv *priv = netdev_priv(netdev); 2364 struct mlx5_core_dev *mdev = priv->mdev; 2365 struct mlx5e_params new_params; 2366 int err; 2367 2368 if (!MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn) || 2369 !MLX5_CAP_GEN_2(mdev, ts_cqe_metadata_size2wqe_counter)) 2370 return -EOPNOTSUPP; 2371 2372 /* Don't allow changing the PTP state if HTB offload is active, because 2373 * the numeration of the QoS SQs will change, while per-queue qdiscs are 2374 * attached. 2375 */ 2376 if (mlx5e_selq_is_htb_enabled(&priv->selq)) { 2377 netdev_err(priv->netdev, "%s: HTB offload is active, cannot change the PTP state\n", 2378 __func__); 2379 return -EINVAL; 2380 } 2381 2382 new_params = priv->channels.params; 2383 /* Don't allow enabling TX-port-TS if MQPRIO mode channel offload is 2384 * active, since it defines explicitly which TC accepts the packet. 2385 * This conflicts with TX-port-TS hijacking the PTP traffic to a specific 2386 * HW TX-queue. 2387 */ 2388 if (enable && new_params.mqprio.mode == TC_MQPRIO_MODE_CHANNEL) { 2389 netdev_err(priv->netdev, 2390 "%s: MQPRIO mode channel offload is active, cannot set the TX-port-TS\n", 2391 __func__); 2392 return -EINVAL; 2393 } 2394 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_TX_PORT_TS, enable); 2395 /* No need to verify SQ stop room as 2396 * ptpsq.txqsq.stop_room <= generic_sq->stop_room, and both 2397 * has the same log_sq_size. 2398 */ 2399 2400 err = mlx5e_safe_switch_params(priv, &new_params, 2401 mlx5e_update_tc_and_tx_queues_ctx, NULL, true); 2402 if (!err) 2403 priv->tx_ptp_opened = true; 2404 2405 return err; 2406 } 2407 2408 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS] = { 2409 { "rx_cqe_moder", set_pflag_rx_cqe_based_moder }, 2410 { "tx_cqe_moder", set_pflag_tx_cqe_based_moder }, 2411 { "rx_cqe_compress", set_pflag_rx_cqe_compress }, 2412 { "rx_striding_rq", set_pflag_rx_striding_rq }, 2413 { "rx_no_csum_complete", set_pflag_rx_no_csum_complete }, 2414 { "xdp_tx_mpwqe", set_pflag_xdp_tx_mpwqe }, 2415 { "skb_tx_mpwqe", set_pflag_skb_tx_mpwqe }, 2416 { "tx_port_ts", set_pflag_tx_port_ts }, 2417 }; 2418 2419 static int mlx5e_handle_pflag(struct net_device *netdev, 2420 u32 wanted_flags, 2421 enum mlx5e_priv_flag flag) 2422 { 2423 struct mlx5e_priv *priv = netdev_priv(netdev); 2424 bool enable = !!(wanted_flags & BIT(flag)); 2425 u32 changes = wanted_flags ^ priv->channels.params.pflags; 2426 int err; 2427 2428 if (!(changes & BIT(flag))) 2429 return 0; 2430 2431 err = mlx5e_priv_flags[flag].handler(netdev, enable); 2432 if (err) { 2433 netdev_err(netdev, "%s private flag '%s' failed err %d\n", 2434 enable ? "Enable" : "Disable", mlx5e_priv_flags[flag].name, err); 2435 return err; 2436 } 2437 2438 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable); 2439 return 0; 2440 } 2441 2442 static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags) 2443 { 2444 struct mlx5e_priv *priv = netdev_priv(netdev); 2445 enum mlx5e_priv_flag pflag; 2446 int err; 2447 2448 mutex_lock(&priv->state_lock); 2449 2450 for (pflag = 0; pflag < MLX5E_NUM_PFLAGS; pflag++) { 2451 err = mlx5e_handle_pflag(netdev, pflags, pflag); 2452 if (err) 2453 break; 2454 } 2455 2456 mutex_unlock(&priv->state_lock); 2457 2458 /* Need to fix some features.. */ 2459 netdev_update_features(netdev); 2460 2461 return err; 2462 } 2463 2464 static u32 mlx5e_get_priv_flags(struct net_device *netdev) 2465 { 2466 struct mlx5e_priv *priv = netdev_priv(netdev); 2467 2468 return priv->channels.params.pflags; 2469 } 2470 2471 static int mlx5e_get_rxfh_fields(struct net_device *dev, 2472 struct ethtool_rxfh_fields *info) 2473 { 2474 struct mlx5e_priv *priv = netdev_priv(dev); 2475 2476 return mlx5e_ethtool_get_rxfh_fields(priv, info); 2477 } 2478 2479 static int mlx5e_set_rxfh_fields(struct net_device *dev, 2480 const struct ethtool_rxfh_fields *cmd, 2481 struct netlink_ext_ack *extack) 2482 { 2483 struct mlx5e_priv *priv = netdev_priv(dev); 2484 2485 return mlx5e_ethtool_set_rxfh_fields(priv, cmd, extack); 2486 } 2487 2488 static u32 mlx5e_get_rx_ring_count(struct net_device *dev) 2489 { 2490 struct mlx5e_priv *priv = netdev_priv(dev); 2491 2492 return priv->channels.params.num_channels; 2493 } 2494 2495 static int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, 2496 u32 *rule_locs) 2497 { 2498 struct mlx5e_priv *priv = netdev_priv(dev); 2499 2500 return mlx5e_ethtool_get_rxnfc(priv, info, rule_locs); 2501 } 2502 2503 static int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2504 { 2505 struct mlx5e_priv *priv = netdev_priv(dev); 2506 2507 return mlx5e_ethtool_set_rxnfc(priv, cmd); 2508 } 2509 2510 static int query_port_status_opcode(struct mlx5_core_dev *mdev, u32 *status_opcode) 2511 { 2512 struct mlx5_ifc_pddr_troubleshooting_page_bits *pddr_troubleshooting_page; 2513 u32 in[MLX5_ST_SZ_DW(pddr_reg)] = {}; 2514 u32 out[MLX5_ST_SZ_DW(pddr_reg)]; 2515 int err; 2516 2517 MLX5_SET(pddr_reg, in, local_port, 1); 2518 MLX5_SET(pddr_reg, in, page_select, 2519 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE); 2520 2521 pddr_troubleshooting_page = MLX5_ADDR_OF(pddr_reg, in, page_data); 2522 MLX5_SET(pddr_troubleshooting_page, pddr_troubleshooting_page, 2523 group_opcode, MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR); 2524 err = mlx5_core_access_reg(mdev, in, sizeof(in), out, 2525 sizeof(out), MLX5_REG_PDDR, 0, 0); 2526 if (err) 2527 return err; 2528 2529 pddr_troubleshooting_page = MLX5_ADDR_OF(pddr_reg, out, page_data); 2530 *status_opcode = MLX5_GET(pddr_troubleshooting_page, pddr_troubleshooting_page, 2531 status_opcode); 2532 return 0; 2533 } 2534 2535 struct mlx5e_ethtool_link_ext_state_opcode_mapping { 2536 u32 status_opcode; 2537 enum ethtool_link_ext_state link_ext_state; 2538 u8 link_ext_substate; 2539 }; 2540 2541 static const struct mlx5e_ethtool_link_ext_state_opcode_mapping 2542 mlx5e_link_ext_state_opcode_map[] = { 2543 /* States relating to the autonegotiation or issues therein */ 2544 {2, ETHTOOL_LINK_EXT_STATE_AUTONEG, 2545 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED}, 2546 {3, ETHTOOL_LINK_EXT_STATE_AUTONEG, 2547 ETHTOOL_LINK_EXT_SUBSTATE_AN_ACK_NOT_RECEIVED}, 2548 {4, ETHTOOL_LINK_EXT_STATE_AUTONEG, 2549 ETHTOOL_LINK_EXT_SUBSTATE_AN_NEXT_PAGE_EXCHANGE_FAILED}, 2550 {36, ETHTOOL_LINK_EXT_STATE_AUTONEG, 2551 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED_FORCE_MODE}, 2552 {38, ETHTOOL_LINK_EXT_STATE_AUTONEG, 2553 ETHTOOL_LINK_EXT_SUBSTATE_AN_FEC_MISMATCH_DURING_OVERRIDE}, 2554 {39, ETHTOOL_LINK_EXT_STATE_AUTONEG, 2555 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_HCD}, 2556 2557 /* Failure during link training */ 2558 {5, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE, 2559 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_FRAME_LOCK_NOT_ACQUIRED}, 2560 {6, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE, 2561 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_INHIBIT_TIMEOUT}, 2562 {7, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE, 2563 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_PARTNER_DID_NOT_SET_RECEIVER_READY}, 2564 {8, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE, 0}, 2565 {14, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE, 2566 ETHTOOL_LINK_EXT_SUBSTATE_LT_REMOTE_FAULT}, 2567 2568 /* Logical mismatch in physical coding sublayer or forward error correction sublayer */ 2569 {9, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH, 2570 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_BLOCK_LOCK}, 2571 {10, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH, 2572 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_AM_LOCK}, 2573 {11, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH, 2574 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_GET_ALIGN_STATUS}, 2575 {12, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH, 2576 ETHTOOL_LINK_EXT_SUBSTATE_LLM_FC_FEC_IS_NOT_LOCKED}, 2577 {13, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH, 2578 ETHTOOL_LINK_EXT_SUBSTATE_LLM_RS_FEC_IS_NOT_LOCKED}, 2579 2580 /* Signal integrity issues */ 2581 {15, ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY, 0}, 2582 {17, ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY, 2583 ETHTOOL_LINK_EXT_SUBSTATE_BSI_LARGE_NUMBER_OF_PHYSICAL_ERRORS}, 2584 {42, ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY, 2585 ETHTOOL_LINK_EXT_SUBSTATE_BSI_UNSUPPORTED_RATE}, 2586 2587 /* No cable connected */ 2588 {1024, ETHTOOL_LINK_EXT_STATE_NO_CABLE, 0}, 2589 2590 /* Failure is related to cable, e.g., unsupported cable */ 2591 {16, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE, 2592 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE}, 2593 {20, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE, 2594 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE}, 2595 {29, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE, 2596 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE}, 2597 {1025, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE, 2598 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE}, 2599 {1029, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE, 2600 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE}, 2601 {1031, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE, 0}, 2602 2603 /* Failure is related to EEPROM, e.g., failure during reading or parsing the data */ 2604 {1027, ETHTOOL_LINK_EXT_STATE_EEPROM_ISSUE, 0}, 2605 2606 /* Failure during calibration algorithm */ 2607 {23, ETHTOOL_LINK_EXT_STATE_CALIBRATION_FAILURE, 0}, 2608 2609 /* The hardware is not able to provide the power required from cable or module */ 2610 {1032, ETHTOOL_LINK_EXT_STATE_POWER_BUDGET_EXCEEDED, 0}, 2611 2612 /* The module is overheated */ 2613 {1030, ETHTOOL_LINK_EXT_STATE_OVERHEAT, 0}, 2614 }; 2615 2616 static void 2617 mlx5e_set_link_ext_state(struct mlx5e_ethtool_link_ext_state_opcode_mapping 2618 link_ext_state_mapping, 2619 struct ethtool_link_ext_state_info *link_ext_state_info) 2620 { 2621 switch (link_ext_state_mapping.link_ext_state) { 2622 case ETHTOOL_LINK_EXT_STATE_AUTONEG: 2623 link_ext_state_info->autoneg = 2624 link_ext_state_mapping.link_ext_substate; 2625 break; 2626 case ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE: 2627 link_ext_state_info->link_training = 2628 link_ext_state_mapping.link_ext_substate; 2629 break; 2630 case ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH: 2631 link_ext_state_info->link_logical_mismatch = 2632 link_ext_state_mapping.link_ext_substate; 2633 break; 2634 case ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY: 2635 link_ext_state_info->bad_signal_integrity = 2636 link_ext_state_mapping.link_ext_substate; 2637 break; 2638 case ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE: 2639 link_ext_state_info->cable_issue = 2640 link_ext_state_mapping.link_ext_substate; 2641 break; 2642 default: 2643 break; 2644 } 2645 2646 link_ext_state_info->link_ext_state = link_ext_state_mapping.link_ext_state; 2647 } 2648 2649 static int 2650 mlx5e_get_link_ext_state(struct net_device *dev, 2651 struct ethtool_link_ext_state_info *link_ext_state_info) 2652 { 2653 struct mlx5e_ethtool_link_ext_state_opcode_mapping link_ext_state_mapping; 2654 struct mlx5e_priv *priv = netdev_priv(dev); 2655 u32 status_opcode = 0; 2656 int i; 2657 2658 /* Exit without data if the interface state is OK, since no extended data is 2659 * available in such case 2660 */ 2661 if (netif_carrier_ok(dev)) 2662 return -ENODATA; 2663 2664 if (query_port_status_opcode(priv->mdev, &status_opcode) || 2665 !status_opcode) 2666 return -ENODATA; 2667 2668 for (i = 0; i < ARRAY_SIZE(mlx5e_link_ext_state_opcode_map); i++) { 2669 link_ext_state_mapping = mlx5e_link_ext_state_opcode_map[i]; 2670 if (link_ext_state_mapping.status_opcode == status_opcode) { 2671 mlx5e_set_link_ext_state(link_ext_state_mapping, 2672 link_ext_state_info); 2673 return 0; 2674 } 2675 } 2676 2677 return -ENODATA; 2678 } 2679 2680 static void mlx5e_get_eth_phy_stats(struct net_device *netdev, 2681 struct ethtool_eth_phy_stats *phy_stats) 2682 { 2683 struct mlx5e_priv *priv = netdev_priv(netdev); 2684 2685 mlx5e_stats_eth_phy_get(priv, phy_stats); 2686 } 2687 2688 static void mlx5e_get_eth_mac_stats(struct net_device *netdev, 2689 struct ethtool_eth_mac_stats *mac_stats) 2690 { 2691 struct mlx5e_priv *priv = netdev_priv(netdev); 2692 2693 mlx5e_stats_eth_mac_get(priv, mac_stats); 2694 } 2695 2696 static void mlx5e_get_eth_ctrl_stats(struct net_device *netdev, 2697 struct ethtool_eth_ctrl_stats *ctrl_stats) 2698 { 2699 struct mlx5e_priv *priv = netdev_priv(netdev); 2700 2701 mlx5e_stats_eth_ctrl_get(priv, ctrl_stats); 2702 } 2703 2704 static void mlx5e_get_rmon_stats(struct net_device *netdev, 2705 struct ethtool_rmon_stats *rmon_stats, 2706 const struct ethtool_rmon_hist_range **ranges) 2707 { 2708 struct mlx5e_priv *priv = netdev_priv(netdev); 2709 2710 mlx5e_stats_rmon_get(priv, rmon_stats, ranges); 2711 } 2712 2713 static void mlx5e_get_ts_stats(struct net_device *netdev, 2714 struct ethtool_ts_stats *ts_stats) 2715 { 2716 struct mlx5e_priv *priv = netdev_priv(netdev); 2717 2718 mlx5e_stats_ts_get(priv, ts_stats); 2719 } 2720 2721 const struct ethtool_ops mlx5e_ethtool_ops = { 2722 .cap_link_lanes_supported = true, 2723 .rxfh_per_ctx_fields = true, 2724 .rxfh_per_ctx_key = true, 2725 .rxfh_max_num_contexts = MLX5E_MAX_NUM_RSS, 2726 .op_needs_rtnl = ETHTOOL_OP_NEEDS_RTNL_SCHANNELS | 2727 ETHTOOL_OP_NEEDS_RTNL_SRINGPARAM | 2728 ETHTOOL_OP_NEEDS_RTNL_SPFLAGS | 2729 ETHTOOL_OP_NEEDS_RTNL_GLINK, 2730 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2731 ETHTOOL_COALESCE_MAX_FRAMES | 2732 ETHTOOL_COALESCE_USE_ADAPTIVE | 2733 ETHTOOL_COALESCE_USE_CQE, 2734 .supported_input_xfrm = RXH_XFRM_SYM_OR_XOR, 2735 .supported_ring_params = ETHTOOL_RING_USE_TCP_DATA_SPLIT | 2736 ETHTOOL_RING_USE_HDS_THRS, 2737 .rxfh_indir_space = MLX5E_MAX_INDIR_RQT_SIZE, 2738 .get_drvinfo = mlx5e_get_drvinfo, 2739 .get_link = ethtool_op_get_link, 2740 .get_link_ext_state = mlx5e_get_link_ext_state, 2741 .get_strings = mlx5e_get_strings, 2742 .get_sset_count = mlx5e_get_sset_count, 2743 .get_ethtool_stats = mlx5e_get_ethtool_stats, 2744 .get_ringparam = mlx5e_get_ringparam, 2745 .set_ringparam = mlx5e_set_ringparam, 2746 .get_channels = mlx5e_get_channels, 2747 .set_channels = mlx5e_set_channels, 2748 .get_coalesce = mlx5e_get_coalesce, 2749 .set_coalesce = mlx5e_set_coalesce, 2750 .get_per_queue_coalesce = mlx5e_get_per_queue_coalesce, 2751 .set_per_queue_coalesce = mlx5e_set_per_queue_coalesce, 2752 .get_link_ksettings = mlx5e_get_link_ksettings, 2753 .set_link_ksettings = mlx5e_set_link_ksettings, 2754 .get_rxfh_key_size = mlx5e_get_rxfh_key_size, 2755 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size, 2756 .get_rxfh = mlx5e_get_rxfh, 2757 .set_rxfh = mlx5e_set_rxfh, 2758 .get_rxfh_fields = mlx5e_get_rxfh_fields, 2759 .set_rxfh_fields = mlx5e_set_rxfh_fields, 2760 .create_rxfh_context = mlx5e_create_rxfh_context, 2761 .modify_rxfh_context = mlx5e_modify_rxfh_context, 2762 .remove_rxfh_context = mlx5e_remove_rxfh_context, 2763 .get_rxnfc = mlx5e_get_rxnfc, 2764 .set_rxnfc = mlx5e_set_rxnfc, 2765 .get_rx_ring_count = mlx5e_get_rx_ring_count, 2766 .get_tunable = mlx5e_get_tunable, 2767 .set_tunable = mlx5e_set_tunable, 2768 .get_pause_stats = mlx5e_get_pause_stats, 2769 .get_pauseparam = mlx5e_get_pauseparam, 2770 .set_pauseparam = mlx5e_set_pauseparam, 2771 .get_ts_info = mlx5e_get_ts_info, 2772 .set_phys_id = mlx5e_set_phys_id, 2773 .get_wol = mlx5e_get_wol, 2774 .set_wol = mlx5e_set_wol, 2775 .get_module_info = mlx5e_get_module_info, 2776 .get_module_eeprom = mlx5e_get_module_eeprom, 2777 .get_module_eeprom_by_page = mlx5e_get_module_eeprom_by_page, 2778 .flash_device = mlx5e_flash_device, 2779 .get_priv_flags = mlx5e_get_priv_flags, 2780 .set_priv_flags = mlx5e_set_priv_flags, 2781 .self_test = mlx5e_self_test, 2782 .get_fec_stats = mlx5e_get_fec_stats, 2783 .get_fecparam = mlx5e_get_fecparam, 2784 .set_fecparam = mlx5e_set_fecparam, 2785 .get_eth_phy_stats = mlx5e_get_eth_phy_stats, 2786 .get_eth_mac_stats = mlx5e_get_eth_mac_stats, 2787 .get_eth_ctrl_stats = mlx5e_get_eth_ctrl_stats, 2788 .get_rmon_stats = mlx5e_get_rmon_stats, 2789 .get_ts_stats = mlx5e_get_ts_stats, 2790 .get_link_ext_stats = mlx5e_get_link_ext_stats 2791 }; 2792