1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/mlx5/port.h> 34 #include "mlx5_core.h" 35 36 /* calling with verbose false will not print error to log */ 37 int mlx5_access_reg(struct mlx5_core_dev *dev, void *data_in, int size_in, 38 void *data_out, int size_out, u16 reg_id, int arg, 39 int write, bool verbose) 40 { 41 int outlen = MLX5_ST_SZ_BYTES(access_register_out) + size_out; 42 int inlen = MLX5_ST_SZ_BYTES(access_register_in) + size_in; 43 int err = -ENOMEM; 44 u32 *out = NULL; 45 u32 *in = NULL; 46 void *data; 47 48 in = kvzalloc(inlen, GFP_KERNEL); 49 out = kvzalloc(outlen, GFP_KERNEL); 50 if (!in || !out) 51 goto out; 52 53 data = MLX5_ADDR_OF(access_register_in, in, register_data); 54 memcpy(data, data_in, size_in); 55 56 MLX5_SET(access_register_in, in, opcode, MLX5_CMD_OP_ACCESS_REG); 57 MLX5_SET(access_register_in, in, op_mod, !write); 58 MLX5_SET(access_register_in, in, argument, arg); 59 MLX5_SET(access_register_in, in, register_id, reg_id); 60 61 err = mlx5_cmd_do(dev, in, inlen, out, outlen); 62 if (verbose) 63 err = mlx5_cmd_check(dev, err, in, out); 64 if (err) 65 goto out; 66 67 data = MLX5_ADDR_OF(access_register_out, out, register_data); 68 memcpy(data_out, data, size_out); 69 70 out: 71 kvfree(out); 72 kvfree(in); 73 return err; 74 } 75 EXPORT_SYMBOL_GPL(mlx5_access_reg); 76 77 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, 78 int size_in, void *data_out, int size_out, 79 u16 reg_id, int arg, int write) 80 { 81 return mlx5_access_reg(dev, data_in, size_in, data_out, size_out, 82 reg_id, arg, write, true); 83 } 84 EXPORT_SYMBOL_GPL(mlx5_core_access_reg); 85 86 int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, u8 feature_group, 87 u8 access_reg_group) 88 { 89 u32 in[MLX5_ST_SZ_DW(pcam_reg)] = {0}; 90 int sz = MLX5_ST_SZ_BYTES(pcam_reg); 91 92 MLX5_SET(pcam_reg, in, feature_group, feature_group); 93 MLX5_SET(pcam_reg, in, access_reg_group, access_reg_group); 94 95 return mlx5_core_access_reg(dev, in, sz, pcam, sz, MLX5_REG_PCAM, 0, 0); 96 } 97 98 int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcam, u8 feature_group, 99 u8 access_reg_group) 100 { 101 u32 in[MLX5_ST_SZ_DW(mcam_reg)] = {0}; 102 int sz = MLX5_ST_SZ_BYTES(mcam_reg); 103 104 MLX5_SET(mcam_reg, in, feature_group, feature_group); 105 MLX5_SET(mcam_reg, in, access_reg_group, access_reg_group); 106 107 return mlx5_core_access_reg(dev, in, sz, mcam, sz, MLX5_REG_MCAM, 0, 0); 108 } 109 110 int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam, 111 u8 feature_group, u8 access_reg_group) 112 { 113 u32 in[MLX5_ST_SZ_DW(qcam_reg)] = {}; 114 int sz = MLX5_ST_SZ_BYTES(qcam_reg); 115 116 MLX5_SET(qcam_reg, in, feature_group, feature_group); 117 MLX5_SET(qcam_reg, in, access_reg_group, access_reg_group); 118 119 return mlx5_core_access_reg(mdev, in, sz, qcam, sz, MLX5_REG_QCAM, 0, 0); 120 } 121 122 struct mlx5_reg_pcap { 123 u8 rsvd0; 124 u8 port_num; 125 u8 rsvd1[2]; 126 __be32 caps_127_96; 127 __be32 caps_95_64; 128 __be32 caps_63_32; 129 __be32 caps_31_0; 130 }; 131 132 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps) 133 { 134 struct mlx5_reg_pcap in; 135 struct mlx5_reg_pcap out; 136 137 memset(&in, 0, sizeof(in)); 138 in.caps_127_96 = cpu_to_be32(caps); 139 in.port_num = port_num; 140 141 return mlx5_core_access_reg(dev, &in, sizeof(in), &out, 142 sizeof(out), MLX5_REG_PCAP, 0, 1); 143 } 144 EXPORT_SYMBOL_GPL(mlx5_set_port_caps); 145 146 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys, 147 int ptys_size, int proto_mask, 148 u8 local_port, u8 plane_index) 149 { 150 u32 in[MLX5_ST_SZ_DW(ptys_reg)] = {0}; 151 152 MLX5_SET(ptys_reg, in, local_port, local_port); 153 MLX5_SET(ptys_reg, in, plane_ind, plane_index); 154 MLX5_SET(ptys_reg, in, proto_mask, proto_mask); 155 return mlx5_core_access_reg(dev, in, sizeof(in), ptys, 156 ptys_size, MLX5_REG_PTYS, 0, 0); 157 } 158 EXPORT_SYMBOL_GPL(mlx5_query_port_ptys); 159 160 int mlx5_set_port_beacon(struct mlx5_core_dev *dev, u16 beacon_duration) 161 { 162 u32 in[MLX5_ST_SZ_DW(mlcr_reg)] = {0}; 163 u32 out[MLX5_ST_SZ_DW(mlcr_reg)]; 164 165 MLX5_SET(mlcr_reg, in, local_port, 1); 166 MLX5_SET(mlcr_reg, in, beacon_duration, beacon_duration); 167 return mlx5_core_access_reg(dev, in, sizeof(in), out, 168 sizeof(out), MLX5_REG_MLCR, 0, 1); 169 } 170 171 int mlx5_query_ib_port_oper(struct mlx5_core_dev *dev, u16 *link_width_oper, 172 u16 *proto_oper, u8 local_port, u8 plane_index) 173 { 174 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 175 int err; 176 177 err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_IB, 178 local_port, plane_index); 179 if (err) 180 return err; 181 182 *link_width_oper = MLX5_GET(ptys_reg, out, ib_link_width_oper); 183 *proto_oper = MLX5_GET(ptys_reg, out, ib_proto_oper); 184 185 return 0; 186 } 187 EXPORT_SYMBOL(mlx5_query_ib_port_oper); 188 189 /* This function should be used after setting a port register only */ 190 void mlx5_toggle_port_link(struct mlx5_core_dev *dev) 191 { 192 enum mlx5_port_status ps; 193 194 mlx5_query_port_admin_status(dev, &ps); 195 mlx5_set_port_admin_status(dev, MLX5_PORT_DOWN); 196 if (ps == MLX5_PORT_UP) 197 mlx5_set_port_admin_status(dev, MLX5_PORT_UP); 198 } 199 200 int mlx5_set_port_admin_status(struct mlx5_core_dev *dev, 201 enum mlx5_port_status status) 202 { 203 u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0}; 204 u32 out[MLX5_ST_SZ_DW(paos_reg)]; 205 206 MLX5_SET(paos_reg, in, local_port, 1); 207 MLX5_SET(paos_reg, in, admin_status, status); 208 MLX5_SET(paos_reg, in, ase, 1); 209 return mlx5_core_access_reg(dev, in, sizeof(in), out, 210 sizeof(out), MLX5_REG_PAOS, 0, 1); 211 } 212 213 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev, 214 enum mlx5_port_status *status) 215 { 216 u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0}; 217 u32 out[MLX5_ST_SZ_DW(paos_reg)]; 218 int err; 219 220 MLX5_SET(paos_reg, in, local_port, 1); 221 err = mlx5_core_access_reg(dev, in, sizeof(in), out, 222 sizeof(out), MLX5_REG_PAOS, 0, 0); 223 if (err) 224 return err; 225 *status = MLX5_GET(paos_reg, out, admin_status); 226 return 0; 227 } 228 229 static void mlx5_query_port_mtu(struct mlx5_core_dev *dev, u16 *admin_mtu, 230 u16 *max_mtu, u16 *oper_mtu, u8 port) 231 { 232 u32 in[MLX5_ST_SZ_DW(pmtu_reg)] = {0}; 233 u32 out[MLX5_ST_SZ_DW(pmtu_reg)]; 234 235 MLX5_SET(pmtu_reg, in, local_port, port); 236 mlx5_core_access_reg(dev, in, sizeof(in), out, 237 sizeof(out), MLX5_REG_PMTU, 0, 0); 238 239 if (max_mtu) 240 *max_mtu = MLX5_GET(pmtu_reg, out, max_mtu); 241 if (oper_mtu) 242 *oper_mtu = MLX5_GET(pmtu_reg, out, oper_mtu); 243 if (admin_mtu) 244 *admin_mtu = MLX5_GET(pmtu_reg, out, admin_mtu); 245 } 246 247 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port) 248 { 249 u32 in[MLX5_ST_SZ_DW(pmtu_reg)] = {0}; 250 u32 out[MLX5_ST_SZ_DW(pmtu_reg)]; 251 252 MLX5_SET(pmtu_reg, in, admin_mtu, mtu); 253 MLX5_SET(pmtu_reg, in, local_port, port); 254 return mlx5_core_access_reg(dev, in, sizeof(in), out, 255 sizeof(out), MLX5_REG_PMTU, 0, 1); 256 } 257 258 void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, u16 *max_mtu, 259 u8 port) 260 { 261 mlx5_query_port_mtu(dev, NULL, max_mtu, NULL, port); 262 } 263 EXPORT_SYMBOL_GPL(mlx5_query_port_max_mtu); 264 265 void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, u16 *oper_mtu, 266 u8 port) 267 { 268 mlx5_query_port_mtu(dev, NULL, NULL, oper_mtu, port); 269 } 270 EXPORT_SYMBOL_GPL(mlx5_query_port_oper_mtu); 271 272 int mlx5_query_module_num(struct mlx5_core_dev *dev, int *module_num) 273 { 274 u32 in[MLX5_ST_SZ_DW(pmlp_reg)] = {0}; 275 u32 out[MLX5_ST_SZ_DW(pmlp_reg)]; 276 int err; 277 278 MLX5_SET(pmlp_reg, in, local_port, 1); 279 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), 280 MLX5_REG_PMLP, 0, 0); 281 if (err) 282 return err; 283 284 *module_num = MLX5_GET(lane_2_module_mapping, 285 MLX5_ADDR_OF(pmlp_reg, out, lane0_module_mapping), 286 module); 287 288 return 0; 289 } 290 291 static int mlx5_query_module_id(struct mlx5_core_dev *dev, int module_num, 292 u8 *module_id, u8 *status) 293 { 294 u32 in[MLX5_ST_SZ_DW(mcia_reg)] = {}; 295 u32 out[MLX5_ST_SZ_DW(mcia_reg)]; 296 int err; 297 u8 *ptr; 298 299 MLX5_SET(mcia_reg, in, i2c_device_address, MLX5_I2C_ADDR_LOW); 300 MLX5_SET(mcia_reg, in, module, module_num); 301 MLX5_SET(mcia_reg, in, device_address, 0); 302 MLX5_SET(mcia_reg, in, page_number, 0); 303 MLX5_SET(mcia_reg, in, size, 1); 304 MLX5_SET(mcia_reg, in, l, 0); 305 306 err = mlx5_core_access_reg(dev, in, sizeof(in), out, 307 sizeof(out), MLX5_REG_MCIA, 0, 0); 308 if (err) 309 return err; 310 311 if (MLX5_GET(mcia_reg, out, status)) { 312 if (status) 313 *status = MLX5_GET(mcia_reg, out, status); 314 return -EIO; 315 } 316 317 ptr = MLX5_ADDR_OF(mcia_reg, out, dword_0); 318 319 *module_id = ptr[0]; 320 321 return 0; 322 } 323 324 static int mlx5_qsfp_eeprom_page(u16 offset) 325 { 326 if (offset < MLX5_EEPROM_PAGE_LENGTH) 327 /* Addresses between 0-255 - page 00 */ 328 return 0; 329 330 /* Addresses between 256 - 639 belongs to pages 01, 02 and 03 331 * For example, offset = 400 belongs to page 02: 332 * 1 + ((400 - 256)/128) = 2 333 */ 334 return 1 + ((offset - MLX5_EEPROM_PAGE_LENGTH) / 335 MLX5_EEPROM_HIGH_PAGE_LENGTH); 336 } 337 338 static int mlx5_qsfp_eeprom_high_page_offset(int page_num) 339 { 340 if (!page_num) /* Page 0 always start from low page */ 341 return 0; 342 343 /* High page */ 344 return page_num * MLX5_EEPROM_HIGH_PAGE_LENGTH; 345 } 346 347 static void mlx5_qsfp_eeprom_params_set(u16 *i2c_addr, int *page_num, u16 *offset) 348 { 349 *i2c_addr = MLX5_I2C_ADDR_LOW; 350 *page_num = mlx5_qsfp_eeprom_page(*offset); 351 *offset -= mlx5_qsfp_eeprom_high_page_offset(*page_num); 352 } 353 354 static void mlx5_sfp_eeprom_params_set(u16 *i2c_addr, int *page_num, u16 *offset) 355 { 356 *i2c_addr = MLX5_I2C_ADDR_LOW; 357 *page_num = 0; 358 359 if (*offset < MLX5_EEPROM_PAGE_LENGTH) 360 return; 361 362 *i2c_addr = MLX5_I2C_ADDR_HIGH; 363 *offset -= MLX5_EEPROM_PAGE_LENGTH; 364 } 365 366 static int mlx5_mcia_max_bytes(struct mlx5_core_dev *dev) 367 { 368 /* mcia supports either 12 dwords or 32 dwords */ 369 return (MLX5_CAP_MCAM_FEATURE(dev, mcia_32dwords) ? 32 : 12) * sizeof(u32); 370 } 371 372 static int mlx5_query_mcia(struct mlx5_core_dev *dev, 373 struct mlx5_module_eeprom_query_params *params, 374 u8 *data, u8 *status) 375 { 376 u32 in[MLX5_ST_SZ_DW(mcia_reg)] = {}; 377 u32 out[MLX5_ST_SZ_DW(mcia_reg)]; 378 void *ptr; 379 u16 size; 380 int err; 381 382 size = min_t(int, params->size, mlx5_mcia_max_bytes(dev)); 383 384 MLX5_SET(mcia_reg, in, l, 0); 385 MLX5_SET(mcia_reg, in, size, size); 386 MLX5_SET(mcia_reg, in, module, params->module_number); 387 MLX5_SET(mcia_reg, in, device_address, params->offset); 388 MLX5_SET(mcia_reg, in, page_number, params->page); 389 MLX5_SET(mcia_reg, in, i2c_device_address, params->i2c_address); 390 391 err = mlx5_core_access_reg(dev, in, sizeof(in), out, 392 sizeof(out), MLX5_REG_MCIA, 0, 0); 393 if (err) 394 return err; 395 396 *status = MLX5_GET(mcia_reg, out, status); 397 if (*status) 398 return -EIO; 399 400 ptr = MLX5_ADDR_OF(mcia_reg, out, dword_0); 401 memcpy(data, ptr, size); 402 403 return size; 404 } 405 406 int mlx5_query_module_eeprom(struct mlx5_core_dev *dev, 407 u16 offset, u16 size, u8 *data, u8 *status) 408 { 409 struct mlx5_module_eeprom_query_params query = {0}; 410 u8 module_id; 411 int err; 412 413 err = mlx5_query_module_num(dev, &query.module_number); 414 if (err) 415 return err; 416 417 err = mlx5_query_module_id(dev, query.module_number, &module_id, 418 status); 419 if (err) 420 return err; 421 422 switch (module_id) { 423 case MLX5_MODULE_ID_SFP: 424 mlx5_sfp_eeprom_params_set(&query.i2c_address, &query.page, &offset); 425 break; 426 case MLX5_MODULE_ID_QSFP: 427 case MLX5_MODULE_ID_QSFP_PLUS: 428 case MLX5_MODULE_ID_QSFP28: 429 mlx5_qsfp_eeprom_params_set(&query.i2c_address, &query.page, &offset); 430 break; 431 default: 432 mlx5_core_err(dev, "Module ID not recognized: 0x%x\n", module_id); 433 return -EINVAL; 434 } 435 436 if (offset + size > MLX5_EEPROM_PAGE_LENGTH) 437 /* Cross pages read, read until offset 256 in low page */ 438 size = MLX5_EEPROM_PAGE_LENGTH - offset; 439 440 query.size = size; 441 query.offset = offset; 442 443 return mlx5_query_mcia(dev, &query, data, status); 444 } 445 446 int mlx5_query_module_eeprom_by_page(struct mlx5_core_dev *dev, 447 struct mlx5_module_eeprom_query_params *params, 448 u8 *data, u8 *status) 449 { 450 int err; 451 452 err = mlx5_query_module_num(dev, ¶ms->module_number); 453 if (err) 454 return err; 455 456 if (params->i2c_address != MLX5_I2C_ADDR_HIGH && 457 params->i2c_address != MLX5_I2C_ADDR_LOW) { 458 mlx5_core_err(dev, "I2C address not recognized: 0x%x\n", params->i2c_address); 459 return -EINVAL; 460 } 461 462 return mlx5_query_mcia(dev, params, data, status); 463 } 464 465 static int mlx5_query_port_pvlc(struct mlx5_core_dev *dev, u32 *pvlc, 466 int pvlc_size, u8 local_port) 467 { 468 u32 in[MLX5_ST_SZ_DW(pvlc_reg)] = {0}; 469 470 MLX5_SET(pvlc_reg, in, local_port, local_port); 471 return mlx5_core_access_reg(dev, in, sizeof(in), pvlc, 472 pvlc_size, MLX5_REG_PVLC, 0, 0); 473 } 474 475 int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev, 476 u8 *vl_hw_cap, u8 local_port) 477 { 478 u32 out[MLX5_ST_SZ_DW(pvlc_reg)]; 479 int err; 480 481 err = mlx5_query_port_pvlc(dev, out, sizeof(out), local_port); 482 if (err) 483 return err; 484 485 *vl_hw_cap = MLX5_GET(pvlc_reg, out, vl_hw_cap); 486 487 return 0; 488 } 489 EXPORT_SYMBOL_GPL(mlx5_query_port_vl_hw_cap); 490 491 static int mlx5_query_pfcc_reg(struct mlx5_core_dev *dev, u32 *out, 492 u32 out_size) 493 { 494 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0}; 495 496 MLX5_SET(pfcc_reg, in, local_port, 1); 497 498 return mlx5_core_access_reg(dev, in, sizeof(in), out, 499 out_size, MLX5_REG_PFCC, 0, 0); 500 } 501 502 int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause) 503 { 504 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0}; 505 u32 out[MLX5_ST_SZ_DW(pfcc_reg)]; 506 507 MLX5_SET(pfcc_reg, in, local_port, 1); 508 MLX5_SET(pfcc_reg, in, pptx, tx_pause); 509 MLX5_SET(pfcc_reg, in, pprx, rx_pause); 510 511 return mlx5_core_access_reg(dev, in, sizeof(in), out, 512 sizeof(out), MLX5_REG_PFCC, 0, 1); 513 } 514 515 int mlx5_query_port_pause(struct mlx5_core_dev *dev, 516 u32 *rx_pause, u32 *tx_pause) 517 { 518 u32 out[MLX5_ST_SZ_DW(pfcc_reg)]; 519 int err; 520 521 err = mlx5_query_pfcc_reg(dev, out, sizeof(out)); 522 if (err) 523 return err; 524 525 if (rx_pause) 526 *rx_pause = MLX5_GET(pfcc_reg, out, pprx); 527 528 if (tx_pause) 529 *tx_pause = MLX5_GET(pfcc_reg, out, pptx); 530 531 return 0; 532 } 533 534 int mlx5_set_port_stall_watermark(struct mlx5_core_dev *dev, 535 u16 stall_critical_watermark, 536 u16 stall_minor_watermark) 537 { 538 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0}; 539 u32 out[MLX5_ST_SZ_DW(pfcc_reg)]; 540 541 MLX5_SET(pfcc_reg, in, local_port, 1); 542 MLX5_SET(pfcc_reg, in, pptx_mask_n, 1); 543 MLX5_SET(pfcc_reg, in, pprx_mask_n, 1); 544 MLX5_SET(pfcc_reg, in, ppan_mask_n, 1); 545 MLX5_SET(pfcc_reg, in, critical_stall_mask, 1); 546 MLX5_SET(pfcc_reg, in, minor_stall_mask, 1); 547 MLX5_SET(pfcc_reg, in, device_stall_critical_watermark, 548 stall_critical_watermark); 549 MLX5_SET(pfcc_reg, in, device_stall_minor_watermark, stall_minor_watermark); 550 551 return mlx5_core_access_reg(dev, in, sizeof(in), out, 552 sizeof(out), MLX5_REG_PFCC, 0, 1); 553 } 554 555 int mlx5_query_port_stall_watermark(struct mlx5_core_dev *dev, 556 u16 *stall_critical_watermark, 557 u16 *stall_minor_watermark) 558 { 559 u32 out[MLX5_ST_SZ_DW(pfcc_reg)]; 560 int err; 561 562 err = mlx5_query_pfcc_reg(dev, out, sizeof(out)); 563 if (err) 564 return err; 565 566 if (stall_critical_watermark) 567 *stall_critical_watermark = MLX5_GET(pfcc_reg, out, 568 device_stall_critical_watermark); 569 570 if (stall_minor_watermark) 571 *stall_minor_watermark = MLX5_GET(pfcc_reg, out, 572 device_stall_minor_watermark); 573 574 return 0; 575 } 576 577 int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx) 578 { 579 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0}; 580 u32 out[MLX5_ST_SZ_DW(pfcc_reg)]; 581 582 MLX5_SET(pfcc_reg, in, local_port, 1); 583 MLX5_SET(pfcc_reg, in, pfctx, pfc_en_tx); 584 MLX5_SET(pfcc_reg, in, pfcrx, pfc_en_rx); 585 MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_tx); 586 MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_rx); 587 588 return mlx5_core_access_reg(dev, in, sizeof(in), out, 589 sizeof(out), MLX5_REG_PFCC, 0, 1); 590 } 591 592 int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx) 593 { 594 u32 out[MLX5_ST_SZ_DW(pfcc_reg)]; 595 int err; 596 597 err = mlx5_query_pfcc_reg(dev, out, sizeof(out)); 598 if (err) 599 return err; 600 601 if (pfc_en_tx) 602 *pfc_en_tx = MLX5_GET(pfcc_reg, out, pfctx); 603 604 if (pfc_en_rx) 605 *pfc_en_rx = MLX5_GET(pfcc_reg, out, pfcrx); 606 607 return 0; 608 } 609 610 int mlx5_max_tc(struct mlx5_core_dev *mdev) 611 { 612 u8 num_tc = MLX5_CAP_GEN(mdev, max_tc) ? : 8; 613 614 return num_tc - 1; 615 } 616 617 int mlx5_query_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *out) 618 { 619 u32 in[MLX5_ST_SZ_DW(dcbx_param)] = {0}; 620 621 MLX5_SET(dcbx_param, in, port_number, 1); 622 623 return mlx5_core_access_reg(mdev, in, sizeof(in), out, 624 sizeof(in), MLX5_REG_DCBX_PARAM, 0, 0); 625 } 626 627 int mlx5_set_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *in) 628 { 629 u32 out[MLX5_ST_SZ_DW(dcbx_param)]; 630 631 MLX5_SET(dcbx_param, in, port_number, 1); 632 633 return mlx5_core_access_reg(mdev, in, sizeof(out), out, 634 sizeof(out), MLX5_REG_DCBX_PARAM, 0, 1); 635 } 636 637 int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc) 638 { 639 u32 in[MLX5_ST_SZ_DW(qtct_reg)] = {0}; 640 u32 out[MLX5_ST_SZ_DW(qtct_reg)]; 641 int err; 642 int i; 643 644 for (i = 0; i < 8; i++) { 645 if (prio_tc[i] > mlx5_max_tc(mdev)) 646 return -EINVAL; 647 648 MLX5_SET(qtct_reg, in, prio, i); 649 MLX5_SET(qtct_reg, in, tclass, prio_tc[i]); 650 651 err = mlx5_core_access_reg(mdev, in, sizeof(in), out, 652 sizeof(out), MLX5_REG_QTCT, 0, 1); 653 if (err) 654 return err; 655 } 656 657 return 0; 658 } 659 660 int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev, 661 u8 prio, u8 *tc) 662 { 663 u32 in[MLX5_ST_SZ_DW(qtct_reg)]; 664 u32 out[MLX5_ST_SZ_DW(qtct_reg)]; 665 int err; 666 667 memset(in, 0, sizeof(in)); 668 memset(out, 0, sizeof(out)); 669 670 MLX5_SET(qtct_reg, in, port_number, 1); 671 MLX5_SET(qtct_reg, in, prio, prio); 672 673 err = mlx5_core_access_reg(mdev, in, sizeof(in), out, 674 sizeof(out), MLX5_REG_QTCT, 0, 0); 675 if (!err) 676 *tc = MLX5_GET(qtct_reg, out, tclass); 677 678 return err; 679 } 680 681 static int mlx5_set_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *in, 682 int inlen) 683 { 684 u32 out[MLX5_ST_SZ_DW(qetc_reg)]; 685 686 if (!MLX5_CAP_GEN(mdev, ets)) 687 return -EOPNOTSUPP; 688 689 return mlx5_core_access_reg(mdev, in, inlen, out, sizeof(out), 690 MLX5_REG_QETCR, 0, 1); 691 } 692 693 static int mlx5_query_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *out, 694 int outlen) 695 { 696 u32 in[MLX5_ST_SZ_DW(qetc_reg)]; 697 698 if (!MLX5_CAP_GEN(mdev, ets)) 699 return -EOPNOTSUPP; 700 701 memset(in, 0, sizeof(in)); 702 return mlx5_core_access_reg(mdev, in, sizeof(in), out, outlen, 703 MLX5_REG_QETCR, 0, 0); 704 } 705 706 int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group) 707 { 708 u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0}; 709 int i; 710 711 for (i = 0; i <= mlx5_max_tc(mdev); i++) { 712 MLX5_SET(qetc_reg, in, tc_configuration[i].g, 1); 713 MLX5_SET(qetc_reg, in, tc_configuration[i].group, tc_group[i]); 714 } 715 716 return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in)); 717 } 718 719 int mlx5_query_port_tc_group(struct mlx5_core_dev *mdev, 720 u8 tc, u8 *tc_group) 721 { 722 u32 out[MLX5_ST_SZ_DW(qetc_reg)]; 723 void *ets_tcn_conf; 724 int err; 725 726 err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out)); 727 if (err) 728 return err; 729 730 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out, 731 tc_configuration[tc]); 732 733 *tc_group = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf, 734 group); 735 736 return 0; 737 } 738 739 int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw) 740 { 741 u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0}; 742 int i; 743 744 for (i = 0; i <= mlx5_max_tc(mdev); i++) { 745 MLX5_SET(qetc_reg, in, tc_configuration[i].b, 1); 746 MLX5_SET(qetc_reg, in, tc_configuration[i].bw_allocation, tc_bw[i]); 747 } 748 749 return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in)); 750 } 751 752 int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev, 753 u8 tc, u8 *bw_pct) 754 { 755 u32 out[MLX5_ST_SZ_DW(qetc_reg)]; 756 void *ets_tcn_conf; 757 int err; 758 759 err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out)); 760 if (err) 761 return err; 762 763 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out, 764 tc_configuration[tc]); 765 766 *bw_pct = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf, 767 bw_allocation); 768 769 return 0; 770 } 771 772 int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev, 773 u8 *max_bw_value, 774 u8 *max_bw_units) 775 { 776 u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0}; 777 void *ets_tcn_conf; 778 int i; 779 780 MLX5_SET(qetc_reg, in, port_number, 1); 781 782 for (i = 0; i <= mlx5_max_tc(mdev); i++) { 783 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, in, tc_configuration[i]); 784 785 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, r, 1); 786 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_units, 787 max_bw_units[i]); 788 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_value, 789 max_bw_value[i]); 790 } 791 792 return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in)); 793 } 794 795 int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev, 796 u8 *max_bw_value, 797 u8 *max_bw_units) 798 { 799 u32 out[MLX5_ST_SZ_DW(qetc_reg)]; 800 void *ets_tcn_conf; 801 int err; 802 int i; 803 804 err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out)); 805 if (err) 806 return err; 807 808 for (i = 0; i <= mlx5_max_tc(mdev); i++) { 809 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out, tc_configuration[i]); 810 811 max_bw_value[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf, 812 max_bw_value); 813 max_bw_units[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf, 814 max_bw_units); 815 } 816 817 return 0; 818 } 819 820 int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode) 821 { 822 u32 in[MLX5_ST_SZ_DW(set_wol_rol_in)] = {}; 823 824 MLX5_SET(set_wol_rol_in, in, opcode, MLX5_CMD_OP_SET_WOL_ROL); 825 MLX5_SET(set_wol_rol_in, in, wol_mode_valid, 1); 826 MLX5_SET(set_wol_rol_in, in, wol_mode, wol_mode); 827 return mlx5_cmd_exec_in(mdev, set_wol_rol, in); 828 } 829 830 int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode) 831 { 832 u32 out[MLX5_ST_SZ_DW(query_wol_rol_out)] = {}; 833 u32 in[MLX5_ST_SZ_DW(query_wol_rol_in)] = {}; 834 int err; 835 836 MLX5_SET(query_wol_rol_in, in, opcode, MLX5_CMD_OP_QUERY_WOL_ROL); 837 err = mlx5_cmd_exec_inout(mdev, query_wol_rol, in, out); 838 if (!err) 839 *wol_mode = MLX5_GET(query_wol_rol_out, out, wol_mode); 840 841 return err; 842 } 843 844 int mlx5_query_ports_check(struct mlx5_core_dev *mdev, u32 *out, int outlen) 845 { 846 u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {0}; 847 848 MLX5_SET(pcmr_reg, in, local_port, 1); 849 return mlx5_core_access_reg(mdev, in, sizeof(in), out, 850 outlen, MLX5_REG_PCMR, 0, 0); 851 } 852 853 int mlx5_set_ports_check(struct mlx5_core_dev *mdev, u32 *in, int inlen) 854 { 855 u32 out[MLX5_ST_SZ_DW(pcmr_reg)]; 856 857 return mlx5_core_access_reg(mdev, in, inlen, out, 858 sizeof(out), MLX5_REG_PCMR, 0, 1); 859 } 860 861 int mlx5_set_port_fcs(struct mlx5_core_dev *mdev, u8 enable) 862 { 863 u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {0}; 864 int err; 865 866 err = mlx5_query_ports_check(mdev, in, sizeof(in)); 867 if (err) 868 return err; 869 MLX5_SET(pcmr_reg, in, local_port, 1); 870 MLX5_SET(pcmr_reg, in, fcs_chk, enable); 871 return mlx5_set_ports_check(mdev, in, sizeof(in)); 872 } 873 874 void mlx5_query_port_fcs(struct mlx5_core_dev *mdev, bool *supported, 875 bool *enabled) 876 { 877 u32 out[MLX5_ST_SZ_DW(pcmr_reg)]; 878 /* Default values for FW which do not support MLX5_REG_PCMR */ 879 *supported = false; 880 *enabled = true; 881 882 if (!MLX5_CAP_GEN(mdev, ports_check)) 883 return; 884 885 if (mlx5_query_ports_check(mdev, out, sizeof(out))) 886 return; 887 888 *supported = !!(MLX5_GET(pcmr_reg, out, fcs_cap)); 889 *enabled = !!(MLX5_GET(pcmr_reg, out, fcs_chk)); 890 } 891 892 int mlx5_query_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size) 893 { 894 u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0}; 895 896 return mlx5_core_access_reg(mdev, in, sizeof(in), mtpps, 897 mtpps_size, MLX5_REG_MTPPS, 0, 0); 898 } 899 900 int mlx5_set_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size) 901 { 902 u32 out[MLX5_ST_SZ_DW(mtpps_reg)] = {0}; 903 904 return mlx5_core_access_reg(mdev, mtpps, mtpps_size, out, 905 sizeof(out), MLX5_REG_MTPPS, 0, 1); 906 } 907 908 int mlx5_query_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 *arm, u8 *mode) 909 { 910 u32 out[MLX5_ST_SZ_DW(mtppse_reg)] = {0}; 911 u32 in[MLX5_ST_SZ_DW(mtppse_reg)] = {0}; 912 int err = 0; 913 914 MLX5_SET(mtppse_reg, in, pin, pin); 915 916 err = mlx5_core_access_reg(mdev, in, sizeof(in), out, 917 sizeof(out), MLX5_REG_MTPPSE, 0, 0); 918 if (err) 919 return err; 920 921 *arm = MLX5_GET(mtppse_reg, in, event_arm); 922 *mode = MLX5_GET(mtppse_reg, in, event_generation_mode); 923 924 return err; 925 } 926 927 int mlx5_set_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 arm, u8 mode) 928 { 929 u32 out[MLX5_ST_SZ_DW(mtppse_reg)] = {0}; 930 u32 in[MLX5_ST_SZ_DW(mtppse_reg)] = {0}; 931 932 MLX5_SET(mtppse_reg, in, pin, pin); 933 MLX5_SET(mtppse_reg, in, event_arm, arm); 934 MLX5_SET(mtppse_reg, in, event_generation_mode, mode); 935 936 return mlx5_core_access_reg(mdev, in, sizeof(in), out, 937 sizeof(out), MLX5_REG_MTPPSE, 0, 1); 938 } 939 940 int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state) 941 { 942 u32 out[MLX5_ST_SZ_DW(qpts_reg)] = {}; 943 u32 in[MLX5_ST_SZ_DW(qpts_reg)] = {}; 944 int err; 945 946 MLX5_SET(qpts_reg, in, local_port, 1); 947 MLX5_SET(qpts_reg, in, trust_state, trust_state); 948 949 err = mlx5_core_access_reg(mdev, in, sizeof(in), out, 950 sizeof(out), MLX5_REG_QPTS, 0, 1); 951 return err; 952 } 953 954 int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state) 955 { 956 u32 out[MLX5_ST_SZ_DW(qpts_reg)] = {}; 957 u32 in[MLX5_ST_SZ_DW(qpts_reg)] = {}; 958 int err; 959 960 MLX5_SET(qpts_reg, in, local_port, 1); 961 962 err = mlx5_core_access_reg(mdev, in, sizeof(in), out, 963 sizeof(out), MLX5_REG_QPTS, 0, 0); 964 if (!err) 965 *trust_state = MLX5_GET(qpts_reg, out, trust_state); 966 967 return err; 968 } 969 970 int mlx5_query_port_buffer_ownership(struct mlx5_core_dev *mdev, 971 u8 *buffer_ownership) 972 { 973 u32 out[MLX5_ST_SZ_DW(pfcc_reg)] = {}; 974 int err; 975 976 if (!MLX5_CAP_PCAM_FEATURE(mdev, buffer_ownership)) { 977 *buffer_ownership = MLX5_BUF_OWNERSHIP_UNKNOWN; 978 return 0; 979 } 980 981 err = mlx5_query_pfcc_reg(mdev, out, sizeof(out)); 982 if (err) 983 return err; 984 985 *buffer_ownership = MLX5_GET(pfcc_reg, out, buf_ownership); 986 987 return 0; 988 } 989 990 int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, u8 dscp, u8 prio) 991 { 992 int sz = MLX5_ST_SZ_BYTES(qpdpm_reg); 993 void *qpdpm_dscp; 994 void *out; 995 void *in; 996 int err; 997 998 in = kzalloc(sz, GFP_KERNEL); 999 out = kzalloc(sz, GFP_KERNEL); 1000 if (!in || !out) { 1001 err = -ENOMEM; 1002 goto out; 1003 } 1004 1005 MLX5_SET(qpdpm_reg, in, local_port, 1); 1006 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 0); 1007 if (err) 1008 goto out; 1009 1010 memcpy(in, out, sz); 1011 MLX5_SET(qpdpm_reg, in, local_port, 1); 1012 1013 /* Update the corresponding dscp entry */ 1014 qpdpm_dscp = MLX5_ADDR_OF(qpdpm_reg, in, dscp[dscp]); 1015 MLX5_SET16(qpdpm_dscp_reg, qpdpm_dscp, prio, prio); 1016 MLX5_SET16(qpdpm_dscp_reg, qpdpm_dscp, e, 1); 1017 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 1); 1018 1019 out: 1020 kfree(in); 1021 kfree(out); 1022 return err; 1023 } 1024 1025 /* dscp2prio[i]: priority that dscp i mapped to */ 1026 #define MLX5E_SUPPORTED_DSCP 64 1027 int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio) 1028 { 1029 int sz = MLX5_ST_SZ_BYTES(qpdpm_reg); 1030 void *qpdpm_dscp; 1031 void *out; 1032 void *in; 1033 int err; 1034 int i; 1035 1036 in = kzalloc(sz, GFP_KERNEL); 1037 out = kzalloc(sz, GFP_KERNEL); 1038 if (!in || !out) { 1039 err = -ENOMEM; 1040 goto out; 1041 } 1042 1043 MLX5_SET(qpdpm_reg, in, local_port, 1); 1044 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 0); 1045 if (err) 1046 goto out; 1047 1048 for (i = 0; i < (MLX5E_SUPPORTED_DSCP); i++) { 1049 qpdpm_dscp = MLX5_ADDR_OF(qpdpm_reg, out, dscp[i]); 1050 dscp2prio[i] = MLX5_GET16(qpdpm_dscp_reg, qpdpm_dscp, prio); 1051 } 1052 1053 out: 1054 kfree(in); 1055 kfree(out); 1056 return err; 1057 } 1058 1059 /* speed in units of 1Mb */ 1060 static const struct mlx5_link_info mlx5e_link_info[MLX5E_LINK_MODES_NUMBER] = { 1061 [MLX5E_1000BASE_CX_SGMII] = {.speed = 1000, .lanes = 1}, 1062 [MLX5E_1000BASE_KX] = {.speed = 1000, .lanes = 1}, 1063 [MLX5E_10GBASE_CX4] = {.speed = 10000, .lanes = 4}, 1064 [MLX5E_10GBASE_KX4] = {.speed = 10000, .lanes = 4}, 1065 [MLX5E_10GBASE_KR] = {.speed = 10000, .lanes = 1}, 1066 [MLX5E_20GBASE_KR2] = {.speed = 20000, .lanes = 2}, 1067 [MLX5E_40GBASE_CR4] = {.speed = 40000, .lanes = 4}, 1068 [MLX5E_40GBASE_KR4] = {.speed = 40000, .lanes = 4}, 1069 [MLX5E_56GBASE_R4] = {.speed = 56000, .lanes = 4}, 1070 [MLX5E_10GBASE_CR] = {.speed = 10000, .lanes = 1}, 1071 [MLX5E_10GBASE_SR] = {.speed = 10000, .lanes = 1}, 1072 [MLX5E_10GBASE_ER] = {.speed = 10000, .lanes = 1}, 1073 [MLX5E_40GBASE_SR4] = {.speed = 40000, .lanes = 4}, 1074 [MLX5E_40GBASE_LR4] = {.speed = 40000, .lanes = 4}, 1075 [MLX5E_50GBASE_SR2] = {.speed = 50000, .lanes = 2}, 1076 [MLX5E_100GBASE_CR4] = {.speed = 100000, .lanes = 4}, 1077 [MLX5E_100GBASE_SR4] = {.speed = 100000, .lanes = 4}, 1078 [MLX5E_100GBASE_KR4] = {.speed = 100000, .lanes = 4}, 1079 [MLX5E_100GBASE_LR4] = {.speed = 100000, .lanes = 4}, 1080 [MLX5E_100BASE_TX] = {.speed = 100, .lanes = 1}, 1081 [MLX5E_1000BASE_T] = {.speed = 1000, .lanes = 1}, 1082 [MLX5E_10GBASE_T] = {.speed = 10000, .lanes = 1}, 1083 [MLX5E_25GBASE_CR] = {.speed = 25000, .lanes = 1}, 1084 [MLX5E_25GBASE_KR] = {.speed = 25000, .lanes = 1}, 1085 [MLX5E_25GBASE_SR] = {.speed = 25000, .lanes = 1}, 1086 [MLX5E_50GBASE_CR2] = {.speed = 50000, .lanes = 2}, 1087 [MLX5E_50GBASE_KR2] = {.speed = 50000, .lanes = 2}, 1088 }; 1089 1090 static const struct mlx5_link_info 1091 mlx5e_ext_link_info[MLX5E_EXT_LINK_MODES_NUMBER] = { 1092 [MLX5E_SGMII_100M] = {.speed = 100, .lanes = 1}, 1093 [MLX5E_1000BASE_X_SGMII] = {.speed = 1000, .lanes = 1}, 1094 [MLX5E_5GBASE_R] = {.speed = 5000, .lanes = 1}, 1095 [MLX5E_10GBASE_XFI_XAUI_1] = {.speed = 10000, .lanes = 1}, 1096 [MLX5E_40GBASE_XLAUI_4_XLPPI_4] = {.speed = 40000, .lanes = 4}, 1097 [MLX5E_25GAUI_1_25GBASE_CR_KR] = {.speed = 25000, .lanes = 1}, 1098 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2] = {.speed = 50000, .lanes = 2}, 1099 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR] = {.speed = 50000, .lanes = 1}, 1100 [MLX5E_CAUI_4_100GBASE_CR4_KR4] = {.speed = 100000, .lanes = 4}, 1101 [MLX5E_100GAUI_2_100GBASE_CR2_KR2] = {.speed = 100000, .lanes = 2}, 1102 [MLX5E_200GAUI_4_200GBASE_CR4_KR4] = {.speed = 200000, .lanes = 4}, 1103 [MLX5E_400GAUI_8_400GBASE_CR8] = {.speed = 400000, .lanes = 8}, 1104 [MLX5E_100GAUI_1_100GBASE_CR_KR] = {.speed = 100000, .lanes = 1}, 1105 [MLX5E_200GAUI_2_200GBASE_CR2_KR2] = {.speed = 200000, .lanes = 2}, 1106 [MLX5E_400GAUI_4_400GBASE_CR4_KR4] = {.speed = 400000, .lanes = 4}, 1107 [MLX5E_800GAUI_8_800GBASE_CR8_KR8] = {.speed = 800000, .lanes = 8}, 1108 [MLX5E_200GAUI_1_200GBASE_CR1_KR1] = {.speed = 200000, .lanes = 1}, 1109 [MLX5E_400GAUI_2_400GBASE_CR2_KR2] = {.speed = 400000, .lanes = 2}, 1110 [MLX5E_800GAUI_4_800GBASE_CR4_KR4] = {.speed = 800000, .lanes = 4}, 1111 [MLX5E_1600TAUI_8_1600TBASE_CR8_KR8] = {.speed = 1600000, .lanes = 8}, 1112 }; 1113 1114 int mlx5_port_query_eth_proto(struct mlx5_core_dev *dev, u8 port, bool ext, 1115 struct mlx5_port_eth_proto *eproto) 1116 { 1117 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 1118 int err; 1119 1120 if (!eproto) 1121 return -EINVAL; 1122 1123 err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_EN, port, 0); 1124 if (err) 1125 return err; 1126 1127 eproto->cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 1128 eth_proto_capability); 1129 eproto->admin = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_admin); 1130 eproto->oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 1131 return 0; 1132 } 1133 1134 bool mlx5_ptys_ext_supported(struct mlx5_core_dev *mdev) 1135 { 1136 struct mlx5_port_eth_proto eproto; 1137 int err; 1138 1139 if (MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet)) 1140 return true; 1141 1142 err = mlx5_port_query_eth_proto(mdev, 1, true, &eproto); 1143 if (err) 1144 return false; 1145 1146 return !!eproto.cap; 1147 } 1148 1149 static void mlx5e_port_get_link_mode_info_arr(struct mlx5_core_dev *mdev, 1150 const struct mlx5_link_info **arr, 1151 u32 *size, 1152 bool force_legacy) 1153 { 1154 bool ext = force_legacy ? false : mlx5_ptys_ext_supported(mdev); 1155 1156 *size = ext ? ARRAY_SIZE(mlx5e_ext_link_info) : 1157 ARRAY_SIZE(mlx5e_link_info); 1158 *arr = ext ? mlx5e_ext_link_info : mlx5e_link_info; 1159 } 1160 1161 const struct mlx5_link_info *mlx5_port_ptys2info(struct mlx5_core_dev *mdev, 1162 u32 eth_proto_oper, 1163 bool force_legacy) 1164 { 1165 unsigned long temp = eth_proto_oper; 1166 const struct mlx5_link_info *table; 1167 u32 max_size; 1168 int i; 1169 1170 mlx5e_port_get_link_mode_info_arr(mdev, &table, &max_size, 1171 force_legacy); 1172 i = find_first_bit(&temp, max_size); 1173 1174 /* mlx5e_link_info has holes. Check speed 1175 * is not zero as indication of one. 1176 */ 1177 if (i < max_size && table[i].speed) 1178 return &table[i]; 1179 1180 return NULL; 1181 } 1182 1183 u32 mlx5_port_info2linkmodes(struct mlx5_core_dev *mdev, 1184 struct mlx5_link_info *info, 1185 bool force_legacy) 1186 { 1187 const struct mlx5_link_info *table; 1188 u32 link_modes = 0; 1189 u32 max_size; 1190 int i; 1191 1192 mlx5e_port_get_link_mode_info_arr(mdev, &table, &max_size, 1193 force_legacy); 1194 for (i = 0; i < max_size; ++i) { 1195 if (table[i].speed == info->speed) { 1196 if (!info->lanes || table[i].lanes == info->lanes) 1197 link_modes |= MLX5E_PROT_MASK(i); 1198 } 1199 } 1200 return link_modes; 1201 } 1202 1203 int mlx5_port_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed) 1204 { 1205 const struct mlx5_link_info *table; 1206 struct mlx5_port_eth_proto eproto; 1207 u32 max_speed = 0; 1208 u32 max_size; 1209 bool ext; 1210 int err; 1211 int i; 1212 1213 ext = mlx5_ptys_ext_supported(mdev); 1214 err = mlx5_port_query_eth_proto(mdev, 1, ext, &eproto); 1215 if (err) 1216 return err; 1217 1218 mlx5e_port_get_link_mode_info_arr(mdev, &table, &max_size, false); 1219 for (i = 0; i < max_size; ++i) 1220 if (eproto.cap & MLX5E_PROT_MASK(i)) 1221 max_speed = max(max_speed, table[i].speed); 1222 1223 *speed = max_speed; 1224 return 0; 1225 } 1226 1227 int mlx5_query_mpir_reg(struct mlx5_core_dev *dev, u32 *mpir) 1228 { 1229 u32 in[MLX5_ST_SZ_DW(mpir_reg)] = {}; 1230 int sz = MLX5_ST_SZ_BYTES(mpir_reg); 1231 1232 MLX5_SET(mpir_reg, in, local_port, 1); 1233 1234 return mlx5_core_access_reg(dev, in, sz, mpir, sz, MLX5_REG_MPIR, 0, 0); 1235 } 1236