1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 /* Copyright (c) 2020, Mellanox Technologies inc. All rights reserved. */
3
4 #include <devlink.h>
5
6 #include "fw_reset.h"
7 #include "diag/fw_tracer.h"
8 #include "lib/tout.h"
9
10 enum {
11 MLX5_FW_RESET_FLAGS_RESET_REQUESTED,
12 MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST,
13 MLX5_FW_RESET_FLAGS_PENDING_COMP,
14 MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS,
15 MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED
16 };
17
18 struct mlx5_fw_reset {
19 struct mlx5_core_dev *dev;
20 struct mlx5_nb nb;
21 struct workqueue_struct *wq;
22 struct work_struct fw_live_patch_work;
23 struct work_struct reset_request_work;
24 struct work_struct reset_unload_work;
25 struct work_struct reset_reload_work;
26 struct work_struct reset_now_work;
27 struct work_struct reset_abort_work;
28 unsigned long reset_flags;
29 u8 reset_method;
30 struct timer_list timer;
31 struct completion done;
32 int ret;
33 };
34
35 enum {
36 MLX5_FW_RST_STATE_IDLE = 0,
37 MLX5_FW_RST_STATE_TOGGLE_REQ = 4,
38 MLX5_FW_RST_STATE_DROP_MODE = 5,
39 };
40
41 enum {
42 MLX5_RST_STATE_BIT_NUM = 12,
43 MLX5_RST_ACK_BIT_NUM = 22,
44 };
45
mlx5_get_fw_rst_state(struct mlx5_core_dev * dev)46 static u8 mlx5_get_fw_rst_state(struct mlx5_core_dev *dev)
47 {
48 return (ioread32be(&dev->iseg->initializing) >> MLX5_RST_STATE_BIT_NUM) & 0xF;
49 }
50
mlx5_set_fw_rst_ack(struct mlx5_core_dev * dev)51 static void mlx5_set_fw_rst_ack(struct mlx5_core_dev *dev)
52 {
53 iowrite32be(BIT(MLX5_RST_ACK_BIT_NUM), &dev->iseg->initializing);
54 }
55
mlx5_fw_reset_enable_remote_dev_reset_set(struct devlink * devlink,u32 id,struct devlink_param_gset_ctx * ctx,struct netlink_ext_ack * extack)56 static int mlx5_fw_reset_enable_remote_dev_reset_set(struct devlink *devlink, u32 id,
57 struct devlink_param_gset_ctx *ctx,
58 struct netlink_ext_ack *extack)
59 {
60 struct mlx5_core_dev *dev = devlink_priv(devlink);
61 struct mlx5_fw_reset *fw_reset;
62
63 fw_reset = dev->priv.fw_reset;
64
65 if (ctx->val.vbool)
66 clear_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags);
67 else
68 set_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags);
69 return 0;
70 }
71
mlx5_fw_reset_enable_remote_dev_reset_get(struct devlink * devlink,u32 id,struct devlink_param_gset_ctx * ctx)72 static int mlx5_fw_reset_enable_remote_dev_reset_get(struct devlink *devlink, u32 id,
73 struct devlink_param_gset_ctx *ctx)
74 {
75 struct mlx5_core_dev *dev = devlink_priv(devlink);
76 struct mlx5_fw_reset *fw_reset;
77
78 fw_reset = dev->priv.fw_reset;
79
80 ctx->val.vbool = !test_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST,
81 &fw_reset->reset_flags);
82 return 0;
83 }
84
mlx5_reg_mfrl_set(struct mlx5_core_dev * dev,u8 reset_level,u8 reset_type_sel,u8 sync_resp,bool sync_start)85 static int mlx5_reg_mfrl_set(struct mlx5_core_dev *dev, u8 reset_level,
86 u8 reset_type_sel, u8 sync_resp, bool sync_start)
87 {
88 u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {};
89 u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
90
91 MLX5_SET(mfrl_reg, in, reset_level, reset_level);
92 MLX5_SET(mfrl_reg, in, rst_type_sel, reset_type_sel);
93 MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_resp, sync_resp);
94 MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_start, sync_start);
95
96 return mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MFRL, 0, 1);
97 }
98
mlx5_reg_mfrl_query(struct mlx5_core_dev * dev,u8 * reset_level,u8 * reset_type,u8 * reset_state,u8 * reset_method)99 static int mlx5_reg_mfrl_query(struct mlx5_core_dev *dev, u8 *reset_level,
100 u8 *reset_type, u8 *reset_state, u8 *reset_method)
101 {
102 u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {};
103 u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
104 int err;
105
106 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MFRL, 0, 0);
107 if (err)
108 return err;
109
110 if (reset_level)
111 *reset_level = MLX5_GET(mfrl_reg, out, reset_level);
112 if (reset_type)
113 *reset_type = MLX5_GET(mfrl_reg, out, reset_type);
114 if (reset_state)
115 *reset_state = MLX5_GET(mfrl_reg, out, reset_state);
116 if (reset_method)
117 *reset_method = MLX5_GET(mfrl_reg, out, pci_reset_req_method);
118
119 return 0;
120 }
121
mlx5_fw_reset_query(struct mlx5_core_dev * dev,u8 * reset_level,u8 * reset_type)122 int mlx5_fw_reset_query(struct mlx5_core_dev *dev, u8 *reset_level, u8 *reset_type)
123 {
124 return mlx5_reg_mfrl_query(dev, reset_level, reset_type, NULL, NULL);
125 }
126
mlx5_fw_reset_get_reset_method(struct mlx5_core_dev * dev,u8 * reset_method)127 static int mlx5_fw_reset_get_reset_method(struct mlx5_core_dev *dev,
128 u8 *reset_method)
129 {
130 if (!MLX5_CAP_GEN(dev, pcie_reset_using_hotreset_method)) {
131 *reset_method = MLX5_MFRL_REG_PCI_RESET_METHOD_LINK_TOGGLE;
132 return 0;
133 }
134
135 return mlx5_reg_mfrl_query(dev, NULL, NULL, NULL, reset_method);
136 }
137
mlx5_fw_reset_get_reset_state_err(struct mlx5_core_dev * dev,struct netlink_ext_ack * extack)138 static int mlx5_fw_reset_get_reset_state_err(struct mlx5_core_dev *dev,
139 struct netlink_ext_ack *extack)
140 {
141 u8 reset_state;
142
143 if (mlx5_reg_mfrl_query(dev, NULL, NULL, &reset_state, NULL))
144 goto out;
145
146 if (!reset_state)
147 return 0;
148
149 switch (reset_state) {
150 case MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION:
151 case MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS:
152 NL_SET_ERR_MSG_MOD(extack, "Sync reset still in progress");
153 return -EBUSY;
154 case MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT:
155 NL_SET_ERR_MSG_MOD(extack, "Sync reset negotiation timeout");
156 return -ETIMEDOUT;
157 case MLX5_MFRL_REG_RESET_STATE_NACK:
158 NL_SET_ERR_MSG_MOD(extack, "One of the hosts disabled reset");
159 return -EPERM;
160 case MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT:
161 NL_SET_ERR_MSG_MOD(extack, "Sync reset unload timeout");
162 return -ETIMEDOUT;
163 }
164
165 out:
166 NL_SET_ERR_MSG_MOD(extack, "Sync reset failed");
167 return -EIO;
168 }
169
mlx5_fw_reset_set_reset_sync(struct mlx5_core_dev * dev,u8 reset_type_sel,struct netlink_ext_ack * extack)170 int mlx5_fw_reset_set_reset_sync(struct mlx5_core_dev *dev, u8 reset_type_sel,
171 struct netlink_ext_ack *extack)
172 {
173 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
174 u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {};
175 u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
176 int err, rst_res;
177
178 set_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
179
180 MLX5_SET(mfrl_reg, in, reset_level, MLX5_MFRL_REG_RESET_LEVEL3);
181 MLX5_SET(mfrl_reg, in, rst_type_sel, reset_type_sel);
182 MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_start, 1);
183 err = mlx5_access_reg(dev, in, sizeof(in), out, sizeof(out),
184 MLX5_REG_MFRL, 0, 1, false);
185 if (!err)
186 return 0;
187
188 clear_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
189 if (err == -EREMOTEIO && MLX5_CAP_MCAM_FEATURE(dev, reset_state)) {
190 rst_res = mlx5_fw_reset_get_reset_state_err(dev, extack);
191 return rst_res ? rst_res : err;
192 }
193
194 NL_SET_ERR_MSG_MOD(extack, "Sync reset command failed");
195 return mlx5_cmd_check(dev, err, in, out);
196 }
197
mlx5_fw_reset_verify_fw_complete(struct mlx5_core_dev * dev,struct netlink_ext_ack * extack)198 int mlx5_fw_reset_verify_fw_complete(struct mlx5_core_dev *dev,
199 struct netlink_ext_ack *extack)
200 {
201 u8 rst_state;
202 int err;
203
204 err = mlx5_fw_reset_get_reset_state_err(dev, extack);
205 if (err)
206 return err;
207
208 rst_state = mlx5_get_fw_rst_state(dev);
209 if (!rst_state)
210 return 0;
211
212 mlx5_core_err(dev, "Sync reset did not complete, state=%d\n", rst_state);
213 NL_SET_ERR_MSG_MOD(extack, "Sync reset did not complete successfully");
214 return rst_state;
215 }
216
mlx5_fw_reset_set_live_patch(struct mlx5_core_dev * dev)217 int mlx5_fw_reset_set_live_patch(struct mlx5_core_dev *dev)
218 {
219 return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL0, 0, 0, false);
220 }
221
mlx5_fw_reset_complete_reload(struct mlx5_core_dev * dev,bool unloaded)222 static void mlx5_fw_reset_complete_reload(struct mlx5_core_dev *dev, bool unloaded)
223 {
224 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
225 struct devlink *devlink = priv_to_devlink(dev);
226
227 /* if this is the driver that initiated the fw reset, devlink completed the reload */
228 if (test_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags)) {
229 complete(&fw_reset->done);
230 } else {
231 if (!unloaded)
232 mlx5_unload_one(dev, false);
233 if (mlx5_health_wait_pci_up(dev))
234 mlx5_core_err(dev, "reset reload flow aborted, PCI reads still not working\n");
235 else
236 mlx5_load_one(dev, true);
237 devl_lock(devlink);
238 devlink_remote_reload_actions_performed(devlink, 0,
239 BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) |
240 BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE));
241 devl_unlock(devlink);
242 }
243 }
244
mlx5_stop_sync_reset_poll(struct mlx5_core_dev * dev)245 static void mlx5_stop_sync_reset_poll(struct mlx5_core_dev *dev)
246 {
247 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
248
249 del_timer_sync(&fw_reset->timer);
250 }
251
mlx5_sync_reset_clear_reset_requested(struct mlx5_core_dev * dev,bool poll_health)252 static int mlx5_sync_reset_clear_reset_requested(struct mlx5_core_dev *dev, bool poll_health)
253 {
254 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
255
256 if (!test_and_clear_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) {
257 mlx5_core_warn(dev, "Reset request was already cleared\n");
258 return -EALREADY;
259 }
260
261 mlx5_stop_sync_reset_poll(dev);
262 if (poll_health)
263 mlx5_start_health_poll(dev);
264 return 0;
265 }
266
mlx5_sync_reset_reload_work(struct work_struct * work)267 static void mlx5_sync_reset_reload_work(struct work_struct *work)
268 {
269 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
270 reset_reload_work);
271 struct mlx5_core_dev *dev = fw_reset->dev;
272
273 mlx5_sync_reset_clear_reset_requested(dev, false);
274 mlx5_enter_error_state(dev, true);
275 mlx5_fw_reset_complete_reload(dev, false);
276 }
277
278 #define MLX5_RESET_POLL_INTERVAL (HZ / 10)
poll_sync_reset(struct timer_list * t)279 static void poll_sync_reset(struct timer_list *t)
280 {
281 struct mlx5_fw_reset *fw_reset = from_timer(fw_reset, t, timer);
282 struct mlx5_core_dev *dev = fw_reset->dev;
283 u32 fatal_error;
284
285 if (!test_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags))
286 return;
287
288 fatal_error = mlx5_health_check_fatal_sensors(dev);
289
290 if (fatal_error) {
291 mlx5_core_warn(dev, "Got Device Reset\n");
292 if (!test_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags))
293 queue_work(fw_reset->wq, &fw_reset->reset_reload_work);
294 else
295 mlx5_core_err(dev, "Device is being removed, Drop new reset work\n");
296 return;
297 }
298
299 mod_timer(&fw_reset->timer, round_jiffies(jiffies + MLX5_RESET_POLL_INTERVAL));
300 }
301
mlx5_start_sync_reset_poll(struct mlx5_core_dev * dev)302 static void mlx5_start_sync_reset_poll(struct mlx5_core_dev *dev)
303 {
304 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
305
306 timer_setup(&fw_reset->timer, poll_sync_reset, 0);
307 fw_reset->timer.expires = round_jiffies(jiffies + MLX5_RESET_POLL_INTERVAL);
308 add_timer(&fw_reset->timer);
309 }
310
mlx5_fw_reset_set_reset_sync_ack(struct mlx5_core_dev * dev)311 static int mlx5_fw_reset_set_reset_sync_ack(struct mlx5_core_dev *dev)
312 {
313 return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL3, 0, 1, false);
314 }
315
mlx5_fw_reset_set_reset_sync_nack(struct mlx5_core_dev * dev)316 static int mlx5_fw_reset_set_reset_sync_nack(struct mlx5_core_dev *dev)
317 {
318 return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL3, 0, 2, false);
319 }
320
mlx5_sync_reset_set_reset_requested(struct mlx5_core_dev * dev)321 static int mlx5_sync_reset_set_reset_requested(struct mlx5_core_dev *dev)
322 {
323 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
324
325 if (test_and_set_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) {
326 mlx5_core_warn(dev, "Reset request was already set\n");
327 return -EALREADY;
328 }
329 mlx5_stop_health_poll(dev, true);
330 mlx5_start_sync_reset_poll(dev);
331 return 0;
332 }
333
mlx5_fw_live_patch_event(struct work_struct * work)334 static void mlx5_fw_live_patch_event(struct work_struct *work)
335 {
336 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
337 fw_live_patch_work);
338 struct mlx5_core_dev *dev = fw_reset->dev;
339
340 mlx5_core_info(dev, "Live patch updated firmware version: %d.%d.%d\n", fw_rev_maj(dev),
341 fw_rev_min(dev), fw_rev_sub(dev));
342
343 if (mlx5_fw_tracer_reload(dev->tracer))
344 mlx5_core_err(dev, "Failed to reload FW tracer\n");
345 }
346
347 #if IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE)
mlx5_check_hotplug_interrupt(struct mlx5_core_dev * dev)348 static int mlx5_check_hotplug_interrupt(struct mlx5_core_dev *dev)
349 {
350 struct pci_dev *bridge = dev->pdev->bus->self;
351 u16 reg16;
352 int err;
353
354 if (!bridge)
355 return -EOPNOTSUPP;
356
357 err = pcie_capability_read_word(bridge, PCI_EXP_SLTCTL, ®16);
358 if (err)
359 return err;
360
361 if ((reg16 & PCI_EXP_SLTCTL_HPIE) && (reg16 & PCI_EXP_SLTCTL_DLLSCE)) {
362 mlx5_core_warn(dev, "FW reset is not supported as HotPlug is enabled\n");
363 return -EOPNOTSUPP;
364 }
365
366 return 0;
367 }
368 #endif
369
370 static const struct pci_device_id mgt_ifc_device_ids[] = {
371 { PCI_VDEVICE(MELLANOX, 0xc2d2) }, /* BlueField1 MGT interface device ID */
372 { PCI_VDEVICE(MELLANOX, 0xc2d3) }, /* BlueField2 MGT interface device ID */
373 { PCI_VDEVICE(MELLANOX, 0xc2d4) }, /* BlueField3-Lx MGT interface device ID */
374 { PCI_VDEVICE(MELLANOX, 0xc2d5) }, /* BlueField3 MGT interface device ID */
375 { PCI_VDEVICE(MELLANOX, 0xc2d6) }, /* BlueField4 MGT interface device ID */
376 };
377
mlx5_is_mgt_ifc_pci_device(struct mlx5_core_dev * dev,u16 dev_id)378 static bool mlx5_is_mgt_ifc_pci_device(struct mlx5_core_dev *dev, u16 dev_id)
379 {
380 int i;
381
382 for (i = 0; i < ARRAY_SIZE(mgt_ifc_device_ids); ++i)
383 if (mgt_ifc_device_ids[i].device == dev_id)
384 return true;
385
386 return false;
387 }
388
mlx5_check_dev_ids(struct mlx5_core_dev * dev,u16 dev_id)389 static int mlx5_check_dev_ids(struct mlx5_core_dev *dev, u16 dev_id)
390 {
391 struct pci_bus *bridge_bus = dev->pdev->bus;
392 struct pci_dev *sdev;
393 u16 sdev_id;
394 int err;
395
396 /* Check that all functions under the pci bridge are PFs of
397 * this device otherwise fail this function.
398 */
399 list_for_each_entry(sdev, &bridge_bus->devices, bus_list) {
400 err = pci_read_config_word(sdev, PCI_DEVICE_ID, &sdev_id);
401 if (err)
402 return pcibios_err_to_errno(err);
403
404 if (sdev_id == dev_id)
405 continue;
406
407 if (mlx5_is_mgt_ifc_pci_device(dev, sdev_id))
408 continue;
409
410 mlx5_core_warn(dev, "unrecognized dev_id (0x%x)\n", sdev_id);
411 return -EPERM;
412 }
413 return 0;
414 }
415
mlx5_is_reset_now_capable(struct mlx5_core_dev * dev,u8 reset_method)416 static bool mlx5_is_reset_now_capable(struct mlx5_core_dev *dev,
417 u8 reset_method)
418 {
419 u16 dev_id;
420 int err;
421
422 if (!MLX5_CAP_GEN(dev, fast_teardown)) {
423 mlx5_core_warn(dev, "fast teardown is not supported by firmware\n");
424 return false;
425 }
426
427 #if IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE)
428 if (reset_method != MLX5_MFRL_REG_PCI_RESET_METHOD_HOT_RESET) {
429 err = mlx5_check_hotplug_interrupt(dev);
430 if (err)
431 return false;
432 }
433 #endif
434
435 err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, &dev_id);
436 if (err)
437 return false;
438 return (!mlx5_check_dev_ids(dev, dev_id));
439 }
440
mlx5_sync_reset_request_event(struct work_struct * work)441 static void mlx5_sync_reset_request_event(struct work_struct *work)
442 {
443 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
444 reset_request_work);
445 struct mlx5_core_dev *dev = fw_reset->dev;
446 int err;
447
448 err = mlx5_fw_reset_get_reset_method(dev, &fw_reset->reset_method);
449 if (err)
450 mlx5_core_warn(dev, "Failed reading MFRL, err %d\n", err);
451
452 if (err || test_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags) ||
453 !mlx5_is_reset_now_capable(dev, fw_reset->reset_method)) {
454 err = mlx5_fw_reset_set_reset_sync_nack(dev);
455 mlx5_core_warn(dev, "PCI Sync FW Update Reset Nack %s",
456 err ? "Failed" : "Sent");
457 return;
458 }
459 if (mlx5_sync_reset_set_reset_requested(dev))
460 return;
461
462 err = mlx5_fw_reset_set_reset_sync_ack(dev);
463 if (err)
464 mlx5_core_warn(dev, "PCI Sync FW Update Reset Ack Failed. Error code: %d\n", err);
465 else
466 mlx5_core_warn(dev, "PCI Sync FW Update Reset Ack. Device reset is expected.\n");
467 }
468
mlx5_pci_link_toggle(struct mlx5_core_dev * dev,u16 dev_id)469 static int mlx5_pci_link_toggle(struct mlx5_core_dev *dev, u16 dev_id)
470 {
471 struct pci_bus *bridge_bus = dev->pdev->bus;
472 struct pci_dev *bridge = bridge_bus->self;
473 unsigned long timeout;
474 struct pci_dev *sdev;
475 int cap, err;
476 u16 reg16;
477
478 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
479 if (!cap)
480 return -EOPNOTSUPP;
481
482 list_for_each_entry(sdev, &bridge_bus->devices, bus_list) {
483 pci_save_state(sdev);
484 pci_cfg_access_lock(sdev);
485 }
486 /* PCI link toggle */
487 err = pcie_capability_set_word(bridge, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_LD);
488 if (err)
489 return pcibios_err_to_errno(err);
490 msleep(500);
491 err = pcie_capability_clear_word(bridge, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_LD);
492 if (err)
493 return pcibios_err_to_errno(err);
494
495 /* Check link */
496 if (!bridge->link_active_reporting) {
497 mlx5_core_warn(dev, "No PCI link reporting capability\n");
498 msleep(1000);
499 goto restore;
500 }
501
502 timeout = jiffies + msecs_to_jiffies(mlx5_tout_ms(dev, PCI_TOGGLE));
503 do {
504 err = pci_read_config_word(bridge, cap + PCI_EXP_LNKSTA, ®16);
505 if (err)
506 return pcibios_err_to_errno(err);
507 if (reg16 & PCI_EXP_LNKSTA_DLLLA)
508 break;
509 msleep(20);
510 } while (!time_after(jiffies, timeout));
511
512 if (reg16 & PCI_EXP_LNKSTA_DLLLA) {
513 mlx5_core_info(dev, "PCI Link up\n");
514 } else {
515 mlx5_core_err(dev, "PCI link not ready (0x%04x) after %llu ms\n",
516 reg16, mlx5_tout_ms(dev, PCI_TOGGLE));
517 err = -ETIMEDOUT;
518 goto restore;
519 }
520
521 do {
522 err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, ®16);
523 if (err)
524 return pcibios_err_to_errno(err);
525 if (reg16 == dev_id)
526 break;
527 msleep(20);
528 } while (!time_after(jiffies, timeout));
529
530 if (reg16 == dev_id) {
531 mlx5_core_info(dev, "Firmware responds to PCI config cycles again\n");
532 } else {
533 mlx5_core_err(dev, "Firmware is not responsive (0x%04x) after %llu ms\n",
534 reg16, mlx5_tout_ms(dev, PCI_TOGGLE));
535 err = -ETIMEDOUT;
536 }
537
538 restore:
539 list_for_each_entry(sdev, &bridge_bus->devices, bus_list) {
540 pci_cfg_access_unlock(sdev);
541 pci_restore_state(sdev);
542 }
543
544 return err;
545 }
546
mlx5_pci_reset_bus(struct mlx5_core_dev * dev)547 static int mlx5_pci_reset_bus(struct mlx5_core_dev *dev)
548 {
549 if (!MLX5_CAP_GEN(dev, pcie_reset_using_hotreset_method))
550 return -EOPNOTSUPP;
551
552 return pci_reset_bus(dev->pdev);
553 }
554
mlx5_sync_pci_reset(struct mlx5_core_dev * dev,u8 reset_method)555 static int mlx5_sync_pci_reset(struct mlx5_core_dev *dev, u8 reset_method)
556 {
557 u16 dev_id;
558 int err;
559
560 err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, &dev_id);
561 if (err)
562 return pcibios_err_to_errno(err);
563 err = mlx5_check_dev_ids(dev, dev_id);
564 if (err)
565 return err;
566
567 switch (reset_method) {
568 case MLX5_MFRL_REG_PCI_RESET_METHOD_LINK_TOGGLE:
569 err = mlx5_pci_link_toggle(dev, dev_id);
570 if (err)
571 mlx5_core_warn(dev, "mlx5_pci_link_toggle failed\n");
572 break;
573 case MLX5_MFRL_REG_PCI_RESET_METHOD_HOT_RESET:
574 err = mlx5_pci_reset_bus(dev);
575 if (err)
576 mlx5_core_warn(dev, "mlx5_pci_reset_bus failed\n");
577 break;
578 default:
579 return -EOPNOTSUPP;
580 }
581
582 return err;
583 }
584
mlx5_sync_reset_now_event(struct work_struct * work)585 static void mlx5_sync_reset_now_event(struct work_struct *work)
586 {
587 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
588 reset_now_work);
589 struct mlx5_core_dev *dev = fw_reset->dev;
590 int err;
591
592 if (mlx5_sync_reset_clear_reset_requested(dev, false))
593 return;
594
595 mlx5_core_warn(dev, "Sync Reset now. Device is going to reset.\n");
596
597 err = mlx5_cmd_fast_teardown_hca(dev);
598 if (err) {
599 mlx5_core_warn(dev, "Fast teardown failed, no reset done, err %d\n", err);
600 goto done;
601 }
602
603 err = mlx5_sync_pci_reset(dev, fw_reset->reset_method);
604 if (err) {
605 mlx5_core_warn(dev, "mlx5_sync_pci_reset failed, no reset done, err %d\n", err);
606 set_bit(MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED, &fw_reset->reset_flags);
607 }
608
609 mlx5_enter_error_state(dev, true);
610 done:
611 fw_reset->ret = err;
612 mlx5_fw_reset_complete_reload(dev, false);
613 }
614
mlx5_sync_reset_unload_event(struct work_struct * work)615 static void mlx5_sync_reset_unload_event(struct work_struct *work)
616 {
617 struct mlx5_fw_reset *fw_reset;
618 struct mlx5_core_dev *dev;
619 unsigned long timeout;
620 int poll_freq = 20;
621 bool reset_action;
622 u8 rst_state;
623 int err;
624
625 fw_reset = container_of(work, struct mlx5_fw_reset, reset_unload_work);
626 dev = fw_reset->dev;
627
628 if (mlx5_sync_reset_clear_reset_requested(dev, false))
629 return;
630
631 mlx5_core_warn(dev, "Sync Reset Unload. Function is forced down.\n");
632
633 err = mlx5_cmd_fast_teardown_hca(dev);
634 if (err)
635 mlx5_core_warn(dev, "Fast teardown failed, unloading, err %d\n", err);
636 else
637 mlx5_enter_error_state(dev, true);
638
639 if (test_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags))
640 mlx5_unload_one_devl_locked(dev, false);
641 else
642 mlx5_unload_one(dev, false);
643
644 mlx5_set_fw_rst_ack(dev);
645 mlx5_core_warn(dev, "Sync Reset Unload done, device reset expected\n");
646
647 reset_action = false;
648 timeout = jiffies + msecs_to_jiffies(mlx5_tout_ms(dev, RESET_UNLOAD));
649 do {
650 rst_state = mlx5_get_fw_rst_state(dev);
651 if (rst_state == MLX5_FW_RST_STATE_TOGGLE_REQ ||
652 rst_state == MLX5_FW_RST_STATE_IDLE) {
653 reset_action = true;
654 break;
655 }
656 if (rst_state == MLX5_FW_RST_STATE_DROP_MODE) {
657 mlx5_core_info(dev, "Sync Reset Drop mode ack\n");
658 mlx5_set_fw_rst_ack(dev);
659 poll_freq = 1000;
660 }
661 msleep(poll_freq);
662 } while (!time_after(jiffies, timeout));
663
664 if (!reset_action) {
665 mlx5_core_err(dev, "Got timeout waiting for sync reset action, state = %u\n",
666 rst_state);
667 fw_reset->ret = -ETIMEDOUT;
668 goto done;
669 }
670
671 mlx5_core_warn(dev, "Sync Reset, got reset action. rst_state = %u\n", rst_state);
672 if (rst_state == MLX5_FW_RST_STATE_TOGGLE_REQ) {
673 err = mlx5_sync_pci_reset(dev, fw_reset->reset_method);
674 if (err) {
675 mlx5_core_warn(dev, "mlx5_sync_pci_reset failed, err %d\n", err);
676 fw_reset->ret = err;
677 }
678 }
679
680 done:
681 mlx5_fw_reset_complete_reload(dev, true);
682 }
683
mlx5_sync_reset_abort_event(struct work_struct * work)684 static void mlx5_sync_reset_abort_event(struct work_struct *work)
685 {
686 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
687 reset_abort_work);
688 struct mlx5_core_dev *dev = fw_reset->dev;
689
690 if (mlx5_sync_reset_clear_reset_requested(dev, true))
691 return;
692 mlx5_core_warn(dev, "PCI Sync FW Update Reset Aborted.\n");
693 }
694
mlx5_sync_reset_events_handle(struct mlx5_fw_reset * fw_reset,struct mlx5_eqe * eqe)695 static void mlx5_sync_reset_events_handle(struct mlx5_fw_reset *fw_reset, struct mlx5_eqe *eqe)
696 {
697 struct mlx5_eqe_sync_fw_update *sync_fw_update_eqe;
698 u8 sync_event_rst_type;
699
700 sync_fw_update_eqe = &eqe->data.sync_fw_update;
701 sync_event_rst_type = sync_fw_update_eqe->sync_rst_state & SYNC_RST_STATE_MASK;
702 switch (sync_event_rst_type) {
703 case MLX5_SYNC_RST_STATE_RESET_REQUEST:
704 queue_work(fw_reset->wq, &fw_reset->reset_request_work);
705 break;
706 case MLX5_SYNC_RST_STATE_RESET_UNLOAD:
707 queue_work(fw_reset->wq, &fw_reset->reset_unload_work);
708 break;
709 case MLX5_SYNC_RST_STATE_RESET_NOW:
710 queue_work(fw_reset->wq, &fw_reset->reset_now_work);
711 break;
712 case MLX5_SYNC_RST_STATE_RESET_ABORT:
713 queue_work(fw_reset->wq, &fw_reset->reset_abort_work);
714 break;
715 }
716 }
717
fw_reset_event_notifier(struct notifier_block * nb,unsigned long action,void * data)718 static int fw_reset_event_notifier(struct notifier_block *nb, unsigned long action, void *data)
719 {
720 struct mlx5_fw_reset *fw_reset = mlx5_nb_cof(nb, struct mlx5_fw_reset, nb);
721 struct mlx5_eqe *eqe = data;
722
723 if (test_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags))
724 return NOTIFY_DONE;
725
726 switch (eqe->sub_type) {
727 case MLX5_GENERAL_SUBTYPE_FW_LIVE_PATCH_EVENT:
728 queue_work(fw_reset->wq, &fw_reset->fw_live_patch_work);
729 break;
730 case MLX5_GENERAL_SUBTYPE_PCI_SYNC_FOR_FW_UPDATE_EVENT:
731 mlx5_sync_reset_events_handle(fw_reset, eqe);
732 break;
733 default:
734 return NOTIFY_DONE;
735 }
736
737 return NOTIFY_OK;
738 }
739
mlx5_fw_reset_wait_reset_done(struct mlx5_core_dev * dev)740 int mlx5_fw_reset_wait_reset_done(struct mlx5_core_dev *dev)
741 {
742 unsigned long pci_sync_update_timeout = mlx5_tout_ms(dev, PCI_SYNC_UPDATE);
743 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
744 unsigned long timeout;
745 int err;
746
747 if (MLX5_CAP_GEN(dev, pci_sync_for_fw_update_with_driver_unload))
748 pci_sync_update_timeout += mlx5_tout_ms(dev, RESET_UNLOAD);
749 timeout = msecs_to_jiffies(pci_sync_update_timeout);
750 if (!wait_for_completion_timeout(&fw_reset->done, timeout)) {
751 mlx5_core_warn(dev, "FW sync reset timeout after %lu seconds\n",
752 pci_sync_update_timeout / 1000);
753 err = -ETIMEDOUT;
754 goto out;
755 }
756 err = fw_reset->ret;
757 if (test_and_clear_bit(MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED, &fw_reset->reset_flags)) {
758 mlx5_unload_one_devl_locked(dev, false);
759 mlx5_load_one_devl_locked(dev, true);
760 }
761 out:
762 clear_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
763 return err;
764 }
765
mlx5_fw_reset_events_start(struct mlx5_core_dev * dev)766 void mlx5_fw_reset_events_start(struct mlx5_core_dev *dev)
767 {
768 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
769
770 if (!fw_reset)
771 return;
772
773 MLX5_NB_INIT(&fw_reset->nb, fw_reset_event_notifier, GENERAL_EVENT);
774 mlx5_eq_notifier_register(dev, &fw_reset->nb);
775 }
776
mlx5_fw_reset_events_stop(struct mlx5_core_dev * dev)777 void mlx5_fw_reset_events_stop(struct mlx5_core_dev *dev)
778 {
779 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
780
781 if (!fw_reset)
782 return;
783
784 mlx5_eq_notifier_unregister(dev, &fw_reset->nb);
785 }
786
mlx5_drain_fw_reset(struct mlx5_core_dev * dev)787 void mlx5_drain_fw_reset(struct mlx5_core_dev *dev)
788 {
789 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
790
791 if (!fw_reset)
792 return;
793
794 set_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags);
795 cancel_work_sync(&fw_reset->fw_live_patch_work);
796 cancel_work_sync(&fw_reset->reset_request_work);
797 cancel_work_sync(&fw_reset->reset_unload_work);
798 cancel_work_sync(&fw_reset->reset_reload_work);
799 cancel_work_sync(&fw_reset->reset_now_work);
800 cancel_work_sync(&fw_reset->reset_abort_work);
801 }
802
803 static const struct devlink_param mlx5_fw_reset_devlink_params[] = {
804 DEVLINK_PARAM_GENERIC(ENABLE_REMOTE_DEV_RESET, BIT(DEVLINK_PARAM_CMODE_RUNTIME),
805 mlx5_fw_reset_enable_remote_dev_reset_get,
806 mlx5_fw_reset_enable_remote_dev_reset_set, NULL),
807 };
808
mlx5_fw_reset_init(struct mlx5_core_dev * dev)809 int mlx5_fw_reset_init(struct mlx5_core_dev *dev)
810 {
811 struct mlx5_fw_reset *fw_reset;
812 int err;
813
814 if (!MLX5_CAP_MCAM_REG(dev, mfrl))
815 return 0;
816
817 fw_reset = kzalloc(sizeof(*fw_reset), GFP_KERNEL);
818 if (!fw_reset)
819 return -ENOMEM;
820 fw_reset->wq = create_singlethread_workqueue("mlx5_fw_reset_events");
821 if (!fw_reset->wq) {
822 kfree(fw_reset);
823 return -ENOMEM;
824 }
825
826 fw_reset->dev = dev;
827 dev->priv.fw_reset = fw_reset;
828
829 err = devl_params_register(priv_to_devlink(dev),
830 mlx5_fw_reset_devlink_params,
831 ARRAY_SIZE(mlx5_fw_reset_devlink_params));
832 if (err) {
833 destroy_workqueue(fw_reset->wq);
834 kfree(fw_reset);
835 return err;
836 }
837
838 INIT_WORK(&fw_reset->fw_live_patch_work, mlx5_fw_live_patch_event);
839 INIT_WORK(&fw_reset->reset_request_work, mlx5_sync_reset_request_event);
840 INIT_WORK(&fw_reset->reset_unload_work, mlx5_sync_reset_unload_event);
841 INIT_WORK(&fw_reset->reset_reload_work, mlx5_sync_reset_reload_work);
842 INIT_WORK(&fw_reset->reset_now_work, mlx5_sync_reset_now_event);
843 INIT_WORK(&fw_reset->reset_abort_work, mlx5_sync_reset_abort_event);
844
845 init_completion(&fw_reset->done);
846 return 0;
847 }
848
mlx5_fw_reset_cleanup(struct mlx5_core_dev * dev)849 void mlx5_fw_reset_cleanup(struct mlx5_core_dev *dev)
850 {
851 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
852
853 if (!fw_reset)
854 return;
855
856 devl_params_unregister(priv_to_devlink(dev),
857 mlx5_fw_reset_devlink_params,
858 ARRAY_SIZE(mlx5_fw_reset_devlink_params));
859 destroy_workqueue(fw_reset->wq);
860 kfree(dev->priv.fw_reset);
861 }
862