1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 /* Copyright (c) 2020, Mellanox Technologies inc. All rights reserved. */
3
4 #include <devlink.h>
5
6 #include "fw_reset.h"
7 #include "diag/fw_tracer.h"
8 #include "lib/tout.h"
9 #include "sf/sf.h"
10
11 enum {
12 MLX5_FW_RESET_FLAGS_RESET_REQUESTED,
13 MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST,
14 MLX5_FW_RESET_FLAGS_PENDING_COMP,
15 MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS,
16 MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED,
17 MLX5_FW_RESET_FLAGS_UNLOAD_EVENT,
18 };
19
20 struct mlx5_fw_reset {
21 struct mlx5_core_dev *dev;
22 struct mlx5_nb nb;
23 struct workqueue_struct *wq;
24 struct work_struct fw_live_patch_work;
25 struct work_struct reset_request_work;
26 struct work_struct reset_unload_work;
27 struct work_struct reset_reload_work;
28 struct work_struct reset_now_work;
29 struct work_struct reset_abort_work;
30 struct delayed_work reset_timeout_work;
31 unsigned long reset_flags;
32 u8 reset_method;
33 struct timer_list timer;
34 struct completion done;
35 int ret;
36 };
37
38 enum {
39 MLX5_FW_RST_STATE_IDLE = 0,
40 MLX5_FW_RST_STATE_TOGGLE_REQ = 4,
41 MLX5_FW_RST_STATE_DROP_MODE = 5,
42 };
43
44 enum {
45 MLX5_RST_STATE_BIT_NUM = 12,
46 MLX5_RST_ACK_BIT_NUM = 22,
47 };
48
mlx5_get_fw_rst_state(struct mlx5_core_dev * dev)49 static u8 mlx5_get_fw_rst_state(struct mlx5_core_dev *dev)
50 {
51 return (ioread32be(&dev->iseg->initializing) >> MLX5_RST_STATE_BIT_NUM) & 0xF;
52 }
53
mlx5_set_fw_rst_ack(struct mlx5_core_dev * dev)54 static void mlx5_set_fw_rst_ack(struct mlx5_core_dev *dev)
55 {
56 iowrite32be(BIT(MLX5_RST_ACK_BIT_NUM), &dev->iseg->initializing);
57 }
58
mlx5_fw_reset_enable_remote_dev_reset_set(struct devlink * devlink,u32 id,struct devlink_param_gset_ctx * ctx,struct netlink_ext_ack * extack)59 static int mlx5_fw_reset_enable_remote_dev_reset_set(struct devlink *devlink, u32 id,
60 struct devlink_param_gset_ctx *ctx,
61 struct netlink_ext_ack *extack)
62 {
63 struct mlx5_core_dev *dev = devlink_priv(devlink);
64 struct mlx5_fw_reset *fw_reset;
65
66 fw_reset = dev->priv.fw_reset;
67
68 if (ctx->val.vbool)
69 clear_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags);
70 else
71 set_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags);
72 return 0;
73 }
74
mlx5_fw_reset_enable_remote_dev_reset_get(struct devlink * devlink,u32 id,struct devlink_param_gset_ctx * ctx)75 static int mlx5_fw_reset_enable_remote_dev_reset_get(struct devlink *devlink, u32 id,
76 struct devlink_param_gset_ctx *ctx)
77 {
78 struct mlx5_core_dev *dev = devlink_priv(devlink);
79 struct mlx5_fw_reset *fw_reset;
80
81 fw_reset = dev->priv.fw_reset;
82
83 ctx->val.vbool = !test_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST,
84 &fw_reset->reset_flags);
85 return 0;
86 }
87
mlx5_reg_mfrl_set(struct mlx5_core_dev * dev,u8 reset_level,u8 reset_type_sel,u8 sync_resp,bool sync_start)88 static int mlx5_reg_mfrl_set(struct mlx5_core_dev *dev, u8 reset_level,
89 u8 reset_type_sel, u8 sync_resp, bool sync_start)
90 {
91 u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {};
92 u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
93
94 MLX5_SET(mfrl_reg, in, reset_level, reset_level);
95 MLX5_SET(mfrl_reg, in, rst_type_sel, reset_type_sel);
96 MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_resp, sync_resp);
97 MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_start, sync_start);
98
99 return mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MFRL, 0, 1);
100 }
101
mlx5_reg_mfrl_query(struct mlx5_core_dev * dev,u8 * reset_level,u8 * reset_type,u8 * reset_state,u8 * reset_method)102 static int mlx5_reg_mfrl_query(struct mlx5_core_dev *dev, u8 *reset_level,
103 u8 *reset_type, u8 *reset_state, u8 *reset_method)
104 {
105 u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {};
106 u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
107 int err;
108
109 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MFRL, 0, 0);
110 if (err)
111 return err;
112
113 if (reset_level)
114 *reset_level = MLX5_GET(mfrl_reg, out, reset_level);
115 if (reset_type)
116 *reset_type = MLX5_GET(mfrl_reg, out, reset_type);
117 if (reset_state)
118 *reset_state = MLX5_GET(mfrl_reg, out, reset_state);
119 if (reset_method)
120 *reset_method = MLX5_GET(mfrl_reg, out, pci_reset_req_method);
121
122 return 0;
123 }
124
mlx5_fw_reset_query(struct mlx5_core_dev * dev,u8 * reset_level,u8 * reset_type)125 int mlx5_fw_reset_query(struct mlx5_core_dev *dev, u8 *reset_level, u8 *reset_type)
126 {
127 return mlx5_reg_mfrl_query(dev, reset_level, reset_type, NULL, NULL);
128 }
129
mlx5_fw_reset_get_reset_method(struct mlx5_core_dev * dev,u8 * reset_method)130 static int mlx5_fw_reset_get_reset_method(struct mlx5_core_dev *dev,
131 u8 *reset_method)
132 {
133 if (!MLX5_CAP_GEN(dev, pcie_reset_using_hotreset_method)) {
134 *reset_method = MLX5_MFRL_REG_PCI_RESET_METHOD_LINK_TOGGLE;
135 return 0;
136 }
137
138 return mlx5_reg_mfrl_query(dev, NULL, NULL, NULL, reset_method);
139 }
140
mlx5_fw_reset_get_reset_state_err(struct mlx5_core_dev * dev,struct netlink_ext_ack * extack)141 static int mlx5_fw_reset_get_reset_state_err(struct mlx5_core_dev *dev,
142 struct netlink_ext_ack *extack)
143 {
144 u8 reset_state;
145
146 if (mlx5_reg_mfrl_query(dev, NULL, NULL, &reset_state, NULL))
147 goto out;
148
149 if (!reset_state)
150 return 0;
151
152 switch (reset_state) {
153 case MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION:
154 case MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS:
155 NL_SET_ERR_MSG_MOD(extack, "Sync reset still in progress");
156 return -EBUSY;
157 case MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT:
158 NL_SET_ERR_MSG_MOD(extack, "Sync reset negotiation timeout");
159 return -ETIMEDOUT;
160 case MLX5_MFRL_REG_RESET_STATE_NACK:
161 NL_SET_ERR_MSG_MOD(extack, "One of the hosts disabled reset");
162 return -EPERM;
163 case MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT:
164 NL_SET_ERR_MSG_MOD(extack, "Sync reset unload timeout");
165 return -ETIMEDOUT;
166 }
167
168 out:
169 NL_SET_ERR_MSG_MOD(extack, "Sync reset failed");
170 return -EIO;
171 }
172
mlx5_fw_reset_set_reset_sync(struct mlx5_core_dev * dev,u8 reset_type_sel,struct netlink_ext_ack * extack)173 int mlx5_fw_reset_set_reset_sync(struct mlx5_core_dev *dev, u8 reset_type_sel,
174 struct netlink_ext_ack *extack)
175 {
176 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
177 u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {};
178 u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
179 int err, rst_res;
180
181 set_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
182
183 MLX5_SET(mfrl_reg, in, reset_level, MLX5_MFRL_REG_RESET_LEVEL3);
184 MLX5_SET(mfrl_reg, in, rst_type_sel, reset_type_sel);
185 MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_start, 1);
186 err = mlx5_access_reg(dev, in, sizeof(in), out, sizeof(out),
187 MLX5_REG_MFRL, 0, 1, false);
188 if (!err)
189 return 0;
190
191 clear_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
192 if (err == -EREMOTEIO && MLX5_CAP_MCAM_FEATURE(dev, reset_state)) {
193 rst_res = mlx5_fw_reset_get_reset_state_err(dev, extack);
194 return rst_res ? rst_res : err;
195 }
196
197 NL_SET_ERR_MSG_MOD(extack, "Sync reset command failed");
198 return mlx5_cmd_check(dev, err, in, out);
199 }
200
mlx5_fw_reset_verify_fw_complete(struct mlx5_core_dev * dev,struct netlink_ext_ack * extack)201 int mlx5_fw_reset_verify_fw_complete(struct mlx5_core_dev *dev,
202 struct netlink_ext_ack *extack)
203 {
204 u8 rst_state;
205 int err;
206
207 err = mlx5_fw_reset_get_reset_state_err(dev, extack);
208 if (err)
209 return err;
210
211 rst_state = mlx5_get_fw_rst_state(dev);
212 if (!rst_state)
213 return 0;
214
215 mlx5_core_err(dev, "Sync reset did not complete, state=%d\n", rst_state);
216 NL_SET_ERR_MSG_MOD(extack, "Sync reset did not complete successfully");
217 return rst_state;
218 }
219
mlx5_fw_reset_set_live_patch(struct mlx5_core_dev * dev)220 int mlx5_fw_reset_set_live_patch(struct mlx5_core_dev *dev)
221 {
222 return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL0, 0, 0, false);
223 }
224
mlx5_fw_reset_complete_reload(struct mlx5_core_dev * dev)225 static void mlx5_fw_reset_complete_reload(struct mlx5_core_dev *dev)
226 {
227 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
228 struct devlink *devlink = priv_to_devlink(dev);
229
230 /* if this is the driver that initiated the fw reset, devlink completed the reload */
231 if (test_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags)) {
232 complete(&fw_reset->done);
233 } else {
234 mlx5_sync_reset_unload_flow(dev, false);
235 if (mlx5_health_wait_pci_up(dev))
236 mlx5_core_err(dev, "reset reload flow aborted, PCI reads still not working\n");
237 else
238 mlx5_load_one(dev, true);
239 devl_lock(devlink);
240 devlink_remote_reload_actions_performed(devlink, 0,
241 BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) |
242 BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE));
243 devl_unlock(devlink);
244 }
245 }
246
mlx5_stop_sync_reset_poll(struct mlx5_core_dev * dev)247 static void mlx5_stop_sync_reset_poll(struct mlx5_core_dev *dev)
248 {
249 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
250
251 timer_delete_sync(&fw_reset->timer);
252 }
253
mlx5_sync_reset_clear_reset_requested(struct mlx5_core_dev * dev,bool poll_health)254 static int mlx5_sync_reset_clear_reset_requested(struct mlx5_core_dev *dev, bool poll_health)
255 {
256 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
257
258 if (!test_and_clear_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) {
259 mlx5_core_warn(dev, "Reset request was already cleared\n");
260 return -EALREADY;
261 }
262
263 if (current_work() != &fw_reset->reset_timeout_work.work)
264 cancel_delayed_work(&fw_reset->reset_timeout_work);
265 mlx5_stop_sync_reset_poll(dev);
266 if (poll_health)
267 mlx5_start_health_poll(dev);
268 return 0;
269 }
270
mlx5_sync_reset_reload_work(struct work_struct * work)271 static void mlx5_sync_reset_reload_work(struct work_struct *work)
272 {
273 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
274 reset_reload_work);
275 struct mlx5_core_dev *dev = fw_reset->dev;
276
277 mlx5_sync_reset_clear_reset_requested(dev, false);
278 mlx5_enter_error_state(dev, true);
279 mlx5_fw_reset_complete_reload(dev);
280 }
281
282 #define MLX5_RESET_POLL_INTERVAL (HZ / 10)
poll_sync_reset(struct timer_list * t)283 static void poll_sync_reset(struct timer_list *t)
284 {
285 struct mlx5_fw_reset *fw_reset = timer_container_of(fw_reset, t,
286 timer);
287 struct mlx5_core_dev *dev = fw_reset->dev;
288 u32 fatal_error;
289
290 if (!test_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags))
291 return;
292
293 fatal_error = mlx5_health_check_fatal_sensors(dev);
294
295 if (fatal_error) {
296 mlx5_core_warn(dev, "Got Device Reset\n");
297 if (!test_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags))
298 queue_work(fw_reset->wq, &fw_reset->reset_reload_work);
299 else
300 mlx5_core_err(dev, "Device is being removed, Drop new reset work\n");
301 return;
302 }
303
304 mod_timer(&fw_reset->timer, round_jiffies(jiffies + MLX5_RESET_POLL_INTERVAL));
305 }
306
mlx5_start_sync_reset_poll(struct mlx5_core_dev * dev)307 static void mlx5_start_sync_reset_poll(struct mlx5_core_dev *dev)
308 {
309 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
310
311 timer_setup(&fw_reset->timer, poll_sync_reset, 0);
312 fw_reset->timer.expires = round_jiffies(jiffies + MLX5_RESET_POLL_INTERVAL);
313 add_timer(&fw_reset->timer);
314 }
315
mlx5_fw_reset_set_reset_sync_ack(struct mlx5_core_dev * dev)316 static int mlx5_fw_reset_set_reset_sync_ack(struct mlx5_core_dev *dev)
317 {
318 return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL3, 0, 1, false);
319 }
320
mlx5_fw_reset_set_reset_sync_nack(struct mlx5_core_dev * dev)321 static int mlx5_fw_reset_set_reset_sync_nack(struct mlx5_core_dev *dev)
322 {
323 return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL3, 0, 2, false);
324 }
325
mlx5_sync_reset_set_reset_requested(struct mlx5_core_dev * dev)326 static int mlx5_sync_reset_set_reset_requested(struct mlx5_core_dev *dev)
327 {
328 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
329
330 if (test_and_set_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) {
331 mlx5_core_warn(dev, "Reset request was already set\n");
332 return -EALREADY;
333 }
334 mlx5_stop_health_poll(dev, true);
335 mlx5_start_sync_reset_poll(dev);
336
337 if (!test_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS,
338 &fw_reset->reset_flags))
339 schedule_delayed_work(&fw_reset->reset_timeout_work,
340 msecs_to_jiffies(mlx5_tout_ms(dev, PCI_SYNC_UPDATE)));
341 return 0;
342 }
343
mlx5_fw_live_patch_event(struct work_struct * work)344 static void mlx5_fw_live_patch_event(struct work_struct *work)
345 {
346 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
347 fw_live_patch_work);
348 struct mlx5_core_dev *dev = fw_reset->dev;
349
350 mlx5_core_info(dev, "Live patch updated firmware version: %d.%d.%d\n", fw_rev_maj(dev),
351 fw_rev_min(dev), fw_rev_sub(dev));
352
353 if (mlx5_fw_tracer_reload(dev->tracer))
354 mlx5_core_err(dev, "Failed to reload FW tracer\n");
355 }
356
357 #if IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE)
mlx5_check_hotplug_interrupt(struct mlx5_core_dev * dev,struct pci_dev * bridge)358 static int mlx5_check_hotplug_interrupt(struct mlx5_core_dev *dev,
359 struct pci_dev *bridge)
360 {
361 u16 reg16;
362 int err;
363
364 err = pcie_capability_read_word(bridge, PCI_EXP_SLTCTL, ®16);
365 if (err)
366 return err;
367
368 if ((reg16 & PCI_EXP_SLTCTL_HPIE) && (reg16 & PCI_EXP_SLTCTL_DLLSCE)) {
369 mlx5_core_warn(dev, "FW reset is not supported as HotPlug is enabled\n");
370 return -EOPNOTSUPP;
371 }
372
373 return 0;
374 }
375 #endif
376
377 static const struct pci_device_id mgt_ifc_device_ids[] = {
378 { PCI_VDEVICE(MELLANOX, 0xc2d2) }, /* BlueField1 MGT interface device ID */
379 { PCI_VDEVICE(MELLANOX, 0xc2d3) }, /* BlueField2 MGT interface device ID */
380 { PCI_VDEVICE(MELLANOX, 0xc2d4) }, /* BlueField3-Lx MGT interface device ID */
381 { PCI_VDEVICE(MELLANOX, 0xc2d5) }, /* BlueField3 MGT interface device ID */
382 { PCI_VDEVICE(MELLANOX, 0xc2d6) }, /* BlueField4 MGT interface device ID */
383 };
384
mlx5_is_mgt_ifc_pci_device(struct mlx5_core_dev * dev,u16 dev_id)385 static bool mlx5_is_mgt_ifc_pci_device(struct mlx5_core_dev *dev, u16 dev_id)
386 {
387 int i;
388
389 for (i = 0; i < ARRAY_SIZE(mgt_ifc_device_ids); ++i)
390 if (mgt_ifc_device_ids[i].device == dev_id)
391 return true;
392
393 return false;
394 }
395
mlx5_check_dev_ids(struct mlx5_core_dev * dev,u16 dev_id)396 static int mlx5_check_dev_ids(struct mlx5_core_dev *dev, u16 dev_id)
397 {
398 struct pci_bus *bridge_bus = dev->pdev->bus;
399 struct pci_dev *sdev;
400 u16 sdev_id;
401 int err;
402
403 /* Check that all functions under the pci bridge are PFs of
404 * this device otherwise fail this function.
405 */
406 list_for_each_entry(sdev, &bridge_bus->devices, bus_list) {
407 err = pci_read_config_word(sdev, PCI_DEVICE_ID, &sdev_id);
408 if (err)
409 return pcibios_err_to_errno(err);
410
411 if (sdev_id == dev_id)
412 continue;
413
414 if (mlx5_is_mgt_ifc_pci_device(dev, sdev_id))
415 continue;
416
417 mlx5_core_warn(dev, "unrecognized dev_id (0x%x)\n", sdev_id);
418 return -EPERM;
419 }
420 return 0;
421 }
422
mlx5_is_reset_now_capable(struct mlx5_core_dev * dev,u8 reset_method)423 static bool mlx5_is_reset_now_capable(struct mlx5_core_dev *dev,
424 u8 reset_method)
425 {
426 struct pci_dev *bridge = dev->pdev->bus->self;
427 u16 dev_id;
428 int err;
429
430 if (!bridge) {
431 mlx5_core_warn(dev, "PCI bus bridge is not accessible\n");
432 return false;
433 }
434
435 if (!MLX5_CAP_GEN(dev, fast_teardown)) {
436 mlx5_core_warn(dev, "fast teardown is not supported by firmware\n");
437 return false;
438 }
439
440 if (!mlx5_core_is_ecpf(dev) && !mlx5_sf_table_empty(dev)) {
441 mlx5_core_warn(dev, "SFs should be removed before reset\n");
442 return false;
443 }
444
445 #if IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE)
446 if (reset_method != MLX5_MFRL_REG_PCI_RESET_METHOD_HOT_RESET) {
447 err = mlx5_check_hotplug_interrupt(dev, bridge);
448 if (err)
449 return false;
450 }
451 #endif
452
453 err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, &dev_id);
454 if (err)
455 return false;
456 return (!mlx5_check_dev_ids(dev, dev_id));
457 }
458
mlx5_sync_reset_request_event(struct work_struct * work)459 static void mlx5_sync_reset_request_event(struct work_struct *work)
460 {
461 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
462 reset_request_work);
463 struct mlx5_core_dev *dev = fw_reset->dev;
464 int err;
465
466 err = mlx5_fw_reset_get_reset_method(dev, &fw_reset->reset_method);
467 if (err)
468 mlx5_core_warn(dev, "Failed reading MFRL, err %d\n", err);
469
470 if (err || test_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags) ||
471 !mlx5_is_reset_now_capable(dev, fw_reset->reset_method)) {
472 err = mlx5_fw_reset_set_reset_sync_nack(dev);
473 mlx5_core_warn(dev, "PCI Sync FW Update Reset Nack %s",
474 err ? "Failed" : "Sent");
475 return;
476 }
477 if (mlx5_sync_reset_set_reset_requested(dev))
478 return;
479
480 err = mlx5_fw_reset_set_reset_sync_ack(dev);
481 if (err)
482 mlx5_core_warn(dev, "PCI Sync FW Update Reset Ack Failed. Error code: %d\n", err);
483 else
484 mlx5_core_warn(dev, "PCI Sync FW Update Reset Ack. Device reset is expected.\n");
485 }
486
mlx5_pci_link_toggle(struct mlx5_core_dev * dev,u16 dev_id)487 static int mlx5_pci_link_toggle(struct mlx5_core_dev *dev, u16 dev_id)
488 {
489 struct pci_bus *bridge_bus = dev->pdev->bus;
490 struct pci_dev *bridge = bridge_bus->self;
491 unsigned long timeout;
492 struct pci_dev *sdev;
493 int cap, err;
494 u16 reg16;
495
496 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
497 if (!cap)
498 return -EOPNOTSUPP;
499
500 list_for_each_entry(sdev, &bridge_bus->devices, bus_list) {
501 pci_save_state(sdev);
502 pci_cfg_access_lock(sdev);
503 }
504 /* PCI link toggle */
505 err = pcie_capability_set_word(bridge, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_LD);
506 if (err)
507 return pcibios_err_to_errno(err);
508 msleep(500);
509 err = pcie_capability_clear_word(bridge, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_LD);
510 if (err)
511 return pcibios_err_to_errno(err);
512
513 /* Check link */
514 if (!bridge->link_active_reporting) {
515 mlx5_core_warn(dev, "No PCI link reporting capability\n");
516 msleep(1000);
517 goto restore;
518 }
519
520 timeout = jiffies + msecs_to_jiffies(mlx5_tout_ms(dev, PCI_TOGGLE));
521 do {
522 err = pci_read_config_word(bridge, cap + PCI_EXP_LNKSTA, ®16);
523 if (err)
524 return pcibios_err_to_errno(err);
525 if (reg16 & PCI_EXP_LNKSTA_DLLLA)
526 break;
527 msleep(20);
528 } while (!time_after(jiffies, timeout));
529
530 if (reg16 & PCI_EXP_LNKSTA_DLLLA) {
531 mlx5_core_info(dev, "PCI Link up\n");
532 } else {
533 mlx5_core_err(dev, "PCI link not ready (0x%04x) after %llu ms\n",
534 reg16, mlx5_tout_ms(dev, PCI_TOGGLE));
535 err = -ETIMEDOUT;
536 goto restore;
537 }
538
539 do {
540 err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, ®16);
541 if (err)
542 return pcibios_err_to_errno(err);
543 if (reg16 == dev_id)
544 break;
545 msleep(20);
546 } while (!time_after(jiffies, timeout));
547
548 if (reg16 == dev_id) {
549 mlx5_core_info(dev, "Firmware responds to PCI config cycles again\n");
550 } else {
551 mlx5_core_err(dev, "Firmware is not responsive (0x%04x) after %llu ms\n",
552 reg16, mlx5_tout_ms(dev, PCI_TOGGLE));
553 err = -ETIMEDOUT;
554 }
555
556 restore:
557 list_for_each_entry(sdev, &bridge_bus->devices, bus_list) {
558 pci_cfg_access_unlock(sdev);
559 pci_restore_state(sdev);
560 }
561
562 return err;
563 }
564
mlx5_pci_reset_bus(struct mlx5_core_dev * dev)565 static int mlx5_pci_reset_bus(struct mlx5_core_dev *dev)
566 {
567 if (!MLX5_CAP_GEN(dev, pcie_reset_using_hotreset_method))
568 return -EOPNOTSUPP;
569
570 return pci_reset_bus(dev->pdev);
571 }
572
mlx5_sync_pci_reset(struct mlx5_core_dev * dev,u8 reset_method)573 static int mlx5_sync_pci_reset(struct mlx5_core_dev *dev, u8 reset_method)
574 {
575 u16 dev_id;
576 int err;
577
578 err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, &dev_id);
579 if (err)
580 return pcibios_err_to_errno(err);
581 err = mlx5_check_dev_ids(dev, dev_id);
582 if (err)
583 return err;
584
585 switch (reset_method) {
586 case MLX5_MFRL_REG_PCI_RESET_METHOD_LINK_TOGGLE:
587 err = mlx5_pci_link_toggle(dev, dev_id);
588 if (err)
589 mlx5_core_warn(dev, "mlx5_pci_link_toggle failed\n");
590 break;
591 case MLX5_MFRL_REG_PCI_RESET_METHOD_HOT_RESET:
592 err = mlx5_pci_reset_bus(dev);
593 if (err)
594 mlx5_core_warn(dev, "mlx5_pci_reset_bus failed\n");
595 break;
596 default:
597 return -EOPNOTSUPP;
598 }
599
600 return err;
601 }
602
mlx5_sync_reset_unload_flow(struct mlx5_core_dev * dev,bool locked)603 void mlx5_sync_reset_unload_flow(struct mlx5_core_dev *dev, bool locked)
604 {
605 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
606 unsigned long timeout;
607 int poll_freq = 20;
608 bool reset_action;
609 u8 rst_state;
610 int err;
611
612 if (locked)
613 mlx5_unload_one_devl_locked(dev, false);
614 else
615 mlx5_unload_one(dev, false);
616
617 if (!test_bit(MLX5_FW_RESET_FLAGS_UNLOAD_EVENT, &fw_reset->reset_flags))
618 return;
619
620 mlx5_set_fw_rst_ack(dev);
621 mlx5_core_warn(dev, "Sync Reset Unload done, device reset expected\n");
622
623 reset_action = false;
624 timeout = jiffies + msecs_to_jiffies(mlx5_tout_ms(dev, RESET_UNLOAD));
625 do {
626 rst_state = mlx5_get_fw_rst_state(dev);
627 if (rst_state == MLX5_FW_RST_STATE_TOGGLE_REQ ||
628 rst_state == MLX5_FW_RST_STATE_IDLE) {
629 reset_action = true;
630 break;
631 }
632 if (rst_state == MLX5_FW_RST_STATE_DROP_MODE) {
633 mlx5_core_info(dev, "Sync Reset Drop mode ack\n");
634 mlx5_set_fw_rst_ack(dev);
635 poll_freq = 1000;
636 }
637 msleep(poll_freq);
638 } while (!time_after(jiffies, timeout));
639
640 if (!reset_action) {
641 mlx5_core_err(dev, "Got timeout waiting for sync reset action, state = %u\n",
642 rst_state);
643 fw_reset->ret = -ETIMEDOUT;
644 goto done;
645 }
646
647 mlx5_core_warn(dev, "Sync Reset, got reset action. rst_state = %u\n",
648 rst_state);
649 if (rst_state == MLX5_FW_RST_STATE_TOGGLE_REQ) {
650 err = mlx5_sync_pci_reset(dev, fw_reset->reset_method);
651 if (err) {
652 mlx5_core_warn(dev, "mlx5_sync_pci_reset failed, err %d\n",
653 err);
654 fw_reset->ret = err;
655 }
656 }
657
658 done:
659 clear_bit(MLX5_FW_RESET_FLAGS_UNLOAD_EVENT, &fw_reset->reset_flags);
660 }
661
mlx5_sync_reset_now_event(struct work_struct * work)662 static void mlx5_sync_reset_now_event(struct work_struct *work)
663 {
664 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
665 reset_now_work);
666 struct mlx5_core_dev *dev = fw_reset->dev;
667 int err;
668
669 if (mlx5_sync_reset_clear_reset_requested(dev, false))
670 return;
671
672 mlx5_core_warn(dev, "Sync Reset now. Device is going to reset.\n");
673
674 err = mlx5_cmd_fast_teardown_hca(dev);
675 if (err) {
676 mlx5_core_warn(dev, "Fast teardown failed, no reset done, err %d\n", err);
677 goto done;
678 }
679
680 err = mlx5_sync_pci_reset(dev, fw_reset->reset_method);
681 if (err) {
682 mlx5_core_warn(dev, "mlx5_sync_pci_reset failed, no reset done, err %d\n", err);
683 set_bit(MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED, &fw_reset->reset_flags);
684 }
685
686 mlx5_enter_error_state(dev, true);
687 done:
688 fw_reset->ret = err;
689 mlx5_fw_reset_complete_reload(dev);
690 }
691
mlx5_sync_reset_unload_event(struct work_struct * work)692 static void mlx5_sync_reset_unload_event(struct work_struct *work)
693 {
694 struct mlx5_fw_reset *fw_reset;
695 struct mlx5_core_dev *dev;
696 int err;
697
698 fw_reset = container_of(work, struct mlx5_fw_reset, reset_unload_work);
699 dev = fw_reset->dev;
700
701 if (mlx5_sync_reset_clear_reset_requested(dev, false))
702 return;
703
704 set_bit(MLX5_FW_RESET_FLAGS_UNLOAD_EVENT, &fw_reset->reset_flags);
705 mlx5_core_warn(dev, "Sync Reset Unload. Function is forced down.\n");
706
707 err = mlx5_cmd_fast_teardown_hca(dev);
708 if (err)
709 mlx5_core_warn(dev, "Fast teardown failed, unloading, err %d\n", err);
710 else
711 mlx5_enter_error_state(dev, true);
712
713 mlx5_fw_reset_complete_reload(dev);
714 }
715
mlx5_sync_reset_abort_event(struct work_struct * work)716 static void mlx5_sync_reset_abort_event(struct work_struct *work)
717 {
718 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
719 reset_abort_work);
720 struct mlx5_core_dev *dev = fw_reset->dev;
721
722 if (mlx5_sync_reset_clear_reset_requested(dev, true))
723 return;
724 mlx5_core_warn(dev, "PCI Sync FW Update Reset Aborted.\n");
725 }
726
mlx5_sync_reset_events_handle(struct mlx5_fw_reset * fw_reset,struct mlx5_eqe * eqe)727 static void mlx5_sync_reset_events_handle(struct mlx5_fw_reset *fw_reset, struct mlx5_eqe *eqe)
728 {
729 struct mlx5_eqe_sync_fw_update *sync_fw_update_eqe;
730 u8 sync_event_rst_type;
731
732 sync_fw_update_eqe = &eqe->data.sync_fw_update;
733 sync_event_rst_type = sync_fw_update_eqe->sync_rst_state & SYNC_RST_STATE_MASK;
734 switch (sync_event_rst_type) {
735 case MLX5_SYNC_RST_STATE_RESET_REQUEST:
736 queue_work(fw_reset->wq, &fw_reset->reset_request_work);
737 break;
738 case MLX5_SYNC_RST_STATE_RESET_UNLOAD:
739 queue_work(fw_reset->wq, &fw_reset->reset_unload_work);
740 break;
741 case MLX5_SYNC_RST_STATE_RESET_NOW:
742 queue_work(fw_reset->wq, &fw_reset->reset_now_work);
743 break;
744 case MLX5_SYNC_RST_STATE_RESET_ABORT:
745 queue_work(fw_reset->wq, &fw_reset->reset_abort_work);
746 break;
747 }
748 }
749
mlx5_sync_reset_timeout_work(struct work_struct * work)750 static void mlx5_sync_reset_timeout_work(struct work_struct *work)
751 {
752 struct delayed_work *dwork = container_of(work, struct delayed_work,
753 work);
754 struct mlx5_fw_reset *fw_reset =
755 container_of(dwork, struct mlx5_fw_reset, reset_timeout_work);
756 struct mlx5_core_dev *dev = fw_reset->dev;
757
758 if (mlx5_sync_reset_clear_reset_requested(dev, true))
759 return;
760 mlx5_core_warn(dev, "PCI Sync FW Update Reset Timeout.\n");
761 }
762
fw_reset_event_notifier(struct notifier_block * nb,unsigned long action,void * data)763 static int fw_reset_event_notifier(struct notifier_block *nb, unsigned long action, void *data)
764 {
765 struct mlx5_fw_reset *fw_reset = mlx5_nb_cof(nb, struct mlx5_fw_reset, nb);
766 struct mlx5_eqe *eqe = data;
767
768 if (test_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags))
769 return NOTIFY_DONE;
770
771 switch (eqe->sub_type) {
772 case MLX5_GENERAL_SUBTYPE_FW_LIVE_PATCH_EVENT:
773 queue_work(fw_reset->wq, &fw_reset->fw_live_patch_work);
774 break;
775 case MLX5_GENERAL_SUBTYPE_PCI_SYNC_FOR_FW_UPDATE_EVENT:
776 mlx5_sync_reset_events_handle(fw_reset, eqe);
777 break;
778 default:
779 return NOTIFY_DONE;
780 }
781
782 return NOTIFY_OK;
783 }
784
mlx5_fw_reset_wait_reset_done(struct mlx5_core_dev * dev)785 int mlx5_fw_reset_wait_reset_done(struct mlx5_core_dev *dev)
786 {
787 unsigned long pci_sync_update_timeout = mlx5_tout_ms(dev, PCI_SYNC_UPDATE);
788 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
789 unsigned long timeout;
790 int err;
791
792 if (MLX5_CAP_GEN(dev, pci_sync_for_fw_update_with_driver_unload))
793 pci_sync_update_timeout += mlx5_tout_ms(dev, RESET_UNLOAD);
794 timeout = msecs_to_jiffies(pci_sync_update_timeout);
795 if (!wait_for_completion_timeout(&fw_reset->done, timeout)) {
796 mlx5_core_warn(dev, "FW sync reset timeout after %lu seconds\n",
797 pci_sync_update_timeout / 1000);
798 err = -ETIMEDOUT;
799 goto out;
800 }
801 err = fw_reset->ret;
802 if (test_and_clear_bit(MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED, &fw_reset->reset_flags)) {
803 mlx5_unload_one_devl_locked(dev, false);
804 mlx5_load_one_devl_locked(dev, true);
805 }
806 out:
807 clear_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
808 return err;
809 }
810
mlx5_fw_reset_events_start(struct mlx5_core_dev * dev)811 void mlx5_fw_reset_events_start(struct mlx5_core_dev *dev)
812 {
813 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
814
815 if (!fw_reset)
816 return;
817
818 MLX5_NB_INIT(&fw_reset->nb, fw_reset_event_notifier, GENERAL_EVENT);
819 mlx5_eq_notifier_register(dev, &fw_reset->nb);
820 }
821
mlx5_fw_reset_events_stop(struct mlx5_core_dev * dev)822 void mlx5_fw_reset_events_stop(struct mlx5_core_dev *dev)
823 {
824 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
825
826 if (!fw_reset)
827 return;
828
829 mlx5_eq_notifier_unregister(dev, &fw_reset->nb);
830 }
831
mlx5_drain_fw_reset(struct mlx5_core_dev * dev)832 void mlx5_drain_fw_reset(struct mlx5_core_dev *dev)
833 {
834 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
835
836 if (!fw_reset)
837 return;
838
839 set_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags);
840 cancel_work_sync(&fw_reset->fw_live_patch_work);
841 cancel_work_sync(&fw_reset->reset_request_work);
842 cancel_work_sync(&fw_reset->reset_unload_work);
843 cancel_work_sync(&fw_reset->reset_reload_work);
844 cancel_work_sync(&fw_reset->reset_now_work);
845 cancel_work_sync(&fw_reset->reset_abort_work);
846 cancel_delayed_work(&fw_reset->reset_timeout_work);
847 }
848
849 static const struct devlink_param mlx5_fw_reset_devlink_params[] = {
850 DEVLINK_PARAM_GENERIC(ENABLE_REMOTE_DEV_RESET, BIT(DEVLINK_PARAM_CMODE_RUNTIME),
851 mlx5_fw_reset_enable_remote_dev_reset_get,
852 mlx5_fw_reset_enable_remote_dev_reset_set, NULL),
853 };
854
mlx5_fw_reset_init(struct mlx5_core_dev * dev)855 int mlx5_fw_reset_init(struct mlx5_core_dev *dev)
856 {
857 struct mlx5_fw_reset *fw_reset;
858 int err;
859
860 if (!MLX5_CAP_MCAM_REG(dev, mfrl))
861 return 0;
862
863 fw_reset = kzalloc(sizeof(*fw_reset), GFP_KERNEL);
864 if (!fw_reset)
865 return -ENOMEM;
866 fw_reset->wq = create_singlethread_workqueue("mlx5_fw_reset_events");
867 if (!fw_reset->wq) {
868 kfree(fw_reset);
869 return -ENOMEM;
870 }
871
872 fw_reset->dev = dev;
873 dev->priv.fw_reset = fw_reset;
874
875 err = devl_params_register(priv_to_devlink(dev),
876 mlx5_fw_reset_devlink_params,
877 ARRAY_SIZE(mlx5_fw_reset_devlink_params));
878 if (err) {
879 destroy_workqueue(fw_reset->wq);
880 kfree(fw_reset);
881 return err;
882 }
883
884 INIT_WORK(&fw_reset->fw_live_patch_work, mlx5_fw_live_patch_event);
885 INIT_WORK(&fw_reset->reset_request_work, mlx5_sync_reset_request_event);
886 INIT_WORK(&fw_reset->reset_unload_work, mlx5_sync_reset_unload_event);
887 INIT_WORK(&fw_reset->reset_reload_work, mlx5_sync_reset_reload_work);
888 INIT_WORK(&fw_reset->reset_now_work, mlx5_sync_reset_now_event);
889 INIT_WORK(&fw_reset->reset_abort_work, mlx5_sync_reset_abort_event);
890 INIT_DELAYED_WORK(&fw_reset->reset_timeout_work,
891 mlx5_sync_reset_timeout_work);
892
893 init_completion(&fw_reset->done);
894 return 0;
895 }
896
mlx5_fw_reset_cleanup(struct mlx5_core_dev * dev)897 void mlx5_fw_reset_cleanup(struct mlx5_core_dev *dev)
898 {
899 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
900
901 if (!fw_reset)
902 return;
903
904 devl_params_unregister(priv_to_devlink(dev),
905 mlx5_fw_reset_devlink_params,
906 ARRAY_SIZE(mlx5_fw_reset_devlink_params));
907 destroy_workqueue(fw_reset->wq);
908 kfree(dev->priv.fw_reset);
909 }
910