1 /*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/etherdevice.h>
34 #include <linux/idr.h>
35 #include <linux/mlx5/driver.h>
36 #include <linux/mlx5/mlx5_ifc.h>
37 #include <linux/mlx5/vport.h>
38 #include <linux/mlx5/fs.h>
39 #include "mlx5_core.h"
40 #include "eswitch.h"
41 #include "esw/indir_table.h"
42 #include "esw/acl/ofld.h"
43 #include "rdma.h"
44 #include "en.h"
45 #include "fs_core.h"
46 #include "lib/mlx5.h"
47 #include "lib/devcom.h"
48 #include "lib/eq.h"
49 #include "lib/fs_chains.h"
50 #include "en_tc.h"
51 #include "en/mapping.h"
52 #include "devlink.h"
53 #include "lag/lag.h"
54 #include "en/tc/post_meter.h"
55
56 /* There are two match-all miss flows, one for unicast dst mac and
57 * one for multicast.
58 */
59 #define MLX5_ESW_MISS_FLOWS (2)
60 #define UPLINK_REP_INDEX 0
61
62 #define MLX5_ESW_VPORT_TBL_SIZE 128
63 #define MLX5_ESW_VPORT_TBL_NUM_GROUPS 4
64
65 #define MLX5_ESW_FT_OFFLOADS_DROP_RULE (1)
66
67 #define MLX5_ESW_MAX_CTRL_EQS 4
68 #define MLX5_ESW_DEFAULT_SF_COMP_EQS 8
69
70 static struct esw_vport_tbl_namespace mlx5_esw_vport_tbl_mirror_ns = {
71 .max_fte = MLX5_ESW_VPORT_TBL_SIZE,
72 .max_num_groups = MLX5_ESW_VPORT_TBL_NUM_GROUPS,
73 .flags = 0,
74 };
75
mlx5_eswitch_get_rep(struct mlx5_eswitch * esw,u16 vport_num)76 static struct mlx5_eswitch_rep *mlx5_eswitch_get_rep(struct mlx5_eswitch *esw,
77 u16 vport_num)
78 {
79 return xa_load(&esw->offloads.vport_reps, vport_num);
80 }
81
82 static void
mlx5_eswitch_set_rule_flow_source(struct mlx5_eswitch * esw,struct mlx5_flow_spec * spec,struct mlx5_esw_flow_attr * attr)83 mlx5_eswitch_set_rule_flow_source(struct mlx5_eswitch *esw,
84 struct mlx5_flow_spec *spec,
85 struct mlx5_esw_flow_attr *attr)
86 {
87 if (!MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source) || !attr || !attr->in_rep)
88 return;
89
90 if (attr->int_port) {
91 spec->flow_context.flow_source = mlx5e_tc_int_port_get_flow_source(attr->int_port);
92
93 return;
94 }
95
96 spec->flow_context.flow_source = (attr->in_rep->vport == MLX5_VPORT_UPLINK) ?
97 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK :
98 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT;
99 }
100
101 /* Actually only the upper 16 bits of reg c0 need to be cleared, but the lower 16 bits
102 * are not needed as well in the following process. So clear them all for simplicity.
103 */
104 void
mlx5_eswitch_clear_rule_source_port(struct mlx5_eswitch * esw,struct mlx5_flow_spec * spec)105 mlx5_eswitch_clear_rule_source_port(struct mlx5_eswitch *esw, struct mlx5_flow_spec *spec)
106 {
107 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
108 void *misc2;
109
110 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
111 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0);
112
113 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
114 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0);
115
116 if (!memchr_inv(misc2, 0, MLX5_ST_SZ_BYTES(fte_match_set_misc2)))
117 spec->match_criteria_enable &= ~MLX5_MATCH_MISC_PARAMETERS_2;
118 }
119 }
120
121 static void
mlx5_eswitch_set_rule_source_port(struct mlx5_eswitch * esw,struct mlx5_flow_spec * spec,struct mlx5_flow_attr * attr,struct mlx5_eswitch * src_esw,u16 vport)122 mlx5_eswitch_set_rule_source_port(struct mlx5_eswitch *esw,
123 struct mlx5_flow_spec *spec,
124 struct mlx5_flow_attr *attr,
125 struct mlx5_eswitch *src_esw,
126 u16 vport)
127 {
128 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
129 u32 metadata;
130 void *misc2;
131 void *misc;
132
133 /* Use metadata matching because vport is not represented by single
134 * VHCA in dual-port RoCE mode, and matching on source vport may fail.
135 */
136 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
137 if (mlx5_esw_indir_table_decap_vport(attr))
138 vport = mlx5_esw_indir_table_decap_vport(attr);
139
140 if (!attr->chain && esw_attr && esw_attr->int_port)
141 metadata =
142 mlx5e_tc_int_port_get_metadata_for_match(esw_attr->int_port);
143 else
144 metadata =
145 mlx5_eswitch_get_vport_metadata_for_match(src_esw, vport);
146
147 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
148 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, metadata);
149
150 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
151 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
152 mlx5_eswitch_get_vport_metadata_mask());
153
154 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
155 } else {
156 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
157 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
158
159 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
160 MLX5_SET(fte_match_set_misc, misc,
161 source_eswitch_owner_vhca_id,
162 MLX5_CAP_GEN(src_esw->dev, vhca_id));
163
164 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
165 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
166 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
167 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
168 source_eswitch_owner_vhca_id);
169
170 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
171 }
172 }
173
174 static int
esw_setup_decap_indir(struct mlx5_eswitch * esw,struct mlx5_flow_attr * attr)175 esw_setup_decap_indir(struct mlx5_eswitch *esw,
176 struct mlx5_flow_attr *attr)
177 {
178 struct mlx5_flow_table *ft;
179
180 if (!(attr->flags & MLX5_ATTR_FLAG_SRC_REWRITE))
181 return -EOPNOTSUPP;
182
183 ft = mlx5_esw_indir_table_get(esw, attr,
184 mlx5_esw_indir_table_decap_vport(attr), true);
185 return PTR_ERR_OR_ZERO(ft);
186 }
187
188 static void
esw_cleanup_decap_indir(struct mlx5_eswitch * esw,struct mlx5_flow_attr * attr)189 esw_cleanup_decap_indir(struct mlx5_eswitch *esw,
190 struct mlx5_flow_attr *attr)
191 {
192 if (mlx5_esw_indir_table_decap_vport(attr))
193 mlx5_esw_indir_table_put(esw,
194 mlx5_esw_indir_table_decap_vport(attr),
195 true);
196 }
197
198 static int
esw_setup_mtu_dest(struct mlx5_flow_destination * dest,struct mlx5e_meter_attr * meter,int i)199 esw_setup_mtu_dest(struct mlx5_flow_destination *dest,
200 struct mlx5e_meter_attr *meter,
201 int i)
202 {
203 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_RANGE;
204 dest[i].range.field = MLX5_FLOW_DEST_RANGE_FIELD_PKT_LEN;
205 dest[i].range.min = 0;
206 dest[i].range.max = meter->params.mtu;
207 dest[i].range.hit_ft = mlx5e_post_meter_get_mtu_true_ft(meter->post_meter);
208 dest[i].range.miss_ft = mlx5e_post_meter_get_mtu_false_ft(meter->post_meter);
209
210 return 0;
211 }
212
213 static int
esw_setup_sampler_dest(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,u32 sampler_id,int i)214 esw_setup_sampler_dest(struct mlx5_flow_destination *dest,
215 struct mlx5_flow_act *flow_act,
216 u32 sampler_id,
217 int i)
218 {
219 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
220 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER;
221 dest[i].sampler_id = sampler_id;
222
223 return 0;
224 }
225
226 static int
esw_setup_ft_dest(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,struct mlx5_eswitch * esw,struct mlx5_flow_attr * attr,int i)227 esw_setup_ft_dest(struct mlx5_flow_destination *dest,
228 struct mlx5_flow_act *flow_act,
229 struct mlx5_eswitch *esw,
230 struct mlx5_flow_attr *attr,
231 int i)
232 {
233 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
234 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
235 dest[i].ft = attr->dest_ft;
236
237 if (mlx5_esw_indir_table_decap_vport(attr))
238 return esw_setup_decap_indir(esw, attr);
239 return 0;
240 }
241
242 static void
esw_setup_accept_dest(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,struct mlx5_fs_chains * chains,int i)243 esw_setup_accept_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
244 struct mlx5_fs_chains *chains, int i)
245 {
246 if (mlx5_chains_ignore_flow_level_supported(chains))
247 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
248 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
249 dest[i].ft = mlx5_chains_get_tc_end_ft(chains);
250 }
251
252 static void
esw_setup_slow_path_dest(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,struct mlx5_eswitch * esw,int i)253 esw_setup_slow_path_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
254 struct mlx5_eswitch *esw, int i)
255 {
256 if (MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ignore_flow_level))
257 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
258 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
259 dest[i].ft = mlx5_eswitch_get_slow_fdb(esw);
260 }
261
262 static int
esw_setup_chain_dest(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,struct mlx5_fs_chains * chains,u32 chain,u32 prio,u32 level,int i)263 esw_setup_chain_dest(struct mlx5_flow_destination *dest,
264 struct mlx5_flow_act *flow_act,
265 struct mlx5_fs_chains *chains,
266 u32 chain, u32 prio, u32 level,
267 int i)
268 {
269 struct mlx5_flow_table *ft;
270
271 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
272 ft = mlx5_chains_get_table(chains, chain, prio, level);
273 if (IS_ERR(ft))
274 return PTR_ERR(ft);
275
276 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
277 dest[i].ft = ft;
278 return 0;
279 }
280
esw_put_dest_tables_loop(struct mlx5_eswitch * esw,struct mlx5_flow_attr * attr,int from,int to)281 static void esw_put_dest_tables_loop(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr,
282 int from, int to)
283 {
284 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
285 struct mlx5_fs_chains *chains = esw_chains(esw);
286 int i;
287
288 for (i = from; i < to; i++)
289 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
290 mlx5_chains_put_table(chains, 0, 1, 0);
291 else if (mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].vport,
292 esw_attr->dests[i].mdev))
293 mlx5_esw_indir_table_put(esw, esw_attr->dests[i].vport, false);
294 }
295
296 static bool
esw_is_chain_src_port_rewrite(struct mlx5_eswitch * esw,struct mlx5_esw_flow_attr * esw_attr)297 esw_is_chain_src_port_rewrite(struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr)
298 {
299 int i;
300
301 for (i = esw_attr->split_count; i < esw_attr->out_count; i++)
302 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
303 return true;
304 return false;
305 }
306
307 static int
esw_setup_chain_src_port_rewrite(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,struct mlx5_eswitch * esw,struct mlx5_fs_chains * chains,struct mlx5_flow_attr * attr,int * i)308 esw_setup_chain_src_port_rewrite(struct mlx5_flow_destination *dest,
309 struct mlx5_flow_act *flow_act,
310 struct mlx5_eswitch *esw,
311 struct mlx5_fs_chains *chains,
312 struct mlx5_flow_attr *attr,
313 int *i)
314 {
315 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
316 int err;
317
318 if (!(attr->flags & MLX5_ATTR_FLAG_SRC_REWRITE))
319 return -EOPNOTSUPP;
320
321 /* flow steering cannot handle more than one dest with the same ft
322 * in a single flow
323 */
324 if (esw_attr->out_count - esw_attr->split_count > 1)
325 return -EOPNOTSUPP;
326
327 err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain, 1, 0, *i);
328 if (err)
329 return err;
330
331 if (esw_attr->dests[esw_attr->split_count].pkt_reformat) {
332 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
333 flow_act->pkt_reformat = esw_attr->dests[esw_attr->split_count].pkt_reformat;
334 }
335 (*i)++;
336
337 return 0;
338 }
339
esw_cleanup_chain_src_port_rewrite(struct mlx5_eswitch * esw,struct mlx5_flow_attr * attr)340 static void esw_cleanup_chain_src_port_rewrite(struct mlx5_eswitch *esw,
341 struct mlx5_flow_attr *attr)
342 {
343 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
344
345 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count);
346 }
347
348 static bool
esw_is_indir_table(struct mlx5_eswitch * esw,struct mlx5_flow_attr * attr)349 esw_is_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
350 {
351 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
352 bool result = false;
353 int i;
354
355 /* Indirect table is supported only for flows with in_port uplink
356 * and the destination is vport on the same eswitch as the uplink,
357 * return false in case at least one of destinations doesn't meet
358 * this criteria.
359 */
360 for (i = esw_attr->split_count; i < esw_attr->out_count; i++) {
361 if (esw_attr->dests[i].vport_valid &&
362 mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].vport,
363 esw_attr->dests[i].mdev)) {
364 result = true;
365 } else {
366 result = false;
367 break;
368 }
369 }
370 return result;
371 }
372
373 static int
esw_setup_indir_table(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,struct mlx5_eswitch * esw,struct mlx5_flow_attr * attr,int * i)374 esw_setup_indir_table(struct mlx5_flow_destination *dest,
375 struct mlx5_flow_act *flow_act,
376 struct mlx5_eswitch *esw,
377 struct mlx5_flow_attr *attr,
378 int *i)
379 {
380 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
381 int j, err;
382
383 if (!(attr->flags & MLX5_ATTR_FLAG_SRC_REWRITE))
384 return -EOPNOTSUPP;
385
386 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, (*i)++) {
387 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
388 dest[*i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
389
390 dest[*i].ft = mlx5_esw_indir_table_get(esw, attr,
391 esw_attr->dests[j].vport, false);
392 if (IS_ERR(dest[*i].ft)) {
393 err = PTR_ERR(dest[*i].ft);
394 goto err_indir_tbl_get;
395 }
396 }
397
398 if (mlx5_esw_indir_table_decap_vport(attr)) {
399 err = esw_setup_decap_indir(esw, attr);
400 if (err)
401 goto err_indir_tbl_get;
402 }
403
404 return 0;
405
406 err_indir_tbl_get:
407 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, j);
408 return err;
409 }
410
esw_cleanup_indir_table(struct mlx5_eswitch * esw,struct mlx5_flow_attr * attr)411 static void esw_cleanup_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
412 {
413 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
414
415 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count);
416 esw_cleanup_decap_indir(esw, attr);
417 }
418
419 static void
esw_cleanup_chain_dest(struct mlx5_fs_chains * chains,u32 chain,u32 prio,u32 level)420 esw_cleanup_chain_dest(struct mlx5_fs_chains *chains, u32 chain, u32 prio, u32 level)
421 {
422 mlx5_chains_put_table(chains, chain, prio, level);
423 }
424
esw_same_vhca_id(struct mlx5_core_dev * mdev1,struct mlx5_core_dev * mdev2)425 static bool esw_same_vhca_id(struct mlx5_core_dev *mdev1, struct mlx5_core_dev *mdev2)
426 {
427 return MLX5_CAP_GEN(mdev1, vhca_id) == MLX5_CAP_GEN(mdev2, vhca_id);
428 }
429
esw_setup_uplink_fwd_ipsec_needed(struct mlx5_eswitch * esw,struct mlx5_esw_flow_attr * esw_attr,int attr_idx)430 static bool esw_setup_uplink_fwd_ipsec_needed(struct mlx5_eswitch *esw,
431 struct mlx5_esw_flow_attr *esw_attr,
432 int attr_idx)
433 {
434 if (esw->offloads.ft_ipsec_tx_pol &&
435 esw_attr->dests[attr_idx].vport_valid &&
436 esw_attr->dests[attr_idx].vport == MLX5_VPORT_UPLINK &&
437 /* To be aligned with software, encryption is needed only for tunnel device */
438 (esw_attr->dests[attr_idx].flags & MLX5_ESW_DEST_ENCAP_VALID) &&
439 esw_attr->dests[attr_idx].vport != esw_attr->in_rep->vport &&
440 esw_same_vhca_id(esw_attr->dests[attr_idx].mdev, esw->dev))
441 return true;
442
443 return false;
444 }
445
esw_flow_dests_fwd_ipsec_check(struct mlx5_eswitch * esw,struct mlx5_esw_flow_attr * esw_attr)446 static bool esw_flow_dests_fwd_ipsec_check(struct mlx5_eswitch *esw,
447 struct mlx5_esw_flow_attr *esw_attr)
448 {
449 int i;
450
451 if (!esw->offloads.ft_ipsec_tx_pol)
452 return true;
453
454 for (i = 0; i < esw_attr->split_count; i++)
455 if (esw_setup_uplink_fwd_ipsec_needed(esw, esw_attr, i))
456 return false;
457
458 for (i = esw_attr->split_count; i < esw_attr->out_count; i++)
459 if (esw_setup_uplink_fwd_ipsec_needed(esw, esw_attr, i) &&
460 (esw_attr->out_count - esw_attr->split_count > 1))
461 return false;
462
463 return true;
464 }
465
466 static void
esw_setup_dest_fwd_vport(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,struct mlx5_eswitch * esw,struct mlx5_esw_flow_attr * esw_attr,int attr_idx,int dest_idx,bool pkt_reformat)467 esw_setup_dest_fwd_vport(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
468 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
469 int attr_idx, int dest_idx, bool pkt_reformat)
470 {
471 dest[dest_idx].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
472 dest[dest_idx].vport.num = esw_attr->dests[attr_idx].vport;
473 if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
474 dest[dest_idx].vport.vhca_id =
475 MLX5_CAP_GEN(esw_attr->dests[attr_idx].mdev, vhca_id);
476 dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
477 if (dest[dest_idx].vport.num == MLX5_VPORT_UPLINK &&
478 mlx5_lag_is_mpesw(esw->dev))
479 dest[dest_idx].type = MLX5_FLOW_DESTINATION_TYPE_UPLINK;
480 }
481 if (esw_attr->dests[attr_idx].flags & MLX5_ESW_DEST_ENCAP_VALID) {
482 if (pkt_reformat) {
483 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
484 flow_act->pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
485 }
486 dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
487 dest[dest_idx].vport.pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
488 }
489 }
490
491 static void
esw_setup_dest_fwd_ipsec(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,struct mlx5_eswitch * esw,struct mlx5_esw_flow_attr * esw_attr,int attr_idx,int dest_idx,bool pkt_reformat)492 esw_setup_dest_fwd_ipsec(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
493 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
494 int attr_idx, int dest_idx, bool pkt_reformat)
495 {
496 dest[dest_idx].ft = esw->offloads.ft_ipsec_tx_pol;
497 dest[dest_idx].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
498 if (pkt_reformat &&
499 esw_attr->dests[attr_idx].flags & MLX5_ESW_DEST_ENCAP_VALID) {
500 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
501 flow_act->pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
502 }
503 }
504
505 static void
esw_setup_vport_dest(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,struct mlx5_eswitch * esw,struct mlx5_esw_flow_attr * esw_attr,int attr_idx,int dest_idx,bool pkt_reformat)506 esw_setup_vport_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
507 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
508 int attr_idx, int dest_idx, bool pkt_reformat)
509 {
510 if (esw_setup_uplink_fwd_ipsec_needed(esw, esw_attr, attr_idx))
511 esw_setup_dest_fwd_ipsec(dest, flow_act, esw, esw_attr,
512 attr_idx, dest_idx, pkt_reformat);
513 else
514 esw_setup_dest_fwd_vport(dest, flow_act, esw, esw_attr,
515 attr_idx, dest_idx, pkt_reformat);
516 }
517
518 static int
esw_setup_vport_dests(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,struct mlx5_eswitch * esw,struct mlx5_esw_flow_attr * esw_attr,int i)519 esw_setup_vport_dests(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
520 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
521 int i)
522 {
523 int j;
524
525 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, i++)
526 esw_setup_vport_dest(dest, flow_act, esw, esw_attr, j, i, true);
527 return i;
528 }
529
530 static bool
esw_src_port_rewrite_supported(struct mlx5_eswitch * esw)531 esw_src_port_rewrite_supported(struct mlx5_eswitch *esw)
532 {
533 return MLX5_CAP_GEN(esw->dev, reg_c_preserve) &&
534 mlx5_eswitch_vport_match_metadata_enabled(esw) &&
535 MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ignore_flow_level);
536 }
537
538 static bool
esw_dests_to_int_external(struct mlx5_flow_destination * dests,int max_dest)539 esw_dests_to_int_external(struct mlx5_flow_destination *dests, int max_dest)
540 {
541 bool internal_dest = false, external_dest = false;
542 int i;
543
544 for (i = 0; i < max_dest; i++) {
545 if (dests[i].type != MLX5_FLOW_DESTINATION_TYPE_VPORT &&
546 dests[i].type != MLX5_FLOW_DESTINATION_TYPE_UPLINK)
547 continue;
548
549 /* Uplink dest is external, but considered as internal
550 * if there is reformat because firmware uses LB+hairpin to support it.
551 */
552 if (dests[i].vport.num == MLX5_VPORT_UPLINK &&
553 !(dests[i].vport.flags & MLX5_FLOW_DEST_VPORT_REFORMAT_ID))
554 external_dest = true;
555 else
556 internal_dest = true;
557
558 if (internal_dest && external_dest)
559 return true;
560 }
561
562 return false;
563 }
564
565 static int
esw_setup_dests(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,struct mlx5_eswitch * esw,struct mlx5_flow_attr * attr,struct mlx5_flow_spec * spec,int * i)566 esw_setup_dests(struct mlx5_flow_destination *dest,
567 struct mlx5_flow_act *flow_act,
568 struct mlx5_eswitch *esw,
569 struct mlx5_flow_attr *attr,
570 struct mlx5_flow_spec *spec,
571 int *i)
572 {
573 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
574 struct mlx5_fs_chains *chains = esw_chains(esw);
575 int err = 0;
576
577 if (!mlx5_eswitch_termtbl_required(esw, attr, flow_act, spec) &&
578 esw_src_port_rewrite_supported(esw))
579 attr->flags |= MLX5_ATTR_FLAG_SRC_REWRITE;
580
581 if (attr->flags & MLX5_ATTR_FLAG_SLOW_PATH) {
582 esw_setup_slow_path_dest(dest, flow_act, esw, *i);
583 (*i)++;
584 goto out;
585 }
586
587 if (attr->flags & MLX5_ATTR_FLAG_SAMPLE) {
588 esw_setup_sampler_dest(dest, flow_act, attr->sample_attr.sampler_id, *i);
589 (*i)++;
590 } else if (attr->flags & MLX5_ATTR_FLAG_ACCEPT) {
591 esw_setup_accept_dest(dest, flow_act, chains, *i);
592 (*i)++;
593 } else if (attr->flags & MLX5_ATTR_FLAG_MTU) {
594 err = esw_setup_mtu_dest(dest, &attr->meter_attr, *i);
595 (*i)++;
596 } else if (esw_is_indir_table(esw, attr)) {
597 err = esw_setup_indir_table(dest, flow_act, esw, attr, i);
598 } else if (esw_is_chain_src_port_rewrite(esw, esw_attr)) {
599 err = esw_setup_chain_src_port_rewrite(dest, flow_act, esw, chains, attr, i);
600 } else {
601 *i = esw_setup_vport_dests(dest, flow_act, esw, esw_attr, *i);
602
603 if (attr->dest_ft) {
604 err = esw_setup_ft_dest(dest, flow_act, esw, attr, *i);
605 (*i)++;
606 } else if (attr->dest_chain) {
607 err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain,
608 1, 0, *i);
609 (*i)++;
610 }
611 }
612
613 if (attr->extra_split_ft) {
614 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
615 dest[*i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
616 dest[*i].ft = attr->extra_split_ft;
617 (*i)++;
618 }
619
620 out:
621 return err;
622 }
623
624 static void
esw_cleanup_dests(struct mlx5_eswitch * esw,struct mlx5_flow_attr * attr)625 esw_cleanup_dests(struct mlx5_eswitch *esw,
626 struct mlx5_flow_attr *attr)
627 {
628 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
629 struct mlx5_fs_chains *chains = esw_chains(esw);
630
631 if (attr->dest_ft) {
632 esw_cleanup_decap_indir(esw, attr);
633 } else if (!mlx5e_tc_attr_flags_skip(attr->flags)) {
634 if (attr->dest_chain)
635 esw_cleanup_chain_dest(chains, attr->dest_chain, 1, 0);
636 else if (esw_is_indir_table(esw, attr))
637 esw_cleanup_indir_table(esw, attr);
638 else if (esw_is_chain_src_port_rewrite(esw, esw_attr))
639 esw_cleanup_chain_src_port_rewrite(esw, attr);
640 }
641 }
642
643 static void
esw_setup_meter(struct mlx5_flow_attr * attr,struct mlx5_flow_act * flow_act)644 esw_setup_meter(struct mlx5_flow_attr *attr, struct mlx5_flow_act *flow_act)
645 {
646 struct mlx5e_flow_meter_handle *meter;
647
648 meter = attr->meter_attr.meter;
649 flow_act->exe_aso.type = attr->exe_aso_type;
650 flow_act->exe_aso.object_id = meter->obj_id;
651 flow_act->exe_aso.base_id = mlx5e_flow_meter_get_base_id(meter);
652 flow_act->exe_aso.flow_meter.meter_idx = meter->idx;
653 flow_act->exe_aso.flow_meter.init_color = MLX5_FLOW_METER_COLOR_GREEN;
654 /* use metadata reg 5 for packet color */
655 flow_act->exe_aso.return_reg_id = 5;
656 }
657
658 struct mlx5_flow_handle *
mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch * esw,struct mlx5_flow_spec * spec,struct mlx5_flow_attr * attr)659 mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
660 struct mlx5_flow_spec *spec,
661 struct mlx5_flow_attr *attr)
662 {
663 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
664 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
665 struct mlx5_fs_chains *chains = esw_chains(esw);
666 bool split = !!(esw_attr->split_count);
667 struct mlx5_vport_tbl_attr fwd_attr;
668 struct mlx5_flow_destination *dest;
669 struct mlx5_flow_handle *rule;
670 struct mlx5_flow_table *fdb;
671 int i = 0;
672
673 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
674 return ERR_PTR(-EOPNOTSUPP);
675
676 if (!mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
677 return ERR_PTR(-EOPNOTSUPP);
678
679 if (!esw_flow_dests_fwd_ipsec_check(esw, esw_attr))
680 return ERR_PTR(-EOPNOTSUPP);
681
682 dest = kcalloc(MLX5_MAX_FLOW_FWD_VPORTS + 1, sizeof(*dest), GFP_KERNEL);
683 if (!dest)
684 return ERR_PTR(-ENOMEM);
685
686 flow_act.action = attr->action;
687
688 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {
689 flow_act.vlan[0].ethtype = ntohs(esw_attr->vlan_proto[0]);
690 flow_act.vlan[0].vid = esw_attr->vlan_vid[0];
691 flow_act.vlan[0].prio = esw_attr->vlan_prio[0];
692 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2) {
693 flow_act.vlan[1].ethtype = ntohs(esw_attr->vlan_proto[1]);
694 flow_act.vlan[1].vid = esw_attr->vlan_vid[1];
695 flow_act.vlan[1].prio = esw_attr->vlan_prio[1];
696 }
697 }
698
699 mlx5_eswitch_set_rule_flow_source(esw, spec, esw_attr);
700
701 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
702 int err;
703
704 err = esw_setup_dests(dest, &flow_act, esw, attr, spec, &i);
705 if (err) {
706 rule = ERR_PTR(err);
707 goto err_create_goto_table;
708 }
709
710 /* Header rewrite with combined wire+loopback in FDB is not allowed */
711 if ((flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) &&
712 esw_dests_to_int_external(dest, i)) {
713 esw_warn(esw->dev,
714 "FDB: Header rewrite with forwarding to both internal and external dests is not allowed\n");
715 rule = ERR_PTR(-EINVAL);
716 goto err_esw_get;
717 }
718 }
719
720 if (esw_attr->decap_pkt_reformat)
721 flow_act.pkt_reformat = esw_attr->decap_pkt_reformat;
722
723 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
724 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
725 dest[i].counter = attr->counter;
726 i++;
727 }
728
729 if (attr->outer_match_level != MLX5_MATCH_NONE)
730 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
731 if (attr->inner_match_level != MLX5_MATCH_NONE)
732 spec->match_criteria_enable |= MLX5_MATCH_INNER_HEADERS;
733
734 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
735 flow_act.modify_hdr = attr->modify_hdr;
736
737 if ((flow_act.action & MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO) &&
738 attr->exe_aso_type == MLX5_EXE_ASO_FLOW_METER)
739 esw_setup_meter(attr, &flow_act);
740
741 if (split) {
742 fwd_attr.chain = attr->chain;
743 fwd_attr.prio = attr->prio;
744 fwd_attr.vport = esw_attr->in_rep->vport;
745 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
746
747 fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr);
748 } else {
749 if (attr->chain || attr->prio)
750 fdb = mlx5_chains_get_table(chains, attr->chain,
751 attr->prio, 0);
752 else
753 fdb = attr->ft;
754
755 if (!(attr->flags & MLX5_ATTR_FLAG_NO_IN_PORT))
756 mlx5_eswitch_set_rule_source_port(esw, spec, attr,
757 esw_attr->in_mdev->priv.eswitch,
758 esw_attr->in_rep->vport);
759 }
760 if (IS_ERR(fdb)) {
761 rule = ERR_CAST(fdb);
762 goto err_esw_get;
763 }
764
765 if (!i) {
766 kfree(dest);
767 dest = NULL;
768 }
769
770 if (mlx5_eswitch_termtbl_required(esw, attr, &flow_act, spec))
771 rule = mlx5_eswitch_add_termtbl_rule(esw, fdb, spec, esw_attr,
772 &flow_act, dest, i);
773 else
774 rule = mlx5_add_flow_rules(fdb, spec, &flow_act, dest, i);
775 if (IS_ERR(rule))
776 goto err_add_rule;
777 else
778 atomic64_inc(&esw->offloads.num_flows);
779
780 kfree(dest);
781 return rule;
782
783 err_add_rule:
784 if (split)
785 mlx5_esw_vporttbl_put(esw, &fwd_attr);
786 else if (attr->chain || attr->prio)
787 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
788 err_esw_get:
789 esw_cleanup_dests(esw, attr);
790 err_create_goto_table:
791 kfree(dest);
792 return rule;
793 }
794
795 struct mlx5_flow_handle *
mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch * esw,struct mlx5_flow_spec * spec,struct mlx5_flow_attr * attr)796 mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
797 struct mlx5_flow_spec *spec,
798 struct mlx5_flow_attr *attr)
799 {
800 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
801 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
802 struct mlx5_fs_chains *chains = esw_chains(esw);
803 struct mlx5_vport_tbl_attr fwd_attr;
804 struct mlx5_flow_destination *dest;
805 struct mlx5_flow_table *fast_fdb;
806 struct mlx5_flow_table *fwd_fdb;
807 struct mlx5_flow_handle *rule;
808 int i, err = 0;
809
810 dest = kcalloc(MLX5_MAX_FLOW_FWD_VPORTS + 1, sizeof(*dest), GFP_KERNEL);
811 if (!dest)
812 return ERR_PTR(-ENOMEM);
813
814 fast_fdb = mlx5_chains_get_table(chains, attr->chain, attr->prio, 0);
815 if (IS_ERR(fast_fdb)) {
816 rule = ERR_CAST(fast_fdb);
817 goto err_get_fast;
818 }
819
820 fwd_attr.chain = attr->chain;
821 fwd_attr.prio = attr->prio;
822 fwd_attr.vport = esw_attr->in_rep->vport;
823 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
824 fwd_fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr);
825 if (IS_ERR(fwd_fdb)) {
826 rule = ERR_CAST(fwd_fdb);
827 goto err_get_fwd;
828 }
829
830 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
831 for (i = 0; i < esw_attr->split_count; i++) {
832 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
833 /* Source port rewrite (forward to ovs internal port or statck device) isn't
834 * supported in the rule of split action.
835 */
836 err = -EOPNOTSUPP;
837 else
838 esw_setup_vport_dest(dest, &flow_act, esw, esw_attr, i, i, false);
839
840 if (err) {
841 rule = ERR_PTR(err);
842 goto err_chain_src_rewrite;
843 }
844 }
845 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
846 dest[i].ft = fwd_fdb;
847 i++;
848
849 mlx5_eswitch_set_rule_source_port(esw, spec, attr,
850 esw_attr->in_mdev->priv.eswitch,
851 esw_attr->in_rep->vport);
852
853 if (attr->outer_match_level != MLX5_MATCH_NONE)
854 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
855
856 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
857 rule = mlx5_add_flow_rules(fast_fdb, spec, &flow_act, dest, i);
858
859 if (IS_ERR(rule)) {
860 i = esw_attr->split_count;
861 goto err_chain_src_rewrite;
862 }
863
864 atomic64_inc(&esw->offloads.num_flows);
865
866 kfree(dest);
867 return rule;
868 err_chain_src_rewrite:
869 mlx5_esw_vporttbl_put(esw, &fwd_attr);
870 err_get_fwd:
871 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
872 err_get_fast:
873 kfree(dest);
874 return rule;
875 }
876
877 static void
__mlx5_eswitch_del_rule(struct mlx5_eswitch * esw,struct mlx5_flow_handle * rule,struct mlx5_flow_attr * attr,bool fwd_rule)878 __mlx5_eswitch_del_rule(struct mlx5_eswitch *esw,
879 struct mlx5_flow_handle *rule,
880 struct mlx5_flow_attr *attr,
881 bool fwd_rule)
882 {
883 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
884 struct mlx5_fs_chains *chains = esw_chains(esw);
885 bool split = (esw_attr->split_count > 0);
886 struct mlx5_vport_tbl_attr fwd_attr;
887 int i;
888
889 mlx5_del_flow_rules(rule);
890
891 if (!mlx5e_tc_attr_flags_skip(attr->flags)) {
892 /* unref the term table */
893 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
894 if (esw_attr->dests[i].termtbl)
895 mlx5_eswitch_termtbl_put(esw, esw_attr->dests[i].termtbl);
896 }
897 }
898
899 atomic64_dec(&esw->offloads.num_flows);
900
901 if (fwd_rule || split) {
902 fwd_attr.chain = attr->chain;
903 fwd_attr.prio = attr->prio;
904 fwd_attr.vport = esw_attr->in_rep->vport;
905 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
906 }
907
908 if (fwd_rule) {
909 mlx5_esw_vporttbl_put(esw, &fwd_attr);
910 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
911 } else {
912 if (split)
913 mlx5_esw_vporttbl_put(esw, &fwd_attr);
914 else if (attr->chain || attr->prio)
915 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
916 esw_cleanup_dests(esw, attr);
917 }
918 }
919
920 void
mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch * esw,struct mlx5_flow_handle * rule,struct mlx5_flow_attr * attr)921 mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
922 struct mlx5_flow_handle *rule,
923 struct mlx5_flow_attr *attr)
924 {
925 __mlx5_eswitch_del_rule(esw, rule, attr, false);
926 }
927
928 void
mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch * esw,struct mlx5_flow_handle * rule,struct mlx5_flow_attr * attr)929 mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
930 struct mlx5_flow_handle *rule,
931 struct mlx5_flow_attr *attr)
932 {
933 __mlx5_eswitch_del_rule(esw, rule, attr, true);
934 }
935
936 struct mlx5_flow_handle *
mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch * on_esw,struct mlx5_eswitch * from_esw,struct mlx5_eswitch_rep * rep,u32 sqn)937 mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *on_esw,
938 struct mlx5_eswitch *from_esw,
939 struct mlx5_eswitch_rep *rep,
940 u32 sqn)
941 {
942 struct mlx5_flow_act flow_act = {0};
943 struct mlx5_flow_destination dest = {};
944 struct mlx5_flow_handle *flow_rule;
945 struct mlx5_flow_spec *spec;
946 void *misc;
947 u16 vport;
948
949 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
950 if (!spec) {
951 flow_rule = ERR_PTR(-ENOMEM);
952 goto out;
953 }
954
955 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
956 MLX5_SET(fte_match_set_misc, misc, source_sqn, sqn);
957
958 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
959 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_sqn);
960
961 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
962
963 /* source vport is the esw manager */
964 vport = from_esw->manager_vport;
965
966 if (mlx5_eswitch_vport_match_metadata_enabled(on_esw)) {
967 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
968 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
969 mlx5_eswitch_get_vport_metadata_for_match(from_esw, vport));
970
971 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
972 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
973 mlx5_eswitch_get_vport_metadata_mask());
974
975 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
976 } else {
977 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
978 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
979
980 if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch))
981 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
982 MLX5_CAP_GEN(from_esw->dev, vhca_id));
983
984 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
985 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
986
987 if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch))
988 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
989 source_eswitch_owner_vhca_id);
990
991 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
992 }
993
994 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
995 dest.vport.num = rep->vport;
996 dest.vport.vhca_id = MLX5_CAP_GEN(rep->esw->dev, vhca_id);
997 dest.vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
998 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
999
1000 if (rep->vport == MLX5_VPORT_UPLINK &&
1001 on_esw == from_esw && on_esw->offloads.ft_ipsec_tx_pol) {
1002 dest.ft = on_esw->offloads.ft_ipsec_tx_pol;
1003 flow_act.flags = FLOW_ACT_IGNORE_FLOW_LEVEL;
1004 dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1005 } else {
1006 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
1007 dest.vport.num = rep->vport;
1008 dest.vport.vhca_id = MLX5_CAP_GEN(rep->esw->dev, vhca_id);
1009 dest.vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
1010 }
1011
1012 if (MLX5_CAP_ESW_FLOWTABLE(on_esw->dev, flow_source) &&
1013 rep->vport == MLX5_VPORT_UPLINK)
1014 spec->flow_context.flow_source = MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT;
1015
1016 flow_rule = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(on_esw),
1017 spec, &flow_act, &dest, 1);
1018 if (IS_ERR(flow_rule))
1019 esw_warn(on_esw->dev, "FDB: Failed to add send to vport rule err %pe\n",
1020 flow_rule);
1021 out:
1022 kvfree(spec);
1023 return flow_rule;
1024 }
1025 EXPORT_SYMBOL(mlx5_eswitch_add_send_to_vport_rule);
1026
mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle * rule)1027 void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule)
1028 {
1029 mlx5_del_flow_rules(rule);
1030 }
1031
mlx5_eswitch_del_send_to_vport_meta_rule(struct mlx5_flow_handle * rule)1032 void mlx5_eswitch_del_send_to_vport_meta_rule(struct mlx5_flow_handle *rule)
1033 {
1034 if (rule)
1035 mlx5_del_flow_rules(rule);
1036 }
1037
1038 struct mlx5_flow_handle *
mlx5_eswitch_add_send_to_vport_meta_rule(struct mlx5_eswitch * esw,u16 vport_num)1039 mlx5_eswitch_add_send_to_vport_meta_rule(struct mlx5_eswitch *esw, u16 vport_num)
1040 {
1041 struct mlx5_flow_destination dest = {};
1042 struct mlx5_flow_act flow_act = {0};
1043 struct mlx5_flow_handle *flow_rule;
1044 struct mlx5_flow_spec *spec;
1045
1046 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1047 if (!spec)
1048 return ERR_PTR(-ENOMEM);
1049
1050 MLX5_SET(fte_match_param, spec->match_criteria,
1051 misc_parameters_2.metadata_reg_c_0, mlx5_eswitch_get_vport_metadata_mask());
1052 MLX5_SET(fte_match_param, spec->match_criteria,
1053 misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK);
1054 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_1,
1055 ESW_TUN_SLOW_TABLE_GOTO_VPORT_MARK);
1056
1057 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1058 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
1059 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1060
1061 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_0,
1062 mlx5_eswitch_get_vport_metadata_for_match(esw, vport_num));
1063 dest.vport.num = vport_num;
1064
1065 flow_rule = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
1066 spec, &flow_act, &dest, 1);
1067 if (IS_ERR(flow_rule))
1068 esw_warn(esw->dev, "FDB: Failed to add send to vport meta rule vport %d, err %pe\n",
1069 vport_num, flow_rule);
1070
1071 kvfree(spec);
1072 return flow_rule;
1073 }
1074
mlx5_eswitch_reg_c1_loopback_supported(struct mlx5_eswitch * esw)1075 static bool mlx5_eswitch_reg_c1_loopback_supported(struct mlx5_eswitch *esw)
1076 {
1077 return MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
1078 MLX5_FDB_TO_VPORT_REG_C_1;
1079 }
1080
esw_set_passing_vport_metadata(struct mlx5_eswitch * esw,bool enable)1081 static int esw_set_passing_vport_metadata(struct mlx5_eswitch *esw, bool enable)
1082 {
1083 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {};
1084 u32 min[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {};
1085 u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)] = {};
1086 u8 curr, wanted;
1087 int err;
1088
1089 if (!mlx5_eswitch_reg_c1_loopback_supported(esw) &&
1090 !mlx5_eswitch_vport_match_metadata_enabled(esw))
1091 return 0;
1092
1093 MLX5_SET(query_esw_vport_context_in, in, opcode,
1094 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT);
1095 err = mlx5_cmd_exec_inout(esw->dev, query_esw_vport_context, in, out);
1096 if (err)
1097 return err;
1098
1099 curr = MLX5_GET(query_esw_vport_context_out, out,
1100 esw_vport_context.fdb_to_vport_reg_c_id);
1101 wanted = MLX5_FDB_TO_VPORT_REG_C_0;
1102 if (mlx5_eswitch_reg_c1_loopback_supported(esw))
1103 wanted |= MLX5_FDB_TO_VPORT_REG_C_1;
1104
1105 if (enable)
1106 curr |= wanted;
1107 else
1108 curr &= ~wanted;
1109
1110 MLX5_SET(modify_esw_vport_context_in, min,
1111 esw_vport_context.fdb_to_vport_reg_c_id, curr);
1112 MLX5_SET(modify_esw_vport_context_in, min,
1113 field_select.fdb_to_vport_reg_c_id, 1);
1114
1115 err = mlx5_eswitch_modify_esw_vport_context(esw->dev, 0, false, min);
1116 if (!err) {
1117 if (enable && (curr & MLX5_FDB_TO_VPORT_REG_C_1))
1118 esw->flags |= MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
1119 else
1120 esw->flags &= ~MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
1121 }
1122
1123 return err;
1124 }
1125
peer_miss_rules_setup(struct mlx5_eswitch * esw,struct mlx5_core_dev * peer_dev,struct mlx5_flow_spec * spec,struct mlx5_flow_destination * dest)1126 static void peer_miss_rules_setup(struct mlx5_eswitch *esw,
1127 struct mlx5_core_dev *peer_dev,
1128 struct mlx5_flow_spec *spec,
1129 struct mlx5_flow_destination *dest)
1130 {
1131 void *misc;
1132
1133 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1134 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1135 misc_parameters_2);
1136 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1137 mlx5_eswitch_get_vport_metadata_mask());
1138
1139 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1140 } else {
1141 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1142 misc_parameters);
1143
1144 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
1145 MLX5_CAP_GEN(peer_dev, vhca_id));
1146
1147 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1148
1149 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1150 misc_parameters);
1151 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1152 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
1153 source_eswitch_owner_vhca_id);
1154 }
1155
1156 dest->type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
1157 dest->vport.num = peer_dev->priv.eswitch->manager_vport;
1158 dest->vport.vhca_id = MLX5_CAP_GEN(peer_dev, vhca_id);
1159 dest->vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
1160 }
1161
esw_set_peer_miss_rule_source_port(struct mlx5_eswitch * esw,struct mlx5_eswitch * peer_esw,struct mlx5_flow_spec * spec,u16 vport)1162 static void esw_set_peer_miss_rule_source_port(struct mlx5_eswitch *esw,
1163 struct mlx5_eswitch *peer_esw,
1164 struct mlx5_flow_spec *spec,
1165 u16 vport)
1166 {
1167 void *misc;
1168
1169 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1170 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1171 misc_parameters_2);
1172 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1173 mlx5_eswitch_get_vport_metadata_for_match(peer_esw,
1174 vport));
1175 } else {
1176 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1177 misc_parameters);
1178 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1179 }
1180 }
1181
esw_add_fdb_peer_miss_rules(struct mlx5_eswitch * esw,struct mlx5_core_dev * peer_dev)1182 static int esw_add_fdb_peer_miss_rules(struct mlx5_eswitch *esw,
1183 struct mlx5_core_dev *peer_dev)
1184 {
1185 struct mlx5_eswitch *peer_esw = peer_dev->priv.eswitch;
1186 struct mlx5_flow_destination dest = {};
1187 struct mlx5_flow_act flow_act = {0};
1188 struct mlx5_flow_handle **flows;
1189 struct mlx5_flow_handle *flow;
1190 struct mlx5_vport *peer_vport;
1191 struct mlx5_flow_spec *spec;
1192 int err, pfindex;
1193 unsigned long i;
1194 void *misc;
1195
1196 if (!MLX5_VPORT_MANAGER(peer_dev) &&
1197 !mlx5_core_is_ecpf_esw_manager(peer_dev))
1198 return 0;
1199
1200 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1201 if (!spec)
1202 return -ENOMEM;
1203
1204 peer_miss_rules_setup(esw, peer_dev, spec, &dest);
1205
1206 flows = kvcalloc(peer_esw->total_vports, sizeof(*flows), GFP_KERNEL);
1207 if (!flows) {
1208 err = -ENOMEM;
1209 goto alloc_flows_err;
1210 }
1211
1212 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1213 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1214 misc_parameters);
1215
1216 if (mlx5_core_is_ecpf_esw_manager(peer_dev) &&
1217 mlx5_esw_host_functions_enabled(peer_dev)) {
1218 peer_vport = mlx5_eswitch_get_vport(peer_esw, MLX5_VPORT_PF);
1219 esw_set_peer_miss_rule_source_port(esw, peer_esw, spec,
1220 MLX5_VPORT_PF);
1221
1222 flow = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
1223 spec, &flow_act, &dest, 1);
1224 if (IS_ERR(flow)) {
1225 err = PTR_ERR(flow);
1226 goto add_pf_flow_err;
1227 }
1228 flows[peer_vport->index] = flow;
1229 }
1230
1231 if (mlx5_ecpf_vport_exists(peer_dev)) {
1232 peer_vport = mlx5_eswitch_get_vport(peer_esw, MLX5_VPORT_ECPF);
1233 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_ECPF);
1234 flow = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
1235 spec, &flow_act, &dest, 1);
1236 if (IS_ERR(flow)) {
1237 err = PTR_ERR(flow);
1238 goto add_ecpf_flow_err;
1239 }
1240 flows[peer_vport->index] = flow;
1241 }
1242
1243 if (mlx5_esw_host_functions_enabled(esw->dev)) {
1244 mlx5_esw_for_each_vf_vport(peer_esw, i, peer_vport,
1245 mlx5_core_max_vfs(peer_dev)) {
1246 esw_set_peer_miss_rule_source_port(esw, peer_esw,
1247 spec,
1248 peer_vport->vport);
1249
1250 flow = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
1251 spec, &flow_act, &dest, 1);
1252 if (IS_ERR(flow)) {
1253 err = PTR_ERR(flow);
1254 goto add_vf_flow_err;
1255 }
1256 flows[peer_vport->index] = flow;
1257 }
1258 }
1259
1260 if (mlx5_core_ec_sriov_enabled(peer_dev)) {
1261 mlx5_esw_for_each_ec_vf_vport(peer_esw, i, peer_vport,
1262 mlx5_core_max_ec_vfs(peer_dev)) {
1263 esw_set_peer_miss_rule_source_port(esw, peer_esw,
1264 spec,
1265 peer_vport->vport);
1266 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1267 spec, &flow_act, &dest, 1);
1268 if (IS_ERR(flow)) {
1269 err = PTR_ERR(flow);
1270 goto add_ec_vf_flow_err;
1271 }
1272 flows[peer_vport->index] = flow;
1273 }
1274 }
1275
1276 pfindex = mlx5_get_dev_index(peer_dev);
1277 if (pfindex >= MLX5_MAX_PORTS) {
1278 esw_warn(esw->dev, "Peer dev index(%d) is over the max num defined(%d)\n",
1279 pfindex, MLX5_MAX_PORTS);
1280 err = -EINVAL;
1281 goto add_ec_vf_flow_err;
1282 }
1283 esw->fdb_table.offloads.peer_miss_rules[pfindex] = flows;
1284
1285 kvfree(spec);
1286 return 0;
1287
1288 add_ec_vf_flow_err:
1289 mlx5_esw_for_each_ec_vf_vport(peer_esw, i, peer_vport,
1290 mlx5_core_max_ec_vfs(peer_dev)) {
1291 if (!flows[peer_vport->index])
1292 continue;
1293 mlx5_del_flow_rules(flows[peer_vport->index]);
1294 }
1295 add_vf_flow_err:
1296 mlx5_esw_for_each_vf_vport(peer_esw, i, peer_vport,
1297 mlx5_core_max_vfs(peer_dev)) {
1298 if (!flows[peer_vport->index])
1299 continue;
1300 mlx5_del_flow_rules(flows[peer_vport->index]);
1301 }
1302 if (mlx5_ecpf_vport_exists(peer_dev)) {
1303 peer_vport = mlx5_eswitch_get_vport(peer_esw, MLX5_VPORT_ECPF);
1304 mlx5_del_flow_rules(flows[peer_vport->index]);
1305 }
1306 add_ecpf_flow_err:
1307
1308 if (mlx5_core_is_ecpf_esw_manager(peer_dev) &&
1309 mlx5_esw_host_functions_enabled(peer_dev)) {
1310 peer_vport = mlx5_eswitch_get_vport(peer_esw, MLX5_VPORT_PF);
1311 mlx5_del_flow_rules(flows[peer_vport->index]);
1312 }
1313 add_pf_flow_err:
1314 esw_warn(esw->dev, "FDB: Failed to add peer miss flow rule err %d\n", err);
1315 kvfree(flows);
1316 alloc_flows_err:
1317 kvfree(spec);
1318 return err;
1319 }
1320
esw_del_fdb_peer_miss_rules(struct mlx5_eswitch * esw,struct mlx5_core_dev * peer_dev)1321 static void esw_del_fdb_peer_miss_rules(struct mlx5_eswitch *esw,
1322 struct mlx5_core_dev *peer_dev)
1323 {
1324 struct mlx5_eswitch *peer_esw = peer_dev->priv.eswitch;
1325 u16 peer_index = mlx5_get_dev_index(peer_dev);
1326 struct mlx5_flow_handle **flows;
1327 struct mlx5_vport *peer_vport;
1328 unsigned long i;
1329
1330 flows = esw->fdb_table.offloads.peer_miss_rules[peer_index];
1331 if (!flows)
1332 return;
1333
1334 if (mlx5_core_ec_sriov_enabled(peer_dev)) {
1335 mlx5_esw_for_each_ec_vf_vport(peer_esw, i, peer_vport,
1336 mlx5_core_max_ec_vfs(peer_dev))
1337 mlx5_del_flow_rules(flows[peer_vport->index]);
1338 }
1339
1340 mlx5_esw_for_each_vf_vport(peer_esw, i, peer_vport,
1341 mlx5_core_max_vfs(peer_dev))
1342 mlx5_del_flow_rules(flows[peer_vport->index]);
1343
1344 if (mlx5_ecpf_vport_exists(peer_dev)) {
1345 peer_vport = mlx5_eswitch_get_vport(peer_esw, MLX5_VPORT_ECPF);
1346 mlx5_del_flow_rules(flows[peer_vport->index]);
1347 }
1348
1349 if (mlx5_core_is_ecpf_esw_manager(peer_dev)) {
1350 peer_vport = mlx5_eswitch_get_vport(peer_esw, MLX5_VPORT_PF);
1351 mlx5_del_flow_rules(flows[peer_vport->index]);
1352 }
1353
1354 kvfree(flows);
1355 esw->fdb_table.offloads.peer_miss_rules[peer_index] = NULL;
1356 }
1357
esw_add_fdb_miss_rule(struct mlx5_eswitch * esw)1358 static int esw_add_fdb_miss_rule(struct mlx5_eswitch *esw)
1359 {
1360 struct mlx5_flow_act flow_act = {0};
1361 struct mlx5_flow_destination dest = {};
1362 struct mlx5_flow_handle *flow_rule = NULL;
1363 struct mlx5_flow_spec *spec;
1364 void *headers_c;
1365 void *headers_v;
1366 int err = 0;
1367 u8 *dmac_c;
1368 u8 *dmac_v;
1369
1370 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1371 if (!spec) {
1372 err = -ENOMEM;
1373 goto out;
1374 }
1375
1376 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
1377 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1378 outer_headers);
1379 dmac_c = MLX5_ADDR_OF(fte_match_param, headers_c,
1380 outer_headers.dmac_47_16);
1381 dmac_c[0] = 0x01;
1382
1383 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
1384 dest.vport.num = esw->manager_vport;
1385 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1386
1387 flow_rule = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
1388 spec, &flow_act, &dest, 1);
1389 if (IS_ERR(flow_rule)) {
1390 err = PTR_ERR(flow_rule);
1391 esw_warn(esw->dev, "FDB: Failed to add unicast miss flow rule err %d\n", err);
1392 goto out;
1393 }
1394
1395 esw->fdb_table.offloads.miss_rule_uni = flow_rule;
1396
1397 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1398 outer_headers);
1399 dmac_v = MLX5_ADDR_OF(fte_match_param, headers_v,
1400 outer_headers.dmac_47_16);
1401 dmac_v[0] = 0x01;
1402 flow_rule = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
1403 spec, &flow_act, &dest, 1);
1404 if (IS_ERR(flow_rule)) {
1405 err = PTR_ERR(flow_rule);
1406 esw_warn(esw->dev, "FDB: Failed to add multicast miss flow rule err %d\n", err);
1407 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
1408 goto out;
1409 }
1410
1411 esw->fdb_table.offloads.miss_rule_multi = flow_rule;
1412
1413 out:
1414 kvfree(spec);
1415 return err;
1416 }
1417
1418 struct mlx5_flow_handle *
esw_add_restore_rule(struct mlx5_eswitch * esw,u32 tag)1419 esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag)
1420 {
1421 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
1422 struct mlx5_flow_table *ft = esw->offloads.ft_offloads_restore;
1423 struct mlx5_flow_context *flow_context;
1424 struct mlx5_flow_handle *flow_rule;
1425 struct mlx5_flow_destination dest;
1426 struct mlx5_flow_spec *spec;
1427 void *misc;
1428
1429 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
1430 return ERR_PTR(-EOPNOTSUPP);
1431
1432 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1433 if (!spec)
1434 return ERR_PTR(-ENOMEM);
1435
1436 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1437 misc_parameters_2);
1438 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1439 ESW_REG_C0_USER_DATA_METADATA_MASK);
1440 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1441 misc_parameters_2);
1442 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, tag);
1443 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1444 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1445 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1446 flow_act.modify_hdr = esw->offloads.restore_copy_hdr_id;
1447
1448 flow_context = &spec->flow_context;
1449 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
1450 flow_context->flow_tag = tag;
1451 dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1452 dest.ft = esw->offloads.ft_offloads;
1453
1454 flow_rule = mlx5_add_flow_rules(ft, spec, &flow_act, &dest, 1);
1455 kvfree(spec);
1456
1457 if (IS_ERR(flow_rule))
1458 esw_warn(esw->dev,
1459 "Failed to create restore rule for tag: %d, err(%d)\n",
1460 tag, (int)PTR_ERR(flow_rule));
1461
1462 return flow_rule;
1463 }
1464
1465 #define MAX_PF_SQ 256
1466 #define MAX_SQ_NVPORTS 32
1467
1468 void
mlx5_esw_set_flow_group_source_port(struct mlx5_eswitch * esw,u32 * flow_group_in,int match_params)1469 mlx5_esw_set_flow_group_source_port(struct mlx5_eswitch *esw,
1470 u32 *flow_group_in,
1471 int match_params)
1472 {
1473 void *match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1474 flow_group_in,
1475 match_criteria);
1476
1477 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1478 MLX5_SET(create_flow_group_in, flow_group_in,
1479 match_criteria_enable,
1480 MLX5_MATCH_MISC_PARAMETERS_2 | match_params);
1481
1482 MLX5_SET(fte_match_param, match_criteria,
1483 misc_parameters_2.metadata_reg_c_0,
1484 mlx5_eswitch_get_vport_metadata_mask());
1485 } else {
1486 MLX5_SET(create_flow_group_in, flow_group_in,
1487 match_criteria_enable,
1488 MLX5_MATCH_MISC_PARAMETERS | match_params);
1489
1490 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1491 misc_parameters.source_port);
1492 }
1493 }
1494
1495 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
esw_vport_tbl_put(struct mlx5_eswitch * esw)1496 static void esw_vport_tbl_put(struct mlx5_eswitch *esw)
1497 {
1498 struct mlx5_vport_tbl_attr attr;
1499 struct mlx5_vport *vport;
1500 unsigned long i;
1501
1502 attr.chain = 0;
1503 attr.prio = 1;
1504 mlx5_esw_for_each_vport(esw, i, vport) {
1505 attr.vport = vport->vport;
1506 attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
1507 mlx5_esw_vporttbl_put(esw, &attr);
1508 }
1509 }
1510
esw_vport_tbl_get(struct mlx5_eswitch * esw)1511 static int esw_vport_tbl_get(struct mlx5_eswitch *esw)
1512 {
1513 struct mlx5_vport_tbl_attr attr;
1514 struct mlx5_flow_table *fdb;
1515 struct mlx5_vport *vport;
1516 unsigned long i;
1517
1518 attr.chain = 0;
1519 attr.prio = 1;
1520 mlx5_esw_for_each_vport(esw, i, vport) {
1521 attr.vport = vport->vport;
1522 attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
1523 fdb = mlx5_esw_vporttbl_get(esw, &attr);
1524 if (IS_ERR(fdb))
1525 goto out;
1526 }
1527 return 0;
1528
1529 out:
1530 esw_vport_tbl_put(esw);
1531 return PTR_ERR(fdb);
1532 }
1533
1534 #define fdb_modify_header_fwd_to_table_supported(esw) \
1535 (MLX5_CAP_ESW_FLOWTABLE((esw)->dev, fdb_modify_header_fwd_to_table))
esw_init_chains_offload_flags(struct mlx5_eswitch * esw,u32 * flags)1536 static void esw_init_chains_offload_flags(struct mlx5_eswitch *esw, u32 *flags)
1537 {
1538 struct mlx5_core_dev *dev = esw->dev;
1539
1540 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev, ignore_flow_level))
1541 *flags |= MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
1542
1543 if (!MLX5_CAP_ESW_FLOWTABLE(dev, multi_fdb_encap) &&
1544 esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) {
1545 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1546 esw_warn(dev, "Tc chains and priorities offload aren't supported, update firmware if needed\n");
1547 } else if (!mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
1548 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1549 esw_warn(dev, "Tc chains and priorities offload aren't supported\n");
1550 } else if (!fdb_modify_header_fwd_to_table_supported(esw)) {
1551 /* Disabled when ttl workaround is needed, e.g
1552 * when ESWITCH_IPV4_TTL_MODIFY_ENABLE = true in mlxconfig
1553 */
1554 esw_warn(dev,
1555 "Tc chains and priorities offload aren't supported, check firmware version, or mlxconfig settings\n");
1556 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1557 } else {
1558 *flags |= MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1559 esw_info(dev, "Supported tc chains and prios offload\n");
1560 }
1561
1562 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1563 *flags |= MLX5_CHAINS_FT_TUNNEL_SUPPORTED;
1564 }
1565
1566 static int
esw_chains_create(struct mlx5_eswitch * esw,struct mlx5_flow_table * miss_fdb)1567 esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1568 {
1569 struct mlx5_core_dev *dev = esw->dev;
1570 struct mlx5_flow_table *nf_ft, *ft;
1571 struct mlx5_chains_attr attr = {};
1572 struct mlx5_fs_chains *chains;
1573 int err;
1574
1575 esw_init_chains_offload_flags(esw, &attr.flags);
1576 attr.ns = MLX5_FLOW_NAMESPACE_FDB;
1577 attr.max_grp_num = esw->params.large_group_num;
1578 attr.default_ft = miss_fdb;
1579 attr.mapping = esw->offloads.reg_c0_obj_pool;
1580
1581 chains = mlx5_chains_create(dev, &attr);
1582 if (IS_ERR(chains)) {
1583 err = PTR_ERR(chains);
1584 esw_warn(dev, "Failed to create fdb chains err(%d)\n", err);
1585 return err;
1586 }
1587 mlx5_chains_print_info(chains);
1588
1589 esw->fdb_table.offloads.esw_chains_priv = chains;
1590
1591 /* Create tc_end_ft which is the always created ft chain */
1592 nf_ft = mlx5_chains_get_table(chains, mlx5_chains_get_nf_ft_chain(chains),
1593 1, 0);
1594 if (IS_ERR(nf_ft)) {
1595 err = PTR_ERR(nf_ft);
1596 goto nf_ft_err;
1597 }
1598
1599 /* Always open the root for fast path */
1600 ft = mlx5_chains_get_table(chains, 0, 1, 0);
1601 if (IS_ERR(ft)) {
1602 err = PTR_ERR(ft);
1603 goto level_0_err;
1604 }
1605
1606 /* Open level 1 for split fdb rules now if prios isn't supported */
1607 if (!mlx5_chains_prios_supported(chains)) {
1608 err = esw_vport_tbl_get(esw);
1609 if (err)
1610 goto level_1_err;
1611 }
1612
1613 mlx5_chains_set_end_ft(chains, nf_ft);
1614
1615 return 0;
1616
1617 level_1_err:
1618 mlx5_chains_put_table(chains, 0, 1, 0);
1619 level_0_err:
1620 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1621 nf_ft_err:
1622 mlx5_chains_destroy(chains);
1623 esw->fdb_table.offloads.esw_chains_priv = NULL;
1624
1625 return err;
1626 }
1627
1628 static void
esw_chains_destroy(struct mlx5_eswitch * esw,struct mlx5_fs_chains * chains)1629 esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1630 {
1631 if (!mlx5_chains_prios_supported(chains))
1632 esw_vport_tbl_put(esw);
1633 mlx5_chains_put_table(chains, 0, 1, 0);
1634 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1635 mlx5_chains_destroy(chains);
1636 }
1637
1638 #else /* CONFIG_MLX5_CLS_ACT */
1639
1640 static int
esw_chains_create(struct mlx5_eswitch * esw,struct mlx5_flow_table * miss_fdb)1641 esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1642 { return 0; }
1643
1644 static void
esw_chains_destroy(struct mlx5_eswitch * esw,struct mlx5_fs_chains * chains)1645 esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1646 {}
1647
1648 #endif
1649
1650 static int
esw_create_send_to_vport_group(struct mlx5_eswitch * esw,struct mlx5_flow_table * fdb,u32 * flow_group_in,int * ix)1651 esw_create_send_to_vport_group(struct mlx5_eswitch *esw,
1652 struct mlx5_flow_table *fdb,
1653 u32 *flow_group_in,
1654 int *ix)
1655 {
1656 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1657 struct mlx5_flow_group *g;
1658 void *match_criteria;
1659 int count, err = 0;
1660
1661 memset(flow_group_in, 0, inlen);
1662
1663 mlx5_esw_set_flow_group_source_port(esw, flow_group_in, MLX5_MATCH_MISC_PARAMETERS);
1664
1665 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1666 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_sqn);
1667
1668 if (!mlx5_eswitch_vport_match_metadata_enabled(esw) &&
1669 MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
1670 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1671 misc_parameters.source_eswitch_owner_vhca_id);
1672 MLX5_SET(create_flow_group_in, flow_group_in,
1673 source_eswitch_owner_vhca_id_valid, 1);
1674 }
1675
1676 /* See comment at table_size calculation */
1677 count = MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ);
1678 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1679 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, *ix + count - 1);
1680 *ix += count;
1681
1682 g = mlx5_create_flow_group(fdb, flow_group_in);
1683 if (IS_ERR(g)) {
1684 err = PTR_ERR(g);
1685 esw_warn(esw->dev, "Failed to create send-to-vport flow group err(%d)\n", err);
1686 goto out;
1687 }
1688 esw->fdb_table.offloads.send_to_vport_grp = g;
1689
1690 out:
1691 return err;
1692 }
1693
1694 static int
esw_create_meta_send_to_vport_group(struct mlx5_eswitch * esw,struct mlx5_flow_table * fdb,u32 * flow_group_in,int * ix)1695 esw_create_meta_send_to_vport_group(struct mlx5_eswitch *esw,
1696 struct mlx5_flow_table *fdb,
1697 u32 *flow_group_in,
1698 int *ix)
1699 {
1700 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1701 struct mlx5_flow_group *g;
1702 void *match_criteria;
1703 int err = 0;
1704
1705 if (!esw_src_port_rewrite_supported(esw))
1706 return 0;
1707
1708 memset(flow_group_in, 0, inlen);
1709
1710 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1711 MLX5_MATCH_MISC_PARAMETERS_2);
1712
1713 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1714
1715 MLX5_SET(fte_match_param, match_criteria,
1716 misc_parameters_2.metadata_reg_c_0,
1717 mlx5_eswitch_get_vport_metadata_mask());
1718 MLX5_SET(fte_match_param, match_criteria,
1719 misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK);
1720
1721 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, *ix);
1722 MLX5_SET(create_flow_group_in, flow_group_in,
1723 end_flow_index, *ix + esw->total_vports - 1);
1724 *ix += esw->total_vports;
1725
1726 g = mlx5_create_flow_group(fdb, flow_group_in);
1727 if (IS_ERR(g)) {
1728 err = PTR_ERR(g);
1729 esw_warn(esw->dev,
1730 "Failed to create send-to-vport meta flow group err(%d)\n", err);
1731 goto send_vport_meta_err;
1732 }
1733 esw->fdb_table.offloads.send_to_vport_meta_grp = g;
1734
1735 return 0;
1736
1737 send_vport_meta_err:
1738 return err;
1739 }
1740
1741 static int
esw_create_peer_esw_miss_group(struct mlx5_eswitch * esw,struct mlx5_flow_table * fdb,u32 * flow_group_in,int * ix)1742 esw_create_peer_esw_miss_group(struct mlx5_eswitch *esw,
1743 struct mlx5_flow_table *fdb,
1744 u32 *flow_group_in,
1745 int *ix)
1746 {
1747 int max_peer_ports = (esw->total_vports - 1) * (MLX5_MAX_PORTS - 1);
1748 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1749 struct mlx5_flow_group *g;
1750 void *match_criteria;
1751 int err = 0;
1752
1753 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
1754 return 0;
1755
1756 memset(flow_group_in, 0, inlen);
1757
1758 mlx5_esw_set_flow_group_source_port(esw, flow_group_in, 0);
1759
1760 if (!mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1761 match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1762 flow_group_in,
1763 match_criteria);
1764
1765 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1766 misc_parameters.source_eswitch_owner_vhca_id);
1767
1768 MLX5_SET(create_flow_group_in, flow_group_in,
1769 source_eswitch_owner_vhca_id_valid, 1);
1770 }
1771
1772 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, *ix);
1773 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1774 *ix + max_peer_ports);
1775 *ix += max_peer_ports + 1;
1776
1777 g = mlx5_create_flow_group(fdb, flow_group_in);
1778 if (IS_ERR(g)) {
1779 err = PTR_ERR(g);
1780 esw_warn(esw->dev, "Failed to create peer miss flow group err(%d)\n", err);
1781 goto out;
1782 }
1783 esw->fdb_table.offloads.peer_miss_grp = g;
1784
1785 out:
1786 return err;
1787 }
1788
1789 static int
esw_create_miss_group(struct mlx5_eswitch * esw,struct mlx5_flow_table * fdb,u32 * flow_group_in,int * ix)1790 esw_create_miss_group(struct mlx5_eswitch *esw,
1791 struct mlx5_flow_table *fdb,
1792 u32 *flow_group_in,
1793 int *ix)
1794 {
1795 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1796 struct mlx5_flow_group *g;
1797 void *match_criteria;
1798 int err = 0;
1799 u8 *dmac;
1800
1801 memset(flow_group_in, 0, inlen);
1802
1803 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1804 MLX5_MATCH_OUTER_HEADERS);
1805 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
1806 match_criteria);
1807 dmac = MLX5_ADDR_OF(fte_match_param, match_criteria,
1808 outer_headers.dmac_47_16);
1809 dmac[0] = 0x01;
1810
1811 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, *ix);
1812 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1813 *ix + MLX5_ESW_MISS_FLOWS);
1814
1815 g = mlx5_create_flow_group(fdb, flow_group_in);
1816 if (IS_ERR(g)) {
1817 err = PTR_ERR(g);
1818 esw_warn(esw->dev, "Failed to create miss flow group err(%d)\n", err);
1819 goto miss_err;
1820 }
1821 esw->fdb_table.offloads.miss_grp = g;
1822
1823 err = esw_add_fdb_miss_rule(esw);
1824 if (err)
1825 goto miss_rule_err;
1826
1827 return 0;
1828
1829 miss_rule_err:
1830 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1831 miss_err:
1832 return err;
1833 }
1834
esw_create_offloads_fdb_tables(struct mlx5_eswitch * esw)1835 static int esw_create_offloads_fdb_tables(struct mlx5_eswitch *esw)
1836 {
1837 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1838 struct mlx5_flow_table_attr ft_attr = {};
1839 struct mlx5_core_dev *dev = esw->dev;
1840 struct mlx5_flow_namespace *root_ns;
1841 struct mlx5_flow_table *fdb = NULL;
1842 int table_size, ix = 0, err = 0;
1843 u32 flags = 0, *flow_group_in;
1844
1845 esw_debug(esw->dev, "Create offloads FDB Tables\n");
1846
1847 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1848 if (!flow_group_in)
1849 return -ENOMEM;
1850
1851 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
1852 if (!root_ns) {
1853 esw_warn(dev, "Failed to get FDB flow namespace\n");
1854 err = -EOPNOTSUPP;
1855 goto ns_err;
1856 }
1857 esw->fdb_table.offloads.ns = root_ns;
1858 err = mlx5_flow_namespace_set_mode(root_ns,
1859 esw->dev->priv.steering->mode);
1860 if (err) {
1861 esw_warn(dev, "Failed to set FDB namespace steering mode\n");
1862 goto ns_err;
1863 }
1864
1865 /* To be strictly correct:
1866 * MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ)
1867 * should be:
1868 * esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ +
1869 * peer_esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ
1870 * but as the peer device might not be in switchdev mode it's not
1871 * possible. We use the fact that by default FW sets max vfs and max sfs
1872 * to the same value on both devices. If it needs to be changed in the future note
1873 * the peer miss group should also be created based on the number of
1874 * total vports of the peer (currently is also uses esw->total_vports).
1875 */
1876 table_size = MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ) +
1877 esw->total_vports * MLX5_MAX_PORTS + MLX5_ESW_MISS_FLOWS;
1878
1879 /* create the slow path fdb with encap set, so further table instances
1880 * can be created at run time while VFs are probed if the FW allows that.
1881 */
1882 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1883 flags |= (MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT |
1884 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP);
1885
1886 ft_attr.flags = flags;
1887 ft_attr.max_fte = table_size;
1888 ft_attr.prio = FDB_SLOW_PATH;
1889
1890 fdb = mlx5_create_flow_table(root_ns, &ft_attr);
1891 if (IS_ERR(fdb)) {
1892 err = PTR_ERR(fdb);
1893 esw_warn(dev, "Failed to create slow path FDB Table err %d\n", err);
1894 goto slow_fdb_err;
1895 }
1896 esw->fdb_table.offloads.slow_fdb = fdb;
1897
1898 /* Create empty TC-miss managed table. This allows plugging in following
1899 * priorities without directly exposing their level 0 table to
1900 * eswitch_offloads and passing it as miss_fdb to following call to
1901 * esw_chains_create().
1902 */
1903 memset(&ft_attr, 0, sizeof(ft_attr));
1904 ft_attr.prio = FDB_TC_MISS;
1905 esw->fdb_table.offloads.tc_miss_table = mlx5_create_flow_table(root_ns, &ft_attr);
1906 if (IS_ERR(esw->fdb_table.offloads.tc_miss_table)) {
1907 err = PTR_ERR(esw->fdb_table.offloads.tc_miss_table);
1908 esw_warn(dev, "Failed to create TC miss FDB Table err %d\n", err);
1909 goto tc_miss_table_err;
1910 }
1911
1912 err = esw_chains_create(esw, esw->fdb_table.offloads.tc_miss_table);
1913 if (err) {
1914 esw_warn(dev, "Failed to open fdb chains err(%d)\n", err);
1915 goto fdb_chains_err;
1916 }
1917
1918 err = esw_create_send_to_vport_group(esw, fdb, flow_group_in, &ix);
1919 if (err)
1920 goto send_vport_err;
1921
1922 err = esw_create_meta_send_to_vport_group(esw, fdb, flow_group_in, &ix);
1923 if (err)
1924 goto send_vport_meta_err;
1925
1926 err = esw_create_peer_esw_miss_group(esw, fdb, flow_group_in, &ix);
1927 if (err)
1928 goto peer_miss_err;
1929
1930 err = esw_create_miss_group(esw, fdb, flow_group_in, &ix);
1931 if (err)
1932 goto miss_err;
1933
1934 kvfree(flow_group_in);
1935 return 0;
1936
1937 miss_err:
1938 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1939 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
1940 peer_miss_err:
1941 if (esw->fdb_table.offloads.send_to_vport_meta_grp)
1942 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp);
1943 send_vport_meta_err:
1944 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1945 send_vport_err:
1946 esw_chains_destroy(esw, esw_chains(esw));
1947 fdb_chains_err:
1948 mlx5_destroy_flow_table(esw->fdb_table.offloads.tc_miss_table);
1949 tc_miss_table_err:
1950 mlx5_destroy_flow_table(mlx5_eswitch_get_slow_fdb(esw));
1951 slow_fdb_err:
1952 /* Holds true only as long as DMFS is the default */
1953 mlx5_flow_namespace_set_mode(root_ns, MLX5_FLOW_STEERING_MODE_DMFS);
1954 ns_err:
1955 kvfree(flow_group_in);
1956 return err;
1957 }
1958
esw_destroy_offloads_fdb_tables(struct mlx5_eswitch * esw)1959 static void esw_destroy_offloads_fdb_tables(struct mlx5_eswitch *esw)
1960 {
1961 if (!mlx5_eswitch_get_slow_fdb(esw))
1962 return;
1963
1964 esw_debug(esw->dev, "Destroy offloads FDB Tables\n");
1965 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_multi);
1966 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
1967 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1968 if (esw->fdb_table.offloads.send_to_vport_meta_grp)
1969 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp);
1970 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1971 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
1972 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1973
1974 esw_chains_destroy(esw, esw_chains(esw));
1975
1976 mlx5_destroy_flow_table(esw->fdb_table.offloads.tc_miss_table);
1977 mlx5_destroy_flow_table(mlx5_eswitch_get_slow_fdb(esw));
1978 /* Holds true only as long as DMFS is the default */
1979 mlx5_flow_namespace_set_mode(esw->fdb_table.offloads.ns,
1980 MLX5_FLOW_STEERING_MODE_DMFS);
1981 }
1982
esw_get_nr_ft_offloads_steering_src_ports(struct mlx5_eswitch * esw)1983 static int esw_get_nr_ft_offloads_steering_src_ports(struct mlx5_eswitch *esw)
1984 {
1985 int nvports;
1986
1987 nvports = esw->total_vports + MLX5_ESW_MISS_FLOWS;
1988 if (mlx5e_tc_int_port_supported(esw))
1989 nvports += MLX5E_TC_MAX_INT_PORT_NUM;
1990
1991 return nvports;
1992 }
1993
esw_create_offloads_table(struct mlx5_eswitch * esw)1994 static int esw_create_offloads_table(struct mlx5_eswitch *esw)
1995 {
1996 struct mlx5_flow_table_attr ft_attr = {};
1997 struct mlx5_core_dev *dev = esw->dev;
1998 struct mlx5_flow_table *ft_offloads;
1999 struct mlx5_flow_namespace *ns;
2000 int err = 0;
2001
2002 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
2003 if (!ns) {
2004 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
2005 return -EOPNOTSUPP;
2006 }
2007
2008 ft_attr.max_fte = esw_get_nr_ft_offloads_steering_src_ports(esw) +
2009 MLX5_ESW_FT_OFFLOADS_DROP_RULE;
2010 ft_attr.prio = 1;
2011
2012 ft_offloads = mlx5_create_flow_table(ns, &ft_attr);
2013 if (IS_ERR(ft_offloads)) {
2014 err = PTR_ERR(ft_offloads);
2015 esw_warn(esw->dev, "Failed to create offloads table, err %d\n", err);
2016 return err;
2017 }
2018
2019 esw->offloads.ft_offloads = ft_offloads;
2020 return 0;
2021 }
2022
esw_destroy_offloads_table(struct mlx5_eswitch * esw)2023 static void esw_destroy_offloads_table(struct mlx5_eswitch *esw)
2024 {
2025 struct mlx5_esw_offload *offloads = &esw->offloads;
2026
2027 mlx5_destroy_flow_table(offloads->ft_offloads);
2028 }
2029
esw_create_vport_rx_group(struct mlx5_eswitch * esw)2030 static int esw_create_vport_rx_group(struct mlx5_eswitch *esw)
2031 {
2032 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
2033 struct mlx5_flow_group *g;
2034 u32 *flow_group_in;
2035 int nvports;
2036 int err = 0;
2037
2038 nvports = esw_get_nr_ft_offloads_steering_src_ports(esw);
2039 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2040 if (!flow_group_in)
2041 return -ENOMEM;
2042
2043 mlx5_esw_set_flow_group_source_port(esw, flow_group_in, 0);
2044
2045 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
2046 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, nvports - 1);
2047
2048 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
2049
2050 if (IS_ERR(g)) {
2051 err = PTR_ERR(g);
2052 mlx5_core_warn(esw->dev, "Failed to create vport rx group err %d\n", err);
2053 goto out;
2054 }
2055
2056 esw->offloads.vport_rx_group = g;
2057 out:
2058 kvfree(flow_group_in);
2059 return err;
2060 }
2061
esw_destroy_vport_rx_group(struct mlx5_eswitch * esw)2062 static void esw_destroy_vport_rx_group(struct mlx5_eswitch *esw)
2063 {
2064 mlx5_destroy_flow_group(esw->offloads.vport_rx_group);
2065 }
2066
esw_create_vport_rx_drop_rule_index(struct mlx5_eswitch * esw)2067 static int esw_create_vport_rx_drop_rule_index(struct mlx5_eswitch *esw)
2068 {
2069 /* ft_offloads table is enlarged by MLX5_ESW_FT_OFFLOADS_DROP_RULE (1)
2070 * for the drop rule, which is placed at the end of the table.
2071 * So return the total of vport and int_port as rule index.
2072 */
2073 return esw_get_nr_ft_offloads_steering_src_ports(esw);
2074 }
2075
esw_create_vport_rx_drop_group(struct mlx5_eswitch * esw)2076 static int esw_create_vport_rx_drop_group(struct mlx5_eswitch *esw)
2077 {
2078 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
2079 struct mlx5_flow_group *g;
2080 u32 *flow_group_in;
2081 int flow_index;
2082 int err = 0;
2083
2084 flow_index = esw_create_vport_rx_drop_rule_index(esw);
2085
2086 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2087 if (!flow_group_in)
2088 return -ENOMEM;
2089
2090 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, flow_index);
2091 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, flow_index);
2092
2093 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
2094
2095 if (IS_ERR(g)) {
2096 err = PTR_ERR(g);
2097 mlx5_core_warn(esw->dev, "Failed to create vport rx drop group err %d\n", err);
2098 goto out;
2099 }
2100
2101 esw->offloads.vport_rx_drop_group = g;
2102 out:
2103 kvfree(flow_group_in);
2104 return err;
2105 }
2106
esw_destroy_vport_rx_drop_group(struct mlx5_eswitch * esw)2107 static void esw_destroy_vport_rx_drop_group(struct mlx5_eswitch *esw)
2108 {
2109 if (esw->offloads.vport_rx_drop_group)
2110 mlx5_destroy_flow_group(esw->offloads.vport_rx_drop_group);
2111 }
2112
2113 void
mlx5_esw_set_spec_source_port(struct mlx5_eswitch * esw,u16 vport,struct mlx5_flow_spec * spec)2114 mlx5_esw_set_spec_source_port(struct mlx5_eswitch *esw,
2115 u16 vport,
2116 struct mlx5_flow_spec *spec)
2117 {
2118 void *misc;
2119
2120 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
2121 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
2122 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
2123 mlx5_eswitch_get_vport_metadata_for_match(esw, vport));
2124
2125 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
2126 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
2127 mlx5_eswitch_get_vport_metadata_mask());
2128
2129 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
2130 } else {
2131 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
2132 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
2133
2134 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
2135 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
2136
2137 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
2138 }
2139 }
2140
2141 struct mlx5_flow_handle *
mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch * esw,u16 vport,struct mlx5_flow_destination * dest)2142 mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
2143 struct mlx5_flow_destination *dest)
2144 {
2145 struct mlx5_flow_act flow_act = {0};
2146 struct mlx5_flow_handle *flow_rule;
2147 struct mlx5_flow_spec *spec;
2148
2149 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
2150 if (!spec) {
2151 flow_rule = ERR_PTR(-ENOMEM);
2152 goto out;
2153 }
2154
2155 mlx5_esw_set_spec_source_port(esw, vport, spec);
2156
2157 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2158 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, spec,
2159 &flow_act, dest, 1);
2160 if (IS_ERR(flow_rule)) {
2161 esw_warn(esw->dev,
2162 "fs offloads: Failed to add vport rx rule err %pe\n",
2163 flow_rule);
2164 goto out;
2165 }
2166
2167 out:
2168 kvfree(spec);
2169 return flow_rule;
2170 }
2171
esw_create_vport_rx_drop_rule(struct mlx5_eswitch * esw)2172 static int esw_create_vport_rx_drop_rule(struct mlx5_eswitch *esw)
2173 {
2174 struct mlx5_flow_act flow_act = {};
2175 struct mlx5_flow_handle *flow_rule;
2176
2177 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
2178 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, NULL,
2179 &flow_act, NULL, 0);
2180 if (IS_ERR(flow_rule)) {
2181 esw_warn(esw->dev,
2182 "fs offloads: Failed to add vport rx drop rule err %pe\n",
2183 flow_rule);
2184 return PTR_ERR(flow_rule);
2185 }
2186
2187 esw->offloads.vport_rx_drop_rule = flow_rule;
2188
2189 return 0;
2190 }
2191
esw_destroy_vport_rx_drop_rule(struct mlx5_eswitch * esw)2192 static void esw_destroy_vport_rx_drop_rule(struct mlx5_eswitch *esw)
2193 {
2194 if (esw->offloads.vport_rx_drop_rule)
2195 mlx5_del_flow_rules(esw->offloads.vport_rx_drop_rule);
2196 }
2197
mlx5_eswitch_inline_mode_get(struct mlx5_eswitch * esw,u8 * mode)2198 static int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, u8 *mode)
2199 {
2200 u8 prev_mlx5_mode, mlx5_mode = MLX5_INLINE_MODE_L2;
2201 struct mlx5_core_dev *dev = esw->dev;
2202 struct mlx5_vport *vport;
2203 unsigned long i;
2204
2205 if (!MLX5_CAP_GEN(dev, vport_group_manager))
2206 return -EOPNOTSUPP;
2207
2208 if (!mlx5_esw_is_fdb_created(esw))
2209 return -EOPNOTSUPP;
2210
2211 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
2212 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2213 mlx5_mode = MLX5_INLINE_MODE_NONE;
2214 goto out;
2215 case MLX5_CAP_INLINE_MODE_L2:
2216 mlx5_mode = MLX5_INLINE_MODE_L2;
2217 goto out;
2218 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2219 goto query_vports;
2220 }
2221
2222 query_vports:
2223 mlx5_query_nic_vport_min_inline(dev, esw->first_host_vport, &prev_mlx5_mode);
2224 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
2225 mlx5_query_nic_vport_min_inline(dev, vport->vport, &mlx5_mode);
2226 if (prev_mlx5_mode != mlx5_mode)
2227 return -EINVAL;
2228 prev_mlx5_mode = mlx5_mode;
2229 }
2230
2231 out:
2232 *mode = mlx5_mode;
2233 return 0;
2234 }
2235
esw_destroy_restore_table(struct mlx5_eswitch * esw)2236 static void esw_destroy_restore_table(struct mlx5_eswitch *esw)
2237 {
2238 struct mlx5_esw_offload *offloads = &esw->offloads;
2239
2240 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
2241 return;
2242
2243 mlx5_modify_header_dealloc(esw->dev, offloads->restore_copy_hdr_id);
2244 mlx5_destroy_flow_group(offloads->restore_group);
2245 mlx5_destroy_flow_table(offloads->ft_offloads_restore);
2246 }
2247
esw_create_restore_table(struct mlx5_eswitch * esw)2248 static int esw_create_restore_table(struct mlx5_eswitch *esw)
2249 {
2250 u8 modact[MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)] = {};
2251 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
2252 struct mlx5_flow_table_attr ft_attr = {};
2253 struct mlx5_core_dev *dev = esw->dev;
2254 struct mlx5_flow_namespace *ns;
2255 struct mlx5_modify_hdr *mod_hdr;
2256 void *match_criteria, *misc;
2257 struct mlx5_flow_table *ft;
2258 struct mlx5_flow_group *g;
2259 u32 *flow_group_in;
2260 int err = 0;
2261
2262 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
2263 return 0;
2264
2265 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
2266 if (!ns) {
2267 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
2268 return -EOPNOTSUPP;
2269 }
2270
2271 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2272 if (!flow_group_in) {
2273 err = -ENOMEM;
2274 goto out_free;
2275 }
2276
2277 ft_attr.max_fte = 1 << ESW_REG_C0_USER_DATA_METADATA_BITS;
2278 ft = mlx5_create_flow_table(ns, &ft_attr);
2279 if (IS_ERR(ft)) {
2280 err = PTR_ERR(ft);
2281 esw_warn(esw->dev, "Failed to create restore table, err %d\n",
2282 err);
2283 goto out_free;
2284 }
2285
2286 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
2287 match_criteria);
2288 misc = MLX5_ADDR_OF(fte_match_param, match_criteria,
2289 misc_parameters_2);
2290
2291 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
2292 ESW_REG_C0_USER_DATA_METADATA_MASK);
2293 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
2294 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
2295 ft_attr.max_fte - 1);
2296 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
2297 MLX5_MATCH_MISC_PARAMETERS_2);
2298 g = mlx5_create_flow_group(ft, flow_group_in);
2299 if (IS_ERR(g)) {
2300 err = PTR_ERR(g);
2301 esw_warn(dev, "Failed to create restore flow group, err: %d\n",
2302 err);
2303 goto err_group;
2304 }
2305
2306 MLX5_SET(copy_action_in, modact, action_type, MLX5_ACTION_TYPE_COPY);
2307 MLX5_SET(copy_action_in, modact, src_field,
2308 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1);
2309 MLX5_SET(copy_action_in, modact, dst_field,
2310 MLX5_ACTION_IN_FIELD_METADATA_REG_B);
2311 mod_hdr = mlx5_modify_header_alloc(esw->dev,
2312 MLX5_FLOW_NAMESPACE_KERNEL, 1,
2313 modact);
2314 if (IS_ERR(mod_hdr)) {
2315 err = PTR_ERR(mod_hdr);
2316 esw_warn(dev, "Failed to create restore mod header, err: %d\n",
2317 err);
2318 goto err_mod_hdr;
2319 }
2320
2321 esw->offloads.ft_offloads_restore = ft;
2322 esw->offloads.restore_group = g;
2323 esw->offloads.restore_copy_hdr_id = mod_hdr;
2324
2325 kvfree(flow_group_in);
2326
2327 return 0;
2328
2329 err_mod_hdr:
2330 mlx5_destroy_flow_group(g);
2331 err_group:
2332 mlx5_destroy_flow_table(ft);
2333 out_free:
2334 kvfree(flow_group_in);
2335
2336 return err;
2337 }
2338
esw_mode_change(struct mlx5_eswitch * esw,u16 mode)2339 static void esw_mode_change(struct mlx5_eswitch *esw, u16 mode)
2340 {
2341 mlx5_devcom_comp_lock(esw->dev->priv.hca_devcom_comp);
2342 if (esw->dev->priv.flags & MLX5_PRIV_FLAGS_DISABLE_IB_ADEV ||
2343 mlx5_core_mp_enabled(esw->dev)) {
2344 esw->mode = mode;
2345 mlx5_rescan_drivers_locked(esw->dev);
2346 mlx5_devcom_comp_unlock(esw->dev->priv.hca_devcom_comp);
2347 return;
2348 }
2349
2350 esw->dev->priv.flags |= MLX5_PRIV_FLAGS_DISABLE_IB_ADEV;
2351 mlx5_rescan_drivers_locked(esw->dev);
2352 esw->mode = mode;
2353 esw->dev->priv.flags &= ~MLX5_PRIV_FLAGS_DISABLE_IB_ADEV;
2354 mlx5_rescan_drivers_locked(esw->dev);
2355 mlx5_devcom_comp_unlock(esw->dev->priv.hca_devcom_comp);
2356 }
2357
esw_offloads_start(struct mlx5_eswitch * esw,struct netlink_ext_ack * extack)2358 static int esw_offloads_start(struct mlx5_eswitch *esw,
2359 struct netlink_ext_ack *extack)
2360 {
2361 int err;
2362
2363 esw_mode_change(esw, MLX5_ESWITCH_OFFLOADS);
2364 err = mlx5_eswitch_enable_locked(esw, esw->dev->priv.sriov.num_vfs);
2365 if (err) {
2366 NL_SET_ERR_MSG_MOD(extack,
2367 "Failed setting eswitch to offloads");
2368 esw_mode_change(esw, MLX5_ESWITCH_LEGACY);
2369 return err;
2370 }
2371 if (esw->offloads.inline_mode == MLX5_INLINE_MODE_NONE) {
2372 if (mlx5_eswitch_inline_mode_get(esw,
2373 &esw->offloads.inline_mode)) {
2374 esw->offloads.inline_mode = MLX5_INLINE_MODE_L2;
2375 NL_SET_ERR_MSG_MOD(extack,
2376 "Inline mode is different between vports");
2377 }
2378 }
2379 return 0;
2380 }
2381
mlx5_esw_offloads_rep_remove(struct mlx5_eswitch * esw,const struct mlx5_vport * vport)2382 void mlx5_esw_offloads_rep_remove(struct mlx5_eswitch *esw,
2383 const struct mlx5_vport *vport)
2384 {
2385 struct mlx5_eswitch_rep *rep = xa_load(&esw->offloads.vport_reps,
2386 vport->vport);
2387
2388 if (!rep)
2389 return;
2390 xa_erase(&esw->offloads.vport_reps, vport->vport);
2391 kfree(rep);
2392 }
2393
mlx5_esw_offloads_rep_add(struct mlx5_eswitch * esw,const struct mlx5_vport * vport)2394 int mlx5_esw_offloads_rep_add(struct mlx5_eswitch *esw,
2395 const struct mlx5_vport *vport)
2396 {
2397 struct mlx5_eswitch_rep *rep;
2398 int rep_type;
2399 int err;
2400
2401 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
2402 if (!rep)
2403 return -ENOMEM;
2404
2405 rep->vport = vport->vport;
2406 rep->vport_index = vport->index;
2407 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++) {
2408 if (!esw->offloads.rep_ops[rep_type]) {
2409 atomic_set(&rep->rep_data[rep_type].state,
2410 REP_UNREGISTERED);
2411 continue;
2412 }
2413 /* Dynamic/delegated vports add their representors after
2414 * mlx5_eswitch_register_vport_reps, so mark them as registered
2415 * for them to be loaded later with the others.
2416 */
2417 rep->esw = esw;
2418 atomic_set(&rep->rep_data[rep_type].state, REP_REGISTERED);
2419 }
2420 err = xa_insert(&esw->offloads.vport_reps, rep->vport, rep, GFP_KERNEL);
2421 if (err)
2422 goto insert_err;
2423
2424 return 0;
2425
2426 insert_err:
2427 kfree(rep);
2428 return err;
2429 }
2430
mlx5_esw_offloads_rep_cleanup(struct mlx5_eswitch * esw,struct mlx5_eswitch_rep * rep)2431 static void mlx5_esw_offloads_rep_cleanup(struct mlx5_eswitch *esw,
2432 struct mlx5_eswitch_rep *rep)
2433 {
2434 xa_erase(&esw->offloads.vport_reps, rep->vport);
2435 kfree(rep);
2436 }
2437
esw_offloads_cleanup_reps(struct mlx5_eswitch * esw)2438 static void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw)
2439 {
2440 struct mlx5_eswitch_rep *rep;
2441 unsigned long i;
2442
2443 mlx5_esw_for_each_rep(esw, i, rep)
2444 mlx5_esw_offloads_rep_cleanup(esw, rep);
2445 xa_destroy(&esw->offloads.vport_reps);
2446 }
2447
esw_offloads_init_reps(struct mlx5_eswitch * esw)2448 static int esw_offloads_init_reps(struct mlx5_eswitch *esw)
2449 {
2450 struct mlx5_vport *vport;
2451 unsigned long i;
2452 int err;
2453
2454 xa_init(&esw->offloads.vport_reps);
2455
2456 mlx5_esw_for_each_vport(esw, i, vport) {
2457 err = mlx5_esw_offloads_rep_add(esw, vport);
2458 if (err)
2459 goto err;
2460 }
2461 return 0;
2462
2463 err:
2464 esw_offloads_cleanup_reps(esw);
2465 return err;
2466 }
2467
esw_port_metadata_set(struct devlink * devlink,u32 id,struct devlink_param_gset_ctx * ctx,struct netlink_ext_ack * extack)2468 static int esw_port_metadata_set(struct devlink *devlink, u32 id,
2469 struct devlink_param_gset_ctx *ctx,
2470 struct netlink_ext_ack *extack)
2471 {
2472 struct mlx5_core_dev *dev = devlink_priv(devlink);
2473 struct mlx5_eswitch *esw = dev->priv.eswitch;
2474 int err = 0;
2475
2476 down_write(&esw->mode_lock);
2477 if (mlx5_esw_is_fdb_created(esw)) {
2478 err = -EBUSY;
2479 goto done;
2480 }
2481 if (!mlx5_esw_vport_match_metadata_supported(esw)) {
2482 err = -EOPNOTSUPP;
2483 goto done;
2484 }
2485 if (ctx->val.vbool)
2486 esw->flags |= MLX5_ESWITCH_VPORT_MATCH_METADATA;
2487 else
2488 esw->flags &= ~MLX5_ESWITCH_VPORT_MATCH_METADATA;
2489 done:
2490 up_write(&esw->mode_lock);
2491 return err;
2492 }
2493
esw_port_metadata_get(struct devlink * devlink,u32 id,struct devlink_param_gset_ctx * ctx)2494 static int esw_port_metadata_get(struct devlink *devlink, u32 id,
2495 struct devlink_param_gset_ctx *ctx)
2496 {
2497 struct mlx5_core_dev *dev = devlink_priv(devlink);
2498
2499 ctx->val.vbool = mlx5_eswitch_vport_match_metadata_enabled(dev->priv.eswitch);
2500 return 0;
2501 }
2502
esw_port_metadata_validate(struct devlink * devlink,u32 id,union devlink_param_value val,struct netlink_ext_ack * extack)2503 static int esw_port_metadata_validate(struct devlink *devlink, u32 id,
2504 union devlink_param_value val,
2505 struct netlink_ext_ack *extack)
2506 {
2507 struct mlx5_core_dev *dev = devlink_priv(devlink);
2508 u8 esw_mode;
2509
2510 esw_mode = mlx5_eswitch_mode(dev);
2511 if (esw_mode == MLX5_ESWITCH_OFFLOADS) {
2512 NL_SET_ERR_MSG_MOD(extack,
2513 "E-Switch must either disabled or non switchdev mode");
2514 return -EBUSY;
2515 }
2516 return 0;
2517 }
2518
2519 static const struct devlink_param esw_devlink_params[] = {
2520 DEVLINK_PARAM_DRIVER(MLX5_DEVLINK_PARAM_ID_ESW_PORT_METADATA,
2521 "esw_port_metadata", DEVLINK_PARAM_TYPE_BOOL,
2522 BIT(DEVLINK_PARAM_CMODE_RUNTIME),
2523 esw_port_metadata_get,
2524 esw_port_metadata_set,
2525 esw_port_metadata_validate),
2526 };
2527
esw_offloads_init(struct mlx5_eswitch * esw)2528 int esw_offloads_init(struct mlx5_eswitch *esw)
2529 {
2530 int err;
2531
2532 err = esw_offloads_init_reps(esw);
2533 if (err)
2534 return err;
2535
2536 if (MLX5_ESWITCH_MANAGER(esw->dev) &&
2537 mlx5_esw_vport_match_metadata_supported(esw))
2538 esw->flags |= MLX5_ESWITCH_VPORT_MATCH_METADATA;
2539
2540 err = devl_params_register(priv_to_devlink(esw->dev),
2541 esw_devlink_params,
2542 ARRAY_SIZE(esw_devlink_params));
2543 if (err)
2544 goto err_params;
2545
2546 return 0;
2547
2548 err_params:
2549 esw_offloads_cleanup_reps(esw);
2550 return err;
2551 }
2552
esw_offloads_cleanup(struct mlx5_eswitch * esw)2553 void esw_offloads_cleanup(struct mlx5_eswitch *esw)
2554 {
2555 devl_params_unregister(priv_to_devlink(esw->dev),
2556 esw_devlink_params,
2557 ARRAY_SIZE(esw_devlink_params));
2558 esw_offloads_cleanup_reps(esw);
2559 }
2560
__esw_offloads_load_rep(struct mlx5_eswitch * esw,struct mlx5_eswitch_rep * rep,u8 rep_type)2561 static int __esw_offloads_load_rep(struct mlx5_eswitch *esw,
2562 struct mlx5_eswitch_rep *rep, u8 rep_type)
2563 {
2564 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
2565 REP_REGISTERED, REP_LOADED) == REP_REGISTERED)
2566 return esw->offloads.rep_ops[rep_type]->load(esw->dev, rep);
2567
2568 return 0;
2569 }
2570
__esw_offloads_unload_rep(struct mlx5_eswitch * esw,struct mlx5_eswitch_rep * rep,u8 rep_type)2571 static void __esw_offloads_unload_rep(struct mlx5_eswitch *esw,
2572 struct mlx5_eswitch_rep *rep, u8 rep_type)
2573 {
2574 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
2575 REP_LOADED, REP_REGISTERED) == REP_LOADED) {
2576 if (rep_type == REP_ETH)
2577 __esw_offloads_unload_rep(esw, rep, REP_IB);
2578 esw->offloads.rep_ops[rep_type]->unload(rep);
2579 }
2580 }
2581
__unload_reps_all_vport(struct mlx5_eswitch * esw,u8 rep_type)2582 static void __unload_reps_all_vport(struct mlx5_eswitch *esw, u8 rep_type)
2583 {
2584 struct mlx5_eswitch_rep *rep;
2585 unsigned long i;
2586
2587 mlx5_esw_for_each_rep(esw, i, rep)
2588 __esw_offloads_unload_rep(esw, rep, rep_type);
2589 }
2590
mlx5_esw_offloads_rep_load(struct mlx5_eswitch * esw,u16 vport_num)2591 static int mlx5_esw_offloads_rep_load(struct mlx5_eswitch *esw, u16 vport_num)
2592 {
2593 struct mlx5_eswitch_rep *rep;
2594 int rep_type;
2595 int err;
2596
2597 rep = mlx5_eswitch_get_rep(esw, vport_num);
2598 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++) {
2599 err = __esw_offloads_load_rep(esw, rep, rep_type);
2600 if (err)
2601 goto err_reps;
2602 }
2603
2604 return 0;
2605
2606 err_reps:
2607 atomic_set(&rep->rep_data[rep_type].state, REP_REGISTERED);
2608 for (--rep_type; rep_type >= 0; rep_type--)
2609 __esw_offloads_unload_rep(esw, rep, rep_type);
2610 return err;
2611 }
2612
mlx5_esw_offloads_rep_unload(struct mlx5_eswitch * esw,u16 vport_num)2613 static void mlx5_esw_offloads_rep_unload(struct mlx5_eswitch *esw, u16 vport_num)
2614 {
2615 struct mlx5_eswitch_rep *rep;
2616 int rep_type;
2617
2618 rep = mlx5_eswitch_get_rep(esw, vport_num);
2619 for (rep_type = NUM_REP_TYPES - 1; rep_type >= 0; rep_type--)
2620 __esw_offloads_unload_rep(esw, rep, rep_type);
2621 }
2622
mlx5_esw_offloads_init_pf_vf_rep(struct mlx5_eswitch * esw,struct mlx5_vport * vport)2623 int mlx5_esw_offloads_init_pf_vf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport)
2624 {
2625 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2626 return 0;
2627
2628 return mlx5_esw_offloads_pf_vf_devlink_port_init(esw, vport);
2629 }
2630
mlx5_esw_offloads_cleanup_pf_vf_rep(struct mlx5_eswitch * esw,struct mlx5_vport * vport)2631 void mlx5_esw_offloads_cleanup_pf_vf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport)
2632 {
2633 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2634 return;
2635
2636 mlx5_esw_offloads_pf_vf_devlink_port_cleanup(esw, vport);
2637 }
2638
mlx5_esw_offloads_init_sf_rep(struct mlx5_eswitch * esw,struct mlx5_vport * vport,struct mlx5_devlink_port * dl_port,u32 controller,u32 sfnum)2639 int mlx5_esw_offloads_init_sf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport,
2640 struct mlx5_devlink_port *dl_port,
2641 u32 controller, u32 sfnum)
2642 {
2643 return mlx5_esw_offloads_sf_devlink_port_init(esw, vport, dl_port, controller, sfnum);
2644 }
2645
mlx5_esw_offloads_cleanup_sf_rep(struct mlx5_eswitch * esw,struct mlx5_vport * vport)2646 void mlx5_esw_offloads_cleanup_sf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport)
2647 {
2648 mlx5_esw_offloads_sf_devlink_port_cleanup(esw, vport);
2649 }
2650
mlx5_esw_offloads_load_rep(struct mlx5_eswitch * esw,struct mlx5_vport * vport)2651 int mlx5_esw_offloads_load_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport)
2652 {
2653 int err;
2654
2655 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2656 return 0;
2657
2658 err = mlx5_esw_offloads_devlink_port_register(esw, vport);
2659 if (err)
2660 return err;
2661
2662 err = mlx5_esw_offloads_rep_load(esw, vport->vport);
2663 if (err)
2664 goto load_err;
2665 return err;
2666
2667 load_err:
2668 mlx5_esw_offloads_devlink_port_unregister(vport);
2669 return err;
2670 }
2671
mlx5_esw_offloads_unload_rep(struct mlx5_eswitch * esw,struct mlx5_vport * vport)2672 void mlx5_esw_offloads_unload_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport)
2673 {
2674 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2675 return;
2676
2677 mlx5_esw_offloads_rep_unload(esw, vport->vport);
2678
2679 mlx5_esw_offloads_devlink_port_unregister(vport);
2680 }
2681
esw_set_slave_root_fdb(struct mlx5_core_dev * master,struct mlx5_core_dev * slave)2682 static int esw_set_slave_root_fdb(struct mlx5_core_dev *master,
2683 struct mlx5_core_dev *slave)
2684 {
2685 u32 in[MLX5_ST_SZ_DW(set_flow_table_root_in)] = {};
2686 u32 out[MLX5_ST_SZ_DW(set_flow_table_root_out)] = {};
2687 struct mlx5_flow_root_namespace *root;
2688 struct mlx5_flow_namespace *ns;
2689 int err;
2690
2691 MLX5_SET(set_flow_table_root_in, in, opcode,
2692 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT);
2693 MLX5_SET(set_flow_table_root_in, in, table_type,
2694 FS_FT_FDB);
2695
2696 if (master) {
2697 ns = mlx5_get_flow_namespace(master,
2698 MLX5_FLOW_NAMESPACE_FDB);
2699 root = find_root(&ns->node);
2700 mutex_lock(&root->chain_lock);
2701 MLX5_SET(set_flow_table_root_in, in,
2702 table_eswitch_owner_vhca_id_valid, 1);
2703 MLX5_SET(set_flow_table_root_in, in,
2704 table_eswitch_owner_vhca_id,
2705 MLX5_CAP_GEN(master, vhca_id));
2706 MLX5_SET(set_flow_table_root_in, in, table_id,
2707 root->root_ft->id);
2708 } else {
2709 ns = mlx5_get_flow_namespace(slave,
2710 MLX5_FLOW_NAMESPACE_FDB);
2711 root = find_root(&ns->node);
2712 mutex_lock(&root->chain_lock);
2713 MLX5_SET(set_flow_table_root_in, in, table_id,
2714 root->root_ft->id);
2715 }
2716
2717 err = mlx5_cmd_exec(slave, in, sizeof(in), out, sizeof(out));
2718 mutex_unlock(&root->chain_lock);
2719
2720 return err;
2721 }
2722
__esw_set_master_egress_rule(struct mlx5_core_dev * master,struct mlx5_core_dev * slave,struct mlx5_vport * vport,struct mlx5_flow_table * acl)2723 static int __esw_set_master_egress_rule(struct mlx5_core_dev *master,
2724 struct mlx5_core_dev *slave,
2725 struct mlx5_vport *vport,
2726 struct mlx5_flow_table *acl)
2727 {
2728 u16 slave_index = MLX5_CAP_GEN(slave, vhca_id);
2729 struct mlx5_flow_handle *flow_rule = NULL;
2730 struct mlx5_flow_destination dest = {};
2731 struct mlx5_flow_act flow_act = {};
2732 struct mlx5_flow_spec *spec;
2733 int err = 0;
2734 void *misc;
2735
2736 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
2737 if (!spec)
2738 return -ENOMEM;
2739
2740 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
2741 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2742 misc_parameters);
2743 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_UPLINK);
2744 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id, slave_index);
2745
2746 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
2747 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
2748 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
2749 source_eswitch_owner_vhca_id);
2750
2751 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2752 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
2753 dest.vport.num = slave->priv.eswitch->manager_vport;
2754 dest.vport.vhca_id = MLX5_CAP_GEN(slave, vhca_id);
2755 dest.vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
2756
2757 flow_rule = mlx5_add_flow_rules(acl, spec, &flow_act,
2758 &dest, 1);
2759 if (IS_ERR(flow_rule)) {
2760 err = PTR_ERR(flow_rule);
2761 } else {
2762 err = xa_insert(&vport->egress.offloads.bounce_rules,
2763 slave_index, flow_rule, GFP_KERNEL);
2764 if (err)
2765 mlx5_del_flow_rules(flow_rule);
2766 }
2767
2768 kvfree(spec);
2769 return err;
2770 }
2771
esw_master_egress_create_resources(struct mlx5_eswitch * esw,struct mlx5_flow_namespace * egress_ns,struct mlx5_vport * vport,size_t count)2772 static int esw_master_egress_create_resources(struct mlx5_eswitch *esw,
2773 struct mlx5_flow_namespace *egress_ns,
2774 struct mlx5_vport *vport, size_t count)
2775 {
2776 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
2777 struct mlx5_flow_table_attr ft_attr = {
2778 .max_fte = count, .prio = 0, .level = 0,
2779 };
2780 struct mlx5_flow_table *acl;
2781 struct mlx5_flow_group *g;
2782 void *match_criteria;
2783 u32 *flow_group_in;
2784 int err;
2785
2786 if (vport->egress.acl)
2787 return 0;
2788
2789 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2790 if (!flow_group_in)
2791 return -ENOMEM;
2792
2793 if (vport->vport || mlx5_core_is_ecpf(esw->dev))
2794 ft_attr.flags = MLX5_FLOW_TABLE_OTHER_VPORT;
2795
2796 acl = mlx5_create_vport_flow_table(egress_ns, &ft_attr, vport->vport);
2797 if (IS_ERR(acl)) {
2798 err = PTR_ERR(acl);
2799 goto out;
2800 }
2801
2802 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
2803 match_criteria);
2804 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
2805 misc_parameters.source_port);
2806 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
2807 misc_parameters.source_eswitch_owner_vhca_id);
2808 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
2809 MLX5_MATCH_MISC_PARAMETERS);
2810
2811 MLX5_SET(create_flow_group_in, flow_group_in,
2812 source_eswitch_owner_vhca_id_valid, 1);
2813 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
2814 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, count);
2815
2816 g = mlx5_create_flow_group(acl, flow_group_in);
2817 if (IS_ERR(g)) {
2818 err = PTR_ERR(g);
2819 goto err_group;
2820 }
2821
2822 vport->egress.acl = acl;
2823 vport->egress.offloads.bounce_grp = g;
2824 vport->egress.type = VPORT_EGRESS_ACL_TYPE_SHARED_FDB;
2825 xa_init_flags(&vport->egress.offloads.bounce_rules, XA_FLAGS_ALLOC);
2826
2827 kvfree(flow_group_in);
2828
2829 return 0;
2830
2831 err_group:
2832 mlx5_destroy_flow_table(acl);
2833 out:
2834 kvfree(flow_group_in);
2835 return err;
2836 }
2837
esw_master_egress_destroy_resources(struct mlx5_vport * vport)2838 static void esw_master_egress_destroy_resources(struct mlx5_vport *vport)
2839 {
2840 if (!xa_empty(&vport->egress.offloads.bounce_rules))
2841 return;
2842 mlx5_destroy_flow_group(vport->egress.offloads.bounce_grp);
2843 vport->egress.offloads.bounce_grp = NULL;
2844 mlx5_destroy_flow_table(vport->egress.acl);
2845 vport->egress.acl = NULL;
2846 }
2847
esw_set_master_egress_rule(struct mlx5_core_dev * master,struct mlx5_core_dev * slave,size_t count)2848 static int esw_set_master_egress_rule(struct mlx5_core_dev *master,
2849 struct mlx5_core_dev *slave, size_t count)
2850 {
2851 struct mlx5_eswitch *esw = master->priv.eswitch;
2852 u16 slave_index = MLX5_CAP_GEN(slave, vhca_id);
2853 struct mlx5_flow_namespace *egress_ns;
2854 struct mlx5_vport *vport;
2855 int err;
2856
2857 vport = mlx5_eswitch_get_vport(esw, esw->manager_vport);
2858 if (IS_ERR(vport))
2859 return PTR_ERR(vport);
2860
2861 egress_ns = mlx5_get_flow_vport_namespace(master,
2862 MLX5_FLOW_NAMESPACE_ESW_EGRESS,
2863 vport->index);
2864 if (!egress_ns)
2865 return -EINVAL;
2866
2867 if (vport->egress.acl && vport->egress.type != VPORT_EGRESS_ACL_TYPE_SHARED_FDB)
2868 return 0;
2869
2870 err = esw_master_egress_create_resources(esw, egress_ns, vport, count);
2871 if (err)
2872 return err;
2873
2874 if (xa_load(&vport->egress.offloads.bounce_rules, slave_index))
2875 return -EINVAL;
2876
2877 err = __esw_set_master_egress_rule(master, slave, vport, vport->egress.acl);
2878 if (err)
2879 goto err_rule;
2880
2881 return 0;
2882
2883 err_rule:
2884 esw_master_egress_destroy_resources(vport);
2885 return err;
2886 }
2887
esw_unset_master_egress_rule(struct mlx5_core_dev * dev,struct mlx5_core_dev * slave_dev)2888 static void esw_unset_master_egress_rule(struct mlx5_core_dev *dev,
2889 struct mlx5_core_dev *slave_dev)
2890 {
2891 struct mlx5_vport *vport;
2892
2893 vport = mlx5_eswitch_get_vport(dev->priv.eswitch,
2894 dev->priv.eswitch->manager_vport);
2895
2896 esw_acl_egress_ofld_bounce_rule_destroy(vport, MLX5_CAP_GEN(slave_dev, vhca_id));
2897
2898 if (xa_empty(&vport->egress.offloads.bounce_rules)) {
2899 esw_acl_egress_ofld_cleanup(vport);
2900 xa_destroy(&vport->egress.offloads.bounce_rules);
2901 }
2902 }
2903
mlx5_eswitch_offloads_single_fdb_add_one(struct mlx5_eswitch * master_esw,struct mlx5_eswitch * slave_esw,int max_slaves)2904 int mlx5_eswitch_offloads_single_fdb_add_one(struct mlx5_eswitch *master_esw,
2905 struct mlx5_eswitch *slave_esw, int max_slaves)
2906 {
2907 int err;
2908
2909 err = esw_set_slave_root_fdb(master_esw->dev,
2910 slave_esw->dev);
2911 if (err)
2912 return err;
2913
2914 err = esw_set_master_egress_rule(master_esw->dev,
2915 slave_esw->dev, max_slaves);
2916 if (err)
2917 goto err_acl;
2918
2919 return err;
2920
2921 err_acl:
2922 esw_set_slave_root_fdb(NULL, slave_esw->dev);
2923 return err;
2924 }
2925
mlx5_eswitch_offloads_single_fdb_del_one(struct mlx5_eswitch * master_esw,struct mlx5_eswitch * slave_esw)2926 void mlx5_eswitch_offloads_single_fdb_del_one(struct mlx5_eswitch *master_esw,
2927 struct mlx5_eswitch *slave_esw)
2928 {
2929 esw_set_slave_root_fdb(NULL, slave_esw->dev);
2930 esw_unset_master_egress_rule(master_esw->dev, slave_esw->dev);
2931 }
2932
2933 #define ESW_OFFLOADS_DEVCOM_PAIR (0)
2934 #define ESW_OFFLOADS_DEVCOM_UNPAIR (1)
2935
mlx5_esw_offloads_rep_event_unpair(struct mlx5_eswitch * esw,struct mlx5_eswitch * peer_esw)2936 static void mlx5_esw_offloads_rep_event_unpair(struct mlx5_eswitch *esw,
2937 struct mlx5_eswitch *peer_esw)
2938 {
2939 const struct mlx5_eswitch_rep_ops *ops;
2940 struct mlx5_eswitch_rep *rep;
2941 unsigned long i;
2942 u8 rep_type;
2943
2944 mlx5_esw_for_each_rep(esw, i, rep) {
2945 rep_type = NUM_REP_TYPES;
2946 while (rep_type--) {
2947 ops = esw->offloads.rep_ops[rep_type];
2948 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
2949 ops->event)
2950 ops->event(esw, rep, MLX5_SWITCHDEV_EVENT_UNPAIR, peer_esw);
2951 }
2952 }
2953 }
2954
mlx5_esw_offloads_unpair(struct mlx5_eswitch * esw,struct mlx5_eswitch * peer_esw)2955 static void mlx5_esw_offloads_unpair(struct mlx5_eswitch *esw,
2956 struct mlx5_eswitch *peer_esw)
2957 {
2958 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
2959 mlx5e_tc_clean_fdb_peer_flows(esw);
2960 #endif
2961 mlx5_esw_offloads_rep_event_unpair(esw, peer_esw);
2962 esw_del_fdb_peer_miss_rules(esw, peer_esw->dev);
2963 }
2964
mlx5_esw_offloads_pair(struct mlx5_eswitch * esw,struct mlx5_eswitch * peer_esw)2965 static int mlx5_esw_offloads_pair(struct mlx5_eswitch *esw,
2966 struct mlx5_eswitch *peer_esw)
2967 {
2968 const struct mlx5_eswitch_rep_ops *ops;
2969 struct mlx5_eswitch_rep *rep;
2970 unsigned long i;
2971 u8 rep_type;
2972 int err;
2973
2974 err = esw_add_fdb_peer_miss_rules(esw, peer_esw->dev);
2975 if (err)
2976 return err;
2977
2978 mlx5_esw_for_each_rep(esw, i, rep) {
2979 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++) {
2980 ops = esw->offloads.rep_ops[rep_type];
2981 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
2982 ops->event) {
2983 err = ops->event(esw, rep, MLX5_SWITCHDEV_EVENT_PAIR, peer_esw);
2984 if (err)
2985 goto err_out;
2986 }
2987 }
2988 }
2989
2990 return 0;
2991
2992 err_out:
2993 mlx5_esw_offloads_unpair(esw, peer_esw);
2994 return err;
2995 }
2996
mlx5_esw_offloads_set_ns_peer(struct mlx5_eswitch * esw,struct mlx5_eswitch * peer_esw,bool pair)2997 static int mlx5_esw_offloads_set_ns_peer(struct mlx5_eswitch *esw,
2998 struct mlx5_eswitch *peer_esw,
2999 bool pair)
3000 {
3001 u16 peer_vhca_id = MLX5_CAP_GEN(peer_esw->dev, vhca_id);
3002 u16 vhca_id = MLX5_CAP_GEN(esw->dev, vhca_id);
3003 struct mlx5_flow_root_namespace *peer_ns;
3004 struct mlx5_flow_root_namespace *ns;
3005 int err;
3006
3007 peer_ns = peer_esw->dev->priv.steering->fdb_root_ns;
3008 ns = esw->dev->priv.steering->fdb_root_ns;
3009
3010 if (pair) {
3011 err = mlx5_flow_namespace_set_peer(ns, peer_ns, peer_vhca_id);
3012 if (err)
3013 return err;
3014
3015 err = mlx5_flow_namespace_set_peer(peer_ns, ns, vhca_id);
3016 if (err) {
3017 mlx5_flow_namespace_set_peer(ns, NULL, peer_vhca_id);
3018 return err;
3019 }
3020 } else {
3021 mlx5_flow_namespace_set_peer(ns, NULL, peer_vhca_id);
3022 mlx5_flow_namespace_set_peer(peer_ns, NULL, vhca_id);
3023 }
3024
3025 return 0;
3026 }
3027
mlx5_esw_offloads_devcom_event(int event,void * my_data,void * event_data)3028 static int mlx5_esw_offloads_devcom_event(int event,
3029 void *my_data,
3030 void *event_data)
3031 {
3032 struct mlx5_eswitch *esw = my_data;
3033 struct mlx5_eswitch *peer_esw = event_data;
3034 u16 esw_i, peer_esw_i;
3035 bool esw_paired;
3036 int err;
3037
3038 peer_esw_i = MLX5_CAP_GEN(peer_esw->dev, vhca_id);
3039 esw_i = MLX5_CAP_GEN(esw->dev, vhca_id);
3040 esw_paired = !!xa_load(&esw->paired, peer_esw_i);
3041
3042 switch (event) {
3043 case ESW_OFFLOADS_DEVCOM_PAIR:
3044 if (mlx5_eswitch_vport_match_metadata_enabled(esw) !=
3045 mlx5_eswitch_vport_match_metadata_enabled(peer_esw))
3046 break;
3047
3048 if (esw_paired)
3049 break;
3050
3051 err = mlx5_esw_offloads_set_ns_peer(esw, peer_esw, true);
3052 if (err)
3053 goto err_out;
3054
3055 err = mlx5_esw_offloads_pair(esw, peer_esw);
3056 if (err)
3057 goto err_peer;
3058
3059 err = mlx5_esw_offloads_pair(peer_esw, esw);
3060 if (err)
3061 goto err_pair;
3062
3063 err = xa_insert(&esw->paired, peer_esw_i, peer_esw, GFP_KERNEL);
3064 if (err)
3065 goto err_xa;
3066
3067 err = xa_insert(&peer_esw->paired, esw_i, esw, GFP_KERNEL);
3068 if (err)
3069 goto err_peer_xa;
3070
3071 esw->num_peers++;
3072 peer_esw->num_peers++;
3073 mlx5_devcom_comp_set_ready(esw->devcom, true);
3074 break;
3075
3076 case ESW_OFFLOADS_DEVCOM_UNPAIR:
3077 if (!esw_paired)
3078 break;
3079
3080 peer_esw->num_peers--;
3081 esw->num_peers--;
3082 if (!esw->num_peers && !peer_esw->num_peers)
3083 mlx5_devcom_comp_set_ready(esw->devcom, false);
3084 xa_erase(&peer_esw->paired, esw_i);
3085 xa_erase(&esw->paired, peer_esw_i);
3086 mlx5_esw_offloads_unpair(peer_esw, esw);
3087 mlx5_esw_offloads_unpair(esw, peer_esw);
3088 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
3089 break;
3090 }
3091
3092 return 0;
3093
3094 err_peer_xa:
3095 xa_erase(&esw->paired, peer_esw_i);
3096 err_xa:
3097 mlx5_esw_offloads_unpair(peer_esw, esw);
3098 err_pair:
3099 mlx5_esw_offloads_unpair(esw, peer_esw);
3100 err_peer:
3101 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
3102 err_out:
3103 mlx5_core_err(esw->dev, "esw offloads devcom event failure, event %u err %d",
3104 event, err);
3105 return err;
3106 }
3107
mlx5_esw_offloads_devcom_init(struct mlx5_eswitch * esw,const struct mlx5_devcom_match_attr * attr)3108 void mlx5_esw_offloads_devcom_init(struct mlx5_eswitch *esw,
3109 const struct mlx5_devcom_match_attr *attr)
3110 {
3111 int i;
3112
3113 for (i = 0; i < MLX5_MAX_PORTS; i++)
3114 INIT_LIST_HEAD(&esw->offloads.peer_flows[i]);
3115 mutex_init(&esw->offloads.peer_mutex);
3116
3117 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
3118 return;
3119
3120 if ((MLX5_VPORT_MANAGER(esw->dev) || mlx5_core_is_ecpf_esw_manager(esw->dev)) &&
3121 !mlx5_lag_is_supported(esw->dev))
3122 return;
3123
3124 xa_init(&esw->paired);
3125 esw->num_peers = 0;
3126 esw->devcom = mlx5_devcom_register_component(esw->dev->priv.devc,
3127 MLX5_DEVCOM_ESW_OFFLOADS,
3128 attr,
3129 mlx5_esw_offloads_devcom_event,
3130 esw);
3131 if (!esw->devcom)
3132 return;
3133
3134 mlx5_devcom_send_event(esw->devcom,
3135 ESW_OFFLOADS_DEVCOM_PAIR,
3136 ESW_OFFLOADS_DEVCOM_UNPAIR,
3137 esw);
3138 }
3139
mlx5_esw_offloads_devcom_cleanup(struct mlx5_eswitch * esw)3140 void mlx5_esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw)
3141 {
3142 if (!esw->devcom)
3143 return;
3144
3145 mlx5_devcom_send_event(esw->devcom,
3146 ESW_OFFLOADS_DEVCOM_UNPAIR,
3147 ESW_OFFLOADS_DEVCOM_UNPAIR,
3148 esw);
3149
3150 mlx5_devcom_unregister_component(esw->devcom);
3151 xa_destroy(&esw->paired);
3152 esw->devcom = NULL;
3153 }
3154
mlx5_esw_offloads_devcom_is_ready(struct mlx5_eswitch * esw)3155 bool mlx5_esw_offloads_devcom_is_ready(struct mlx5_eswitch *esw)
3156 {
3157 return mlx5_devcom_comp_is_ready(esw->devcom);
3158 }
3159
mlx5_esw_vport_match_metadata_supported(const struct mlx5_eswitch * esw)3160 bool mlx5_esw_vport_match_metadata_supported(const struct mlx5_eswitch *esw)
3161 {
3162 if (!MLX5_CAP_ESW(esw->dev, esw_uplink_ingress_acl))
3163 return false;
3164
3165 if (!(MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
3166 MLX5_FDB_TO_VPORT_REG_C_0))
3167 return false;
3168
3169 return true;
3170 }
3171
3172 #define MLX5_ESW_METADATA_RSVD_UPLINK 1
3173
3174 /* Share the same metadata for uplink's. This is fine because:
3175 * (a) In shared FDB mode (LAG) both uplink's are treated the
3176 * same and tagged with the same metadata.
3177 * (b) In non shared FDB mode, packets from physical port0
3178 * cannot hit eswitch of PF1 and vice versa.
3179 */
mlx5_esw_match_metadata_reserved(struct mlx5_eswitch * esw)3180 static u32 mlx5_esw_match_metadata_reserved(struct mlx5_eswitch *esw)
3181 {
3182 return MLX5_ESW_METADATA_RSVD_UPLINK;
3183 }
3184
mlx5_esw_match_metadata_alloc(struct mlx5_eswitch * esw)3185 u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswitch *esw)
3186 {
3187 u32 vport_end_ida = (1 << ESW_VPORT_BITS) - 1;
3188 /* Reserve 0xf for internal port offload */
3189 u32 max_pf_num = (1 << ESW_PFNUM_BITS) - 2;
3190 u32 pf_num;
3191 int id;
3192
3193 /* Only 4 bits of pf_num */
3194 pf_num = mlx5_get_dev_index(esw->dev);
3195 if (pf_num > max_pf_num)
3196 return 0;
3197
3198 /* Metadata is 4 bits of PFNUM and 12 bits of unique id */
3199 /* Use only non-zero vport_id (2-4095) for all PF's */
3200 id = ida_alloc_range(&esw->offloads.vport_metadata_ida,
3201 MLX5_ESW_METADATA_RSVD_UPLINK + 1,
3202 vport_end_ida, GFP_KERNEL);
3203 if (id < 0)
3204 return 0;
3205 id = (pf_num << ESW_VPORT_BITS) | id;
3206 return id;
3207 }
3208
mlx5_esw_match_metadata_free(struct mlx5_eswitch * esw,u32 metadata)3209 void mlx5_esw_match_metadata_free(struct mlx5_eswitch *esw, u32 metadata)
3210 {
3211 u32 vport_bit_mask = (1 << ESW_VPORT_BITS) - 1;
3212
3213 /* Metadata contains only 12 bits of actual ida id */
3214 ida_free(&esw->offloads.vport_metadata_ida, metadata & vport_bit_mask);
3215 }
3216
esw_offloads_vport_metadata_setup(struct mlx5_eswitch * esw,struct mlx5_vport * vport)3217 static int esw_offloads_vport_metadata_setup(struct mlx5_eswitch *esw,
3218 struct mlx5_vport *vport)
3219 {
3220 if (vport->vport == MLX5_VPORT_UPLINK)
3221 vport->default_metadata = mlx5_esw_match_metadata_reserved(esw);
3222 else
3223 vport->default_metadata = mlx5_esw_match_metadata_alloc(esw);
3224
3225 vport->metadata = vport->default_metadata;
3226 return vport->metadata ? 0 : -ENOSPC;
3227 }
3228
esw_offloads_vport_metadata_cleanup(struct mlx5_eswitch * esw,struct mlx5_vport * vport)3229 static void esw_offloads_vport_metadata_cleanup(struct mlx5_eswitch *esw,
3230 struct mlx5_vport *vport)
3231 {
3232 if (!vport->default_metadata)
3233 return;
3234
3235 if (vport->vport == MLX5_VPORT_UPLINK)
3236 return;
3237
3238 WARN_ON(vport->metadata != vport->default_metadata);
3239 mlx5_esw_match_metadata_free(esw, vport->default_metadata);
3240 }
3241
esw_offloads_metadata_uninit(struct mlx5_eswitch * esw)3242 static void esw_offloads_metadata_uninit(struct mlx5_eswitch *esw)
3243 {
3244 struct mlx5_vport *vport;
3245 unsigned long i;
3246
3247 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
3248 return;
3249
3250 mlx5_esw_for_each_vport(esw, i, vport)
3251 esw_offloads_vport_metadata_cleanup(esw, vport);
3252 }
3253
esw_offloads_metadata_init(struct mlx5_eswitch * esw)3254 static int esw_offloads_metadata_init(struct mlx5_eswitch *esw)
3255 {
3256 struct mlx5_vport *vport;
3257 unsigned long i;
3258 int err;
3259
3260 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
3261 return 0;
3262
3263 mlx5_esw_for_each_vport(esw, i, vport) {
3264 err = esw_offloads_vport_metadata_setup(esw, vport);
3265 if (err)
3266 goto metadata_err;
3267 }
3268
3269 return 0;
3270
3271 metadata_err:
3272 esw_offloads_metadata_uninit(esw);
3273 return err;
3274 }
3275
3276 int
esw_vport_create_offloads_acl_tables(struct mlx5_eswitch * esw,struct mlx5_vport * vport)3277 esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw,
3278 struct mlx5_vport *vport)
3279 {
3280 int err;
3281
3282 err = esw_acl_ingress_ofld_setup(esw, vport);
3283 if (err)
3284 return err;
3285
3286 err = esw_acl_egress_ofld_setup(esw, vport);
3287 if (err)
3288 goto egress_err;
3289
3290 return 0;
3291
3292 egress_err:
3293 esw_acl_ingress_ofld_cleanup(esw, vport);
3294 return err;
3295 }
3296
3297 void
esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch * esw,struct mlx5_vport * vport)3298 esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw,
3299 struct mlx5_vport *vport)
3300 {
3301 esw_acl_egress_ofld_cleanup(vport);
3302 esw_acl_ingress_ofld_cleanup(esw, vport);
3303 }
3304
esw_create_offloads_acl_tables(struct mlx5_eswitch * esw)3305 static int esw_create_offloads_acl_tables(struct mlx5_eswitch *esw)
3306 {
3307 struct mlx5_vport *uplink, *manager;
3308 int ret;
3309
3310 uplink = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
3311 if (IS_ERR(uplink))
3312 return PTR_ERR(uplink);
3313
3314 ret = esw_vport_create_offloads_acl_tables(esw, uplink);
3315 if (ret)
3316 return ret;
3317
3318 manager = mlx5_eswitch_get_vport(esw, esw->manager_vport);
3319 if (IS_ERR(manager)) {
3320 ret = PTR_ERR(manager);
3321 goto err_manager;
3322 }
3323
3324 ret = esw_vport_create_offloads_acl_tables(esw, manager);
3325 if (ret)
3326 goto err_manager;
3327
3328 return 0;
3329
3330 err_manager:
3331 esw_vport_destroy_offloads_acl_tables(esw, uplink);
3332 return ret;
3333 }
3334
esw_destroy_offloads_acl_tables(struct mlx5_eswitch * esw)3335 static void esw_destroy_offloads_acl_tables(struct mlx5_eswitch *esw)
3336 {
3337 struct mlx5_vport *vport;
3338
3339 vport = mlx5_eswitch_get_vport(esw, esw->manager_vport);
3340 if (!IS_ERR(vport))
3341 esw_vport_destroy_offloads_acl_tables(esw, vport);
3342
3343 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
3344 if (!IS_ERR(vport))
3345 esw_vport_destroy_offloads_acl_tables(esw, vport);
3346 }
3347
mlx5_eswitch_reload_ib_reps(struct mlx5_eswitch * esw)3348 int mlx5_eswitch_reload_ib_reps(struct mlx5_eswitch *esw)
3349 {
3350 struct mlx5_eswitch_rep *rep;
3351 unsigned long i;
3352 int ret;
3353
3354 if (!esw || esw->mode != MLX5_ESWITCH_OFFLOADS)
3355 return 0;
3356
3357 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
3358 if (atomic_read(&rep->rep_data[REP_ETH].state) != REP_LOADED)
3359 return 0;
3360
3361 ret = __esw_offloads_load_rep(esw, rep, REP_IB);
3362 if (ret)
3363 return ret;
3364
3365 mlx5_esw_for_each_rep(esw, i, rep) {
3366 if (atomic_read(&rep->rep_data[REP_ETH].state) == REP_LOADED)
3367 __esw_offloads_load_rep(esw, rep, REP_IB);
3368 }
3369
3370 return 0;
3371 }
3372
esw_offloads_steering_init(struct mlx5_eswitch * esw)3373 static int esw_offloads_steering_init(struct mlx5_eswitch *esw)
3374 {
3375 struct mlx5_esw_indir_table *indir;
3376 int err;
3377
3378 memset(&esw->fdb_table.offloads, 0, sizeof(struct offloads_fdb));
3379 mutex_init(&esw->fdb_table.offloads.vports.lock);
3380 hash_init(esw->fdb_table.offloads.vports.table);
3381 atomic64_set(&esw->user_count, 0);
3382
3383 indir = mlx5_esw_indir_table_init();
3384 if (IS_ERR(indir)) {
3385 err = PTR_ERR(indir);
3386 goto create_indir_err;
3387 }
3388 esw->fdb_table.offloads.indir = indir;
3389
3390 err = esw_create_offloads_acl_tables(esw);
3391 if (err)
3392 goto create_acl_err;
3393
3394 err = esw_create_offloads_table(esw);
3395 if (err)
3396 goto create_offloads_err;
3397
3398 err = esw_create_restore_table(esw);
3399 if (err)
3400 goto create_restore_err;
3401
3402 err = esw_create_offloads_fdb_tables(esw);
3403 if (err)
3404 goto create_fdb_err;
3405
3406 err = esw_create_vport_rx_group(esw);
3407 if (err)
3408 goto create_fg_err;
3409
3410 err = esw_create_vport_rx_drop_group(esw);
3411 if (err)
3412 goto create_rx_drop_fg_err;
3413
3414 err = esw_create_vport_rx_drop_rule(esw);
3415 if (err)
3416 goto create_rx_drop_rule_err;
3417
3418 return 0;
3419
3420 create_rx_drop_rule_err:
3421 esw_destroy_vport_rx_drop_group(esw);
3422 create_rx_drop_fg_err:
3423 esw_destroy_vport_rx_group(esw);
3424 create_fg_err:
3425 esw_destroy_offloads_fdb_tables(esw);
3426 create_fdb_err:
3427 esw_destroy_restore_table(esw);
3428 create_restore_err:
3429 esw_destroy_offloads_table(esw);
3430 create_offloads_err:
3431 esw_destroy_offloads_acl_tables(esw);
3432 create_acl_err:
3433 mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir);
3434 create_indir_err:
3435 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
3436 return err;
3437 }
3438
esw_offloads_steering_cleanup(struct mlx5_eswitch * esw)3439 static void esw_offloads_steering_cleanup(struct mlx5_eswitch *esw)
3440 {
3441 esw_destroy_vport_rx_drop_rule(esw);
3442 esw_destroy_vport_rx_drop_group(esw);
3443 esw_destroy_vport_rx_group(esw);
3444 esw_destroy_offloads_fdb_tables(esw);
3445 esw_destroy_restore_table(esw);
3446 esw_destroy_offloads_table(esw);
3447 esw_destroy_offloads_acl_tables(esw);
3448 mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir);
3449 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
3450 }
3451
3452 static void
esw_vfs_changed_event_handler(struct mlx5_eswitch * esw,const u32 * out)3453 esw_vfs_changed_event_handler(struct mlx5_eswitch *esw, const u32 *out)
3454 {
3455 struct devlink *devlink;
3456 bool host_pf_disabled;
3457 u16 new_num_vfs;
3458
3459 new_num_vfs = MLX5_GET(query_esw_functions_out, out,
3460 host_params_context.host_num_of_vfs);
3461 host_pf_disabled = MLX5_GET(query_esw_functions_out, out,
3462 host_params_context.host_pf_disabled);
3463
3464 if (new_num_vfs == esw->esw_funcs.num_vfs || host_pf_disabled)
3465 return;
3466
3467 devlink = priv_to_devlink(esw->dev);
3468 devl_lock(devlink);
3469 /* Number of VFs can only change from "0 to x" or "x to 0". */
3470 if (esw->esw_funcs.num_vfs > 0) {
3471 mlx5_eswitch_unload_vf_vports(esw, esw->esw_funcs.num_vfs);
3472 } else {
3473 int err;
3474
3475 err = mlx5_eswitch_load_vf_vports(esw, new_num_vfs,
3476 MLX5_VPORT_UC_ADDR_CHANGE);
3477 if (err) {
3478 devl_unlock(devlink);
3479 return;
3480 }
3481 }
3482 esw->esw_funcs.num_vfs = new_num_vfs;
3483 devl_unlock(devlink);
3484 }
3485
esw_functions_changed_event_handler(struct work_struct * work)3486 static void esw_functions_changed_event_handler(struct work_struct *work)
3487 {
3488 struct mlx5_host_work *host_work;
3489 struct mlx5_eswitch *esw;
3490 const u32 *out;
3491
3492 host_work = container_of(work, struct mlx5_host_work, work);
3493 esw = host_work->esw;
3494
3495 out = mlx5_esw_query_functions(esw->dev);
3496 if (IS_ERR(out))
3497 goto out;
3498
3499 esw_vfs_changed_event_handler(esw, out);
3500 kvfree(out);
3501 out:
3502 kfree(host_work);
3503 }
3504
mlx5_esw_funcs_changed_handler(struct notifier_block * nb,unsigned long type,void * data)3505 int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data)
3506 {
3507 struct mlx5_esw_functions *esw_funcs;
3508 struct mlx5_host_work *host_work;
3509 struct mlx5_eswitch *esw;
3510
3511 host_work = kzalloc(sizeof(*host_work), GFP_ATOMIC);
3512 if (!host_work)
3513 return NOTIFY_DONE;
3514
3515 esw_funcs = mlx5_nb_cof(nb, struct mlx5_esw_functions, nb);
3516 esw = container_of(esw_funcs, struct mlx5_eswitch, esw_funcs);
3517
3518 host_work->esw = esw;
3519
3520 INIT_WORK(&host_work->work, esw_functions_changed_event_handler);
3521 queue_work(esw->work_queue, &host_work->work);
3522
3523 return NOTIFY_OK;
3524 }
3525
mlx5_esw_host_number_init(struct mlx5_eswitch * esw)3526 static int mlx5_esw_host_number_init(struct mlx5_eswitch *esw)
3527 {
3528 const u32 *query_host_out;
3529
3530 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
3531 return 0;
3532
3533 query_host_out = mlx5_esw_query_functions(esw->dev);
3534 if (IS_ERR(query_host_out))
3535 return PTR_ERR(query_host_out);
3536
3537 /* Mark non local controller with non zero controller number. */
3538 esw->offloads.host_number = MLX5_GET(query_esw_functions_out, query_host_out,
3539 host_params_context.host_number);
3540 kvfree(query_host_out);
3541 return 0;
3542 }
3543
mlx5_esw_offloads_controller_valid(const struct mlx5_eswitch * esw,u32 controller)3544 bool mlx5_esw_offloads_controller_valid(const struct mlx5_eswitch *esw, u32 controller)
3545 {
3546 /* Local controller is always valid */
3547 if (controller == 0)
3548 return true;
3549
3550 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
3551 return false;
3552
3553 /* External host number starts with zero in device */
3554 return (controller == esw->offloads.host_number + 1);
3555 }
3556
esw_offloads_enable(struct mlx5_eswitch * esw)3557 int esw_offloads_enable(struct mlx5_eswitch *esw)
3558 {
3559 struct mapping_ctx *reg_c0_obj_pool;
3560 struct mlx5_vport *vport;
3561 unsigned long i;
3562 u64 mapping_id;
3563 int err;
3564
3565 mutex_init(&esw->offloads.termtbl_mutex);
3566 mlx5_esw_adjacent_vhcas_setup(esw);
3567
3568 err = mlx5_rdma_enable_roce(esw->dev);
3569 if (err)
3570 goto err_roce;
3571
3572 err = mlx5_esw_host_number_init(esw);
3573 if (err)
3574 goto err_metadata;
3575
3576 err = esw_offloads_metadata_init(esw);
3577 if (err)
3578 goto err_metadata;
3579
3580 err = esw_set_passing_vport_metadata(esw, true);
3581 if (err)
3582 goto err_vport_metadata;
3583
3584 mapping_id = mlx5_query_nic_system_image_guid(esw->dev);
3585
3586 reg_c0_obj_pool = mapping_create_for_id(mapping_id, MAPPING_TYPE_CHAIN,
3587 sizeof(struct mlx5_mapped_obj),
3588 ESW_REG_C0_USER_DATA_METADATA_MASK,
3589 true);
3590
3591 if (IS_ERR(reg_c0_obj_pool)) {
3592 err = PTR_ERR(reg_c0_obj_pool);
3593 goto err_pool;
3594 }
3595 esw->offloads.reg_c0_obj_pool = reg_c0_obj_pool;
3596
3597 err = esw_offloads_steering_init(esw);
3598 if (err)
3599 goto err_steering_init;
3600
3601 /* Representor will control the vport link state */
3602 mlx5_esw_for_each_vf_vport(esw, i, vport, esw->esw_funcs.num_vfs)
3603 vport->info.link_state = MLX5_VPORT_ADMIN_STATE_DOWN;
3604 if (mlx5_core_ec_sriov_enabled(esw->dev))
3605 mlx5_esw_for_each_ec_vf_vport(esw, i, vport, esw->esw_funcs.num_ec_vfs)
3606 vport->info.link_state = MLX5_VPORT_ADMIN_STATE_DOWN;
3607
3608 /* Uplink vport rep must load first. */
3609 err = mlx5_esw_offloads_rep_load(esw, MLX5_VPORT_UPLINK);
3610 if (err)
3611 goto err_uplink;
3612
3613 err = mlx5_eswitch_enable_pf_vf_vports(esw, MLX5_VPORT_UC_ADDR_CHANGE);
3614 if (err)
3615 goto err_vports;
3616
3617 return 0;
3618
3619 err_vports:
3620 mlx5_esw_offloads_rep_unload(esw, MLX5_VPORT_UPLINK);
3621 err_uplink:
3622 esw_offloads_steering_cleanup(esw);
3623 err_steering_init:
3624 mapping_destroy(reg_c0_obj_pool);
3625 err_pool:
3626 esw_set_passing_vport_metadata(esw, false);
3627 err_vport_metadata:
3628 esw_offloads_metadata_uninit(esw);
3629 err_metadata:
3630 mlx5_rdma_disable_roce(esw->dev);
3631 err_roce:
3632 mlx5_esw_adjacent_vhcas_cleanup(esw);
3633 mutex_destroy(&esw->offloads.termtbl_mutex);
3634 return err;
3635 }
3636
esw_offloads_stop(struct mlx5_eswitch * esw,struct netlink_ext_ack * extack)3637 static int esw_offloads_stop(struct mlx5_eswitch *esw,
3638 struct netlink_ext_ack *extack)
3639 {
3640 int err;
3641
3642 esw_mode_change(esw, MLX5_ESWITCH_LEGACY);
3643
3644 /* If changing from switchdev to legacy mode without sriov enabled,
3645 * no need to create legacy fdb.
3646 */
3647 if (!mlx5_core_is_pf(esw->dev) || !mlx5_sriov_is_enabled(esw->dev))
3648 return 0;
3649
3650 err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_IGNORE_NUM_VFS);
3651 if (err)
3652 NL_SET_ERR_MSG_MOD(extack, "Failed setting eswitch to legacy");
3653
3654 return err;
3655 }
3656
esw_offloads_disable(struct mlx5_eswitch * esw)3657 void esw_offloads_disable(struct mlx5_eswitch *esw)
3658 {
3659 mlx5_eswitch_disable_pf_vf_vports(esw);
3660 mlx5_esw_offloads_rep_unload(esw, MLX5_VPORT_UPLINK);
3661 esw_set_passing_vport_metadata(esw, false);
3662 esw_offloads_steering_cleanup(esw);
3663 mapping_destroy(esw->offloads.reg_c0_obj_pool);
3664 esw_offloads_metadata_uninit(esw);
3665 mlx5_rdma_disable_roce(esw->dev);
3666 mlx5_esw_adjacent_vhcas_cleanup(esw);
3667 mutex_destroy(&esw->offloads.termtbl_mutex);
3668 }
3669
esw_mode_from_devlink(u16 mode,u16 * mlx5_mode)3670 static int esw_mode_from_devlink(u16 mode, u16 *mlx5_mode)
3671 {
3672 switch (mode) {
3673 case DEVLINK_ESWITCH_MODE_LEGACY:
3674 *mlx5_mode = MLX5_ESWITCH_LEGACY;
3675 break;
3676 case DEVLINK_ESWITCH_MODE_SWITCHDEV:
3677 *mlx5_mode = MLX5_ESWITCH_OFFLOADS;
3678 break;
3679 default:
3680 return -EINVAL;
3681 }
3682
3683 return 0;
3684 }
3685
esw_mode_to_devlink(u16 mlx5_mode,u16 * mode)3686 static int esw_mode_to_devlink(u16 mlx5_mode, u16 *mode)
3687 {
3688 switch (mlx5_mode) {
3689 case MLX5_ESWITCH_LEGACY:
3690 *mode = DEVLINK_ESWITCH_MODE_LEGACY;
3691 break;
3692 case MLX5_ESWITCH_OFFLOADS:
3693 *mode = DEVLINK_ESWITCH_MODE_SWITCHDEV;
3694 break;
3695 default:
3696 return -EINVAL;
3697 }
3698
3699 return 0;
3700 }
3701
esw_inline_mode_from_devlink(u8 mode,u8 * mlx5_mode)3702 static int esw_inline_mode_from_devlink(u8 mode, u8 *mlx5_mode)
3703 {
3704 switch (mode) {
3705 case DEVLINK_ESWITCH_INLINE_MODE_NONE:
3706 *mlx5_mode = MLX5_INLINE_MODE_NONE;
3707 break;
3708 case DEVLINK_ESWITCH_INLINE_MODE_LINK:
3709 *mlx5_mode = MLX5_INLINE_MODE_L2;
3710 break;
3711 case DEVLINK_ESWITCH_INLINE_MODE_NETWORK:
3712 *mlx5_mode = MLX5_INLINE_MODE_IP;
3713 break;
3714 case DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT:
3715 *mlx5_mode = MLX5_INLINE_MODE_TCP_UDP;
3716 break;
3717 default:
3718 return -EINVAL;
3719 }
3720
3721 return 0;
3722 }
3723
esw_inline_mode_to_devlink(u8 mlx5_mode,u8 * mode)3724 static int esw_inline_mode_to_devlink(u8 mlx5_mode, u8 *mode)
3725 {
3726 switch (mlx5_mode) {
3727 case MLX5_INLINE_MODE_NONE:
3728 *mode = DEVLINK_ESWITCH_INLINE_MODE_NONE;
3729 break;
3730 case MLX5_INLINE_MODE_L2:
3731 *mode = DEVLINK_ESWITCH_INLINE_MODE_LINK;
3732 break;
3733 case MLX5_INLINE_MODE_IP:
3734 *mode = DEVLINK_ESWITCH_INLINE_MODE_NETWORK;
3735 break;
3736 case MLX5_INLINE_MODE_TCP_UDP:
3737 *mode = DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT;
3738 break;
3739 default:
3740 return -EINVAL;
3741 }
3742
3743 return 0;
3744 }
3745
mlx5_eswitch_block_mode(struct mlx5_core_dev * dev)3746 int mlx5_eswitch_block_mode(struct mlx5_core_dev *dev)
3747 {
3748 struct mlx5_eswitch *esw = dev->priv.eswitch;
3749 int err;
3750
3751 if (!mlx5_esw_allowed(esw))
3752 return 0;
3753
3754 /* Take TC into account */
3755 err = mlx5_esw_try_lock(esw);
3756 if (err < 0)
3757 return err;
3758
3759 esw->offloads.num_block_mode++;
3760 mlx5_esw_unlock(esw);
3761 return 0;
3762 }
3763
mlx5_eswitch_unblock_mode(struct mlx5_core_dev * dev)3764 void mlx5_eswitch_unblock_mode(struct mlx5_core_dev *dev)
3765 {
3766 struct mlx5_eswitch *esw = dev->priv.eswitch;
3767
3768 if (!mlx5_esw_allowed(esw))
3769 return;
3770
3771 down_write(&esw->mode_lock);
3772 esw->offloads.num_block_mode--;
3773 up_write(&esw->mode_lock);
3774 }
3775
3776 /* Returns false only when uplink netdev exists and its netns is different from
3777 * devlink's netns. True for all others so entering switchdev mode is allowed.
3778 */
mlx5_devlink_netdev_netns_immutable_set(struct devlink * devlink,bool immutable)3779 static bool mlx5_devlink_netdev_netns_immutable_set(struct devlink *devlink,
3780 bool immutable)
3781 {
3782 struct mlx5_core_dev *mdev = devlink_priv(devlink);
3783 struct net_device *netdev;
3784 bool ret;
3785
3786 netdev = mlx5_uplink_netdev_get(mdev);
3787 if (!netdev)
3788 return true;
3789
3790 rtnl_lock();
3791 netdev->netns_immutable = immutable;
3792 ret = net_eq(dev_net(netdev), devlink_net(devlink));
3793 rtnl_unlock();
3794
3795 mlx5_uplink_netdev_put(mdev, netdev);
3796 return ret;
3797 }
3798
mlx5_devlink_eswitch_mode_set(struct devlink * devlink,u16 mode,struct netlink_ext_ack * extack)3799 int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
3800 struct netlink_ext_ack *extack)
3801 {
3802 u16 cur_mlx5_mode, mlx5_mode = 0;
3803 struct mlx5_eswitch *esw;
3804 int err = 0;
3805
3806 esw = mlx5_devlink_eswitch_get(devlink);
3807 if (IS_ERR(esw))
3808 return PTR_ERR(esw);
3809
3810 if (esw_mode_from_devlink(mode, &mlx5_mode))
3811 return -EINVAL;
3812
3813 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV && mlx5_get_sd(esw->dev)) {
3814 NL_SET_ERR_MSG_MOD(extack,
3815 "Can't change E-Switch mode to switchdev when multi-PF netdev (Socket Direct) is configured.");
3816 return -EPERM;
3817 }
3818
3819 mlx5_lag_disable_change(esw->dev);
3820 err = mlx5_esw_try_lock(esw);
3821 if (err < 0) {
3822 NL_SET_ERR_MSG_MOD(extack, "Can't change mode, E-Switch is busy");
3823 goto enable_lag;
3824 }
3825 cur_mlx5_mode = err;
3826 err = 0;
3827
3828 if (cur_mlx5_mode == mlx5_mode)
3829 goto unlock;
3830
3831 if (esw->offloads.num_block_mode) {
3832 NL_SET_ERR_MSG_MOD(extack,
3833 "Can't change eswitch mode when IPsec SA and/or policies are configured");
3834 err = -EOPNOTSUPP;
3835 goto unlock;
3836 }
3837
3838 esw->eswitch_operation_in_progress = true;
3839 up_write(&esw->mode_lock);
3840
3841 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV &&
3842 !mlx5_devlink_netdev_netns_immutable_set(devlink, true)) {
3843 NL_SET_ERR_MSG_MOD(extack,
3844 "Can't change E-Switch mode to switchdev when netdev net namespace has diverged from the devlink's.");
3845 err = -EINVAL;
3846 goto skip;
3847 }
3848
3849 if (mode == DEVLINK_ESWITCH_MODE_LEGACY)
3850 esw->dev->priv.flags |= MLX5_PRIV_FLAGS_SWITCH_LEGACY;
3851 mlx5_eswitch_disable_locked(esw);
3852 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV) {
3853 if (mlx5_devlink_trap_get_num_active(esw->dev)) {
3854 NL_SET_ERR_MSG_MOD(extack,
3855 "Can't change mode while devlink traps are active");
3856 err = -EOPNOTSUPP;
3857 goto skip;
3858 }
3859 err = esw_offloads_start(esw, extack);
3860 } else if (mode == DEVLINK_ESWITCH_MODE_LEGACY) {
3861 err = esw_offloads_stop(esw, extack);
3862 } else {
3863 err = -EINVAL;
3864 }
3865
3866 skip:
3867 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV && err)
3868 mlx5_devlink_netdev_netns_immutable_set(devlink, false);
3869 down_write(&esw->mode_lock);
3870 esw->eswitch_operation_in_progress = false;
3871 unlock:
3872 mlx5_esw_unlock(esw);
3873 enable_lag:
3874 mlx5_lag_enable_change(esw->dev);
3875 return err;
3876 }
3877
mlx5_devlink_eswitch_mode_get(struct devlink * devlink,u16 * mode)3878 int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode)
3879 {
3880 struct mlx5_eswitch *esw;
3881
3882 esw = mlx5_devlink_eswitch_get(devlink);
3883 if (IS_ERR(esw))
3884 return PTR_ERR(esw);
3885
3886 return esw_mode_to_devlink(esw->mode, mode);
3887 }
3888
mlx5_esw_vports_inline_set(struct mlx5_eswitch * esw,u8 mlx5_mode,struct netlink_ext_ack * extack)3889 static int mlx5_esw_vports_inline_set(struct mlx5_eswitch *esw, u8 mlx5_mode,
3890 struct netlink_ext_ack *extack)
3891 {
3892 struct mlx5_core_dev *dev = esw->dev;
3893 struct mlx5_vport *vport;
3894 u16 err_vport_num = 0;
3895 unsigned long i;
3896 int err = 0;
3897
3898 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
3899 err = mlx5_modify_nic_vport_min_inline(dev, vport->vport, mlx5_mode);
3900 if (err) {
3901 err_vport_num = vport->vport;
3902 NL_SET_ERR_MSG_MOD(extack,
3903 "Failed to set min inline on vport");
3904 goto revert_inline_mode;
3905 }
3906 }
3907 if (mlx5_core_ec_sriov_enabled(esw->dev)) {
3908 mlx5_esw_for_each_ec_vf_vport(esw, i, vport, esw->esw_funcs.num_ec_vfs) {
3909 err = mlx5_modify_nic_vport_min_inline(dev, vport->vport, mlx5_mode);
3910 if (err) {
3911 err_vport_num = vport->vport;
3912 NL_SET_ERR_MSG_MOD(extack,
3913 "Failed to set min inline on vport");
3914 goto revert_ec_vf_inline_mode;
3915 }
3916 }
3917 }
3918 return 0;
3919
3920 revert_ec_vf_inline_mode:
3921 mlx5_esw_for_each_ec_vf_vport(esw, i, vport, esw->esw_funcs.num_ec_vfs) {
3922 if (vport->vport == err_vport_num)
3923 break;
3924 mlx5_modify_nic_vport_min_inline(dev,
3925 vport->vport,
3926 esw->offloads.inline_mode);
3927 }
3928 revert_inline_mode:
3929 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
3930 if (vport->vport == err_vport_num)
3931 break;
3932 mlx5_modify_nic_vport_min_inline(dev,
3933 vport->vport,
3934 esw->offloads.inline_mode);
3935 }
3936 return err;
3937 }
3938
mlx5_devlink_eswitch_inline_mode_set(struct devlink * devlink,u8 mode,struct netlink_ext_ack * extack)3939 int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
3940 struct netlink_ext_ack *extack)
3941 {
3942 struct mlx5_core_dev *dev = devlink_priv(devlink);
3943 struct mlx5_eswitch *esw;
3944 u8 mlx5_mode;
3945 int err;
3946
3947 esw = mlx5_devlink_eswitch_get(devlink);
3948 if (IS_ERR(esw))
3949 return PTR_ERR(esw);
3950
3951 down_write(&esw->mode_lock);
3952
3953 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
3954 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
3955 if (mode == DEVLINK_ESWITCH_INLINE_MODE_NONE) {
3956 err = 0;
3957 goto out;
3958 }
3959
3960 fallthrough;
3961 case MLX5_CAP_INLINE_MODE_L2:
3962 NL_SET_ERR_MSG_MOD(extack, "Inline mode can't be set");
3963 err = -EOPNOTSUPP;
3964 goto out;
3965 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
3966 break;
3967 }
3968
3969 if (atomic64_read(&esw->offloads.num_flows) > 0) {
3970 NL_SET_ERR_MSG_MOD(extack,
3971 "Can't set inline mode when flows are configured");
3972 err = -EOPNOTSUPP;
3973 goto out;
3974 }
3975
3976 err = esw_inline_mode_from_devlink(mode, &mlx5_mode);
3977 if (err)
3978 goto out;
3979
3980 esw->eswitch_operation_in_progress = true;
3981 up_write(&esw->mode_lock);
3982
3983 err = mlx5_esw_vports_inline_set(esw, mlx5_mode, extack);
3984 if (!err)
3985 esw->offloads.inline_mode = mlx5_mode;
3986
3987 down_write(&esw->mode_lock);
3988 esw->eswitch_operation_in_progress = false;
3989 up_write(&esw->mode_lock);
3990 return 0;
3991
3992 out:
3993 up_write(&esw->mode_lock);
3994 return err;
3995 }
3996
mlx5_devlink_eswitch_inline_mode_get(struct devlink * devlink,u8 * mode)3997 int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode)
3998 {
3999 struct mlx5_eswitch *esw;
4000
4001 esw = mlx5_devlink_eswitch_get(devlink);
4002 if (IS_ERR(esw))
4003 return PTR_ERR(esw);
4004
4005 return esw_inline_mode_to_devlink(esw->offloads.inline_mode, mode);
4006 }
4007
mlx5_eswitch_block_encap(struct mlx5_core_dev * dev,bool from_fdb)4008 bool mlx5_eswitch_block_encap(struct mlx5_core_dev *dev, bool from_fdb)
4009 {
4010 struct mlx5_eswitch *esw = dev->priv.eswitch;
4011 enum devlink_eswitch_encap_mode encap;
4012 bool allow_tunnel = false;
4013
4014 if (!mlx5_esw_allowed(esw))
4015 return true;
4016
4017 down_write(&esw->mode_lock);
4018 encap = esw->offloads.encap;
4019 if (esw->mode == MLX5_ESWITCH_LEGACY ||
4020 (encap == DEVLINK_ESWITCH_ENCAP_MODE_NONE && !from_fdb)) {
4021 allow_tunnel = true;
4022 esw->offloads.num_block_encap++;
4023 }
4024 up_write(&esw->mode_lock);
4025
4026 return allow_tunnel;
4027 }
4028
mlx5_eswitch_unblock_encap(struct mlx5_core_dev * dev)4029 void mlx5_eswitch_unblock_encap(struct mlx5_core_dev *dev)
4030 {
4031 struct mlx5_eswitch *esw = dev->priv.eswitch;
4032
4033 if (!mlx5_esw_allowed(esw))
4034 return;
4035
4036 down_write(&esw->mode_lock);
4037 esw->offloads.num_block_encap--;
4038 up_write(&esw->mode_lock);
4039 }
4040
mlx5_devlink_eswitch_encap_mode_set(struct devlink * devlink,enum devlink_eswitch_encap_mode encap,struct netlink_ext_ack * extack)4041 int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,
4042 enum devlink_eswitch_encap_mode encap,
4043 struct netlink_ext_ack *extack)
4044 {
4045 struct mlx5_core_dev *dev = devlink_priv(devlink);
4046 struct mlx5_eswitch *esw;
4047 int err = 0;
4048
4049 esw = mlx5_devlink_eswitch_get(devlink);
4050 if (IS_ERR(esw))
4051 return PTR_ERR(esw);
4052
4053 down_write(&esw->mode_lock);
4054
4055 if (encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE &&
4056 (!MLX5_CAP_ESW_FLOWTABLE_FDB(dev, reformat) ||
4057 !MLX5_CAP_ESW_FLOWTABLE_FDB(dev, decap))) {
4058 err = -EOPNOTSUPP;
4059 goto unlock;
4060 }
4061
4062 if (encap && encap != DEVLINK_ESWITCH_ENCAP_MODE_BASIC) {
4063 err = -EOPNOTSUPP;
4064 goto unlock;
4065 }
4066
4067 if (esw->mode == MLX5_ESWITCH_LEGACY) {
4068 esw->offloads.encap = encap;
4069 goto unlock;
4070 }
4071
4072 if (esw->offloads.encap == encap)
4073 goto unlock;
4074
4075 if (atomic64_read(&esw->offloads.num_flows) > 0) {
4076 NL_SET_ERR_MSG_MOD(extack,
4077 "Can't set encapsulation when flows are configured");
4078 err = -EOPNOTSUPP;
4079 goto unlock;
4080 }
4081
4082 if (esw->offloads.num_block_encap) {
4083 NL_SET_ERR_MSG_MOD(extack,
4084 "Can't set encapsulation when IPsec SA and/or policies are configured");
4085 err = -EOPNOTSUPP;
4086 goto unlock;
4087 }
4088
4089 esw->eswitch_operation_in_progress = true;
4090 up_write(&esw->mode_lock);
4091
4092 esw_destroy_offloads_fdb_tables(esw);
4093
4094 esw->offloads.encap = encap;
4095
4096 err = esw_create_offloads_fdb_tables(esw);
4097
4098 if (err) {
4099 NL_SET_ERR_MSG_MOD(extack,
4100 "Failed re-creating fast FDB table");
4101 esw->offloads.encap = !encap;
4102 (void)esw_create_offloads_fdb_tables(esw);
4103 }
4104
4105 down_write(&esw->mode_lock);
4106 esw->eswitch_operation_in_progress = false;
4107
4108 unlock:
4109 up_write(&esw->mode_lock);
4110 return err;
4111 }
4112
mlx5_devlink_eswitch_encap_mode_get(struct devlink * devlink,enum devlink_eswitch_encap_mode * encap)4113 int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink,
4114 enum devlink_eswitch_encap_mode *encap)
4115 {
4116 struct mlx5_eswitch *esw;
4117
4118 esw = mlx5_devlink_eswitch_get(devlink);
4119 if (IS_ERR(esw))
4120 return PTR_ERR(esw);
4121
4122 *encap = esw->offloads.encap;
4123 return 0;
4124 }
4125
4126 static bool
mlx5_eswitch_vport_has_rep(const struct mlx5_eswitch * esw,u16 vport_num)4127 mlx5_eswitch_vport_has_rep(const struct mlx5_eswitch *esw, u16 vport_num)
4128 {
4129 /* Currently, only ECPF based device has representor for host PF. */
4130 if (vport_num == MLX5_VPORT_PF &&
4131 (!mlx5_core_is_ecpf_esw_manager(esw->dev) ||
4132 !mlx5_esw_host_functions_enabled(esw->dev)))
4133 return false;
4134
4135 if (vport_num == MLX5_VPORT_ECPF &&
4136 !mlx5_ecpf_vport_exists(esw->dev))
4137 return false;
4138
4139 return true;
4140 }
4141
mlx5_eswitch_register_vport_reps(struct mlx5_eswitch * esw,const struct mlx5_eswitch_rep_ops * ops,u8 rep_type)4142 void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw,
4143 const struct mlx5_eswitch_rep_ops *ops,
4144 u8 rep_type)
4145 {
4146 struct mlx5_eswitch_rep_data *rep_data;
4147 struct mlx5_eswitch_rep *rep;
4148 unsigned long i;
4149
4150 esw->offloads.rep_ops[rep_type] = ops;
4151 mlx5_esw_for_each_rep(esw, i, rep) {
4152 if (likely(mlx5_eswitch_vport_has_rep(esw, rep->vport))) {
4153 rep->esw = esw;
4154 rep_data = &rep->rep_data[rep_type];
4155 atomic_set(&rep_data->state, REP_REGISTERED);
4156 }
4157 }
4158 }
4159 EXPORT_SYMBOL(mlx5_eswitch_register_vport_reps);
4160
mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch * esw,u8 rep_type)4161 void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type)
4162 {
4163 struct mlx5_eswitch_rep *rep;
4164 unsigned long i;
4165
4166 if (esw->mode == MLX5_ESWITCH_OFFLOADS)
4167 __unload_reps_all_vport(esw, rep_type);
4168
4169 mlx5_esw_for_each_rep(esw, i, rep)
4170 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
4171 }
4172 EXPORT_SYMBOL(mlx5_eswitch_unregister_vport_reps);
4173
mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch * esw,u8 rep_type)4174 void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type)
4175 {
4176 struct mlx5_eswitch_rep *rep;
4177
4178 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
4179 return rep->rep_data[rep_type].priv;
4180 }
4181
mlx5_eswitch_get_proto_dev(struct mlx5_eswitch * esw,u16 vport,u8 rep_type)4182 void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,
4183 u16 vport,
4184 u8 rep_type)
4185 {
4186 struct mlx5_eswitch_rep *rep;
4187
4188 rep = mlx5_eswitch_get_rep(esw, vport);
4189
4190 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
4191 esw->offloads.rep_ops[rep_type]->get_proto_dev)
4192 return esw->offloads.rep_ops[rep_type]->get_proto_dev(rep);
4193 return NULL;
4194 }
4195 EXPORT_SYMBOL(mlx5_eswitch_get_proto_dev);
4196
mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch * esw,u8 rep_type)4197 void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type)
4198 {
4199 return mlx5_eswitch_get_proto_dev(esw, MLX5_VPORT_UPLINK, rep_type);
4200 }
4201 EXPORT_SYMBOL(mlx5_eswitch_uplink_get_proto_dev);
4202
mlx5_eswitch_vport_rep(struct mlx5_eswitch * esw,u16 vport)4203 struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
4204 u16 vport)
4205 {
4206 return mlx5_eswitch_get_rep(esw, vport);
4207 }
4208 EXPORT_SYMBOL(mlx5_eswitch_vport_rep);
4209
mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch * esw)4210 bool mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch *esw)
4211 {
4212 return !!(esw->flags & MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED);
4213 }
4214 EXPORT_SYMBOL(mlx5_eswitch_reg_c1_loopback_enabled);
4215
mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch * esw)4216 bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw)
4217 {
4218 return !!(esw->flags & MLX5_ESWITCH_VPORT_MATCH_METADATA);
4219 }
4220 EXPORT_SYMBOL(mlx5_eswitch_vport_match_metadata_enabled);
4221
mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch * esw,u16 vport_num)4222 u32 mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw,
4223 u16 vport_num)
4224 {
4225 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
4226
4227 if (WARN_ON_ONCE(IS_ERR(vport)))
4228 return 0;
4229
4230 return vport->metadata << (32 - ESW_SOURCE_PORT_METADATA_BITS);
4231 }
4232 EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_match);
4233
mlx5_esw_vport_vhca_id_map(struct mlx5_eswitch * esw,struct mlx5_vport * vport)4234 int mlx5_esw_vport_vhca_id_map(struct mlx5_eswitch *esw,
4235 struct mlx5_vport *vport)
4236 {
4237 u16 *old_entry, *vhca_map_entry, vhca_id;
4238
4239 if (WARN_ONCE(MLX5_VPORT_INVAL_VHCA_ID(vport),
4240 "vport %d vhca_id is not set", vport->vport)) {
4241 int err;
4242
4243 err = mlx5_vport_get_vhca_id(vport->dev, vport->vport,
4244 &vhca_id);
4245 if (err)
4246 return err;
4247 vport->vhca_id = vhca_id;
4248 }
4249
4250 vhca_id = vport->vhca_id;
4251 vhca_map_entry = kmalloc(sizeof(*vhca_map_entry), GFP_KERNEL);
4252 if (!vhca_map_entry)
4253 return -ENOMEM;
4254
4255 *vhca_map_entry = vport->vport;
4256 old_entry = xa_store(&esw->offloads.vhca_map, vhca_id, vhca_map_entry, GFP_KERNEL);
4257 if (xa_is_err(old_entry)) {
4258 kfree(vhca_map_entry);
4259 return xa_err(old_entry);
4260 }
4261 kfree(old_entry);
4262 return 0;
4263 }
4264
mlx5_esw_vport_vhca_id_unmap(struct mlx5_eswitch * esw,struct mlx5_vport * vport)4265 void mlx5_esw_vport_vhca_id_unmap(struct mlx5_eswitch *esw,
4266 struct mlx5_vport *vport)
4267 {
4268 u16 *vhca_map_entry;
4269
4270 vhca_map_entry = xa_erase(&esw->offloads.vhca_map, vport->vhca_id);
4271 kfree(vhca_map_entry);
4272 }
4273
mlx5_eswitch_vhca_id_to_vport(struct mlx5_eswitch * esw,u16 vhca_id,u16 * vport_num)4274 int mlx5_eswitch_vhca_id_to_vport(struct mlx5_eswitch *esw, u16 vhca_id, u16 *vport_num)
4275 {
4276 u16 *res = xa_load(&esw->offloads.vhca_map, vhca_id);
4277
4278 if (!res)
4279 return -ENOENT;
4280
4281 *vport_num = *res;
4282 return 0;
4283 }
4284
mlx5_eswitch_get_vport_metadata_for_set(struct mlx5_eswitch * esw,u16 vport_num)4285 u32 mlx5_eswitch_get_vport_metadata_for_set(struct mlx5_eswitch *esw,
4286 u16 vport_num)
4287 {
4288 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
4289
4290 if (WARN_ON_ONCE(IS_ERR(vport)))
4291 return 0;
4292
4293 return vport->metadata;
4294 }
4295 EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_set);
4296
mlx5_devlink_port_fn_hw_addr_get(struct devlink_port * port,u8 * hw_addr,int * hw_addr_len,struct netlink_ext_ack * extack)4297 int mlx5_devlink_port_fn_hw_addr_get(struct devlink_port *port,
4298 u8 *hw_addr, int *hw_addr_len,
4299 struct netlink_ext_ack *extack)
4300 {
4301 struct mlx5_eswitch *esw = mlx5_devlink_eswitch_nocheck_get(port->devlink);
4302 struct mlx5_vport *vport = mlx5_devlink_port_vport_get(port);
4303
4304 mutex_lock(&esw->state_lock);
4305 ether_addr_copy(hw_addr, vport->info.mac);
4306 *hw_addr_len = ETH_ALEN;
4307 mutex_unlock(&esw->state_lock);
4308 return 0;
4309 }
4310
mlx5_devlink_port_fn_hw_addr_set(struct devlink_port * port,const u8 * hw_addr,int hw_addr_len,struct netlink_ext_ack * extack)4311 int mlx5_devlink_port_fn_hw_addr_set(struct devlink_port *port,
4312 const u8 *hw_addr, int hw_addr_len,
4313 struct netlink_ext_ack *extack)
4314 {
4315 struct mlx5_eswitch *esw = mlx5_devlink_eswitch_nocheck_get(port->devlink);
4316 struct mlx5_vport *vport = mlx5_devlink_port_vport_get(port);
4317
4318 return mlx5_eswitch_set_vport_mac(esw, vport->vport, hw_addr);
4319 }
4320
mlx5_devlink_port_fn_migratable_get(struct devlink_port * port,bool * is_enabled,struct netlink_ext_ack * extack)4321 int mlx5_devlink_port_fn_migratable_get(struct devlink_port *port, bool *is_enabled,
4322 struct netlink_ext_ack *extack)
4323 {
4324 struct mlx5_eswitch *esw = mlx5_devlink_eswitch_nocheck_get(port->devlink);
4325 struct mlx5_vport *vport = mlx5_devlink_port_vport_get(port);
4326
4327 if (!MLX5_CAP_GEN(esw->dev, migration)) {
4328 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support migration");
4329 return -EOPNOTSUPP;
4330 }
4331
4332 if (!MLX5_CAP_GEN(esw->dev, vhca_resource_manager)) {
4333 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support VHCA management");
4334 return -EOPNOTSUPP;
4335 }
4336
4337 mutex_lock(&esw->state_lock);
4338 *is_enabled = vport->info.mig_enabled;
4339 mutex_unlock(&esw->state_lock);
4340 return 0;
4341 }
4342
mlx5_devlink_port_fn_migratable_set(struct devlink_port * port,bool enable,struct netlink_ext_ack * extack)4343 int mlx5_devlink_port_fn_migratable_set(struct devlink_port *port, bool enable,
4344 struct netlink_ext_ack *extack)
4345 {
4346 struct mlx5_eswitch *esw = mlx5_devlink_eswitch_nocheck_get(port->devlink);
4347 struct mlx5_vport *vport = mlx5_devlink_port_vport_get(port);
4348 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
4349 void *query_ctx;
4350 void *hca_caps;
4351 int err;
4352
4353 if (!MLX5_CAP_GEN(esw->dev, migration)) {
4354 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support migration");
4355 return -EOPNOTSUPP;
4356 }
4357
4358 if (!MLX5_CAP_GEN(esw->dev, vhca_resource_manager)) {
4359 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support VHCA management");
4360 return -EOPNOTSUPP;
4361 }
4362
4363 mutex_lock(&esw->state_lock);
4364
4365 if (vport->info.mig_enabled == enable) {
4366 err = 0;
4367 goto out;
4368 }
4369
4370 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
4371 if (!query_ctx) {
4372 err = -ENOMEM;
4373 goto out;
4374 }
4375
4376 err = mlx5_vport_get_other_func_cap(esw->dev, vport->vport, query_ctx,
4377 MLX5_CAP_GENERAL_2);
4378 if (err) {
4379 NL_SET_ERR_MSG_MOD(extack, "Failed getting HCA caps");
4380 goto out_free;
4381 }
4382
4383 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
4384 MLX5_SET(cmd_hca_cap_2, hca_caps, migratable, enable);
4385
4386 err = mlx5_vport_set_other_func_cap(esw->dev, hca_caps, vport->vport,
4387 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2);
4388 if (err) {
4389 NL_SET_ERR_MSG_MOD(extack, "Failed setting HCA migratable cap");
4390 goto out_free;
4391 }
4392
4393 vport->info.mig_enabled = enable;
4394
4395 out_free:
4396 kfree(query_ctx);
4397 out:
4398 mutex_unlock(&esw->state_lock);
4399 return err;
4400 }
4401
mlx5_devlink_port_fn_roce_get(struct devlink_port * port,bool * is_enabled,struct netlink_ext_ack * extack)4402 int mlx5_devlink_port_fn_roce_get(struct devlink_port *port, bool *is_enabled,
4403 struct netlink_ext_ack *extack)
4404 {
4405 struct mlx5_eswitch *esw = mlx5_devlink_eswitch_nocheck_get(port->devlink);
4406 struct mlx5_vport *vport = mlx5_devlink_port_vport_get(port);
4407
4408 if (!MLX5_CAP_GEN(esw->dev, vhca_resource_manager)) {
4409 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support VHCA management");
4410 return -EOPNOTSUPP;
4411 }
4412
4413 mutex_lock(&esw->state_lock);
4414 *is_enabled = vport->info.roce_enabled;
4415 mutex_unlock(&esw->state_lock);
4416 return 0;
4417 }
4418
mlx5_devlink_port_fn_roce_set(struct devlink_port * port,bool enable,struct netlink_ext_ack * extack)4419 int mlx5_devlink_port_fn_roce_set(struct devlink_port *port, bool enable,
4420 struct netlink_ext_ack *extack)
4421 {
4422 struct mlx5_eswitch *esw = mlx5_devlink_eswitch_nocheck_get(port->devlink);
4423 struct mlx5_vport *vport = mlx5_devlink_port_vport_get(port);
4424 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
4425 u16 vport_num = vport->vport;
4426 void *query_ctx;
4427 void *hca_caps;
4428 int err;
4429
4430 if (!MLX5_CAP_GEN(esw->dev, vhca_resource_manager)) {
4431 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support VHCA management");
4432 return -EOPNOTSUPP;
4433 }
4434
4435 mutex_lock(&esw->state_lock);
4436
4437 if (vport->info.roce_enabled == enable) {
4438 err = 0;
4439 goto out;
4440 }
4441
4442 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
4443 if (!query_ctx) {
4444 err = -ENOMEM;
4445 goto out;
4446 }
4447
4448 err = mlx5_vport_get_other_func_cap(esw->dev, vport_num, query_ctx,
4449 MLX5_CAP_GENERAL);
4450 if (err) {
4451 NL_SET_ERR_MSG_MOD(extack, "Failed getting HCA caps");
4452 goto out_free;
4453 }
4454
4455 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
4456 MLX5_SET(cmd_hca_cap, hca_caps, roce, enable);
4457
4458 err = mlx5_vport_set_other_func_cap(esw->dev, hca_caps, vport_num,
4459 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
4460 if (err) {
4461 NL_SET_ERR_MSG_MOD(extack, "Failed setting HCA roce cap");
4462 goto out_free;
4463 }
4464
4465 vport->info.roce_enabled = enable;
4466
4467 out_free:
4468 kfree(query_ctx);
4469 out:
4470 mutex_unlock(&esw->state_lock);
4471 return err;
4472 }
4473
4474 int
mlx5_eswitch_restore_ipsec_rule(struct mlx5_eswitch * esw,struct mlx5_flow_handle * rule,struct mlx5_esw_flow_attr * esw_attr,int attr_idx)4475 mlx5_eswitch_restore_ipsec_rule(struct mlx5_eswitch *esw, struct mlx5_flow_handle *rule,
4476 struct mlx5_esw_flow_attr *esw_attr, int attr_idx)
4477 {
4478 struct mlx5_flow_destination new_dest = {};
4479 struct mlx5_flow_destination old_dest = {};
4480
4481 if (!esw_setup_uplink_fwd_ipsec_needed(esw, esw_attr, attr_idx))
4482 return 0;
4483
4484 esw_setup_dest_fwd_ipsec(&old_dest, NULL, esw, esw_attr, attr_idx, 0, false);
4485 esw_setup_dest_fwd_vport(&new_dest, NULL, esw, esw_attr, attr_idx, 0, false);
4486
4487 return mlx5_modify_rule_destination(rule, &new_dest, &old_dest);
4488 }
4489
4490 #ifdef CONFIG_XFRM_OFFLOAD
mlx5_devlink_port_fn_ipsec_crypto_get(struct devlink_port * port,bool * is_enabled,struct netlink_ext_ack * extack)4491 int mlx5_devlink_port_fn_ipsec_crypto_get(struct devlink_port *port, bool *is_enabled,
4492 struct netlink_ext_ack *extack)
4493 {
4494 struct mlx5_eswitch *esw;
4495 struct mlx5_vport *vport;
4496 int err = 0;
4497
4498 esw = mlx5_devlink_eswitch_get(port->devlink);
4499 if (IS_ERR(esw))
4500 return PTR_ERR(esw);
4501
4502 if (!mlx5_esw_ipsec_vf_offload_supported(esw->dev)) {
4503 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support IPSec crypto");
4504 return -EOPNOTSUPP;
4505 }
4506
4507 vport = mlx5_devlink_port_vport_get(port);
4508
4509 mutex_lock(&esw->state_lock);
4510 if (!vport->enabled) {
4511 err = -EOPNOTSUPP;
4512 goto unlock;
4513 }
4514
4515 *is_enabled = vport->info.ipsec_crypto_enabled;
4516 unlock:
4517 mutex_unlock(&esw->state_lock);
4518 return err;
4519 }
4520
mlx5_devlink_port_fn_ipsec_crypto_set(struct devlink_port * port,bool enable,struct netlink_ext_ack * extack)4521 int mlx5_devlink_port_fn_ipsec_crypto_set(struct devlink_port *port, bool enable,
4522 struct netlink_ext_ack *extack)
4523 {
4524 struct mlx5_eswitch *esw;
4525 struct mlx5_vport *vport;
4526 u16 vport_num;
4527 int err;
4528
4529 esw = mlx5_devlink_eswitch_get(port->devlink);
4530 if (IS_ERR(esw))
4531 return PTR_ERR(esw);
4532
4533 vport_num = mlx5_esw_devlink_port_index_to_vport_num(port->index);
4534 err = mlx5_esw_ipsec_vf_crypto_offload_supported(esw->dev, vport_num);
4535 if (err) {
4536 NL_SET_ERR_MSG_MOD(extack,
4537 "Device doesn't support IPsec crypto");
4538 return err;
4539 }
4540
4541 vport = mlx5_devlink_port_vport_get(port);
4542
4543 mutex_lock(&esw->state_lock);
4544 if (!vport->enabled) {
4545 err = -EOPNOTSUPP;
4546 NL_SET_ERR_MSG_MOD(extack, "Eswitch vport is disabled");
4547 goto unlock;
4548 }
4549
4550 if (vport->info.ipsec_crypto_enabled == enable)
4551 goto unlock;
4552
4553 if (!esw->enabled_ipsec_vf_count && esw->dev->num_ipsec_offloads) {
4554 err = -EBUSY;
4555 goto unlock;
4556 }
4557
4558 err = mlx5_esw_ipsec_vf_crypto_offload_set(esw, vport, enable);
4559 if (err) {
4560 NL_SET_ERR_MSG_MOD(extack, "Failed to set IPsec crypto");
4561 goto unlock;
4562 }
4563
4564 vport->info.ipsec_crypto_enabled = enable;
4565 if (enable)
4566 esw->enabled_ipsec_vf_count++;
4567 else
4568 esw->enabled_ipsec_vf_count--;
4569 unlock:
4570 mutex_unlock(&esw->state_lock);
4571 return err;
4572 }
4573
mlx5_devlink_port_fn_ipsec_packet_get(struct devlink_port * port,bool * is_enabled,struct netlink_ext_ack * extack)4574 int mlx5_devlink_port_fn_ipsec_packet_get(struct devlink_port *port, bool *is_enabled,
4575 struct netlink_ext_ack *extack)
4576 {
4577 struct mlx5_eswitch *esw;
4578 struct mlx5_vport *vport;
4579 int err = 0;
4580
4581 esw = mlx5_devlink_eswitch_get(port->devlink);
4582 if (IS_ERR(esw))
4583 return PTR_ERR(esw);
4584
4585 if (!mlx5_esw_ipsec_vf_offload_supported(esw->dev)) {
4586 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support IPsec packet");
4587 return -EOPNOTSUPP;
4588 }
4589
4590 vport = mlx5_devlink_port_vport_get(port);
4591
4592 mutex_lock(&esw->state_lock);
4593 if (!vport->enabled) {
4594 err = -EOPNOTSUPP;
4595 goto unlock;
4596 }
4597
4598 *is_enabled = vport->info.ipsec_packet_enabled;
4599 unlock:
4600 mutex_unlock(&esw->state_lock);
4601 return err;
4602 }
4603
mlx5_devlink_port_fn_ipsec_packet_set(struct devlink_port * port,bool enable,struct netlink_ext_ack * extack)4604 int mlx5_devlink_port_fn_ipsec_packet_set(struct devlink_port *port,
4605 bool enable,
4606 struct netlink_ext_ack *extack)
4607 {
4608 struct mlx5_eswitch *esw;
4609 struct mlx5_vport *vport;
4610 u16 vport_num;
4611 int err;
4612
4613 esw = mlx5_devlink_eswitch_get(port->devlink);
4614 if (IS_ERR(esw))
4615 return PTR_ERR(esw);
4616
4617 vport_num = mlx5_esw_devlink_port_index_to_vport_num(port->index);
4618 err = mlx5_esw_ipsec_vf_packet_offload_supported(esw->dev, vport_num);
4619 if (err) {
4620 NL_SET_ERR_MSG_MOD(extack,
4621 "Device doesn't support IPsec packet mode");
4622 return err;
4623 }
4624
4625 vport = mlx5_devlink_port_vport_get(port);
4626 mutex_lock(&esw->state_lock);
4627 if (!vport->enabled) {
4628 err = -EOPNOTSUPP;
4629 NL_SET_ERR_MSG_MOD(extack, "Eswitch vport is disabled");
4630 goto unlock;
4631 }
4632
4633 if (vport->info.ipsec_packet_enabled == enable)
4634 goto unlock;
4635
4636 if (!esw->enabled_ipsec_vf_count && esw->dev->num_ipsec_offloads) {
4637 err = -EBUSY;
4638 goto unlock;
4639 }
4640
4641 err = mlx5_esw_ipsec_vf_packet_offload_set(esw, vport, enable);
4642 if (err) {
4643 NL_SET_ERR_MSG_MOD(extack,
4644 "Failed to set IPsec packet mode");
4645 goto unlock;
4646 }
4647
4648 vport->info.ipsec_packet_enabled = enable;
4649 if (enable)
4650 esw->enabled_ipsec_vf_count++;
4651 else
4652 esw->enabled_ipsec_vf_count--;
4653 unlock:
4654 mutex_unlock(&esw->state_lock);
4655 return err;
4656 }
4657 #endif /* CONFIG_XFRM_OFFLOAD */
4658
4659 int
mlx5_devlink_port_fn_max_io_eqs_get(struct devlink_port * port,u32 * max_io_eqs,struct netlink_ext_ack * extack)4660 mlx5_devlink_port_fn_max_io_eqs_get(struct devlink_port *port, u32 *max_io_eqs,
4661 struct netlink_ext_ack *extack)
4662 {
4663 struct mlx5_vport *vport = mlx5_devlink_port_vport_get(port);
4664 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
4665 u16 vport_num = vport->vport;
4666 struct mlx5_eswitch *esw;
4667 void *query_ctx;
4668 void *hca_caps;
4669 u32 max_eqs;
4670 int err;
4671
4672 esw = mlx5_devlink_eswitch_nocheck_get(port->devlink);
4673 if (!MLX5_CAP_GEN(esw->dev, vhca_resource_manager)) {
4674 NL_SET_ERR_MSG_MOD(extack,
4675 "Device doesn't support VHCA management");
4676 return -EOPNOTSUPP;
4677 }
4678
4679 if (!MLX5_CAP_GEN_2(esw->dev, max_num_eqs_24b)) {
4680 NL_SET_ERR_MSG_MOD(extack,
4681 "Device doesn't support getting the max number of EQs");
4682 return -EOPNOTSUPP;
4683 }
4684
4685 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
4686 if (!query_ctx)
4687 return -ENOMEM;
4688
4689 mutex_lock(&esw->state_lock);
4690 err = mlx5_vport_get_other_func_cap(esw->dev, vport_num, query_ctx,
4691 MLX5_CAP_GENERAL_2);
4692 if (err) {
4693 NL_SET_ERR_MSG_MOD(extack, "Failed getting HCA caps");
4694 goto out;
4695 }
4696
4697 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
4698 max_eqs = MLX5_GET(cmd_hca_cap_2, hca_caps, max_num_eqs_24b);
4699 if (max_eqs < MLX5_ESW_MAX_CTRL_EQS)
4700 *max_io_eqs = 0;
4701 else
4702 *max_io_eqs = max_eqs - MLX5_ESW_MAX_CTRL_EQS;
4703 out:
4704 mutex_unlock(&esw->state_lock);
4705 kfree(query_ctx);
4706 return err;
4707 }
4708
4709 int
mlx5_devlink_port_fn_max_io_eqs_set(struct devlink_port * port,u32 max_io_eqs,struct netlink_ext_ack * extack)4710 mlx5_devlink_port_fn_max_io_eqs_set(struct devlink_port *port, u32 max_io_eqs,
4711 struct netlink_ext_ack *extack)
4712 {
4713 struct mlx5_vport *vport = mlx5_devlink_port_vport_get(port);
4714 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
4715 u16 vport_num = vport->vport;
4716 struct mlx5_eswitch *esw;
4717 void *query_ctx;
4718 void *hca_caps;
4719 u16 max_eqs;
4720 int err;
4721
4722 esw = mlx5_devlink_eswitch_nocheck_get(port->devlink);
4723 if (!MLX5_CAP_GEN(esw->dev, vhca_resource_manager)) {
4724 NL_SET_ERR_MSG_MOD(extack,
4725 "Device doesn't support VHCA management");
4726 return -EOPNOTSUPP;
4727 }
4728
4729 if (!MLX5_CAP_GEN_2(esw->dev, max_num_eqs_24b)) {
4730 NL_SET_ERR_MSG_MOD(extack,
4731 "Device doesn't support changing the max number of EQs");
4732 return -EOPNOTSUPP;
4733 }
4734
4735 if (check_add_overflow(max_io_eqs, MLX5_ESW_MAX_CTRL_EQS, &max_eqs)) {
4736 NL_SET_ERR_MSG_MOD(extack, "Supplied value out of range");
4737 return -EINVAL;
4738 }
4739
4740 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
4741 if (!query_ctx)
4742 return -ENOMEM;
4743
4744 mutex_lock(&esw->state_lock);
4745 err = mlx5_vport_get_other_func_cap(esw->dev, vport_num, query_ctx,
4746 MLX5_CAP_GENERAL_2);
4747 if (err) {
4748 NL_SET_ERR_MSG_MOD(extack, "Failed getting HCA caps");
4749 goto out;
4750 }
4751
4752 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
4753 MLX5_SET(cmd_hca_cap_2, hca_caps, max_num_eqs_24b, max_eqs);
4754
4755 if (mlx5_esw_is_sf_vport(esw, vport_num))
4756 MLX5_SET(cmd_hca_cap_2, hca_caps, sf_eq_usage, 1);
4757
4758 err = mlx5_vport_set_other_func_cap(esw->dev, hca_caps, vport_num,
4759 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2);
4760 if (err)
4761 NL_SET_ERR_MSG_MOD(extack, "Failed setting HCA caps");
4762 vport->max_eqs_set = true;
4763 out:
4764 mutex_unlock(&esw->state_lock);
4765 kfree(query_ctx);
4766 return err;
4767 }
4768
4769 int
mlx5_devlink_port_fn_max_io_eqs_set_sf_default(struct devlink_port * port,struct netlink_ext_ack * extack)4770 mlx5_devlink_port_fn_max_io_eqs_set_sf_default(struct devlink_port *port,
4771 struct netlink_ext_ack *extack)
4772 {
4773 return mlx5_devlink_port_fn_max_io_eqs_set(port,
4774 MLX5_ESW_DEFAULT_SF_COMP_EQS,
4775 extack);
4776 }
4777