1 /*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/etherdevice.h>
34 #include <linux/idr.h>
35 #include <linux/mlx5/driver.h>
36 #include <linux/mlx5/mlx5_ifc.h>
37 #include <linux/mlx5/vport.h>
38 #include <linux/mlx5/fs.h>
39 #include "mlx5_core.h"
40 #include "eswitch.h"
41 #include "esw/indir_table.h"
42 #include "esw/acl/ofld.h"
43 #include "rdma.h"
44 #include "en.h"
45 #include "fs_core.h"
46 #include "lib/mlx5.h"
47 #include "lib/devcom.h"
48 #include "lib/eq.h"
49 #include "lib/fs_chains.h"
50 #include "en_tc.h"
51 #include "en/mapping.h"
52 #include "devlink.h"
53 #include "lag/lag.h"
54 #include "en/tc/post_meter.h"
55
56 /* There are two match-all miss flows, one for unicast dst mac and
57 * one for multicast.
58 */
59 #define MLX5_ESW_MISS_FLOWS (2)
60 #define UPLINK_REP_INDEX 0
61
62 #define MLX5_ESW_VPORT_TBL_SIZE 128
63 #define MLX5_ESW_VPORT_TBL_NUM_GROUPS 4
64
65 #define MLX5_ESW_FT_OFFLOADS_DROP_RULE (1)
66
67 #define MLX5_ESW_MAX_CTRL_EQS 4
68 #define MLX5_ESW_DEFAULT_SF_COMP_EQS 8
69
70 static struct esw_vport_tbl_namespace mlx5_esw_vport_tbl_mirror_ns = {
71 .max_fte = MLX5_ESW_VPORT_TBL_SIZE,
72 .max_num_groups = MLX5_ESW_VPORT_TBL_NUM_GROUPS,
73 .flags = 0,
74 };
75
mlx5_eswitch_get_rep(struct mlx5_eswitch * esw,u16 vport_num)76 static struct mlx5_eswitch_rep *mlx5_eswitch_get_rep(struct mlx5_eswitch *esw,
77 u16 vport_num)
78 {
79 return xa_load(&esw->offloads.vport_reps, vport_num);
80 }
81
82 static void
mlx5_eswitch_set_rule_flow_source(struct mlx5_eswitch * esw,struct mlx5_flow_spec * spec,struct mlx5_esw_flow_attr * attr)83 mlx5_eswitch_set_rule_flow_source(struct mlx5_eswitch *esw,
84 struct mlx5_flow_spec *spec,
85 struct mlx5_esw_flow_attr *attr)
86 {
87 if (!MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source) || !attr || !attr->in_rep)
88 return;
89
90 if (attr->int_port) {
91 spec->flow_context.flow_source = mlx5e_tc_int_port_get_flow_source(attr->int_port);
92
93 return;
94 }
95
96 spec->flow_context.flow_source = (attr->in_rep->vport == MLX5_VPORT_UPLINK) ?
97 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK :
98 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT;
99 }
100
101 /* Actually only the upper 16 bits of reg c0 need to be cleared, but the lower 16 bits
102 * are not needed as well in the following process. So clear them all for simplicity.
103 */
104 void
mlx5_eswitch_clear_rule_source_port(struct mlx5_eswitch * esw,struct mlx5_flow_spec * spec)105 mlx5_eswitch_clear_rule_source_port(struct mlx5_eswitch *esw, struct mlx5_flow_spec *spec)
106 {
107 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
108 void *misc2;
109
110 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
111 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0);
112
113 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
114 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0);
115
116 if (!memchr_inv(misc2, 0, MLX5_ST_SZ_BYTES(fte_match_set_misc2)))
117 spec->match_criteria_enable &= ~MLX5_MATCH_MISC_PARAMETERS_2;
118 }
119 }
120
121 static void
mlx5_eswitch_set_rule_source_port(struct mlx5_eswitch * esw,struct mlx5_flow_spec * spec,struct mlx5_flow_attr * attr,struct mlx5_eswitch * src_esw,u16 vport)122 mlx5_eswitch_set_rule_source_port(struct mlx5_eswitch *esw,
123 struct mlx5_flow_spec *spec,
124 struct mlx5_flow_attr *attr,
125 struct mlx5_eswitch *src_esw,
126 u16 vport)
127 {
128 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
129 u32 metadata;
130 void *misc2;
131 void *misc;
132
133 /* Use metadata matching because vport is not represented by single
134 * VHCA in dual-port RoCE mode, and matching on source vport may fail.
135 */
136 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
137 if (mlx5_esw_indir_table_decap_vport(attr))
138 vport = mlx5_esw_indir_table_decap_vport(attr);
139
140 if (!attr->chain && esw_attr && esw_attr->int_port)
141 metadata =
142 mlx5e_tc_int_port_get_metadata_for_match(esw_attr->int_port);
143 else
144 metadata =
145 mlx5_eswitch_get_vport_metadata_for_match(src_esw, vport);
146
147 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
148 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, metadata);
149
150 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
151 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
152 mlx5_eswitch_get_vport_metadata_mask());
153
154 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
155 } else {
156 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
157 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
158
159 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
160 MLX5_SET(fte_match_set_misc, misc,
161 source_eswitch_owner_vhca_id,
162 MLX5_CAP_GEN(src_esw->dev, vhca_id));
163
164 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
165 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
166 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
167 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
168 source_eswitch_owner_vhca_id);
169
170 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
171 }
172 }
173
174 static int
esw_setup_decap_indir(struct mlx5_eswitch * esw,struct mlx5_flow_attr * attr)175 esw_setup_decap_indir(struct mlx5_eswitch *esw,
176 struct mlx5_flow_attr *attr)
177 {
178 struct mlx5_flow_table *ft;
179
180 if (!(attr->flags & MLX5_ATTR_FLAG_SRC_REWRITE))
181 return -EOPNOTSUPP;
182
183 ft = mlx5_esw_indir_table_get(esw, attr,
184 mlx5_esw_indir_table_decap_vport(attr), true);
185 return PTR_ERR_OR_ZERO(ft);
186 }
187
188 static void
esw_cleanup_decap_indir(struct mlx5_eswitch * esw,struct mlx5_flow_attr * attr)189 esw_cleanup_decap_indir(struct mlx5_eswitch *esw,
190 struct mlx5_flow_attr *attr)
191 {
192 if (mlx5_esw_indir_table_decap_vport(attr))
193 mlx5_esw_indir_table_put(esw,
194 mlx5_esw_indir_table_decap_vport(attr),
195 true);
196 }
197
198 static int
esw_setup_mtu_dest(struct mlx5_flow_destination * dest,struct mlx5e_meter_attr * meter,int i)199 esw_setup_mtu_dest(struct mlx5_flow_destination *dest,
200 struct mlx5e_meter_attr *meter,
201 int i)
202 {
203 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_RANGE;
204 dest[i].range.field = MLX5_FLOW_DEST_RANGE_FIELD_PKT_LEN;
205 dest[i].range.min = 0;
206 dest[i].range.max = meter->params.mtu;
207 dest[i].range.hit_ft = mlx5e_post_meter_get_mtu_true_ft(meter->post_meter);
208 dest[i].range.miss_ft = mlx5e_post_meter_get_mtu_false_ft(meter->post_meter);
209
210 return 0;
211 }
212
213 static int
esw_setup_sampler_dest(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,u32 sampler_id,int i)214 esw_setup_sampler_dest(struct mlx5_flow_destination *dest,
215 struct mlx5_flow_act *flow_act,
216 u32 sampler_id,
217 int i)
218 {
219 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
220 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER;
221 dest[i].sampler_id = sampler_id;
222
223 return 0;
224 }
225
226 static int
esw_setup_ft_dest(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,struct mlx5_eswitch * esw,struct mlx5_flow_attr * attr,int i)227 esw_setup_ft_dest(struct mlx5_flow_destination *dest,
228 struct mlx5_flow_act *flow_act,
229 struct mlx5_eswitch *esw,
230 struct mlx5_flow_attr *attr,
231 int i)
232 {
233 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
234 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
235 dest[i].ft = attr->dest_ft;
236
237 if (mlx5_esw_indir_table_decap_vport(attr))
238 return esw_setup_decap_indir(esw, attr);
239 return 0;
240 }
241
242 static void
esw_setup_accept_dest(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,struct mlx5_fs_chains * chains,int i)243 esw_setup_accept_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
244 struct mlx5_fs_chains *chains, int i)
245 {
246 if (mlx5_chains_ignore_flow_level_supported(chains))
247 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
248 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
249 dest[i].ft = mlx5_chains_get_tc_end_ft(chains);
250 }
251
252 static void
esw_setup_slow_path_dest(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,struct mlx5_eswitch * esw,int i)253 esw_setup_slow_path_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
254 struct mlx5_eswitch *esw, int i)
255 {
256 if (MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ignore_flow_level))
257 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
258 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
259 dest[i].ft = mlx5_eswitch_get_slow_fdb(esw);
260 }
261
262 static int
esw_setup_chain_dest(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,struct mlx5_fs_chains * chains,u32 chain,u32 prio,u32 level,int i)263 esw_setup_chain_dest(struct mlx5_flow_destination *dest,
264 struct mlx5_flow_act *flow_act,
265 struct mlx5_fs_chains *chains,
266 u32 chain, u32 prio, u32 level,
267 int i)
268 {
269 struct mlx5_flow_table *ft;
270
271 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
272 ft = mlx5_chains_get_table(chains, chain, prio, level);
273 if (IS_ERR(ft))
274 return PTR_ERR(ft);
275
276 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
277 dest[i].ft = ft;
278 return 0;
279 }
280
esw_put_dest_tables_loop(struct mlx5_eswitch * esw,struct mlx5_flow_attr * attr,int from,int to)281 static void esw_put_dest_tables_loop(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr,
282 int from, int to)
283 {
284 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
285 struct mlx5_fs_chains *chains = esw_chains(esw);
286 int i;
287
288 for (i = from; i < to; i++)
289 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
290 mlx5_chains_put_table(chains, 0, 1, 0);
291 else if (mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].vport,
292 esw_attr->dests[i].mdev))
293 mlx5_esw_indir_table_put(esw, esw_attr->dests[i].vport, false);
294 }
295
296 static bool
esw_is_chain_src_port_rewrite(struct mlx5_eswitch * esw,struct mlx5_esw_flow_attr * esw_attr)297 esw_is_chain_src_port_rewrite(struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr)
298 {
299 int i;
300
301 for (i = esw_attr->split_count; i < esw_attr->out_count; i++)
302 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
303 return true;
304 return false;
305 }
306
307 static int
esw_setup_chain_src_port_rewrite(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,struct mlx5_eswitch * esw,struct mlx5_fs_chains * chains,struct mlx5_flow_attr * attr,int * i)308 esw_setup_chain_src_port_rewrite(struct mlx5_flow_destination *dest,
309 struct mlx5_flow_act *flow_act,
310 struct mlx5_eswitch *esw,
311 struct mlx5_fs_chains *chains,
312 struct mlx5_flow_attr *attr,
313 int *i)
314 {
315 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
316 int err;
317
318 if (!(attr->flags & MLX5_ATTR_FLAG_SRC_REWRITE))
319 return -EOPNOTSUPP;
320
321 /* flow steering cannot handle more than one dest with the same ft
322 * in a single flow
323 */
324 if (esw_attr->out_count - esw_attr->split_count > 1)
325 return -EOPNOTSUPP;
326
327 err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain, 1, 0, *i);
328 if (err)
329 return err;
330
331 if (esw_attr->dests[esw_attr->split_count].pkt_reformat) {
332 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
333 flow_act->pkt_reformat = esw_attr->dests[esw_attr->split_count].pkt_reformat;
334 }
335 (*i)++;
336
337 return 0;
338 }
339
esw_cleanup_chain_src_port_rewrite(struct mlx5_eswitch * esw,struct mlx5_flow_attr * attr)340 static void esw_cleanup_chain_src_port_rewrite(struct mlx5_eswitch *esw,
341 struct mlx5_flow_attr *attr)
342 {
343 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
344
345 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count);
346 }
347
348 static bool
esw_is_indir_table(struct mlx5_eswitch * esw,struct mlx5_flow_attr * attr)349 esw_is_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
350 {
351 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
352 bool result = false;
353 int i;
354
355 /* Indirect table is supported only for flows with in_port uplink
356 * and the destination is vport on the same eswitch as the uplink,
357 * return false in case at least one of destinations doesn't meet
358 * this criteria.
359 */
360 for (i = esw_attr->split_count; i < esw_attr->out_count; i++) {
361 if (esw_attr->dests[i].vport_valid &&
362 mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].vport,
363 esw_attr->dests[i].mdev)) {
364 result = true;
365 } else {
366 result = false;
367 break;
368 }
369 }
370 return result;
371 }
372
373 static int
esw_setup_indir_table(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,struct mlx5_eswitch * esw,struct mlx5_flow_attr * attr,int * i)374 esw_setup_indir_table(struct mlx5_flow_destination *dest,
375 struct mlx5_flow_act *flow_act,
376 struct mlx5_eswitch *esw,
377 struct mlx5_flow_attr *attr,
378 int *i)
379 {
380 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
381 int j, err;
382
383 if (!(attr->flags & MLX5_ATTR_FLAG_SRC_REWRITE))
384 return -EOPNOTSUPP;
385
386 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, (*i)++) {
387 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
388 dest[*i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
389
390 dest[*i].ft = mlx5_esw_indir_table_get(esw, attr,
391 esw_attr->dests[j].vport, false);
392 if (IS_ERR(dest[*i].ft)) {
393 err = PTR_ERR(dest[*i].ft);
394 goto err_indir_tbl_get;
395 }
396 }
397
398 if (mlx5_esw_indir_table_decap_vport(attr)) {
399 err = esw_setup_decap_indir(esw, attr);
400 if (err)
401 goto err_indir_tbl_get;
402 }
403
404 return 0;
405
406 err_indir_tbl_get:
407 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, j);
408 return err;
409 }
410
esw_cleanup_indir_table(struct mlx5_eswitch * esw,struct mlx5_flow_attr * attr)411 static void esw_cleanup_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
412 {
413 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
414
415 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count);
416 esw_cleanup_decap_indir(esw, attr);
417 }
418
419 static void
esw_cleanup_chain_dest(struct mlx5_fs_chains * chains,u32 chain,u32 prio,u32 level)420 esw_cleanup_chain_dest(struct mlx5_fs_chains *chains, u32 chain, u32 prio, u32 level)
421 {
422 mlx5_chains_put_table(chains, chain, prio, level);
423 }
424
esw_same_vhca_id(struct mlx5_core_dev * mdev1,struct mlx5_core_dev * mdev2)425 static bool esw_same_vhca_id(struct mlx5_core_dev *mdev1, struct mlx5_core_dev *mdev2)
426 {
427 return MLX5_CAP_GEN(mdev1, vhca_id) == MLX5_CAP_GEN(mdev2, vhca_id);
428 }
429
esw_setup_uplink_fwd_ipsec_needed(struct mlx5_eswitch * esw,struct mlx5_esw_flow_attr * esw_attr,int attr_idx)430 static bool esw_setup_uplink_fwd_ipsec_needed(struct mlx5_eswitch *esw,
431 struct mlx5_esw_flow_attr *esw_attr,
432 int attr_idx)
433 {
434 if (esw->offloads.ft_ipsec_tx_pol &&
435 esw_attr->dests[attr_idx].vport_valid &&
436 esw_attr->dests[attr_idx].vport == MLX5_VPORT_UPLINK &&
437 /* To be aligned with software, encryption is needed only for tunnel device */
438 (esw_attr->dests[attr_idx].flags & MLX5_ESW_DEST_ENCAP_VALID) &&
439 esw_attr->dests[attr_idx].vport != esw_attr->in_rep->vport &&
440 esw_same_vhca_id(esw_attr->dests[attr_idx].mdev, esw->dev))
441 return true;
442
443 return false;
444 }
445
esw_flow_dests_fwd_ipsec_check(struct mlx5_eswitch * esw,struct mlx5_esw_flow_attr * esw_attr)446 static bool esw_flow_dests_fwd_ipsec_check(struct mlx5_eswitch *esw,
447 struct mlx5_esw_flow_attr *esw_attr)
448 {
449 int i;
450
451 if (!esw->offloads.ft_ipsec_tx_pol)
452 return true;
453
454 for (i = 0; i < esw_attr->split_count; i++)
455 if (esw_setup_uplink_fwd_ipsec_needed(esw, esw_attr, i))
456 return false;
457
458 for (i = esw_attr->split_count; i < esw_attr->out_count; i++)
459 if (esw_setup_uplink_fwd_ipsec_needed(esw, esw_attr, i) &&
460 (esw_attr->out_count - esw_attr->split_count > 1))
461 return false;
462
463 return true;
464 }
465
466 static void
esw_setup_dest_fwd_vport(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,struct mlx5_eswitch * esw,struct mlx5_esw_flow_attr * esw_attr,int attr_idx,int dest_idx,bool pkt_reformat)467 esw_setup_dest_fwd_vport(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
468 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
469 int attr_idx, int dest_idx, bool pkt_reformat)
470 {
471 dest[dest_idx].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
472 dest[dest_idx].vport.num = esw_attr->dests[attr_idx].vport;
473 if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
474 dest[dest_idx].vport.vhca_id =
475 MLX5_CAP_GEN(esw_attr->dests[attr_idx].mdev, vhca_id);
476 dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
477 if (dest[dest_idx].vport.num == MLX5_VPORT_UPLINK &&
478 mlx5_lag_is_mpesw(esw->dev))
479 dest[dest_idx].type = MLX5_FLOW_DESTINATION_TYPE_UPLINK;
480 }
481 if (esw_attr->dests[attr_idx].flags & MLX5_ESW_DEST_ENCAP_VALID) {
482 if (pkt_reformat) {
483 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
484 flow_act->pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
485 }
486 dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
487 dest[dest_idx].vport.pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
488 }
489 }
490
491 static void
esw_setup_dest_fwd_ipsec(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,struct mlx5_eswitch * esw,struct mlx5_esw_flow_attr * esw_attr,int attr_idx,int dest_idx,bool pkt_reformat)492 esw_setup_dest_fwd_ipsec(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
493 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
494 int attr_idx, int dest_idx, bool pkt_reformat)
495 {
496 dest[dest_idx].ft = esw->offloads.ft_ipsec_tx_pol;
497 dest[dest_idx].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
498 if (pkt_reformat &&
499 esw_attr->dests[attr_idx].flags & MLX5_ESW_DEST_ENCAP_VALID) {
500 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
501 flow_act->pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
502 }
503 }
504
505 static void
esw_setup_vport_dest(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,struct mlx5_eswitch * esw,struct mlx5_esw_flow_attr * esw_attr,int attr_idx,int dest_idx,bool pkt_reformat)506 esw_setup_vport_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
507 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
508 int attr_idx, int dest_idx, bool pkt_reformat)
509 {
510 if (esw_setup_uplink_fwd_ipsec_needed(esw, esw_attr, attr_idx))
511 esw_setup_dest_fwd_ipsec(dest, flow_act, esw, esw_attr,
512 attr_idx, dest_idx, pkt_reformat);
513 else
514 esw_setup_dest_fwd_vport(dest, flow_act, esw, esw_attr,
515 attr_idx, dest_idx, pkt_reformat);
516 }
517
518 static int
esw_setup_vport_dests(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,struct mlx5_eswitch * esw,struct mlx5_esw_flow_attr * esw_attr,int i)519 esw_setup_vport_dests(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
520 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
521 int i)
522 {
523 int j;
524
525 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, i++)
526 esw_setup_vport_dest(dest, flow_act, esw, esw_attr, j, i, true);
527 return i;
528 }
529
530 static bool
esw_src_port_rewrite_supported(struct mlx5_eswitch * esw)531 esw_src_port_rewrite_supported(struct mlx5_eswitch *esw)
532 {
533 return MLX5_CAP_GEN(esw->dev, reg_c_preserve) &&
534 mlx5_eswitch_vport_match_metadata_enabled(esw) &&
535 MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ignore_flow_level);
536 }
537
538 static bool
esw_dests_to_int_external(struct mlx5_flow_destination * dests,int max_dest)539 esw_dests_to_int_external(struct mlx5_flow_destination *dests, int max_dest)
540 {
541 bool internal_dest = false, external_dest = false;
542 int i;
543
544 for (i = 0; i < max_dest; i++) {
545 if (dests[i].type != MLX5_FLOW_DESTINATION_TYPE_VPORT &&
546 dests[i].type != MLX5_FLOW_DESTINATION_TYPE_UPLINK)
547 continue;
548
549 /* Uplink dest is external, but considered as internal
550 * if there is reformat because firmware uses LB+hairpin to support it.
551 */
552 if (dests[i].vport.num == MLX5_VPORT_UPLINK &&
553 !(dests[i].vport.flags & MLX5_FLOW_DEST_VPORT_REFORMAT_ID))
554 external_dest = true;
555 else
556 internal_dest = true;
557
558 if (internal_dest && external_dest)
559 return true;
560 }
561
562 return false;
563 }
564
565 static int
esw_setup_dests(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,struct mlx5_eswitch * esw,struct mlx5_flow_attr * attr,struct mlx5_flow_spec * spec,int * i)566 esw_setup_dests(struct mlx5_flow_destination *dest,
567 struct mlx5_flow_act *flow_act,
568 struct mlx5_eswitch *esw,
569 struct mlx5_flow_attr *attr,
570 struct mlx5_flow_spec *spec,
571 int *i)
572 {
573 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
574 struct mlx5_fs_chains *chains = esw_chains(esw);
575 int err = 0;
576
577 if (!mlx5_eswitch_termtbl_required(esw, attr, flow_act, spec) &&
578 esw_src_port_rewrite_supported(esw))
579 attr->flags |= MLX5_ATTR_FLAG_SRC_REWRITE;
580
581 if (attr->flags & MLX5_ATTR_FLAG_SLOW_PATH) {
582 esw_setup_slow_path_dest(dest, flow_act, esw, *i);
583 (*i)++;
584 goto out;
585 }
586
587 if (attr->flags & MLX5_ATTR_FLAG_SAMPLE) {
588 esw_setup_sampler_dest(dest, flow_act, attr->sample_attr.sampler_id, *i);
589 (*i)++;
590 } else if (attr->flags & MLX5_ATTR_FLAG_ACCEPT) {
591 esw_setup_accept_dest(dest, flow_act, chains, *i);
592 (*i)++;
593 } else if (attr->flags & MLX5_ATTR_FLAG_MTU) {
594 err = esw_setup_mtu_dest(dest, &attr->meter_attr, *i);
595 (*i)++;
596 } else if (esw_is_indir_table(esw, attr)) {
597 err = esw_setup_indir_table(dest, flow_act, esw, attr, i);
598 } else if (esw_is_chain_src_port_rewrite(esw, esw_attr)) {
599 err = esw_setup_chain_src_port_rewrite(dest, flow_act, esw, chains, attr, i);
600 } else {
601 *i = esw_setup_vport_dests(dest, flow_act, esw, esw_attr, *i);
602
603 if (attr->dest_ft) {
604 err = esw_setup_ft_dest(dest, flow_act, esw, attr, *i);
605 (*i)++;
606 } else if (attr->dest_chain) {
607 err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain,
608 1, 0, *i);
609 (*i)++;
610 }
611 }
612
613 if (attr->extra_split_ft) {
614 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
615 dest[*i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
616 dest[*i].ft = attr->extra_split_ft;
617 (*i)++;
618 }
619
620 out:
621 return err;
622 }
623
624 static void
esw_cleanup_dests(struct mlx5_eswitch * esw,struct mlx5_flow_attr * attr)625 esw_cleanup_dests(struct mlx5_eswitch *esw,
626 struct mlx5_flow_attr *attr)
627 {
628 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
629 struct mlx5_fs_chains *chains = esw_chains(esw);
630
631 if (attr->dest_ft) {
632 esw_cleanup_decap_indir(esw, attr);
633 } else if (!mlx5e_tc_attr_flags_skip(attr->flags)) {
634 if (attr->dest_chain)
635 esw_cleanup_chain_dest(chains, attr->dest_chain, 1, 0);
636 else if (esw_is_indir_table(esw, attr))
637 esw_cleanup_indir_table(esw, attr);
638 else if (esw_is_chain_src_port_rewrite(esw, esw_attr))
639 esw_cleanup_chain_src_port_rewrite(esw, attr);
640 }
641 }
642
643 static void
esw_setup_meter(struct mlx5_flow_attr * attr,struct mlx5_flow_act * flow_act)644 esw_setup_meter(struct mlx5_flow_attr *attr, struct mlx5_flow_act *flow_act)
645 {
646 struct mlx5e_flow_meter_handle *meter;
647
648 meter = attr->meter_attr.meter;
649 flow_act->exe_aso.type = attr->exe_aso_type;
650 flow_act->exe_aso.object_id = meter->obj_id;
651 flow_act->exe_aso.base_id = mlx5e_flow_meter_get_base_id(meter);
652 flow_act->exe_aso.flow_meter.meter_idx = meter->idx;
653 flow_act->exe_aso.flow_meter.init_color = MLX5_FLOW_METER_COLOR_GREEN;
654 /* use metadata reg 5 for packet color */
655 flow_act->exe_aso.return_reg_id = 5;
656 }
657
658 struct mlx5_flow_handle *
mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch * esw,struct mlx5_flow_spec * spec,struct mlx5_flow_attr * attr)659 mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
660 struct mlx5_flow_spec *spec,
661 struct mlx5_flow_attr *attr)
662 {
663 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
664 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
665 struct mlx5_fs_chains *chains = esw_chains(esw);
666 bool split = !!(esw_attr->split_count);
667 struct mlx5_vport_tbl_attr fwd_attr;
668 struct mlx5_flow_destination *dest;
669 struct mlx5_flow_handle *rule;
670 struct mlx5_flow_table *fdb;
671 int i = 0;
672
673 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
674 return ERR_PTR(-EOPNOTSUPP);
675
676 if (!mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
677 return ERR_PTR(-EOPNOTSUPP);
678
679 if (!esw_flow_dests_fwd_ipsec_check(esw, esw_attr))
680 return ERR_PTR(-EOPNOTSUPP);
681
682 dest = kcalloc(MLX5_MAX_FLOW_FWD_VPORTS + 1, sizeof(*dest), GFP_KERNEL);
683 if (!dest)
684 return ERR_PTR(-ENOMEM);
685
686 flow_act.action = attr->action;
687
688 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {
689 flow_act.vlan[0].ethtype = ntohs(esw_attr->vlan_proto[0]);
690 flow_act.vlan[0].vid = esw_attr->vlan_vid[0];
691 flow_act.vlan[0].prio = esw_attr->vlan_prio[0];
692 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2) {
693 flow_act.vlan[1].ethtype = ntohs(esw_attr->vlan_proto[1]);
694 flow_act.vlan[1].vid = esw_attr->vlan_vid[1];
695 flow_act.vlan[1].prio = esw_attr->vlan_prio[1];
696 }
697 }
698
699 mlx5_eswitch_set_rule_flow_source(esw, spec, esw_attr);
700
701 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
702 int err;
703
704 err = esw_setup_dests(dest, &flow_act, esw, attr, spec, &i);
705 if (err) {
706 rule = ERR_PTR(err);
707 goto err_create_goto_table;
708 }
709
710 /* Header rewrite with combined wire+loopback in FDB is not allowed */
711 if ((flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) &&
712 esw_dests_to_int_external(dest, i)) {
713 esw_warn(esw->dev,
714 "FDB: Header rewrite with forwarding to both internal and external dests is not allowed\n");
715 rule = ERR_PTR(-EINVAL);
716 goto err_esw_get;
717 }
718 }
719
720 if (esw_attr->decap_pkt_reformat)
721 flow_act.pkt_reformat = esw_attr->decap_pkt_reformat;
722
723 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
724 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
725 dest[i].counter = attr->counter;
726 i++;
727 }
728
729 if (attr->outer_match_level != MLX5_MATCH_NONE)
730 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
731 if (attr->inner_match_level != MLX5_MATCH_NONE)
732 spec->match_criteria_enable |= MLX5_MATCH_INNER_HEADERS;
733
734 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
735 flow_act.modify_hdr = attr->modify_hdr;
736
737 if ((flow_act.action & MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO) &&
738 attr->exe_aso_type == MLX5_EXE_ASO_FLOW_METER)
739 esw_setup_meter(attr, &flow_act);
740
741 if (split) {
742 fwd_attr.chain = attr->chain;
743 fwd_attr.prio = attr->prio;
744 fwd_attr.vport = esw_attr->in_rep->vport;
745 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
746
747 fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr);
748 } else {
749 if (attr->chain || attr->prio)
750 fdb = mlx5_chains_get_table(chains, attr->chain,
751 attr->prio, 0);
752 else
753 fdb = attr->ft;
754
755 if (!(attr->flags & MLX5_ATTR_FLAG_NO_IN_PORT))
756 mlx5_eswitch_set_rule_source_port(esw, spec, attr,
757 esw_attr->in_mdev->priv.eswitch,
758 esw_attr->in_rep->vport);
759 }
760 if (IS_ERR(fdb)) {
761 rule = ERR_CAST(fdb);
762 goto err_esw_get;
763 }
764
765 if (!i) {
766 kfree(dest);
767 dest = NULL;
768 }
769
770 if (mlx5_eswitch_termtbl_required(esw, attr, &flow_act, spec))
771 rule = mlx5_eswitch_add_termtbl_rule(esw, fdb, spec, esw_attr,
772 &flow_act, dest, i);
773 else
774 rule = mlx5_add_flow_rules(fdb, spec, &flow_act, dest, i);
775 if (IS_ERR(rule))
776 goto err_add_rule;
777 else
778 atomic64_inc(&esw->offloads.num_flows);
779
780 kfree(dest);
781 return rule;
782
783 err_add_rule:
784 if (split)
785 mlx5_esw_vporttbl_put(esw, &fwd_attr);
786 else if (attr->chain || attr->prio)
787 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
788 err_esw_get:
789 esw_cleanup_dests(esw, attr);
790 err_create_goto_table:
791 kfree(dest);
792 return rule;
793 }
794
795 struct mlx5_flow_handle *
mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch * esw,struct mlx5_flow_spec * spec,struct mlx5_flow_attr * attr)796 mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
797 struct mlx5_flow_spec *spec,
798 struct mlx5_flow_attr *attr)
799 {
800 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
801 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
802 struct mlx5_fs_chains *chains = esw_chains(esw);
803 struct mlx5_vport_tbl_attr fwd_attr;
804 struct mlx5_flow_destination *dest;
805 struct mlx5_flow_table *fast_fdb;
806 struct mlx5_flow_table *fwd_fdb;
807 struct mlx5_flow_handle *rule;
808 int i, err = 0;
809
810 dest = kcalloc(MLX5_MAX_FLOW_FWD_VPORTS + 1, sizeof(*dest), GFP_KERNEL);
811 if (!dest)
812 return ERR_PTR(-ENOMEM);
813
814 fast_fdb = mlx5_chains_get_table(chains, attr->chain, attr->prio, 0);
815 if (IS_ERR(fast_fdb)) {
816 rule = ERR_CAST(fast_fdb);
817 goto err_get_fast;
818 }
819
820 fwd_attr.chain = attr->chain;
821 fwd_attr.prio = attr->prio;
822 fwd_attr.vport = esw_attr->in_rep->vport;
823 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
824 fwd_fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr);
825 if (IS_ERR(fwd_fdb)) {
826 rule = ERR_CAST(fwd_fdb);
827 goto err_get_fwd;
828 }
829
830 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
831 for (i = 0; i < esw_attr->split_count; i++) {
832 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
833 /* Source port rewrite (forward to ovs internal port or statck device) isn't
834 * supported in the rule of split action.
835 */
836 err = -EOPNOTSUPP;
837 else
838 esw_setup_vport_dest(dest, &flow_act, esw, esw_attr, i, i, false);
839
840 if (err) {
841 rule = ERR_PTR(err);
842 goto err_chain_src_rewrite;
843 }
844 }
845 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
846 dest[i].ft = fwd_fdb;
847 i++;
848
849 mlx5_eswitch_set_rule_source_port(esw, spec, attr,
850 esw_attr->in_mdev->priv.eswitch,
851 esw_attr->in_rep->vport);
852
853 if (attr->outer_match_level != MLX5_MATCH_NONE)
854 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
855
856 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
857 rule = mlx5_add_flow_rules(fast_fdb, spec, &flow_act, dest, i);
858
859 if (IS_ERR(rule)) {
860 i = esw_attr->split_count;
861 goto err_chain_src_rewrite;
862 }
863
864 atomic64_inc(&esw->offloads.num_flows);
865
866 kfree(dest);
867 return rule;
868 err_chain_src_rewrite:
869 mlx5_esw_vporttbl_put(esw, &fwd_attr);
870 err_get_fwd:
871 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
872 err_get_fast:
873 kfree(dest);
874 return rule;
875 }
876
877 static void
__mlx5_eswitch_del_rule(struct mlx5_eswitch * esw,struct mlx5_flow_handle * rule,struct mlx5_flow_attr * attr,bool fwd_rule)878 __mlx5_eswitch_del_rule(struct mlx5_eswitch *esw,
879 struct mlx5_flow_handle *rule,
880 struct mlx5_flow_attr *attr,
881 bool fwd_rule)
882 {
883 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
884 struct mlx5_fs_chains *chains = esw_chains(esw);
885 bool split = (esw_attr->split_count > 0);
886 struct mlx5_vport_tbl_attr fwd_attr;
887 int i;
888
889 mlx5_del_flow_rules(rule);
890
891 if (!mlx5e_tc_attr_flags_skip(attr->flags)) {
892 /* unref the term table */
893 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
894 if (esw_attr->dests[i].termtbl)
895 mlx5_eswitch_termtbl_put(esw, esw_attr->dests[i].termtbl);
896 }
897 }
898
899 atomic64_dec(&esw->offloads.num_flows);
900
901 if (fwd_rule || split) {
902 fwd_attr.chain = attr->chain;
903 fwd_attr.prio = attr->prio;
904 fwd_attr.vport = esw_attr->in_rep->vport;
905 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
906 }
907
908 if (fwd_rule) {
909 mlx5_esw_vporttbl_put(esw, &fwd_attr);
910 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
911 } else {
912 if (split)
913 mlx5_esw_vporttbl_put(esw, &fwd_attr);
914 else if (attr->chain || attr->prio)
915 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
916 esw_cleanup_dests(esw, attr);
917 }
918 }
919
920 void
mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch * esw,struct mlx5_flow_handle * rule,struct mlx5_flow_attr * attr)921 mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
922 struct mlx5_flow_handle *rule,
923 struct mlx5_flow_attr *attr)
924 {
925 __mlx5_eswitch_del_rule(esw, rule, attr, false);
926 }
927
928 void
mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch * esw,struct mlx5_flow_handle * rule,struct mlx5_flow_attr * attr)929 mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
930 struct mlx5_flow_handle *rule,
931 struct mlx5_flow_attr *attr)
932 {
933 __mlx5_eswitch_del_rule(esw, rule, attr, true);
934 }
935
936 struct mlx5_flow_handle *
mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch * on_esw,struct mlx5_eswitch * from_esw,struct mlx5_eswitch_rep * rep,u32 sqn)937 mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *on_esw,
938 struct mlx5_eswitch *from_esw,
939 struct mlx5_eswitch_rep *rep,
940 u32 sqn)
941 {
942 struct mlx5_flow_act flow_act = {0};
943 struct mlx5_flow_destination dest = {};
944 struct mlx5_flow_handle *flow_rule;
945 struct mlx5_flow_spec *spec;
946 void *misc;
947 u16 vport;
948
949 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
950 if (!spec) {
951 flow_rule = ERR_PTR(-ENOMEM);
952 goto out;
953 }
954
955 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
956 MLX5_SET(fte_match_set_misc, misc, source_sqn, sqn);
957
958 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
959 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_sqn);
960
961 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
962
963 /* source vport is the esw manager */
964 vport = from_esw->manager_vport;
965
966 if (mlx5_eswitch_vport_match_metadata_enabled(on_esw)) {
967 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
968 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
969 mlx5_eswitch_get_vport_metadata_for_match(from_esw, vport));
970
971 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
972 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
973 mlx5_eswitch_get_vport_metadata_mask());
974
975 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
976 } else {
977 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
978 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
979
980 if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch))
981 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
982 MLX5_CAP_GEN(from_esw->dev, vhca_id));
983
984 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
985 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
986
987 if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch))
988 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
989 source_eswitch_owner_vhca_id);
990
991 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
992 }
993
994 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
995 dest.vport.num = rep->vport;
996 dest.vport.vhca_id = MLX5_CAP_GEN(rep->esw->dev, vhca_id);
997 dest.vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
998 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
999
1000 if (rep->vport == MLX5_VPORT_UPLINK &&
1001 on_esw == from_esw && on_esw->offloads.ft_ipsec_tx_pol) {
1002 dest.ft = on_esw->offloads.ft_ipsec_tx_pol;
1003 flow_act.flags = FLOW_ACT_IGNORE_FLOW_LEVEL;
1004 dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1005 } else {
1006 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
1007 dest.vport.num = rep->vport;
1008 dest.vport.vhca_id = MLX5_CAP_GEN(rep->esw->dev, vhca_id);
1009 dest.vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
1010 }
1011
1012 if (MLX5_CAP_ESW_FLOWTABLE(on_esw->dev, flow_source) &&
1013 rep->vport == MLX5_VPORT_UPLINK)
1014 spec->flow_context.flow_source = MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT;
1015
1016 flow_rule = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(on_esw),
1017 spec, &flow_act, &dest, 1);
1018 if (IS_ERR(flow_rule))
1019 esw_warn(on_esw->dev, "FDB: Failed to add send to vport rule err %pe\n",
1020 flow_rule);
1021 out:
1022 kvfree(spec);
1023 return flow_rule;
1024 }
1025 EXPORT_SYMBOL(mlx5_eswitch_add_send_to_vport_rule);
1026
mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle * rule)1027 void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule)
1028 {
1029 mlx5_del_flow_rules(rule);
1030 }
1031
mlx5_eswitch_del_send_to_vport_meta_rule(struct mlx5_flow_handle * rule)1032 void mlx5_eswitch_del_send_to_vport_meta_rule(struct mlx5_flow_handle *rule)
1033 {
1034 if (rule)
1035 mlx5_del_flow_rules(rule);
1036 }
1037
1038 struct mlx5_flow_handle *
mlx5_eswitch_add_send_to_vport_meta_rule(struct mlx5_eswitch * esw,u16 vport_num)1039 mlx5_eswitch_add_send_to_vport_meta_rule(struct mlx5_eswitch *esw, u16 vport_num)
1040 {
1041 struct mlx5_flow_destination dest = {};
1042 struct mlx5_flow_act flow_act = {0};
1043 struct mlx5_flow_handle *flow_rule;
1044 struct mlx5_flow_spec *spec;
1045
1046 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1047 if (!spec)
1048 return ERR_PTR(-ENOMEM);
1049
1050 MLX5_SET(fte_match_param, spec->match_criteria,
1051 misc_parameters_2.metadata_reg_c_0, mlx5_eswitch_get_vport_metadata_mask());
1052 MLX5_SET(fte_match_param, spec->match_criteria,
1053 misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK);
1054 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_1,
1055 ESW_TUN_SLOW_TABLE_GOTO_VPORT_MARK);
1056
1057 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1058 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
1059 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1060
1061 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_0,
1062 mlx5_eswitch_get_vport_metadata_for_match(esw, vport_num));
1063 dest.vport.num = vport_num;
1064
1065 flow_rule = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
1066 spec, &flow_act, &dest, 1);
1067 if (IS_ERR(flow_rule))
1068 esw_warn(esw->dev, "FDB: Failed to add send to vport meta rule vport %d, err %pe\n",
1069 vport_num, flow_rule);
1070
1071 kvfree(spec);
1072 return flow_rule;
1073 }
1074
mlx5_eswitch_reg_c1_loopback_supported(struct mlx5_eswitch * esw)1075 static bool mlx5_eswitch_reg_c1_loopback_supported(struct mlx5_eswitch *esw)
1076 {
1077 return MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
1078 MLX5_FDB_TO_VPORT_REG_C_1;
1079 }
1080
esw_set_passing_vport_metadata(struct mlx5_eswitch * esw,bool enable)1081 static int esw_set_passing_vport_metadata(struct mlx5_eswitch *esw, bool enable)
1082 {
1083 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {};
1084 u32 min[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {};
1085 u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)] = {};
1086 u8 curr, wanted;
1087 int err;
1088
1089 if (!mlx5_eswitch_reg_c1_loopback_supported(esw) &&
1090 !mlx5_eswitch_vport_match_metadata_enabled(esw))
1091 return 0;
1092
1093 MLX5_SET(query_esw_vport_context_in, in, opcode,
1094 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT);
1095 err = mlx5_cmd_exec_inout(esw->dev, query_esw_vport_context, in, out);
1096 if (err)
1097 return err;
1098
1099 curr = MLX5_GET(query_esw_vport_context_out, out,
1100 esw_vport_context.fdb_to_vport_reg_c_id);
1101 wanted = MLX5_FDB_TO_VPORT_REG_C_0;
1102 if (mlx5_eswitch_reg_c1_loopback_supported(esw))
1103 wanted |= MLX5_FDB_TO_VPORT_REG_C_1;
1104
1105 if (enable)
1106 curr |= wanted;
1107 else
1108 curr &= ~wanted;
1109
1110 MLX5_SET(modify_esw_vport_context_in, min,
1111 esw_vport_context.fdb_to_vport_reg_c_id, curr);
1112 MLX5_SET(modify_esw_vport_context_in, min,
1113 field_select.fdb_to_vport_reg_c_id, 1);
1114
1115 err = mlx5_eswitch_modify_esw_vport_context(esw->dev, 0, false, min);
1116 if (!err) {
1117 if (enable && (curr & MLX5_FDB_TO_VPORT_REG_C_1))
1118 esw->flags |= MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
1119 else
1120 esw->flags &= ~MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
1121 }
1122
1123 return err;
1124 }
1125
peer_miss_rules_setup(struct mlx5_eswitch * esw,struct mlx5_core_dev * peer_dev,struct mlx5_flow_spec * spec,struct mlx5_flow_destination * dest)1126 static void peer_miss_rules_setup(struct mlx5_eswitch *esw,
1127 struct mlx5_core_dev *peer_dev,
1128 struct mlx5_flow_spec *spec,
1129 struct mlx5_flow_destination *dest)
1130 {
1131 void *misc;
1132
1133 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1134 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1135 misc_parameters_2);
1136 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1137 mlx5_eswitch_get_vport_metadata_mask());
1138
1139 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1140 } else {
1141 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1142 misc_parameters);
1143
1144 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
1145 MLX5_CAP_GEN(peer_dev, vhca_id));
1146
1147 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1148
1149 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1150 misc_parameters);
1151 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1152 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
1153 source_eswitch_owner_vhca_id);
1154 }
1155
1156 dest->type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
1157 dest->vport.num = peer_dev->priv.eswitch->manager_vport;
1158 dest->vport.vhca_id = MLX5_CAP_GEN(peer_dev, vhca_id);
1159 dest->vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
1160 }
1161
esw_set_peer_miss_rule_source_port(struct mlx5_eswitch * esw,struct mlx5_eswitch * peer_esw,struct mlx5_flow_spec * spec,u16 vport)1162 static void esw_set_peer_miss_rule_source_port(struct mlx5_eswitch *esw,
1163 struct mlx5_eswitch *peer_esw,
1164 struct mlx5_flow_spec *spec,
1165 u16 vport)
1166 {
1167 void *misc;
1168
1169 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1170 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1171 misc_parameters_2);
1172 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1173 mlx5_eswitch_get_vport_metadata_for_match(peer_esw,
1174 vport));
1175 } else {
1176 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1177 misc_parameters);
1178 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1179 }
1180 }
1181
esw_add_fdb_peer_miss_rules(struct mlx5_eswitch * esw,struct mlx5_core_dev * peer_dev)1182 static int esw_add_fdb_peer_miss_rules(struct mlx5_eswitch *esw,
1183 struct mlx5_core_dev *peer_dev)
1184 {
1185 struct mlx5_eswitch *peer_esw = peer_dev->priv.eswitch;
1186 struct mlx5_flow_destination dest = {};
1187 struct mlx5_flow_act flow_act = {0};
1188 struct mlx5_flow_handle **flows;
1189 struct mlx5_flow_handle *flow;
1190 struct mlx5_vport *peer_vport;
1191 struct mlx5_flow_spec *spec;
1192 int err, pfindex;
1193 unsigned long i;
1194 void *misc;
1195
1196 if (!MLX5_VPORT_MANAGER(peer_dev) &&
1197 !mlx5_core_is_ecpf_esw_manager(peer_dev))
1198 return 0;
1199
1200 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1201 if (!spec)
1202 return -ENOMEM;
1203
1204 peer_miss_rules_setup(esw, peer_dev, spec, &dest);
1205
1206 flows = kvcalloc(peer_esw->total_vports, sizeof(*flows), GFP_KERNEL);
1207 if (!flows) {
1208 err = -ENOMEM;
1209 goto alloc_flows_err;
1210 }
1211
1212 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1213 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1214 misc_parameters);
1215
1216 if (mlx5_core_is_ecpf_esw_manager(peer_dev) &&
1217 mlx5_esw_host_functions_enabled(peer_dev)) {
1218 peer_vport = mlx5_eswitch_get_vport(peer_esw, MLX5_VPORT_PF);
1219 esw_set_peer_miss_rule_source_port(esw, peer_esw, spec,
1220 MLX5_VPORT_PF);
1221
1222 flow = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
1223 spec, &flow_act, &dest, 1);
1224 if (IS_ERR(flow)) {
1225 err = PTR_ERR(flow);
1226 goto add_pf_flow_err;
1227 }
1228 flows[peer_vport->index] = flow;
1229 }
1230
1231 if (mlx5_ecpf_vport_exists(peer_dev)) {
1232 peer_vport = mlx5_eswitch_get_vport(peer_esw, MLX5_VPORT_ECPF);
1233 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_ECPF);
1234 flow = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
1235 spec, &flow_act, &dest, 1);
1236 if (IS_ERR(flow)) {
1237 err = PTR_ERR(flow);
1238 goto add_ecpf_flow_err;
1239 }
1240 flows[peer_vport->index] = flow;
1241 }
1242
1243 if (mlx5_esw_host_functions_enabled(esw->dev)) {
1244 mlx5_esw_for_each_vf_vport(peer_esw, i, peer_vport,
1245 mlx5_core_max_vfs(peer_dev)) {
1246 esw_set_peer_miss_rule_source_port(esw, peer_esw,
1247 spec,
1248 peer_vport->vport);
1249
1250 flow = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
1251 spec, &flow_act, &dest, 1);
1252 if (IS_ERR(flow)) {
1253 err = PTR_ERR(flow);
1254 goto add_vf_flow_err;
1255 }
1256 flows[peer_vport->index] = flow;
1257 }
1258 }
1259
1260 if (mlx5_core_ec_sriov_enabled(peer_dev)) {
1261 mlx5_esw_for_each_ec_vf_vport(peer_esw, i, peer_vport,
1262 mlx5_core_max_ec_vfs(peer_dev)) {
1263 esw_set_peer_miss_rule_source_port(esw, peer_esw,
1264 spec,
1265 peer_vport->vport);
1266 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1267 spec, &flow_act, &dest, 1);
1268 if (IS_ERR(flow)) {
1269 err = PTR_ERR(flow);
1270 goto add_ec_vf_flow_err;
1271 }
1272 flows[peer_vport->index] = flow;
1273 }
1274 }
1275
1276 pfindex = mlx5_get_dev_index(peer_dev);
1277 if (pfindex >= MLX5_MAX_PORTS) {
1278 esw_warn(esw->dev, "Peer dev index(%d) is over the max num defined(%d)\n",
1279 pfindex, MLX5_MAX_PORTS);
1280 err = -EINVAL;
1281 goto add_ec_vf_flow_err;
1282 }
1283 esw->fdb_table.offloads.peer_miss_rules[pfindex] = flows;
1284
1285 kvfree(spec);
1286 return 0;
1287
1288 add_ec_vf_flow_err:
1289 mlx5_esw_for_each_ec_vf_vport(peer_esw, i, peer_vport,
1290 mlx5_core_max_ec_vfs(peer_dev)) {
1291 if (!flows[peer_vport->index])
1292 continue;
1293 mlx5_del_flow_rules(flows[peer_vport->index]);
1294 }
1295 add_vf_flow_err:
1296 mlx5_esw_for_each_vf_vport(peer_esw, i, peer_vport,
1297 mlx5_core_max_vfs(peer_dev)) {
1298 if (!flows[peer_vport->index])
1299 continue;
1300 mlx5_del_flow_rules(flows[peer_vport->index]);
1301 }
1302 if (mlx5_ecpf_vport_exists(peer_dev)) {
1303 peer_vport = mlx5_eswitch_get_vport(peer_esw, MLX5_VPORT_ECPF);
1304 mlx5_del_flow_rules(flows[peer_vport->index]);
1305 }
1306 add_ecpf_flow_err:
1307
1308 if (mlx5_core_is_ecpf_esw_manager(peer_dev) &&
1309 mlx5_esw_host_functions_enabled(peer_dev)) {
1310 peer_vport = mlx5_eswitch_get_vport(peer_esw, MLX5_VPORT_PF);
1311 mlx5_del_flow_rules(flows[peer_vport->index]);
1312 }
1313 add_pf_flow_err:
1314 esw_warn(esw->dev, "FDB: Failed to add peer miss flow rule err %d\n", err);
1315 kvfree(flows);
1316 alloc_flows_err:
1317 kvfree(spec);
1318 return err;
1319 }
1320
esw_del_fdb_peer_miss_rules(struct mlx5_eswitch * esw,struct mlx5_core_dev * peer_dev)1321 static void esw_del_fdb_peer_miss_rules(struct mlx5_eswitch *esw,
1322 struct mlx5_core_dev *peer_dev)
1323 {
1324 struct mlx5_eswitch *peer_esw = peer_dev->priv.eswitch;
1325 u16 peer_index = mlx5_get_dev_index(peer_dev);
1326 struct mlx5_flow_handle **flows;
1327 struct mlx5_vport *peer_vport;
1328 unsigned long i;
1329
1330 flows = esw->fdb_table.offloads.peer_miss_rules[peer_index];
1331 if (!flows)
1332 return;
1333
1334 if (mlx5_core_ec_sriov_enabled(peer_dev)) {
1335 mlx5_esw_for_each_ec_vf_vport(peer_esw, i, peer_vport,
1336 mlx5_core_max_ec_vfs(peer_dev))
1337 mlx5_del_flow_rules(flows[peer_vport->index]);
1338 }
1339
1340 mlx5_esw_for_each_vf_vport(peer_esw, i, peer_vport,
1341 mlx5_core_max_vfs(peer_dev))
1342 mlx5_del_flow_rules(flows[peer_vport->index]);
1343
1344 if (mlx5_ecpf_vport_exists(peer_dev)) {
1345 peer_vport = mlx5_eswitch_get_vport(peer_esw, MLX5_VPORT_ECPF);
1346 mlx5_del_flow_rules(flows[peer_vport->index]);
1347 }
1348
1349 if (mlx5_core_is_ecpf_esw_manager(peer_dev)) {
1350 peer_vport = mlx5_eswitch_get_vport(peer_esw, MLX5_VPORT_PF);
1351 mlx5_del_flow_rules(flows[peer_vport->index]);
1352 }
1353
1354 kvfree(flows);
1355 esw->fdb_table.offloads.peer_miss_rules[peer_index] = NULL;
1356 }
1357
esw_add_fdb_miss_rule(struct mlx5_eswitch * esw)1358 static int esw_add_fdb_miss_rule(struct mlx5_eswitch *esw)
1359 {
1360 struct mlx5_flow_act flow_act = {0};
1361 struct mlx5_flow_destination dest = {};
1362 struct mlx5_flow_handle *flow_rule = NULL;
1363 struct mlx5_flow_spec *spec;
1364 void *headers_c;
1365 void *headers_v;
1366 int err = 0;
1367 u8 *dmac_c;
1368 u8 *dmac_v;
1369
1370 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1371 if (!spec) {
1372 err = -ENOMEM;
1373 goto out;
1374 }
1375
1376 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
1377 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1378 outer_headers);
1379 dmac_c = MLX5_ADDR_OF(fte_match_param, headers_c,
1380 outer_headers.dmac_47_16);
1381 dmac_c[0] = 0x01;
1382
1383 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
1384 dest.vport.num = esw->manager_vport;
1385 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1386
1387 flow_rule = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
1388 spec, &flow_act, &dest, 1);
1389 if (IS_ERR(flow_rule)) {
1390 err = PTR_ERR(flow_rule);
1391 esw_warn(esw->dev, "FDB: Failed to add unicast miss flow rule err %d\n", err);
1392 goto out;
1393 }
1394
1395 esw->fdb_table.offloads.miss_rule_uni = flow_rule;
1396
1397 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1398 outer_headers);
1399 dmac_v = MLX5_ADDR_OF(fte_match_param, headers_v,
1400 outer_headers.dmac_47_16);
1401 dmac_v[0] = 0x01;
1402 flow_rule = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
1403 spec, &flow_act, &dest, 1);
1404 if (IS_ERR(flow_rule)) {
1405 err = PTR_ERR(flow_rule);
1406 esw_warn(esw->dev, "FDB: Failed to add multicast miss flow rule err %d\n", err);
1407 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
1408 goto out;
1409 }
1410
1411 esw->fdb_table.offloads.miss_rule_multi = flow_rule;
1412
1413 out:
1414 kvfree(spec);
1415 return err;
1416 }
1417
1418 struct mlx5_flow_handle *
esw_add_restore_rule(struct mlx5_eswitch * esw,u32 tag)1419 esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag)
1420 {
1421 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
1422 struct mlx5_flow_table *ft = esw->offloads.ft_offloads_restore;
1423 struct mlx5_flow_context *flow_context;
1424 struct mlx5_flow_handle *flow_rule;
1425 struct mlx5_flow_destination dest;
1426 struct mlx5_flow_spec *spec;
1427 void *misc;
1428
1429 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
1430 return ERR_PTR(-EOPNOTSUPP);
1431
1432 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1433 if (!spec)
1434 return ERR_PTR(-ENOMEM);
1435
1436 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1437 misc_parameters_2);
1438 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1439 ESW_REG_C0_USER_DATA_METADATA_MASK);
1440 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1441 misc_parameters_2);
1442 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, tag);
1443 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1444 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1445 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1446 flow_act.modify_hdr = esw->offloads.restore_copy_hdr_id;
1447
1448 flow_context = &spec->flow_context;
1449 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
1450 flow_context->flow_tag = tag;
1451 dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1452 dest.ft = esw->offloads.ft_offloads;
1453
1454 flow_rule = mlx5_add_flow_rules(ft, spec, &flow_act, &dest, 1);
1455 kvfree(spec);
1456
1457 if (IS_ERR(flow_rule))
1458 esw_warn(esw->dev,
1459 "Failed to create restore rule for tag: %d, err(%d)\n",
1460 tag, (int)PTR_ERR(flow_rule));
1461
1462 return flow_rule;
1463 }
1464
1465 #define MAX_PF_SQ 256
1466 #define MAX_SQ_NVPORTS 32
1467
1468 void
mlx5_esw_set_flow_group_source_port(struct mlx5_eswitch * esw,u32 * flow_group_in,int match_params)1469 mlx5_esw_set_flow_group_source_port(struct mlx5_eswitch *esw,
1470 u32 *flow_group_in,
1471 int match_params)
1472 {
1473 void *match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1474 flow_group_in,
1475 match_criteria);
1476
1477 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1478 MLX5_SET(create_flow_group_in, flow_group_in,
1479 match_criteria_enable,
1480 MLX5_MATCH_MISC_PARAMETERS_2 | match_params);
1481
1482 MLX5_SET(fte_match_param, match_criteria,
1483 misc_parameters_2.metadata_reg_c_0,
1484 mlx5_eswitch_get_vport_metadata_mask());
1485 } else {
1486 MLX5_SET(create_flow_group_in, flow_group_in,
1487 match_criteria_enable,
1488 MLX5_MATCH_MISC_PARAMETERS | match_params);
1489
1490 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1491 misc_parameters.source_port);
1492 }
1493 }
1494
1495 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
esw_vport_tbl_put(struct mlx5_eswitch * esw)1496 static void esw_vport_tbl_put(struct mlx5_eswitch *esw)
1497 {
1498 struct mlx5_vport_tbl_attr attr;
1499 struct mlx5_vport *vport;
1500 unsigned long i;
1501
1502 attr.chain = 0;
1503 attr.prio = 1;
1504 mlx5_esw_for_each_vport(esw, i, vport) {
1505 attr.vport = vport->vport;
1506 attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
1507 mlx5_esw_vporttbl_put(esw, &attr);
1508 }
1509 }
1510
esw_vport_tbl_get(struct mlx5_eswitch * esw)1511 static int esw_vport_tbl_get(struct mlx5_eswitch *esw)
1512 {
1513 struct mlx5_vport_tbl_attr attr;
1514 struct mlx5_flow_table *fdb;
1515 struct mlx5_vport *vport;
1516 unsigned long i;
1517
1518 attr.chain = 0;
1519 attr.prio = 1;
1520 mlx5_esw_for_each_vport(esw, i, vport) {
1521 attr.vport = vport->vport;
1522 attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
1523 fdb = mlx5_esw_vporttbl_get(esw, &attr);
1524 if (IS_ERR(fdb))
1525 goto out;
1526 }
1527 return 0;
1528
1529 out:
1530 esw_vport_tbl_put(esw);
1531 return PTR_ERR(fdb);
1532 }
1533
1534 #define fdb_modify_header_fwd_to_table_supported(esw) \
1535 (MLX5_CAP_ESW_FLOWTABLE((esw)->dev, fdb_modify_header_fwd_to_table))
esw_init_chains_offload_flags(struct mlx5_eswitch * esw,u32 * flags)1536 static void esw_init_chains_offload_flags(struct mlx5_eswitch *esw, u32 *flags)
1537 {
1538 struct mlx5_core_dev *dev = esw->dev;
1539
1540 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev, ignore_flow_level))
1541 *flags |= MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
1542
1543 if (!MLX5_CAP_ESW_FLOWTABLE(dev, multi_fdb_encap) &&
1544 esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) {
1545 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1546 esw_warn(dev, "Tc chains and priorities offload aren't supported, update firmware if needed\n");
1547 } else if (!mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
1548 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1549 esw_warn(dev, "Tc chains and priorities offload aren't supported\n");
1550 } else if (!fdb_modify_header_fwd_to_table_supported(esw)) {
1551 /* Disabled when ttl workaround is needed, e.g
1552 * when ESWITCH_IPV4_TTL_MODIFY_ENABLE = true in mlxconfig
1553 */
1554 esw_warn(dev,
1555 "Tc chains and priorities offload aren't supported, check firmware version, or mlxconfig settings\n");
1556 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1557 } else {
1558 *flags |= MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1559 esw_info(dev, "Supported tc chains and prios offload\n");
1560 }
1561
1562 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1563 *flags |= MLX5_CHAINS_FT_TUNNEL_SUPPORTED;
1564 }
1565
1566 static int
esw_chains_create(struct mlx5_eswitch * esw,struct mlx5_flow_table * miss_fdb)1567 esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1568 {
1569 struct mlx5_core_dev *dev = esw->dev;
1570 struct mlx5_flow_table *nf_ft, *ft;
1571 struct mlx5_chains_attr attr = {};
1572 struct mlx5_fs_chains *chains;
1573 int err;
1574
1575 esw_init_chains_offload_flags(esw, &attr.flags);
1576 attr.ns = MLX5_FLOW_NAMESPACE_FDB;
1577 attr.max_grp_num = esw->params.large_group_num;
1578 attr.default_ft = miss_fdb;
1579 attr.mapping = esw->offloads.reg_c0_obj_pool;
1580 attr.fs_base_prio = FDB_BYPASS_PATH;
1581
1582 chains = mlx5_chains_create(dev, &attr);
1583 if (IS_ERR(chains)) {
1584 err = PTR_ERR(chains);
1585 esw_warn(dev, "Failed to create fdb chains err(%d)\n", err);
1586 return err;
1587 }
1588 mlx5_chains_print_info(chains);
1589
1590 esw->fdb_table.offloads.esw_chains_priv = chains;
1591
1592 /* Create tc_end_ft which is the always created ft chain */
1593 nf_ft = mlx5_chains_get_table(chains, mlx5_chains_get_nf_ft_chain(chains),
1594 1, 0);
1595 if (IS_ERR(nf_ft)) {
1596 err = PTR_ERR(nf_ft);
1597 goto nf_ft_err;
1598 }
1599
1600 /* Always open the root for fast path */
1601 ft = mlx5_chains_get_table(chains, 0, 1, 0);
1602 if (IS_ERR(ft)) {
1603 err = PTR_ERR(ft);
1604 goto level_0_err;
1605 }
1606
1607 /* Open level 1 for split fdb rules now if prios isn't supported */
1608 if (!mlx5_chains_prios_supported(chains)) {
1609 err = esw_vport_tbl_get(esw);
1610 if (err)
1611 goto level_1_err;
1612 }
1613
1614 mlx5_chains_set_end_ft(chains, nf_ft);
1615
1616 return 0;
1617
1618 level_1_err:
1619 mlx5_chains_put_table(chains, 0, 1, 0);
1620 level_0_err:
1621 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1622 nf_ft_err:
1623 mlx5_chains_destroy(chains);
1624 esw->fdb_table.offloads.esw_chains_priv = NULL;
1625
1626 return err;
1627 }
1628
1629 static void
esw_chains_destroy(struct mlx5_eswitch * esw,struct mlx5_fs_chains * chains)1630 esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1631 {
1632 if (!mlx5_chains_prios_supported(chains))
1633 esw_vport_tbl_put(esw);
1634 mlx5_chains_put_table(chains, 0, 1, 0);
1635 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1636 mlx5_chains_destroy(chains);
1637 }
1638
1639 #else /* CONFIG_MLX5_CLS_ACT */
1640
1641 static int
esw_chains_create(struct mlx5_eswitch * esw,struct mlx5_flow_table * miss_fdb)1642 esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1643 { return 0; }
1644
1645 static void
esw_chains_destroy(struct mlx5_eswitch * esw,struct mlx5_fs_chains * chains)1646 esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1647 {}
1648
1649 #endif
1650
1651 static int
esw_create_send_to_vport_group(struct mlx5_eswitch * esw,struct mlx5_flow_table * fdb,u32 * flow_group_in,int * ix)1652 esw_create_send_to_vport_group(struct mlx5_eswitch *esw,
1653 struct mlx5_flow_table *fdb,
1654 u32 *flow_group_in,
1655 int *ix)
1656 {
1657 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1658 struct mlx5_flow_group *g;
1659 void *match_criteria;
1660 int count, err = 0;
1661
1662 memset(flow_group_in, 0, inlen);
1663
1664 mlx5_esw_set_flow_group_source_port(esw, flow_group_in, MLX5_MATCH_MISC_PARAMETERS);
1665
1666 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1667 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_sqn);
1668
1669 if (!mlx5_eswitch_vport_match_metadata_enabled(esw) &&
1670 MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
1671 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1672 misc_parameters.source_eswitch_owner_vhca_id);
1673 MLX5_SET(create_flow_group_in, flow_group_in,
1674 source_eswitch_owner_vhca_id_valid, 1);
1675 }
1676
1677 /* See comment at table_size calculation */
1678 count = MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ);
1679 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1680 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, *ix + count - 1);
1681 *ix += count;
1682
1683 g = mlx5_create_flow_group(fdb, flow_group_in);
1684 if (IS_ERR(g)) {
1685 err = PTR_ERR(g);
1686 esw_warn(esw->dev, "Failed to create send-to-vport flow group err(%d)\n", err);
1687 goto out;
1688 }
1689 esw->fdb_table.offloads.send_to_vport_grp = g;
1690
1691 out:
1692 return err;
1693 }
1694
1695 static int
esw_create_meta_send_to_vport_group(struct mlx5_eswitch * esw,struct mlx5_flow_table * fdb,u32 * flow_group_in,int * ix)1696 esw_create_meta_send_to_vport_group(struct mlx5_eswitch *esw,
1697 struct mlx5_flow_table *fdb,
1698 u32 *flow_group_in,
1699 int *ix)
1700 {
1701 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1702 struct mlx5_flow_group *g;
1703 void *match_criteria;
1704 int err = 0;
1705
1706 if (!esw_src_port_rewrite_supported(esw))
1707 return 0;
1708
1709 memset(flow_group_in, 0, inlen);
1710
1711 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1712 MLX5_MATCH_MISC_PARAMETERS_2);
1713
1714 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1715
1716 MLX5_SET(fte_match_param, match_criteria,
1717 misc_parameters_2.metadata_reg_c_0,
1718 mlx5_eswitch_get_vport_metadata_mask());
1719 MLX5_SET(fte_match_param, match_criteria,
1720 misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK);
1721
1722 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, *ix);
1723 MLX5_SET(create_flow_group_in, flow_group_in,
1724 end_flow_index, *ix + esw->total_vports - 1);
1725 *ix += esw->total_vports;
1726
1727 g = mlx5_create_flow_group(fdb, flow_group_in);
1728 if (IS_ERR(g)) {
1729 err = PTR_ERR(g);
1730 esw_warn(esw->dev,
1731 "Failed to create send-to-vport meta flow group err(%d)\n", err);
1732 goto send_vport_meta_err;
1733 }
1734 esw->fdb_table.offloads.send_to_vport_meta_grp = g;
1735
1736 return 0;
1737
1738 send_vport_meta_err:
1739 return err;
1740 }
1741
1742 static int
esw_create_peer_esw_miss_group(struct mlx5_eswitch * esw,struct mlx5_flow_table * fdb,u32 * flow_group_in,int * ix)1743 esw_create_peer_esw_miss_group(struct mlx5_eswitch *esw,
1744 struct mlx5_flow_table *fdb,
1745 u32 *flow_group_in,
1746 int *ix)
1747 {
1748 int max_peer_ports = (esw->total_vports - 1) * (MLX5_MAX_PORTS - 1);
1749 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1750 struct mlx5_flow_group *g;
1751 void *match_criteria;
1752 int err = 0;
1753
1754 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
1755 return 0;
1756
1757 memset(flow_group_in, 0, inlen);
1758
1759 mlx5_esw_set_flow_group_source_port(esw, flow_group_in, 0);
1760
1761 if (!mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1762 match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1763 flow_group_in,
1764 match_criteria);
1765
1766 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1767 misc_parameters.source_eswitch_owner_vhca_id);
1768
1769 MLX5_SET(create_flow_group_in, flow_group_in,
1770 source_eswitch_owner_vhca_id_valid, 1);
1771 }
1772
1773 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, *ix);
1774 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1775 *ix + max_peer_ports);
1776 *ix += max_peer_ports + 1;
1777
1778 g = mlx5_create_flow_group(fdb, flow_group_in);
1779 if (IS_ERR(g)) {
1780 err = PTR_ERR(g);
1781 esw_warn(esw->dev, "Failed to create peer miss flow group err(%d)\n", err);
1782 goto out;
1783 }
1784 esw->fdb_table.offloads.peer_miss_grp = g;
1785
1786 out:
1787 return err;
1788 }
1789
1790 static int
esw_create_miss_group(struct mlx5_eswitch * esw,struct mlx5_flow_table * fdb,u32 * flow_group_in,int * ix)1791 esw_create_miss_group(struct mlx5_eswitch *esw,
1792 struct mlx5_flow_table *fdb,
1793 u32 *flow_group_in,
1794 int *ix)
1795 {
1796 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1797 struct mlx5_flow_group *g;
1798 void *match_criteria;
1799 int err = 0;
1800 u8 *dmac;
1801
1802 memset(flow_group_in, 0, inlen);
1803
1804 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1805 MLX5_MATCH_OUTER_HEADERS);
1806 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
1807 match_criteria);
1808 dmac = MLX5_ADDR_OF(fte_match_param, match_criteria,
1809 outer_headers.dmac_47_16);
1810 dmac[0] = 0x01;
1811
1812 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, *ix);
1813 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1814 *ix + MLX5_ESW_MISS_FLOWS);
1815
1816 g = mlx5_create_flow_group(fdb, flow_group_in);
1817 if (IS_ERR(g)) {
1818 err = PTR_ERR(g);
1819 esw_warn(esw->dev, "Failed to create miss flow group err(%d)\n", err);
1820 goto miss_err;
1821 }
1822 esw->fdb_table.offloads.miss_grp = g;
1823
1824 err = esw_add_fdb_miss_rule(esw);
1825 if (err)
1826 goto miss_rule_err;
1827
1828 return 0;
1829
1830 miss_rule_err:
1831 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1832 miss_err:
1833 return err;
1834 }
1835
esw_create_offloads_fdb_tables(struct mlx5_eswitch * esw)1836 static int esw_create_offloads_fdb_tables(struct mlx5_eswitch *esw)
1837 {
1838 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1839 struct mlx5_flow_table_attr ft_attr = {};
1840 struct mlx5_core_dev *dev = esw->dev;
1841 struct mlx5_flow_namespace *root_ns;
1842 struct mlx5_flow_table *fdb = NULL;
1843 int table_size, ix = 0, err = 0;
1844 u32 flags = 0, *flow_group_in;
1845
1846 esw_debug(esw->dev, "Create offloads FDB Tables\n");
1847
1848 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1849 if (!flow_group_in)
1850 return -ENOMEM;
1851
1852 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
1853 if (!root_ns) {
1854 esw_warn(dev, "Failed to get FDB flow namespace\n");
1855 err = -EOPNOTSUPP;
1856 goto ns_err;
1857 }
1858 esw->fdb_table.offloads.ns = root_ns;
1859 err = mlx5_flow_namespace_set_mode(root_ns,
1860 esw->dev->priv.steering->mode);
1861 if (err) {
1862 esw_warn(dev, "Failed to set FDB namespace steering mode\n");
1863 goto ns_err;
1864 }
1865
1866 /* To be strictly correct:
1867 * MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ)
1868 * should be:
1869 * esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ +
1870 * peer_esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ
1871 * but as the peer device might not be in switchdev mode it's not
1872 * possible. We use the fact that by default FW sets max vfs and max sfs
1873 * to the same value on both devices. If it needs to be changed in the future note
1874 * the peer miss group should also be created based on the number of
1875 * total vports of the peer (currently is also uses esw->total_vports).
1876 */
1877 table_size = MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ) +
1878 esw->total_vports * MLX5_MAX_PORTS + MLX5_ESW_MISS_FLOWS;
1879
1880 /* create the slow path fdb with encap set, so further table instances
1881 * can be created at run time while VFs are probed if the FW allows that.
1882 */
1883 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1884 flags |= (MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT |
1885 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP);
1886
1887 ft_attr.flags = flags;
1888 ft_attr.max_fte = table_size;
1889 ft_attr.prio = FDB_SLOW_PATH;
1890
1891 fdb = mlx5_create_flow_table(root_ns, &ft_attr);
1892 if (IS_ERR(fdb)) {
1893 err = PTR_ERR(fdb);
1894 esw_warn(dev, "Failed to create slow path FDB Table err %d\n", err);
1895 goto slow_fdb_err;
1896 }
1897 esw->fdb_table.offloads.slow_fdb = fdb;
1898
1899 /* Create empty TC-miss managed table. This allows plugging in following
1900 * priorities without directly exposing their level 0 table to
1901 * eswitch_offloads and passing it as miss_fdb to following call to
1902 * esw_chains_create().
1903 */
1904 memset(&ft_attr, 0, sizeof(ft_attr));
1905 ft_attr.prio = FDB_TC_MISS;
1906 esw->fdb_table.offloads.tc_miss_table = mlx5_create_flow_table(root_ns, &ft_attr);
1907 if (IS_ERR(esw->fdb_table.offloads.tc_miss_table)) {
1908 err = PTR_ERR(esw->fdb_table.offloads.tc_miss_table);
1909 esw_warn(dev, "Failed to create TC miss FDB Table err %d\n", err);
1910 goto tc_miss_table_err;
1911 }
1912
1913 err = esw_chains_create(esw, esw->fdb_table.offloads.tc_miss_table);
1914 if (err) {
1915 esw_warn(dev, "Failed to open fdb chains err(%d)\n", err);
1916 goto fdb_chains_err;
1917 }
1918
1919 err = esw_create_send_to_vport_group(esw, fdb, flow_group_in, &ix);
1920 if (err)
1921 goto send_vport_err;
1922
1923 err = esw_create_meta_send_to_vport_group(esw, fdb, flow_group_in, &ix);
1924 if (err)
1925 goto send_vport_meta_err;
1926
1927 err = esw_create_peer_esw_miss_group(esw, fdb, flow_group_in, &ix);
1928 if (err)
1929 goto peer_miss_err;
1930
1931 err = esw_create_miss_group(esw, fdb, flow_group_in, &ix);
1932 if (err)
1933 goto miss_err;
1934
1935 kvfree(flow_group_in);
1936 return 0;
1937
1938 miss_err:
1939 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1940 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
1941 peer_miss_err:
1942 if (esw->fdb_table.offloads.send_to_vport_meta_grp)
1943 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp);
1944 send_vport_meta_err:
1945 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1946 send_vport_err:
1947 esw_chains_destroy(esw, esw_chains(esw));
1948 fdb_chains_err:
1949 mlx5_destroy_flow_table(esw->fdb_table.offloads.tc_miss_table);
1950 tc_miss_table_err:
1951 mlx5_destroy_flow_table(mlx5_eswitch_get_slow_fdb(esw));
1952 slow_fdb_err:
1953 /* Holds true only as long as DMFS is the default */
1954 mlx5_flow_namespace_set_mode(root_ns, MLX5_FLOW_STEERING_MODE_DMFS);
1955 ns_err:
1956 kvfree(flow_group_in);
1957 return err;
1958 }
1959
esw_destroy_offloads_fdb_tables(struct mlx5_eswitch * esw)1960 static void esw_destroy_offloads_fdb_tables(struct mlx5_eswitch *esw)
1961 {
1962 if (!mlx5_eswitch_get_slow_fdb(esw))
1963 return;
1964
1965 esw_debug(esw->dev, "Destroy offloads FDB Tables\n");
1966 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_multi);
1967 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
1968 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1969 if (esw->fdb_table.offloads.send_to_vport_meta_grp)
1970 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp);
1971 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1972 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
1973 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1974
1975 esw_chains_destroy(esw, esw_chains(esw));
1976
1977 mlx5_destroy_flow_table(esw->fdb_table.offloads.tc_miss_table);
1978 mlx5_destroy_flow_table(mlx5_eswitch_get_slow_fdb(esw));
1979 /* Holds true only as long as DMFS is the default */
1980 mlx5_flow_namespace_set_mode(esw->fdb_table.offloads.ns,
1981 MLX5_FLOW_STEERING_MODE_DMFS);
1982 }
1983
esw_get_nr_ft_offloads_steering_src_ports(struct mlx5_eswitch * esw)1984 static int esw_get_nr_ft_offloads_steering_src_ports(struct mlx5_eswitch *esw)
1985 {
1986 int nvports;
1987
1988 nvports = esw->total_vports + MLX5_ESW_MISS_FLOWS;
1989 if (mlx5e_tc_int_port_supported(esw))
1990 nvports += MLX5E_TC_MAX_INT_PORT_NUM;
1991
1992 return nvports;
1993 }
1994
esw_create_offloads_table(struct mlx5_eswitch * esw)1995 static int esw_create_offloads_table(struct mlx5_eswitch *esw)
1996 {
1997 struct mlx5_flow_table_attr ft_attr = {};
1998 struct mlx5_core_dev *dev = esw->dev;
1999 struct mlx5_flow_table *ft_offloads;
2000 struct mlx5_flow_namespace *ns;
2001 int err = 0;
2002
2003 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
2004 if (!ns) {
2005 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
2006 return -EOPNOTSUPP;
2007 }
2008
2009 ft_attr.max_fte = esw_get_nr_ft_offloads_steering_src_ports(esw) +
2010 MLX5_ESW_FT_OFFLOADS_DROP_RULE;
2011 ft_attr.prio = 1;
2012
2013 ft_offloads = mlx5_create_flow_table(ns, &ft_attr);
2014 if (IS_ERR(ft_offloads)) {
2015 err = PTR_ERR(ft_offloads);
2016 esw_warn(esw->dev, "Failed to create offloads table, err %d\n", err);
2017 return err;
2018 }
2019
2020 esw->offloads.ft_offloads = ft_offloads;
2021 return 0;
2022 }
2023
esw_destroy_offloads_table(struct mlx5_eswitch * esw)2024 static void esw_destroy_offloads_table(struct mlx5_eswitch *esw)
2025 {
2026 struct mlx5_esw_offload *offloads = &esw->offloads;
2027
2028 mlx5_destroy_flow_table(offloads->ft_offloads);
2029 }
2030
esw_create_vport_rx_group(struct mlx5_eswitch * esw)2031 static int esw_create_vport_rx_group(struct mlx5_eswitch *esw)
2032 {
2033 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
2034 struct mlx5_flow_group *g;
2035 u32 *flow_group_in;
2036 int nvports;
2037 int err = 0;
2038
2039 nvports = esw_get_nr_ft_offloads_steering_src_ports(esw);
2040 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2041 if (!flow_group_in)
2042 return -ENOMEM;
2043
2044 mlx5_esw_set_flow_group_source_port(esw, flow_group_in, 0);
2045
2046 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
2047 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, nvports - 1);
2048
2049 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
2050
2051 if (IS_ERR(g)) {
2052 err = PTR_ERR(g);
2053 mlx5_core_warn(esw->dev, "Failed to create vport rx group err %d\n", err);
2054 goto out;
2055 }
2056
2057 esw->offloads.vport_rx_group = g;
2058 out:
2059 kvfree(flow_group_in);
2060 return err;
2061 }
2062
esw_destroy_vport_rx_group(struct mlx5_eswitch * esw)2063 static void esw_destroy_vport_rx_group(struct mlx5_eswitch *esw)
2064 {
2065 mlx5_destroy_flow_group(esw->offloads.vport_rx_group);
2066 }
2067
esw_create_vport_rx_drop_rule_index(struct mlx5_eswitch * esw)2068 static int esw_create_vport_rx_drop_rule_index(struct mlx5_eswitch *esw)
2069 {
2070 /* ft_offloads table is enlarged by MLX5_ESW_FT_OFFLOADS_DROP_RULE (1)
2071 * for the drop rule, which is placed at the end of the table.
2072 * So return the total of vport and int_port as rule index.
2073 */
2074 return esw_get_nr_ft_offloads_steering_src_ports(esw);
2075 }
2076
esw_create_vport_rx_drop_group(struct mlx5_eswitch * esw)2077 static int esw_create_vport_rx_drop_group(struct mlx5_eswitch *esw)
2078 {
2079 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
2080 struct mlx5_flow_group *g;
2081 u32 *flow_group_in;
2082 int flow_index;
2083 int err = 0;
2084
2085 flow_index = esw_create_vport_rx_drop_rule_index(esw);
2086
2087 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2088 if (!flow_group_in)
2089 return -ENOMEM;
2090
2091 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, flow_index);
2092 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, flow_index);
2093
2094 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
2095
2096 if (IS_ERR(g)) {
2097 err = PTR_ERR(g);
2098 mlx5_core_warn(esw->dev, "Failed to create vport rx drop group err %d\n", err);
2099 goto out;
2100 }
2101
2102 esw->offloads.vport_rx_drop_group = g;
2103 out:
2104 kvfree(flow_group_in);
2105 return err;
2106 }
2107
esw_destroy_vport_rx_drop_group(struct mlx5_eswitch * esw)2108 static void esw_destroy_vport_rx_drop_group(struct mlx5_eswitch *esw)
2109 {
2110 if (esw->offloads.vport_rx_drop_group)
2111 mlx5_destroy_flow_group(esw->offloads.vport_rx_drop_group);
2112 }
2113
2114 void
mlx5_esw_set_spec_source_port(struct mlx5_eswitch * esw,u16 vport,struct mlx5_flow_spec * spec)2115 mlx5_esw_set_spec_source_port(struct mlx5_eswitch *esw,
2116 u16 vport,
2117 struct mlx5_flow_spec *spec)
2118 {
2119 void *misc;
2120
2121 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
2122 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
2123 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
2124 mlx5_eswitch_get_vport_metadata_for_match(esw, vport));
2125
2126 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
2127 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
2128 mlx5_eswitch_get_vport_metadata_mask());
2129
2130 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
2131 } else {
2132 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
2133 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
2134
2135 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
2136 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
2137
2138 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
2139 }
2140 }
2141
2142 struct mlx5_flow_handle *
mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch * esw,u16 vport,struct mlx5_flow_destination * dest)2143 mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
2144 struct mlx5_flow_destination *dest)
2145 {
2146 struct mlx5_flow_act flow_act = {0};
2147 struct mlx5_flow_handle *flow_rule;
2148 struct mlx5_flow_spec *spec;
2149
2150 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
2151 if (!spec) {
2152 flow_rule = ERR_PTR(-ENOMEM);
2153 goto out;
2154 }
2155
2156 mlx5_esw_set_spec_source_port(esw, vport, spec);
2157
2158 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2159 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, spec,
2160 &flow_act, dest, 1);
2161 if (IS_ERR(flow_rule)) {
2162 esw_warn(esw->dev,
2163 "fs offloads: Failed to add vport rx rule err %pe\n",
2164 flow_rule);
2165 goto out;
2166 }
2167
2168 out:
2169 kvfree(spec);
2170 return flow_rule;
2171 }
2172
esw_create_vport_rx_drop_rule(struct mlx5_eswitch * esw)2173 static int esw_create_vport_rx_drop_rule(struct mlx5_eswitch *esw)
2174 {
2175 struct mlx5_flow_act flow_act = {};
2176 struct mlx5_flow_handle *flow_rule;
2177
2178 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
2179 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, NULL,
2180 &flow_act, NULL, 0);
2181 if (IS_ERR(flow_rule)) {
2182 esw_warn(esw->dev,
2183 "fs offloads: Failed to add vport rx drop rule err %pe\n",
2184 flow_rule);
2185 return PTR_ERR(flow_rule);
2186 }
2187
2188 esw->offloads.vport_rx_drop_rule = flow_rule;
2189
2190 return 0;
2191 }
2192
esw_destroy_vport_rx_drop_rule(struct mlx5_eswitch * esw)2193 static void esw_destroy_vport_rx_drop_rule(struct mlx5_eswitch *esw)
2194 {
2195 if (esw->offloads.vport_rx_drop_rule)
2196 mlx5_del_flow_rules(esw->offloads.vport_rx_drop_rule);
2197 }
2198
mlx5_eswitch_inline_mode_get(struct mlx5_eswitch * esw,u8 * mode)2199 static int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, u8 *mode)
2200 {
2201 u8 prev_mlx5_mode, mlx5_mode = MLX5_INLINE_MODE_L2;
2202 struct mlx5_core_dev *dev = esw->dev;
2203 struct mlx5_vport *vport;
2204 unsigned long i;
2205
2206 if (!MLX5_CAP_GEN(dev, vport_group_manager))
2207 return -EOPNOTSUPP;
2208
2209 if (!mlx5_esw_is_fdb_created(esw))
2210 return -EOPNOTSUPP;
2211
2212 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
2213 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2214 mlx5_mode = MLX5_INLINE_MODE_NONE;
2215 goto out;
2216 case MLX5_CAP_INLINE_MODE_L2:
2217 mlx5_mode = MLX5_INLINE_MODE_L2;
2218 goto out;
2219 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2220 goto query_vports;
2221 }
2222
2223 query_vports:
2224 mlx5_query_nic_vport_min_inline(dev, esw->first_host_vport, &prev_mlx5_mode);
2225 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
2226 mlx5_query_nic_vport_min_inline(dev, vport->vport, &mlx5_mode);
2227 if (prev_mlx5_mode != mlx5_mode)
2228 return -EINVAL;
2229 prev_mlx5_mode = mlx5_mode;
2230 }
2231
2232 out:
2233 *mode = mlx5_mode;
2234 return 0;
2235 }
2236
esw_destroy_restore_table(struct mlx5_eswitch * esw)2237 static void esw_destroy_restore_table(struct mlx5_eswitch *esw)
2238 {
2239 struct mlx5_esw_offload *offloads = &esw->offloads;
2240
2241 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
2242 return;
2243
2244 mlx5_modify_header_dealloc(esw->dev, offloads->restore_copy_hdr_id);
2245 mlx5_destroy_flow_group(offloads->restore_group);
2246 mlx5_destroy_flow_table(offloads->ft_offloads_restore);
2247 }
2248
esw_create_restore_table(struct mlx5_eswitch * esw)2249 static int esw_create_restore_table(struct mlx5_eswitch *esw)
2250 {
2251 u8 modact[MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)] = {};
2252 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
2253 struct mlx5_flow_table_attr ft_attr = {};
2254 struct mlx5_core_dev *dev = esw->dev;
2255 struct mlx5_flow_namespace *ns;
2256 struct mlx5_modify_hdr *mod_hdr;
2257 void *match_criteria, *misc;
2258 struct mlx5_flow_table *ft;
2259 struct mlx5_flow_group *g;
2260 u32 *flow_group_in;
2261 int err = 0;
2262
2263 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
2264 return 0;
2265
2266 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
2267 if (!ns) {
2268 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
2269 return -EOPNOTSUPP;
2270 }
2271
2272 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2273 if (!flow_group_in) {
2274 err = -ENOMEM;
2275 goto out_free;
2276 }
2277
2278 ft_attr.max_fte = 1 << ESW_REG_C0_USER_DATA_METADATA_BITS;
2279 ft = mlx5_create_flow_table(ns, &ft_attr);
2280 if (IS_ERR(ft)) {
2281 err = PTR_ERR(ft);
2282 esw_warn(esw->dev, "Failed to create restore table, err %d\n",
2283 err);
2284 goto out_free;
2285 }
2286
2287 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
2288 match_criteria);
2289 misc = MLX5_ADDR_OF(fte_match_param, match_criteria,
2290 misc_parameters_2);
2291
2292 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
2293 ESW_REG_C0_USER_DATA_METADATA_MASK);
2294 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
2295 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
2296 ft_attr.max_fte - 1);
2297 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
2298 MLX5_MATCH_MISC_PARAMETERS_2);
2299 g = mlx5_create_flow_group(ft, flow_group_in);
2300 if (IS_ERR(g)) {
2301 err = PTR_ERR(g);
2302 esw_warn(dev, "Failed to create restore flow group, err: %d\n",
2303 err);
2304 goto err_group;
2305 }
2306
2307 MLX5_SET(copy_action_in, modact, action_type, MLX5_ACTION_TYPE_COPY);
2308 MLX5_SET(copy_action_in, modact, src_field,
2309 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1);
2310 MLX5_SET(copy_action_in, modact, dst_field,
2311 MLX5_ACTION_IN_FIELD_METADATA_REG_B);
2312 mod_hdr = mlx5_modify_header_alloc(esw->dev,
2313 MLX5_FLOW_NAMESPACE_KERNEL, 1,
2314 modact);
2315 if (IS_ERR(mod_hdr)) {
2316 err = PTR_ERR(mod_hdr);
2317 esw_warn(dev, "Failed to create restore mod header, err: %d\n",
2318 err);
2319 goto err_mod_hdr;
2320 }
2321
2322 esw->offloads.ft_offloads_restore = ft;
2323 esw->offloads.restore_group = g;
2324 esw->offloads.restore_copy_hdr_id = mod_hdr;
2325
2326 kvfree(flow_group_in);
2327
2328 return 0;
2329
2330 err_mod_hdr:
2331 mlx5_destroy_flow_group(g);
2332 err_group:
2333 mlx5_destroy_flow_table(ft);
2334 out_free:
2335 kvfree(flow_group_in);
2336
2337 return err;
2338 }
2339
esw_mode_change(struct mlx5_eswitch * esw,u16 mode)2340 static void esw_mode_change(struct mlx5_eswitch *esw, u16 mode)
2341 {
2342 mlx5_devcom_comp_lock(esw->dev->priv.hca_devcom_comp);
2343 if (esw->dev->priv.flags & MLX5_PRIV_FLAGS_DISABLE_IB_ADEV ||
2344 mlx5_core_mp_enabled(esw->dev)) {
2345 esw->mode = mode;
2346 mlx5_rescan_drivers_locked(esw->dev);
2347 mlx5_devcom_comp_unlock(esw->dev->priv.hca_devcom_comp);
2348 return;
2349 }
2350
2351 esw->dev->priv.flags |= MLX5_PRIV_FLAGS_DISABLE_IB_ADEV;
2352 mlx5_rescan_drivers_locked(esw->dev);
2353 esw->mode = mode;
2354 esw->dev->priv.flags &= ~MLX5_PRIV_FLAGS_DISABLE_IB_ADEV;
2355 mlx5_rescan_drivers_locked(esw->dev);
2356 mlx5_devcom_comp_unlock(esw->dev->priv.hca_devcom_comp);
2357 }
2358
mlx5_esw_fdb_drop_destroy(struct mlx5_eswitch * esw)2359 static void mlx5_esw_fdb_drop_destroy(struct mlx5_eswitch *esw)
2360 {
2361 if (!esw->fdb_table.offloads.drop_root)
2362 return;
2363
2364 esw_debug(esw->dev, "Destroying FDB drop root table %#x fc %#x\n",
2365 esw->fdb_table.offloads.drop_root->id,
2366 esw->fdb_table.offloads.drop_root_fc->id);
2367 mlx5_del_flow_rules(esw->fdb_table.offloads.drop_root_rule);
2368 /* Don't free flow counter here, can be reused on a later activation */
2369 mlx5_destroy_flow_table(esw->fdb_table.offloads.drop_root);
2370 esw->fdb_table.offloads.drop_root_rule = NULL;
2371 esw->fdb_table.offloads.drop_root = NULL;
2372 }
2373
mlx5_esw_fdb_drop_create(struct mlx5_eswitch * esw)2374 static int mlx5_esw_fdb_drop_create(struct mlx5_eswitch *esw)
2375 {
2376 struct mlx5_flow_destination drop_fc_dst = {};
2377 struct mlx5_flow_table_attr ft_attr = {};
2378 struct mlx5_flow_destination *dst = NULL;
2379 struct mlx5_core_dev *dev = esw->dev;
2380 struct mlx5_flow_namespace *root_ns;
2381 struct mlx5_flow_act flow_act = {};
2382 struct mlx5_flow_handle *flow_rule;
2383 struct mlx5_flow_table *table;
2384 int err = 0, dst_num = 0;
2385
2386 if (esw->fdb_table.offloads.drop_root)
2387 return 0;
2388
2389 root_ns = esw->fdb_table.offloads.ns;
2390
2391 ft_attr.prio = FDB_DROP_ROOT;
2392 ft_attr.max_fte = 1;
2393 ft_attr.autogroup.max_num_groups = 1;
2394 table = mlx5_create_auto_grouped_flow_table(root_ns, &ft_attr);
2395 if (IS_ERR(table)) {
2396 esw_warn(dev, "Failed to create fdb drop root table, err %pe\n",
2397 table);
2398 return PTR_ERR(table);
2399 }
2400
2401 /* Drop FC reusable, create once on first deactivation of FDB */
2402 if (!esw->fdb_table.offloads.drop_root_fc) {
2403 struct mlx5_fc *counter = mlx5_fc_create(dev, 0);
2404
2405 err = PTR_ERR_OR_ZERO(counter);
2406 if (err)
2407 esw_warn(esw->dev, "create fdb drop fc err %d\n", err);
2408 else
2409 esw->fdb_table.offloads.drop_root_fc = counter;
2410 }
2411
2412 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
2413
2414 if (esw->fdb_table.offloads.drop_root_fc) {
2415 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2416 drop_fc_dst.type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
2417 drop_fc_dst.counter = esw->fdb_table.offloads.drop_root_fc;
2418 dst = &drop_fc_dst;
2419 dst_num++;
2420 }
2421
2422 flow_rule = mlx5_add_flow_rules(table, NULL, &flow_act, dst, dst_num);
2423 err = PTR_ERR_OR_ZERO(flow_rule);
2424 if (err) {
2425 esw_warn(esw->dev,
2426 "fs offloads: Failed to add vport rx drop rule err %d\n",
2427 err);
2428 goto err_flow_rule;
2429 }
2430
2431 esw->fdb_table.offloads.drop_root = table;
2432 esw->fdb_table.offloads.drop_root_rule = flow_rule;
2433 esw_debug(esw->dev, "Created FDB drop root table %#x fc %#x\n",
2434 table->id, dst ? dst->counter->id : 0);
2435 return 0;
2436
2437 err_flow_rule:
2438 /* no need to free drop fc, esw_offloads_steering_cleanup will do it */
2439 mlx5_destroy_flow_table(table);
2440 return err;
2441 }
2442
mlx5_esw_fdb_active(struct mlx5_eswitch * esw)2443 static void mlx5_esw_fdb_active(struct mlx5_eswitch *esw)
2444 {
2445 struct mlx5_vport *vport;
2446 unsigned long i;
2447
2448 mlx5_esw_fdb_drop_destroy(esw);
2449 mlx5_mpfs_enable(esw->dev);
2450
2451 mlx5_esw_for_each_vf_vport(esw, i, vport, U16_MAX) {
2452 if (!vport->adjacent)
2453 continue;
2454 esw_debug(esw->dev, "Connecting vport %d to eswitch\n",
2455 vport->vport);
2456 mlx5_esw_adj_vport_modify(esw->dev, vport->vport, true);
2457 }
2458
2459 esw->offloads_inactive = false;
2460 esw_warn(esw->dev, "MPFS/FDB active\n");
2461 }
2462
mlx5_esw_fdb_inactive(struct mlx5_eswitch * esw)2463 static void mlx5_esw_fdb_inactive(struct mlx5_eswitch *esw)
2464 {
2465 struct mlx5_vport *vport;
2466 unsigned long i;
2467
2468 mlx5_mpfs_disable(esw->dev);
2469 mlx5_esw_fdb_drop_create(esw);
2470
2471 mlx5_esw_for_each_vf_vport(esw, i, vport, U16_MAX) {
2472 if (!vport->adjacent)
2473 continue;
2474 esw_debug(esw->dev, "Disconnecting vport %u from eswitch\n",
2475 vport->vport);
2476
2477 mlx5_esw_adj_vport_modify(esw->dev, vport->vport, false);
2478 }
2479
2480 esw->offloads_inactive = true;
2481 esw_warn(esw->dev, "MPFS/FDB inactive\n");
2482 }
2483
esw_offloads_start(struct mlx5_eswitch * esw,struct netlink_ext_ack * extack)2484 static int esw_offloads_start(struct mlx5_eswitch *esw,
2485 struct netlink_ext_ack *extack)
2486 {
2487 int err;
2488
2489 esw_mode_change(esw, MLX5_ESWITCH_OFFLOADS);
2490 err = mlx5_eswitch_enable_locked(esw, esw->dev->priv.sriov.num_vfs);
2491 if (err) {
2492 NL_SET_ERR_MSG_MOD(extack,
2493 "Failed setting eswitch to offloads");
2494 esw_mode_change(esw, MLX5_ESWITCH_LEGACY);
2495 return err;
2496 }
2497 if (esw->offloads.inline_mode == MLX5_INLINE_MODE_NONE) {
2498 if (mlx5_eswitch_inline_mode_get(esw,
2499 &esw->offloads.inline_mode)) {
2500 esw->offloads.inline_mode = MLX5_INLINE_MODE_L2;
2501 NL_SET_ERR_MSG_MOD(extack,
2502 "Inline mode is different between vports");
2503 }
2504 }
2505 return 0;
2506 }
2507
mlx5_esw_offloads_rep_remove(struct mlx5_eswitch * esw,const struct mlx5_vport * vport)2508 void mlx5_esw_offloads_rep_remove(struct mlx5_eswitch *esw,
2509 const struct mlx5_vport *vport)
2510 {
2511 struct mlx5_eswitch_rep *rep = xa_load(&esw->offloads.vport_reps,
2512 vport->vport);
2513
2514 if (!rep)
2515 return;
2516 xa_erase(&esw->offloads.vport_reps, vport->vport);
2517 kfree(rep);
2518 }
2519
mlx5_esw_offloads_rep_add(struct mlx5_eswitch * esw,const struct mlx5_vport * vport)2520 int mlx5_esw_offloads_rep_add(struct mlx5_eswitch *esw,
2521 const struct mlx5_vport *vport)
2522 {
2523 struct mlx5_eswitch_rep *rep;
2524 int rep_type;
2525 int err;
2526
2527 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
2528 if (!rep)
2529 return -ENOMEM;
2530
2531 rep->vport = vport->vport;
2532 rep->vport_index = vport->index;
2533 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++) {
2534 if (!esw->offloads.rep_ops[rep_type]) {
2535 atomic_set(&rep->rep_data[rep_type].state,
2536 REP_UNREGISTERED);
2537 continue;
2538 }
2539 /* Dynamic/delegated vports add their representors after
2540 * mlx5_eswitch_register_vport_reps, so mark them as registered
2541 * for them to be loaded later with the others.
2542 */
2543 rep->esw = esw;
2544 atomic_set(&rep->rep_data[rep_type].state, REP_REGISTERED);
2545 }
2546 err = xa_insert(&esw->offloads.vport_reps, rep->vport, rep, GFP_KERNEL);
2547 if (err)
2548 goto insert_err;
2549
2550 return 0;
2551
2552 insert_err:
2553 kfree(rep);
2554 return err;
2555 }
2556
mlx5_esw_offloads_rep_cleanup(struct mlx5_eswitch * esw,struct mlx5_eswitch_rep * rep)2557 static void mlx5_esw_offloads_rep_cleanup(struct mlx5_eswitch *esw,
2558 struct mlx5_eswitch_rep *rep)
2559 {
2560 xa_erase(&esw->offloads.vport_reps, rep->vport);
2561 kfree(rep);
2562 }
2563
esw_offloads_cleanup_reps(struct mlx5_eswitch * esw)2564 static void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw)
2565 {
2566 struct mlx5_eswitch_rep *rep;
2567 unsigned long i;
2568
2569 mlx5_esw_for_each_rep(esw, i, rep)
2570 mlx5_esw_offloads_rep_cleanup(esw, rep);
2571 xa_destroy(&esw->offloads.vport_reps);
2572 }
2573
esw_offloads_init_reps(struct mlx5_eswitch * esw)2574 static int esw_offloads_init_reps(struct mlx5_eswitch *esw)
2575 {
2576 struct mlx5_vport *vport;
2577 unsigned long i;
2578 int err;
2579
2580 xa_init(&esw->offloads.vport_reps);
2581
2582 mlx5_esw_for_each_vport(esw, i, vport) {
2583 err = mlx5_esw_offloads_rep_add(esw, vport);
2584 if (err)
2585 goto err;
2586 }
2587 return 0;
2588
2589 err:
2590 esw_offloads_cleanup_reps(esw);
2591 return err;
2592 }
2593
esw_port_metadata_set(struct devlink * devlink,u32 id,struct devlink_param_gset_ctx * ctx,struct netlink_ext_ack * extack)2594 static int esw_port_metadata_set(struct devlink *devlink, u32 id,
2595 struct devlink_param_gset_ctx *ctx,
2596 struct netlink_ext_ack *extack)
2597 {
2598 struct mlx5_core_dev *dev = devlink_priv(devlink);
2599 struct mlx5_eswitch *esw = dev->priv.eswitch;
2600 int err = 0;
2601
2602 down_write(&esw->mode_lock);
2603 if (mlx5_esw_is_fdb_created(esw)) {
2604 err = -EBUSY;
2605 goto done;
2606 }
2607 if (!mlx5_esw_vport_match_metadata_supported(esw)) {
2608 err = -EOPNOTSUPP;
2609 goto done;
2610 }
2611 if (ctx->val.vbool)
2612 esw->flags |= MLX5_ESWITCH_VPORT_MATCH_METADATA;
2613 else
2614 esw->flags &= ~MLX5_ESWITCH_VPORT_MATCH_METADATA;
2615 done:
2616 up_write(&esw->mode_lock);
2617 return err;
2618 }
2619
esw_port_metadata_get(struct devlink * devlink,u32 id,struct devlink_param_gset_ctx * ctx,struct netlink_ext_ack * extack)2620 static int esw_port_metadata_get(struct devlink *devlink, u32 id,
2621 struct devlink_param_gset_ctx *ctx,
2622 struct netlink_ext_ack *extack)
2623 {
2624 struct mlx5_core_dev *dev = devlink_priv(devlink);
2625
2626 ctx->val.vbool = mlx5_eswitch_vport_match_metadata_enabled(dev->priv.eswitch);
2627 return 0;
2628 }
2629
esw_port_metadata_validate(struct devlink * devlink,u32 id,union devlink_param_value val,struct netlink_ext_ack * extack)2630 static int esw_port_metadata_validate(struct devlink *devlink, u32 id,
2631 union devlink_param_value val,
2632 struct netlink_ext_ack *extack)
2633 {
2634 struct mlx5_core_dev *dev = devlink_priv(devlink);
2635 u8 esw_mode;
2636
2637 esw_mode = mlx5_eswitch_mode(dev);
2638 if (esw_mode == MLX5_ESWITCH_OFFLOADS) {
2639 NL_SET_ERR_MSG_MOD(extack,
2640 "E-Switch must either disabled or non switchdev mode");
2641 return -EBUSY;
2642 }
2643 return 0;
2644 }
2645
2646 static const struct devlink_param esw_devlink_params[] = {
2647 DEVLINK_PARAM_DRIVER(MLX5_DEVLINK_PARAM_ID_ESW_PORT_METADATA,
2648 "esw_port_metadata", DEVLINK_PARAM_TYPE_BOOL,
2649 BIT(DEVLINK_PARAM_CMODE_RUNTIME),
2650 esw_port_metadata_get,
2651 esw_port_metadata_set,
2652 esw_port_metadata_validate),
2653 };
2654
esw_offloads_init(struct mlx5_eswitch * esw)2655 int esw_offloads_init(struct mlx5_eswitch *esw)
2656 {
2657 int err;
2658
2659 err = esw_offloads_init_reps(esw);
2660 if (err)
2661 return err;
2662
2663 if (MLX5_ESWITCH_MANAGER(esw->dev) &&
2664 mlx5_esw_vport_match_metadata_supported(esw))
2665 esw->flags |= MLX5_ESWITCH_VPORT_MATCH_METADATA;
2666
2667 err = devl_params_register(priv_to_devlink(esw->dev),
2668 esw_devlink_params,
2669 ARRAY_SIZE(esw_devlink_params));
2670 if (err)
2671 goto err_params;
2672
2673 return 0;
2674
2675 err_params:
2676 esw_offloads_cleanup_reps(esw);
2677 return err;
2678 }
2679
esw_offloads_cleanup(struct mlx5_eswitch * esw)2680 void esw_offloads_cleanup(struct mlx5_eswitch *esw)
2681 {
2682 devl_params_unregister(priv_to_devlink(esw->dev),
2683 esw_devlink_params,
2684 ARRAY_SIZE(esw_devlink_params));
2685 esw_offloads_cleanup_reps(esw);
2686 }
2687
__esw_offloads_load_rep(struct mlx5_eswitch * esw,struct mlx5_eswitch_rep * rep,u8 rep_type)2688 static int __esw_offloads_load_rep(struct mlx5_eswitch *esw,
2689 struct mlx5_eswitch_rep *rep, u8 rep_type)
2690 {
2691 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
2692 REP_REGISTERED, REP_LOADED) == REP_REGISTERED)
2693 return esw->offloads.rep_ops[rep_type]->load(esw->dev, rep);
2694
2695 return 0;
2696 }
2697
__esw_offloads_unload_rep(struct mlx5_eswitch * esw,struct mlx5_eswitch_rep * rep,u8 rep_type)2698 static void __esw_offloads_unload_rep(struct mlx5_eswitch *esw,
2699 struct mlx5_eswitch_rep *rep, u8 rep_type)
2700 {
2701 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
2702 REP_LOADED, REP_REGISTERED) == REP_LOADED) {
2703 if (rep_type == REP_ETH)
2704 __esw_offloads_unload_rep(esw, rep, REP_IB);
2705 esw->offloads.rep_ops[rep_type]->unload(rep);
2706 }
2707 }
2708
__unload_reps_all_vport(struct mlx5_eswitch * esw,u8 rep_type)2709 static void __unload_reps_all_vport(struct mlx5_eswitch *esw, u8 rep_type)
2710 {
2711 struct mlx5_eswitch_rep *rep;
2712 unsigned long i;
2713
2714 mlx5_esw_for_each_rep(esw, i, rep)
2715 __esw_offloads_unload_rep(esw, rep, rep_type);
2716 }
2717
mlx5_esw_offloads_rep_load(struct mlx5_eswitch * esw,u16 vport_num)2718 static int mlx5_esw_offloads_rep_load(struct mlx5_eswitch *esw, u16 vport_num)
2719 {
2720 struct mlx5_eswitch_rep *rep;
2721 int rep_type;
2722 int err;
2723
2724 rep = mlx5_eswitch_get_rep(esw, vport_num);
2725 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++) {
2726 err = __esw_offloads_load_rep(esw, rep, rep_type);
2727 if (err)
2728 goto err_reps;
2729 }
2730
2731 return 0;
2732
2733 err_reps:
2734 atomic_set(&rep->rep_data[rep_type].state, REP_REGISTERED);
2735 for (--rep_type; rep_type >= 0; rep_type--)
2736 __esw_offloads_unload_rep(esw, rep, rep_type);
2737 return err;
2738 }
2739
mlx5_esw_offloads_rep_unload(struct mlx5_eswitch * esw,u16 vport_num)2740 static void mlx5_esw_offloads_rep_unload(struct mlx5_eswitch *esw, u16 vport_num)
2741 {
2742 struct mlx5_eswitch_rep *rep;
2743 int rep_type;
2744
2745 rep = mlx5_eswitch_get_rep(esw, vport_num);
2746 for (rep_type = NUM_REP_TYPES - 1; rep_type >= 0; rep_type--)
2747 __esw_offloads_unload_rep(esw, rep, rep_type);
2748 }
2749
mlx5_esw_offloads_init_pf_vf_rep(struct mlx5_eswitch * esw,struct mlx5_vport * vport)2750 int mlx5_esw_offloads_init_pf_vf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport)
2751 {
2752 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2753 return 0;
2754
2755 return mlx5_esw_offloads_pf_vf_devlink_port_init(esw, vport);
2756 }
2757
mlx5_esw_offloads_cleanup_pf_vf_rep(struct mlx5_eswitch * esw,struct mlx5_vport * vport)2758 void mlx5_esw_offloads_cleanup_pf_vf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport)
2759 {
2760 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2761 return;
2762
2763 mlx5_esw_offloads_pf_vf_devlink_port_cleanup(esw, vport);
2764 }
2765
mlx5_esw_offloads_init_sf_rep(struct mlx5_eswitch * esw,struct mlx5_vport * vport,struct mlx5_devlink_port * dl_port,u32 controller,u32 sfnum)2766 int mlx5_esw_offloads_init_sf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport,
2767 struct mlx5_devlink_port *dl_port,
2768 u32 controller, u32 sfnum)
2769 {
2770 return mlx5_esw_offloads_sf_devlink_port_init(esw, vport, dl_port, controller, sfnum);
2771 }
2772
mlx5_esw_offloads_cleanup_sf_rep(struct mlx5_eswitch * esw,struct mlx5_vport * vport)2773 void mlx5_esw_offloads_cleanup_sf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport)
2774 {
2775 mlx5_esw_offloads_sf_devlink_port_cleanup(esw, vport);
2776 }
2777
mlx5_esw_offloads_load_rep(struct mlx5_eswitch * esw,struct mlx5_vport * vport)2778 int mlx5_esw_offloads_load_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport)
2779 {
2780 int err;
2781
2782 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2783 return 0;
2784
2785 err = mlx5_esw_offloads_devlink_port_register(esw, vport);
2786 if (err)
2787 return err;
2788
2789 err = mlx5_esw_offloads_rep_load(esw, vport->vport);
2790 if (err)
2791 goto load_err;
2792 return err;
2793
2794 load_err:
2795 mlx5_esw_offloads_devlink_port_unregister(vport);
2796 return err;
2797 }
2798
mlx5_esw_offloads_unload_rep(struct mlx5_eswitch * esw,struct mlx5_vport * vport)2799 void mlx5_esw_offloads_unload_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport)
2800 {
2801 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2802 return;
2803
2804 mlx5_esw_offloads_rep_unload(esw, vport->vport);
2805
2806 mlx5_esw_offloads_devlink_port_unregister(vport);
2807 }
2808
esw_set_slave_root_fdb(struct mlx5_core_dev * master,struct mlx5_core_dev * slave)2809 static int esw_set_slave_root_fdb(struct mlx5_core_dev *master,
2810 struct mlx5_core_dev *slave)
2811 {
2812 u32 in[MLX5_ST_SZ_DW(set_flow_table_root_in)] = {};
2813 u32 out[MLX5_ST_SZ_DW(set_flow_table_root_out)] = {};
2814 struct mlx5_flow_root_namespace *root;
2815 struct mlx5_flow_namespace *ns;
2816 int err;
2817
2818 MLX5_SET(set_flow_table_root_in, in, opcode,
2819 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT);
2820 MLX5_SET(set_flow_table_root_in, in, table_type,
2821 FS_FT_FDB);
2822
2823 if (master) {
2824 ns = mlx5_get_flow_namespace(master,
2825 MLX5_FLOW_NAMESPACE_FDB);
2826 root = find_root(&ns->node);
2827 mutex_lock(&root->chain_lock);
2828 MLX5_SET(set_flow_table_root_in, in,
2829 table_eswitch_owner_vhca_id_valid, 1);
2830 MLX5_SET(set_flow_table_root_in, in,
2831 table_eswitch_owner_vhca_id,
2832 MLX5_CAP_GEN(master, vhca_id));
2833 MLX5_SET(set_flow_table_root_in, in, table_id,
2834 root->root_ft->id);
2835 } else {
2836 ns = mlx5_get_flow_namespace(slave,
2837 MLX5_FLOW_NAMESPACE_FDB);
2838 root = find_root(&ns->node);
2839 mutex_lock(&root->chain_lock);
2840 MLX5_SET(set_flow_table_root_in, in, table_id,
2841 root->root_ft->id);
2842 }
2843
2844 err = mlx5_cmd_exec(slave, in, sizeof(in), out, sizeof(out));
2845 mutex_unlock(&root->chain_lock);
2846
2847 return err;
2848 }
2849
__esw_set_master_egress_rule(struct mlx5_core_dev * master,struct mlx5_core_dev * slave,struct mlx5_vport * vport,struct mlx5_flow_table * acl)2850 static int __esw_set_master_egress_rule(struct mlx5_core_dev *master,
2851 struct mlx5_core_dev *slave,
2852 struct mlx5_vport *vport,
2853 struct mlx5_flow_table *acl)
2854 {
2855 u16 slave_index = MLX5_CAP_GEN(slave, vhca_id);
2856 struct mlx5_flow_handle *flow_rule = NULL;
2857 struct mlx5_flow_destination dest = {};
2858 struct mlx5_flow_act flow_act = {};
2859 struct mlx5_flow_spec *spec;
2860 int err = 0;
2861 void *misc;
2862
2863 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
2864 if (!spec)
2865 return -ENOMEM;
2866
2867 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
2868 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2869 misc_parameters);
2870 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_UPLINK);
2871 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id, slave_index);
2872
2873 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
2874 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
2875 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
2876 source_eswitch_owner_vhca_id);
2877
2878 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2879 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
2880 dest.vport.num = slave->priv.eswitch->manager_vport;
2881 dest.vport.vhca_id = MLX5_CAP_GEN(slave, vhca_id);
2882 dest.vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
2883
2884 flow_rule = mlx5_add_flow_rules(acl, spec, &flow_act,
2885 &dest, 1);
2886 if (IS_ERR(flow_rule)) {
2887 err = PTR_ERR(flow_rule);
2888 } else {
2889 err = xa_insert(&vport->egress.offloads.bounce_rules,
2890 slave_index, flow_rule, GFP_KERNEL);
2891 if (err)
2892 mlx5_del_flow_rules(flow_rule);
2893 }
2894
2895 kvfree(spec);
2896 return err;
2897 }
2898
esw_master_egress_create_resources(struct mlx5_eswitch * esw,struct mlx5_flow_namespace * egress_ns,struct mlx5_vport * vport,size_t count)2899 static int esw_master_egress_create_resources(struct mlx5_eswitch *esw,
2900 struct mlx5_flow_namespace *egress_ns,
2901 struct mlx5_vport *vport, size_t count)
2902 {
2903 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
2904 struct mlx5_flow_table_attr ft_attr = {
2905 .max_fte = count, .prio = 0, .level = 0,
2906 };
2907 struct mlx5_flow_table *acl;
2908 struct mlx5_flow_group *g;
2909 void *match_criteria;
2910 u32 *flow_group_in;
2911 int err;
2912
2913 if (vport->egress.acl)
2914 return 0;
2915
2916 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2917 if (!flow_group_in)
2918 return -ENOMEM;
2919
2920 if (vport->vport || mlx5_core_is_ecpf(esw->dev))
2921 ft_attr.flags = MLX5_FLOW_TABLE_OTHER_VPORT;
2922
2923 acl = mlx5_create_vport_flow_table(egress_ns, &ft_attr, vport->vport);
2924 if (IS_ERR(acl)) {
2925 err = PTR_ERR(acl);
2926 goto out;
2927 }
2928
2929 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
2930 match_criteria);
2931 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
2932 misc_parameters.source_port);
2933 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
2934 misc_parameters.source_eswitch_owner_vhca_id);
2935 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
2936 MLX5_MATCH_MISC_PARAMETERS);
2937
2938 MLX5_SET(create_flow_group_in, flow_group_in,
2939 source_eswitch_owner_vhca_id_valid, 1);
2940 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
2941 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, count);
2942
2943 g = mlx5_create_flow_group(acl, flow_group_in);
2944 if (IS_ERR(g)) {
2945 err = PTR_ERR(g);
2946 goto err_group;
2947 }
2948
2949 vport->egress.acl = acl;
2950 vport->egress.offloads.bounce_grp = g;
2951 vport->egress.type = VPORT_EGRESS_ACL_TYPE_SHARED_FDB;
2952 xa_init_flags(&vport->egress.offloads.bounce_rules, XA_FLAGS_ALLOC);
2953
2954 kvfree(flow_group_in);
2955
2956 return 0;
2957
2958 err_group:
2959 mlx5_destroy_flow_table(acl);
2960 out:
2961 kvfree(flow_group_in);
2962 return err;
2963 }
2964
esw_master_egress_destroy_resources(struct mlx5_vport * vport)2965 static void esw_master_egress_destroy_resources(struct mlx5_vport *vport)
2966 {
2967 if (!xa_empty(&vport->egress.offloads.bounce_rules))
2968 return;
2969 mlx5_destroy_flow_group(vport->egress.offloads.bounce_grp);
2970 vport->egress.offloads.bounce_grp = NULL;
2971 mlx5_destroy_flow_table(vport->egress.acl);
2972 vport->egress.acl = NULL;
2973 }
2974
esw_set_master_egress_rule(struct mlx5_core_dev * master,struct mlx5_core_dev * slave,size_t count)2975 static int esw_set_master_egress_rule(struct mlx5_core_dev *master,
2976 struct mlx5_core_dev *slave, size_t count)
2977 {
2978 struct mlx5_eswitch *esw = master->priv.eswitch;
2979 u16 slave_index = MLX5_CAP_GEN(slave, vhca_id);
2980 struct mlx5_flow_namespace *egress_ns;
2981 struct mlx5_vport *vport;
2982 int err;
2983
2984 vport = mlx5_eswitch_get_vport(esw, esw->manager_vport);
2985 if (IS_ERR(vport))
2986 return PTR_ERR(vport);
2987
2988 egress_ns = mlx5_get_flow_vport_namespace(master,
2989 MLX5_FLOW_NAMESPACE_ESW_EGRESS,
2990 vport->index);
2991 if (!egress_ns)
2992 return -EINVAL;
2993
2994 if (vport->egress.acl && vport->egress.type != VPORT_EGRESS_ACL_TYPE_SHARED_FDB)
2995 return 0;
2996
2997 err = esw_master_egress_create_resources(esw, egress_ns, vport, count);
2998 if (err)
2999 return err;
3000
3001 if (xa_load(&vport->egress.offloads.bounce_rules, slave_index))
3002 return -EINVAL;
3003
3004 err = __esw_set_master_egress_rule(master, slave, vport, vport->egress.acl);
3005 if (err)
3006 goto err_rule;
3007
3008 return 0;
3009
3010 err_rule:
3011 esw_master_egress_destroy_resources(vport);
3012 return err;
3013 }
3014
esw_unset_master_egress_rule(struct mlx5_core_dev * dev,struct mlx5_core_dev * slave_dev)3015 static void esw_unset_master_egress_rule(struct mlx5_core_dev *dev,
3016 struct mlx5_core_dev *slave_dev)
3017 {
3018 struct mlx5_vport *vport;
3019
3020 vport = mlx5_eswitch_get_vport(dev->priv.eswitch,
3021 dev->priv.eswitch->manager_vport);
3022
3023 esw_acl_egress_ofld_bounce_rule_destroy(vport, MLX5_CAP_GEN(slave_dev, vhca_id));
3024
3025 if (xa_empty(&vport->egress.offloads.bounce_rules)) {
3026 esw_acl_egress_ofld_cleanup(vport);
3027 xa_destroy(&vport->egress.offloads.bounce_rules);
3028 }
3029 }
3030
mlx5_eswitch_offloads_single_fdb_add_one(struct mlx5_eswitch * master_esw,struct mlx5_eswitch * slave_esw,int max_slaves)3031 int mlx5_eswitch_offloads_single_fdb_add_one(struct mlx5_eswitch *master_esw,
3032 struct mlx5_eswitch *slave_esw, int max_slaves)
3033 {
3034 int err;
3035
3036 err = esw_set_slave_root_fdb(master_esw->dev,
3037 slave_esw->dev);
3038 if (err)
3039 return err;
3040
3041 err = esw_set_master_egress_rule(master_esw->dev,
3042 slave_esw->dev, max_slaves);
3043 if (err)
3044 goto err_acl;
3045
3046 return err;
3047
3048 err_acl:
3049 esw_set_slave_root_fdb(NULL, slave_esw->dev);
3050 return err;
3051 }
3052
mlx5_eswitch_offloads_single_fdb_del_one(struct mlx5_eswitch * master_esw,struct mlx5_eswitch * slave_esw)3053 void mlx5_eswitch_offloads_single_fdb_del_one(struct mlx5_eswitch *master_esw,
3054 struct mlx5_eswitch *slave_esw)
3055 {
3056 esw_set_slave_root_fdb(NULL, slave_esw->dev);
3057 esw_unset_master_egress_rule(master_esw->dev, slave_esw->dev);
3058 }
3059
3060 #define ESW_OFFLOADS_DEVCOM_PAIR (0)
3061 #define ESW_OFFLOADS_DEVCOM_UNPAIR (1)
3062
mlx5_esw_offloads_rep_event_unpair(struct mlx5_eswitch * esw,struct mlx5_eswitch * peer_esw)3063 static void mlx5_esw_offloads_rep_event_unpair(struct mlx5_eswitch *esw,
3064 struct mlx5_eswitch *peer_esw)
3065 {
3066 const struct mlx5_eswitch_rep_ops *ops;
3067 struct mlx5_eswitch_rep *rep;
3068 unsigned long i;
3069 u8 rep_type;
3070
3071 mlx5_esw_for_each_rep(esw, i, rep) {
3072 rep_type = NUM_REP_TYPES;
3073 while (rep_type--) {
3074 ops = esw->offloads.rep_ops[rep_type];
3075 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
3076 ops->event)
3077 ops->event(esw, rep, MLX5_SWITCHDEV_EVENT_UNPAIR, peer_esw);
3078 }
3079 }
3080 }
3081
mlx5_esw_offloads_unpair(struct mlx5_eswitch * esw,struct mlx5_eswitch * peer_esw)3082 static void mlx5_esw_offloads_unpair(struct mlx5_eswitch *esw,
3083 struct mlx5_eswitch *peer_esw)
3084 {
3085 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3086 mlx5e_tc_clean_fdb_peer_flows(esw);
3087 #endif
3088 mlx5_esw_offloads_rep_event_unpair(esw, peer_esw);
3089 esw_del_fdb_peer_miss_rules(esw, peer_esw->dev);
3090 }
3091
mlx5_esw_offloads_pair(struct mlx5_eswitch * esw,struct mlx5_eswitch * peer_esw)3092 static int mlx5_esw_offloads_pair(struct mlx5_eswitch *esw,
3093 struct mlx5_eswitch *peer_esw)
3094 {
3095 const struct mlx5_eswitch_rep_ops *ops;
3096 struct mlx5_eswitch_rep *rep;
3097 unsigned long i;
3098 u8 rep_type;
3099 int err;
3100
3101 err = esw_add_fdb_peer_miss_rules(esw, peer_esw->dev);
3102 if (err)
3103 return err;
3104
3105 mlx5_esw_for_each_rep(esw, i, rep) {
3106 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++) {
3107 ops = esw->offloads.rep_ops[rep_type];
3108 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
3109 ops->event) {
3110 err = ops->event(esw, rep, MLX5_SWITCHDEV_EVENT_PAIR, peer_esw);
3111 if (err)
3112 goto err_out;
3113 }
3114 }
3115 }
3116
3117 return 0;
3118
3119 err_out:
3120 mlx5_esw_offloads_unpair(esw, peer_esw);
3121 return err;
3122 }
3123
mlx5_esw_offloads_set_ns_peer(struct mlx5_eswitch * esw,struct mlx5_eswitch * peer_esw,bool pair)3124 static int mlx5_esw_offloads_set_ns_peer(struct mlx5_eswitch *esw,
3125 struct mlx5_eswitch *peer_esw,
3126 bool pair)
3127 {
3128 u16 peer_vhca_id = MLX5_CAP_GEN(peer_esw->dev, vhca_id);
3129 u16 vhca_id = MLX5_CAP_GEN(esw->dev, vhca_id);
3130 struct mlx5_flow_root_namespace *peer_ns;
3131 struct mlx5_flow_root_namespace *ns;
3132 int err;
3133
3134 peer_ns = peer_esw->dev->priv.steering->fdb_root_ns;
3135 ns = esw->dev->priv.steering->fdb_root_ns;
3136
3137 if (pair) {
3138 err = mlx5_flow_namespace_set_peer(ns, peer_ns, peer_vhca_id);
3139 if (err)
3140 return err;
3141
3142 err = mlx5_flow_namespace_set_peer(peer_ns, ns, vhca_id);
3143 if (err) {
3144 mlx5_flow_namespace_set_peer(ns, NULL, peer_vhca_id);
3145 return err;
3146 }
3147 } else {
3148 mlx5_flow_namespace_set_peer(ns, NULL, peer_vhca_id);
3149 mlx5_flow_namespace_set_peer(peer_ns, NULL, vhca_id);
3150 }
3151
3152 return 0;
3153 }
3154
mlx5_esw_offloads_devcom_event(int event,void * my_data,void * event_data)3155 static int mlx5_esw_offloads_devcom_event(int event,
3156 void *my_data,
3157 void *event_data)
3158 {
3159 struct mlx5_eswitch *esw = my_data;
3160 struct mlx5_eswitch *peer_esw = event_data;
3161 u16 esw_i, peer_esw_i;
3162 bool esw_paired;
3163 int err;
3164
3165 peer_esw_i = MLX5_CAP_GEN(peer_esw->dev, vhca_id);
3166 esw_i = MLX5_CAP_GEN(esw->dev, vhca_id);
3167 esw_paired = !!xa_load(&esw->paired, peer_esw_i);
3168
3169 switch (event) {
3170 case ESW_OFFLOADS_DEVCOM_PAIR:
3171 if (mlx5_eswitch_vport_match_metadata_enabled(esw) !=
3172 mlx5_eswitch_vport_match_metadata_enabled(peer_esw))
3173 break;
3174
3175 if (esw_paired)
3176 break;
3177
3178 err = mlx5_esw_offloads_set_ns_peer(esw, peer_esw, true);
3179 if (err)
3180 goto err_out;
3181
3182 err = mlx5_esw_offloads_pair(esw, peer_esw);
3183 if (err)
3184 goto err_peer;
3185
3186 err = mlx5_esw_offloads_pair(peer_esw, esw);
3187 if (err)
3188 goto err_pair;
3189
3190 err = xa_insert(&esw->paired, peer_esw_i, peer_esw, GFP_KERNEL);
3191 if (err)
3192 goto err_xa;
3193
3194 err = xa_insert(&peer_esw->paired, esw_i, esw, GFP_KERNEL);
3195 if (err)
3196 goto err_peer_xa;
3197
3198 esw->num_peers++;
3199 peer_esw->num_peers++;
3200 mlx5_devcom_comp_set_ready(esw->devcom, true);
3201 break;
3202
3203 case ESW_OFFLOADS_DEVCOM_UNPAIR:
3204 if (!esw_paired)
3205 break;
3206
3207 peer_esw->num_peers--;
3208 esw->num_peers--;
3209 if (!esw->num_peers && !peer_esw->num_peers)
3210 mlx5_devcom_comp_set_ready(esw->devcom, false);
3211 xa_erase(&peer_esw->paired, esw_i);
3212 xa_erase(&esw->paired, peer_esw_i);
3213 mlx5_esw_offloads_unpair(peer_esw, esw);
3214 mlx5_esw_offloads_unpair(esw, peer_esw);
3215 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
3216 break;
3217 }
3218
3219 return 0;
3220
3221 err_peer_xa:
3222 xa_erase(&esw->paired, peer_esw_i);
3223 err_xa:
3224 mlx5_esw_offloads_unpair(peer_esw, esw);
3225 err_pair:
3226 mlx5_esw_offloads_unpair(esw, peer_esw);
3227 err_peer:
3228 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
3229 err_out:
3230 mlx5_core_err(esw->dev, "esw offloads devcom event failure, event %u err %d",
3231 event, err);
3232 return err;
3233 }
3234
mlx5_esw_offloads_devcom_init(struct mlx5_eswitch * esw,const struct mlx5_devcom_match_attr * attr)3235 void mlx5_esw_offloads_devcom_init(struct mlx5_eswitch *esw,
3236 const struct mlx5_devcom_match_attr *attr)
3237 {
3238 int i;
3239
3240 for (i = 0; i < MLX5_MAX_PORTS; i++)
3241 INIT_LIST_HEAD(&esw->offloads.peer_flows[i]);
3242 mutex_init(&esw->offloads.peer_mutex);
3243
3244 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
3245 return;
3246
3247 if ((MLX5_VPORT_MANAGER(esw->dev) || mlx5_core_is_ecpf_esw_manager(esw->dev)) &&
3248 !mlx5_lag_is_supported(esw->dev))
3249 return;
3250
3251 xa_init(&esw->paired);
3252 esw->num_peers = 0;
3253 esw->devcom = mlx5_devcom_register_component(esw->dev->priv.devc,
3254 MLX5_DEVCOM_ESW_OFFLOADS,
3255 attr,
3256 mlx5_esw_offloads_devcom_event,
3257 esw);
3258 if (!esw->devcom)
3259 return;
3260
3261 mlx5_devcom_send_event(esw->devcom,
3262 ESW_OFFLOADS_DEVCOM_PAIR,
3263 ESW_OFFLOADS_DEVCOM_UNPAIR,
3264 esw);
3265 }
3266
mlx5_esw_offloads_devcom_cleanup(struct mlx5_eswitch * esw)3267 void mlx5_esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw)
3268 {
3269 if (!esw->devcom)
3270 return;
3271
3272 mlx5_devcom_send_event(esw->devcom,
3273 ESW_OFFLOADS_DEVCOM_UNPAIR,
3274 ESW_OFFLOADS_DEVCOM_UNPAIR,
3275 esw);
3276
3277 mlx5_devcom_unregister_component(esw->devcom);
3278 xa_destroy(&esw->paired);
3279 esw->devcom = NULL;
3280 }
3281
mlx5_esw_offloads_devcom_is_ready(struct mlx5_eswitch * esw)3282 bool mlx5_esw_offloads_devcom_is_ready(struct mlx5_eswitch *esw)
3283 {
3284 return mlx5_devcom_comp_is_ready(esw->devcom);
3285 }
3286
mlx5_esw_vport_match_metadata_supported(const struct mlx5_eswitch * esw)3287 bool mlx5_esw_vport_match_metadata_supported(const struct mlx5_eswitch *esw)
3288 {
3289 if (!MLX5_CAP_ESW(esw->dev, esw_uplink_ingress_acl))
3290 return false;
3291
3292 if (!(MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
3293 MLX5_FDB_TO_VPORT_REG_C_0))
3294 return false;
3295
3296 return true;
3297 }
3298
3299 #define MLX5_ESW_METADATA_RSVD_UPLINK 1
3300
3301 /* Share the same metadata for uplink's. This is fine because:
3302 * (a) In shared FDB mode (LAG) both uplink's are treated the
3303 * same and tagged with the same metadata.
3304 * (b) In non shared FDB mode, packets from physical port0
3305 * cannot hit eswitch of PF1 and vice versa.
3306 */
mlx5_esw_match_metadata_reserved(struct mlx5_eswitch * esw)3307 static u32 mlx5_esw_match_metadata_reserved(struct mlx5_eswitch *esw)
3308 {
3309 return MLX5_ESW_METADATA_RSVD_UPLINK;
3310 }
3311
mlx5_esw_match_metadata_alloc(struct mlx5_eswitch * esw)3312 u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswitch *esw)
3313 {
3314 u32 vport_end_ida = (1 << ESW_VPORT_BITS) - 1;
3315 /* Reserve 0xf for internal port offload */
3316 u32 max_pf_num = (1 << ESW_PFNUM_BITS) - 2;
3317 u32 pf_num;
3318 int id;
3319
3320 /* Only 4 bits of pf_num */
3321 pf_num = mlx5_get_dev_index(esw->dev);
3322 if (pf_num > max_pf_num)
3323 return 0;
3324
3325 /* Metadata is 4 bits of PFNUM and 12 bits of unique id */
3326 /* Use only non-zero vport_id (2-4095) for all PF's */
3327 id = ida_alloc_range(&esw->offloads.vport_metadata_ida,
3328 MLX5_ESW_METADATA_RSVD_UPLINK + 1,
3329 vport_end_ida, GFP_KERNEL);
3330 if (id < 0)
3331 return 0;
3332 id = (pf_num << ESW_VPORT_BITS) | id;
3333 return id;
3334 }
3335
mlx5_esw_match_metadata_free(struct mlx5_eswitch * esw,u32 metadata)3336 void mlx5_esw_match_metadata_free(struct mlx5_eswitch *esw, u32 metadata)
3337 {
3338 u32 vport_bit_mask = (1 << ESW_VPORT_BITS) - 1;
3339
3340 /* Metadata contains only 12 bits of actual ida id */
3341 ida_free(&esw->offloads.vport_metadata_ida, metadata & vport_bit_mask);
3342 }
3343
esw_offloads_vport_metadata_setup(struct mlx5_eswitch * esw,struct mlx5_vport * vport)3344 static int esw_offloads_vport_metadata_setup(struct mlx5_eswitch *esw,
3345 struct mlx5_vport *vport)
3346 {
3347 if (vport->vport == MLX5_VPORT_UPLINK)
3348 vport->default_metadata = mlx5_esw_match_metadata_reserved(esw);
3349 else
3350 vport->default_metadata = mlx5_esw_match_metadata_alloc(esw);
3351
3352 vport->metadata = vport->default_metadata;
3353 return vport->metadata ? 0 : -ENOSPC;
3354 }
3355
esw_offloads_vport_metadata_cleanup(struct mlx5_eswitch * esw,struct mlx5_vport * vport)3356 static void esw_offloads_vport_metadata_cleanup(struct mlx5_eswitch *esw,
3357 struct mlx5_vport *vport)
3358 {
3359 if (!vport->default_metadata)
3360 return;
3361
3362 if (vport->vport == MLX5_VPORT_UPLINK)
3363 return;
3364
3365 WARN_ON(vport->metadata != vport->default_metadata);
3366 mlx5_esw_match_metadata_free(esw, vport->default_metadata);
3367 }
3368
esw_offloads_metadata_uninit(struct mlx5_eswitch * esw)3369 static void esw_offloads_metadata_uninit(struct mlx5_eswitch *esw)
3370 {
3371 struct mlx5_vport *vport;
3372 unsigned long i;
3373
3374 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
3375 return;
3376
3377 mlx5_esw_for_each_vport(esw, i, vport)
3378 esw_offloads_vport_metadata_cleanup(esw, vport);
3379 }
3380
esw_offloads_metadata_init(struct mlx5_eswitch * esw)3381 static int esw_offloads_metadata_init(struct mlx5_eswitch *esw)
3382 {
3383 struct mlx5_vport *vport;
3384 unsigned long i;
3385 int err;
3386
3387 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
3388 return 0;
3389
3390 mlx5_esw_for_each_vport(esw, i, vport) {
3391 err = esw_offloads_vport_metadata_setup(esw, vport);
3392 if (err)
3393 goto metadata_err;
3394 }
3395
3396 return 0;
3397
3398 metadata_err:
3399 esw_offloads_metadata_uninit(esw);
3400 return err;
3401 }
3402
3403 int
esw_vport_create_offloads_acl_tables(struct mlx5_eswitch * esw,struct mlx5_vport * vport)3404 esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw,
3405 struct mlx5_vport *vport)
3406 {
3407 int err;
3408
3409 err = esw_acl_ingress_ofld_setup(esw, vport);
3410 if (err)
3411 return err;
3412
3413 err = esw_acl_egress_ofld_setup(esw, vport);
3414 if (err)
3415 goto egress_err;
3416
3417 return 0;
3418
3419 egress_err:
3420 esw_acl_ingress_ofld_cleanup(esw, vport);
3421 return err;
3422 }
3423
3424 void
esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch * esw,struct mlx5_vport * vport)3425 esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw,
3426 struct mlx5_vport *vport)
3427 {
3428 esw_acl_egress_ofld_cleanup(vport);
3429 esw_acl_ingress_ofld_cleanup(esw, vport);
3430 }
3431
esw_create_offloads_acl_tables(struct mlx5_eswitch * esw)3432 static int esw_create_offloads_acl_tables(struct mlx5_eswitch *esw)
3433 {
3434 struct mlx5_vport *uplink, *manager;
3435 int ret;
3436
3437 uplink = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
3438 if (IS_ERR(uplink))
3439 return PTR_ERR(uplink);
3440
3441 ret = esw_vport_create_offloads_acl_tables(esw, uplink);
3442 if (ret)
3443 return ret;
3444
3445 manager = mlx5_eswitch_get_vport(esw, esw->manager_vport);
3446 if (IS_ERR(manager)) {
3447 ret = PTR_ERR(manager);
3448 goto err_manager;
3449 }
3450
3451 ret = esw_vport_create_offloads_acl_tables(esw, manager);
3452 if (ret)
3453 goto err_manager;
3454
3455 return 0;
3456
3457 err_manager:
3458 esw_vport_destroy_offloads_acl_tables(esw, uplink);
3459 return ret;
3460 }
3461
esw_destroy_offloads_acl_tables(struct mlx5_eswitch * esw)3462 static void esw_destroy_offloads_acl_tables(struct mlx5_eswitch *esw)
3463 {
3464 struct mlx5_vport *vport;
3465
3466 vport = mlx5_eswitch_get_vport(esw, esw->manager_vport);
3467 if (!IS_ERR(vport))
3468 esw_vport_destroy_offloads_acl_tables(esw, vport);
3469
3470 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
3471 if (!IS_ERR(vport))
3472 esw_vport_destroy_offloads_acl_tables(esw, vport);
3473 }
3474
mlx5_eswitch_reload_ib_reps(struct mlx5_eswitch * esw)3475 int mlx5_eswitch_reload_ib_reps(struct mlx5_eswitch *esw)
3476 {
3477 struct mlx5_eswitch_rep *rep;
3478 unsigned long i;
3479 int ret;
3480
3481 if (!esw || esw->mode != MLX5_ESWITCH_OFFLOADS)
3482 return 0;
3483
3484 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
3485 if (atomic_read(&rep->rep_data[REP_ETH].state) != REP_LOADED)
3486 return 0;
3487
3488 ret = __esw_offloads_load_rep(esw, rep, REP_IB);
3489 if (ret)
3490 return ret;
3491
3492 mlx5_esw_for_each_rep(esw, i, rep) {
3493 if (atomic_read(&rep->rep_data[REP_ETH].state) == REP_LOADED)
3494 __esw_offloads_load_rep(esw, rep, REP_IB);
3495 }
3496
3497 return 0;
3498 }
3499
esw_offloads_steering_init(struct mlx5_eswitch * esw)3500 static int esw_offloads_steering_init(struct mlx5_eswitch *esw)
3501 {
3502 struct mlx5_esw_indir_table *indir;
3503 int err;
3504
3505 memset(&esw->fdb_table.offloads, 0, sizeof(struct offloads_fdb));
3506 mutex_init(&esw->fdb_table.offloads.vports.lock);
3507 hash_init(esw->fdb_table.offloads.vports.table);
3508 atomic64_set(&esw->user_count, 0);
3509
3510 indir = mlx5_esw_indir_table_init();
3511 if (IS_ERR(indir)) {
3512 err = PTR_ERR(indir);
3513 goto create_indir_err;
3514 }
3515 esw->fdb_table.offloads.indir = indir;
3516
3517 err = esw_create_offloads_acl_tables(esw);
3518 if (err)
3519 goto create_acl_err;
3520
3521 err = esw_create_offloads_table(esw);
3522 if (err)
3523 goto create_offloads_err;
3524
3525 err = esw_create_restore_table(esw);
3526 if (err)
3527 goto create_restore_err;
3528
3529 err = esw_create_offloads_fdb_tables(esw);
3530 if (err)
3531 goto create_fdb_err;
3532
3533 err = esw_create_vport_rx_group(esw);
3534 if (err)
3535 goto create_fg_err;
3536
3537 err = esw_create_vport_rx_drop_group(esw);
3538 if (err)
3539 goto create_rx_drop_fg_err;
3540
3541 err = esw_create_vport_rx_drop_rule(esw);
3542 if (err)
3543 goto create_rx_drop_rule_err;
3544
3545 return 0;
3546
3547 create_rx_drop_rule_err:
3548 esw_destroy_vport_rx_drop_group(esw);
3549 create_rx_drop_fg_err:
3550 esw_destroy_vport_rx_group(esw);
3551 create_fg_err:
3552 esw_destroy_offloads_fdb_tables(esw);
3553 create_fdb_err:
3554 esw_destroy_restore_table(esw);
3555 create_restore_err:
3556 esw_destroy_offloads_table(esw);
3557 create_offloads_err:
3558 esw_destroy_offloads_acl_tables(esw);
3559 create_acl_err:
3560 mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir);
3561 create_indir_err:
3562 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
3563 return err;
3564 }
3565
esw_offloads_steering_cleanup(struct mlx5_eswitch * esw)3566 static void esw_offloads_steering_cleanup(struct mlx5_eswitch *esw)
3567 {
3568 mlx5_esw_fdb_drop_destroy(esw);
3569 if (esw->fdb_table.offloads.drop_root_fc)
3570 mlx5_fc_destroy(esw->dev, esw->fdb_table.offloads.drop_root_fc);
3571 esw->fdb_table.offloads.drop_root_fc = NULL;
3572 esw_destroy_vport_rx_drop_rule(esw);
3573 esw_destroy_vport_rx_drop_group(esw);
3574 esw_destroy_vport_rx_group(esw);
3575 esw_destroy_offloads_fdb_tables(esw);
3576 esw_destroy_restore_table(esw);
3577 esw_destroy_offloads_table(esw);
3578 esw_destroy_offloads_acl_tables(esw);
3579 mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir);
3580 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
3581 }
3582
3583 static void
esw_vfs_changed_event_handler(struct mlx5_eswitch * esw,const u32 * out)3584 esw_vfs_changed_event_handler(struct mlx5_eswitch *esw, const u32 *out)
3585 {
3586 struct devlink *devlink;
3587 bool host_pf_disabled;
3588 u16 new_num_vfs;
3589
3590 new_num_vfs = MLX5_GET(query_esw_functions_out, out,
3591 host_params_context.host_num_of_vfs);
3592 host_pf_disabled = MLX5_GET(query_esw_functions_out, out,
3593 host_params_context.host_pf_disabled);
3594
3595 if (new_num_vfs == esw->esw_funcs.num_vfs || host_pf_disabled)
3596 return;
3597
3598 devlink = priv_to_devlink(esw->dev);
3599 devl_lock(devlink);
3600 /* Number of VFs can only change from "0 to x" or "x to 0". */
3601 if (esw->esw_funcs.num_vfs > 0) {
3602 mlx5_eswitch_unload_vf_vports(esw, esw->esw_funcs.num_vfs);
3603 } else {
3604 int err;
3605
3606 err = mlx5_eswitch_load_vf_vports(esw, new_num_vfs,
3607 MLX5_VPORT_UC_ADDR_CHANGE);
3608 if (err) {
3609 devl_unlock(devlink);
3610 return;
3611 }
3612 }
3613 esw->esw_funcs.num_vfs = new_num_vfs;
3614 devl_unlock(devlink);
3615 }
3616
esw_functions_changed_event_handler(struct work_struct * work)3617 static void esw_functions_changed_event_handler(struct work_struct *work)
3618 {
3619 struct mlx5_host_work *host_work;
3620 struct mlx5_eswitch *esw;
3621 const u32 *out;
3622
3623 host_work = container_of(work, struct mlx5_host_work, work);
3624 esw = host_work->esw;
3625
3626 out = mlx5_esw_query_functions(esw->dev);
3627 if (IS_ERR(out))
3628 goto out;
3629
3630 esw_vfs_changed_event_handler(esw, out);
3631 kvfree(out);
3632 out:
3633 kfree(host_work);
3634 }
3635
mlx5_esw_funcs_changed_handler(struct notifier_block * nb,unsigned long type,void * data)3636 int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data)
3637 {
3638 struct mlx5_esw_functions *esw_funcs;
3639 struct mlx5_host_work *host_work;
3640 struct mlx5_eswitch *esw;
3641
3642 host_work = kzalloc(sizeof(*host_work), GFP_ATOMIC);
3643 if (!host_work)
3644 return NOTIFY_DONE;
3645
3646 esw_funcs = mlx5_nb_cof(nb, struct mlx5_esw_functions, nb);
3647 esw = container_of(esw_funcs, struct mlx5_eswitch, esw_funcs);
3648
3649 host_work->esw = esw;
3650
3651 INIT_WORK(&host_work->work, esw_functions_changed_event_handler);
3652 queue_work(esw->work_queue, &host_work->work);
3653
3654 return NOTIFY_OK;
3655 }
3656
mlx5_esw_host_number_init(struct mlx5_eswitch * esw)3657 static int mlx5_esw_host_number_init(struct mlx5_eswitch *esw)
3658 {
3659 const u32 *query_host_out;
3660
3661 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
3662 return 0;
3663
3664 query_host_out = mlx5_esw_query_functions(esw->dev);
3665 if (IS_ERR(query_host_out))
3666 return PTR_ERR(query_host_out);
3667
3668 /* Mark non local controller with non zero controller number. */
3669 esw->offloads.host_number = MLX5_GET(query_esw_functions_out, query_host_out,
3670 host_params_context.host_number);
3671 kvfree(query_host_out);
3672 return 0;
3673 }
3674
mlx5_esw_offloads_controller_valid(const struct mlx5_eswitch * esw,u32 controller)3675 bool mlx5_esw_offloads_controller_valid(const struct mlx5_eswitch *esw, u32 controller)
3676 {
3677 /* Local controller is always valid */
3678 if (controller == 0)
3679 return true;
3680
3681 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
3682 return false;
3683
3684 /* External host number starts with zero in device */
3685 return (controller == esw->offloads.host_number + 1);
3686 }
3687
esw_offloads_enable(struct mlx5_eswitch * esw)3688 int esw_offloads_enable(struct mlx5_eswitch *esw)
3689 {
3690 u8 mapping_id[MLX5_SW_IMAGE_GUID_MAX_BYTES];
3691 struct mapping_ctx *reg_c0_obj_pool;
3692 struct mlx5_vport *vport;
3693 unsigned long i;
3694 u8 id_len;
3695 int err;
3696
3697 mutex_init(&esw->offloads.termtbl_mutex);
3698 mlx5_esw_adjacent_vhcas_setup(esw);
3699
3700 err = mlx5_rdma_enable_roce(esw->dev);
3701 if (err)
3702 goto err_roce;
3703
3704 err = mlx5_esw_host_number_init(esw);
3705 if (err)
3706 goto err_metadata;
3707
3708 err = esw_offloads_metadata_init(esw);
3709 if (err)
3710 goto err_metadata;
3711
3712 err = esw_set_passing_vport_metadata(esw, true);
3713 if (err)
3714 goto err_vport_metadata;
3715
3716 mlx5_query_nic_sw_system_image_guid(esw->dev, mapping_id, &id_len);
3717
3718 reg_c0_obj_pool = mapping_create_for_id(mapping_id, id_len,
3719 MAPPING_TYPE_CHAIN,
3720 sizeof(struct mlx5_mapped_obj),
3721 ESW_REG_C0_USER_DATA_METADATA_MASK,
3722 true);
3723
3724 if (IS_ERR(reg_c0_obj_pool)) {
3725 err = PTR_ERR(reg_c0_obj_pool);
3726 goto err_pool;
3727 }
3728 esw->offloads.reg_c0_obj_pool = reg_c0_obj_pool;
3729
3730 err = esw_offloads_steering_init(esw);
3731 if (err)
3732 goto err_steering_init;
3733
3734 if (esw->offloads_inactive)
3735 mlx5_esw_fdb_inactive(esw);
3736 else
3737 mlx5_esw_fdb_active(esw);
3738
3739 /* Representor will control the vport link state */
3740 mlx5_esw_for_each_vf_vport(esw, i, vport, esw->esw_funcs.num_vfs)
3741 vport->info.link_state = MLX5_VPORT_ADMIN_STATE_DOWN;
3742 if (mlx5_core_ec_sriov_enabled(esw->dev))
3743 mlx5_esw_for_each_ec_vf_vport(esw, i, vport, esw->esw_funcs.num_ec_vfs)
3744 vport->info.link_state = MLX5_VPORT_ADMIN_STATE_DOWN;
3745
3746 /* Uplink vport rep must load first. */
3747 err = mlx5_esw_offloads_rep_load(esw, MLX5_VPORT_UPLINK);
3748 if (err)
3749 goto err_uplink;
3750
3751 err = mlx5_eswitch_enable_pf_vf_vports(esw, MLX5_VPORT_UC_ADDR_CHANGE);
3752 if (err)
3753 goto err_vports;
3754
3755 return 0;
3756
3757 err_vports:
3758 mlx5_esw_offloads_rep_unload(esw, MLX5_VPORT_UPLINK);
3759 err_uplink:
3760 esw_offloads_steering_cleanup(esw);
3761 err_steering_init:
3762 mapping_destroy(reg_c0_obj_pool);
3763 err_pool:
3764 esw_set_passing_vport_metadata(esw, false);
3765 err_vport_metadata:
3766 esw_offloads_metadata_uninit(esw);
3767 err_metadata:
3768 mlx5_rdma_disable_roce(esw->dev);
3769 err_roce:
3770 mlx5_esw_adjacent_vhcas_cleanup(esw);
3771 mutex_destroy(&esw->offloads.termtbl_mutex);
3772 return err;
3773 }
3774
esw_offloads_stop(struct mlx5_eswitch * esw,struct netlink_ext_ack * extack)3775 static int esw_offloads_stop(struct mlx5_eswitch *esw,
3776 struct netlink_ext_ack *extack)
3777 {
3778 int err;
3779
3780 esw_mode_change(esw, MLX5_ESWITCH_LEGACY);
3781
3782 /* If changing from switchdev to legacy mode without sriov enabled,
3783 * no need to create legacy fdb.
3784 */
3785 if (!mlx5_core_is_pf(esw->dev) || !mlx5_sriov_is_enabled(esw->dev))
3786 return 0;
3787
3788 err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_IGNORE_NUM_VFS);
3789 if (err)
3790 NL_SET_ERR_MSG_MOD(extack, "Failed setting eswitch to legacy");
3791
3792 return err;
3793 }
3794
esw_offloads_disable(struct mlx5_eswitch * esw)3795 void esw_offloads_disable(struct mlx5_eswitch *esw)
3796 {
3797 mlx5_eswitch_disable_pf_vf_vports(esw);
3798 mlx5_esw_offloads_rep_unload(esw, MLX5_VPORT_UPLINK);
3799 esw_set_passing_vport_metadata(esw, false);
3800 esw_offloads_steering_cleanup(esw);
3801 mapping_destroy(esw->offloads.reg_c0_obj_pool);
3802 esw_offloads_metadata_uninit(esw);
3803 mlx5_rdma_disable_roce(esw->dev);
3804 mlx5_esw_adjacent_vhcas_cleanup(esw);
3805 /* must be done after vhcas cleanup to avoid adjacent vports connect */
3806 if (esw->offloads_inactive)
3807 mlx5_esw_fdb_active(esw); /* legacy mode always active */
3808 mutex_destroy(&esw->offloads.termtbl_mutex);
3809 }
3810
esw_mode_from_devlink(u16 mode,u16 * mlx5_mode)3811 static int esw_mode_from_devlink(u16 mode, u16 *mlx5_mode)
3812 {
3813 switch (mode) {
3814 case DEVLINK_ESWITCH_MODE_LEGACY:
3815 *mlx5_mode = MLX5_ESWITCH_LEGACY;
3816 break;
3817 case DEVLINK_ESWITCH_MODE_SWITCHDEV:
3818 case DEVLINK_ESWITCH_MODE_SWITCHDEV_INACTIVE:
3819 *mlx5_mode = MLX5_ESWITCH_OFFLOADS;
3820 break;
3821 default:
3822 return -EINVAL;
3823 }
3824
3825 return 0;
3826 }
3827
esw_mode_to_devlink(struct mlx5_eswitch * esw,u16 * mode)3828 static int esw_mode_to_devlink(struct mlx5_eswitch *esw, u16 *mode)
3829 {
3830 switch (esw->mode) {
3831 case MLX5_ESWITCH_LEGACY:
3832 *mode = DEVLINK_ESWITCH_MODE_LEGACY;
3833 break;
3834 case MLX5_ESWITCH_OFFLOADS:
3835 if (esw->offloads_inactive)
3836 *mode = DEVLINK_ESWITCH_MODE_SWITCHDEV_INACTIVE;
3837 else
3838 *mode = DEVLINK_ESWITCH_MODE_SWITCHDEV;
3839 break;
3840 default:
3841 return -EINVAL;
3842 }
3843
3844 return 0;
3845 }
3846
esw_inline_mode_from_devlink(u8 mode,u8 * mlx5_mode)3847 static int esw_inline_mode_from_devlink(u8 mode, u8 *mlx5_mode)
3848 {
3849 switch (mode) {
3850 case DEVLINK_ESWITCH_INLINE_MODE_NONE:
3851 *mlx5_mode = MLX5_INLINE_MODE_NONE;
3852 break;
3853 case DEVLINK_ESWITCH_INLINE_MODE_LINK:
3854 *mlx5_mode = MLX5_INLINE_MODE_L2;
3855 break;
3856 case DEVLINK_ESWITCH_INLINE_MODE_NETWORK:
3857 *mlx5_mode = MLX5_INLINE_MODE_IP;
3858 break;
3859 case DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT:
3860 *mlx5_mode = MLX5_INLINE_MODE_TCP_UDP;
3861 break;
3862 default:
3863 return -EINVAL;
3864 }
3865
3866 return 0;
3867 }
3868
esw_inline_mode_to_devlink(u8 mlx5_mode,u8 * mode)3869 static int esw_inline_mode_to_devlink(u8 mlx5_mode, u8 *mode)
3870 {
3871 switch (mlx5_mode) {
3872 case MLX5_INLINE_MODE_NONE:
3873 *mode = DEVLINK_ESWITCH_INLINE_MODE_NONE;
3874 break;
3875 case MLX5_INLINE_MODE_L2:
3876 *mode = DEVLINK_ESWITCH_INLINE_MODE_LINK;
3877 break;
3878 case MLX5_INLINE_MODE_IP:
3879 *mode = DEVLINK_ESWITCH_INLINE_MODE_NETWORK;
3880 break;
3881 case MLX5_INLINE_MODE_TCP_UDP:
3882 *mode = DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT;
3883 break;
3884 default:
3885 return -EINVAL;
3886 }
3887
3888 return 0;
3889 }
3890
mlx5_eswitch_block_mode(struct mlx5_core_dev * dev)3891 int mlx5_eswitch_block_mode(struct mlx5_core_dev *dev)
3892 {
3893 struct mlx5_eswitch *esw = dev->priv.eswitch;
3894 int err;
3895
3896 if (!mlx5_esw_allowed(esw))
3897 return 0;
3898
3899 /* Take TC into account */
3900 err = mlx5_esw_try_lock(esw);
3901 if (err < 0)
3902 return err;
3903
3904 esw->offloads.num_block_mode++;
3905 mlx5_esw_unlock(esw);
3906 return 0;
3907 }
3908
mlx5_eswitch_unblock_mode(struct mlx5_core_dev * dev)3909 void mlx5_eswitch_unblock_mode(struct mlx5_core_dev *dev)
3910 {
3911 struct mlx5_eswitch *esw = dev->priv.eswitch;
3912
3913 if (!mlx5_esw_allowed(esw))
3914 return;
3915
3916 down_write(&esw->mode_lock);
3917 esw->offloads.num_block_mode--;
3918 up_write(&esw->mode_lock);
3919 }
3920
3921 /* Returns false only when uplink netdev exists and its netns is different from
3922 * devlink's netns. True for all others so entering switchdev mode is allowed.
3923 */
mlx5_devlink_netdev_netns_immutable_set(struct devlink * devlink,bool immutable)3924 static bool mlx5_devlink_netdev_netns_immutable_set(struct devlink *devlink,
3925 bool immutable)
3926 {
3927 struct mlx5_core_dev *mdev = devlink_priv(devlink);
3928 struct net_device *netdev;
3929 bool ret;
3930
3931 netdev = mlx5_uplink_netdev_get(mdev);
3932 if (!netdev)
3933 return true;
3934
3935 rtnl_lock();
3936 netdev->netns_immutable = immutable;
3937 ret = net_eq(dev_net(netdev), devlink_net(devlink));
3938 rtnl_unlock();
3939
3940 mlx5_uplink_netdev_put(mdev, netdev);
3941 return ret;
3942 }
3943
3944 /* Returns true when only changing between active and inactive switchdev mode */
mlx5_devlink_switchdev_active_mode_change(struct mlx5_eswitch * esw,u16 devlink_mode)3945 static bool mlx5_devlink_switchdev_active_mode_change(struct mlx5_eswitch *esw,
3946 u16 devlink_mode)
3947 {
3948 /* current mode is not switchdev */
3949 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
3950 return false;
3951
3952 /* new mode is not switchdev */
3953 if (devlink_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV &&
3954 devlink_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV_INACTIVE)
3955 return false;
3956
3957 /* already inactive: no change in current state */
3958 if (devlink_mode == DEVLINK_ESWITCH_MODE_SWITCHDEV_INACTIVE &&
3959 esw->offloads_inactive)
3960 return false;
3961
3962 /* already active: no change in current state */
3963 if (devlink_mode == DEVLINK_ESWITCH_MODE_SWITCHDEV &&
3964 !esw->offloads_inactive)
3965 return false;
3966
3967 down_write(&esw->mode_lock);
3968 esw->offloads_inactive = !esw->offloads_inactive;
3969 esw->eswitch_operation_in_progress = true;
3970 up_write(&esw->mode_lock);
3971
3972 if (esw->offloads_inactive)
3973 mlx5_esw_fdb_inactive(esw);
3974 else
3975 mlx5_esw_fdb_active(esw);
3976
3977 down_write(&esw->mode_lock);
3978 esw->eswitch_operation_in_progress = false;
3979 up_write(&esw->mode_lock);
3980 return true;
3981 }
3982
mlx5_devlink_eswitch_mode_set(struct devlink * devlink,u16 mode,struct netlink_ext_ack * extack)3983 int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
3984 struct netlink_ext_ack *extack)
3985 {
3986 u16 cur_mlx5_mode, mlx5_mode = 0;
3987 struct mlx5_eswitch *esw;
3988 int err = 0;
3989
3990 esw = mlx5_devlink_eswitch_get(devlink);
3991 if (IS_ERR(esw))
3992 return PTR_ERR(esw);
3993
3994 if (esw_mode_from_devlink(mode, &mlx5_mode))
3995 return -EINVAL;
3996
3997 if (mlx5_mode == MLX5_ESWITCH_OFFLOADS && mlx5_get_sd(esw->dev)) {
3998 NL_SET_ERR_MSG_MOD(extack,
3999 "Can't change E-Switch mode to switchdev when multi-PF netdev (Socket Direct) is configured.");
4000 return -EPERM;
4001 }
4002
4003 /* Avoid try_lock, active/inactive mode change is not restricted */
4004 if (mlx5_devlink_switchdev_active_mode_change(esw, mode))
4005 return 0;
4006
4007 mlx5_lag_disable_change(esw->dev);
4008 err = mlx5_esw_try_lock(esw);
4009 if (err < 0) {
4010 NL_SET_ERR_MSG_MOD(extack, "Can't change mode, E-Switch is busy");
4011 goto enable_lag;
4012 }
4013 cur_mlx5_mode = err;
4014 err = 0;
4015
4016 if (cur_mlx5_mode == mlx5_mode)
4017 goto unlock;
4018
4019 if (esw->offloads.num_block_mode) {
4020 NL_SET_ERR_MSG_MOD(extack,
4021 "Can't change eswitch mode when IPsec SA and/or policies are configured");
4022 err = -EOPNOTSUPP;
4023 goto unlock;
4024 }
4025
4026 esw->eswitch_operation_in_progress = true;
4027 up_write(&esw->mode_lock);
4028
4029 if (mlx5_mode == MLX5_ESWITCH_OFFLOADS &&
4030 !mlx5_devlink_netdev_netns_immutable_set(devlink, true)) {
4031 NL_SET_ERR_MSG_MOD(extack,
4032 "Can't change E-Switch mode to switchdev when netdev net namespace has diverged from the devlink's.");
4033 err = -EINVAL;
4034 goto skip;
4035 }
4036
4037 if (mlx5_mode == MLX5_ESWITCH_LEGACY)
4038 esw->dev->priv.flags |= MLX5_PRIV_FLAGS_SWITCH_LEGACY;
4039 mlx5_eswitch_disable_locked(esw);
4040 if (mlx5_mode == MLX5_ESWITCH_OFFLOADS) {
4041 if (mlx5_devlink_trap_get_num_active(esw->dev)) {
4042 NL_SET_ERR_MSG_MOD(extack,
4043 "Can't change mode while devlink traps are active");
4044 err = -EOPNOTSUPP;
4045 goto skip;
4046 }
4047 esw->offloads_inactive =
4048 (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV_INACTIVE);
4049 err = esw_offloads_start(esw, extack);
4050 } else if (mlx5_mode == MLX5_ESWITCH_LEGACY) {
4051 err = esw_offloads_stop(esw, extack);
4052 } else {
4053 err = -EINVAL;
4054 }
4055
4056 skip:
4057 if (mlx5_mode == MLX5_ESWITCH_OFFLOADS && err)
4058 mlx5_devlink_netdev_netns_immutable_set(devlink, false);
4059 down_write(&esw->mode_lock);
4060 esw->eswitch_operation_in_progress = false;
4061 unlock:
4062 mlx5_esw_unlock(esw);
4063 enable_lag:
4064 mlx5_lag_enable_change(esw->dev);
4065 return err;
4066 }
4067
mlx5_devlink_eswitch_mode_get(struct devlink * devlink,u16 * mode)4068 int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode)
4069 {
4070 struct mlx5_eswitch *esw;
4071
4072 esw = mlx5_devlink_eswitch_get(devlink);
4073 if (IS_ERR(esw))
4074 return PTR_ERR(esw);
4075
4076 return esw_mode_to_devlink(esw, mode);
4077 }
4078
mlx5_esw_vports_inline_set(struct mlx5_eswitch * esw,u8 mlx5_mode,struct netlink_ext_ack * extack)4079 static int mlx5_esw_vports_inline_set(struct mlx5_eswitch *esw, u8 mlx5_mode,
4080 struct netlink_ext_ack *extack)
4081 {
4082 struct mlx5_core_dev *dev = esw->dev;
4083 struct mlx5_vport *vport;
4084 u16 err_vport_num = 0;
4085 unsigned long i;
4086 int err = 0;
4087
4088 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
4089 err = mlx5_modify_nic_vport_min_inline(dev, vport->vport, mlx5_mode);
4090 if (err) {
4091 err_vport_num = vport->vport;
4092 NL_SET_ERR_MSG_MOD(extack,
4093 "Failed to set min inline on vport");
4094 goto revert_inline_mode;
4095 }
4096 }
4097 if (mlx5_core_ec_sriov_enabled(esw->dev)) {
4098 mlx5_esw_for_each_ec_vf_vport(esw, i, vport, esw->esw_funcs.num_ec_vfs) {
4099 err = mlx5_modify_nic_vport_min_inline(dev, vport->vport, mlx5_mode);
4100 if (err) {
4101 err_vport_num = vport->vport;
4102 NL_SET_ERR_MSG_MOD(extack,
4103 "Failed to set min inline on vport");
4104 goto revert_ec_vf_inline_mode;
4105 }
4106 }
4107 }
4108 return 0;
4109
4110 revert_ec_vf_inline_mode:
4111 mlx5_esw_for_each_ec_vf_vport(esw, i, vport, esw->esw_funcs.num_ec_vfs) {
4112 if (vport->vport == err_vport_num)
4113 break;
4114 mlx5_modify_nic_vport_min_inline(dev,
4115 vport->vport,
4116 esw->offloads.inline_mode);
4117 }
4118 revert_inline_mode:
4119 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
4120 if (vport->vport == err_vport_num)
4121 break;
4122 mlx5_modify_nic_vport_min_inline(dev,
4123 vport->vport,
4124 esw->offloads.inline_mode);
4125 }
4126 return err;
4127 }
4128
mlx5_devlink_eswitch_inline_mode_set(struct devlink * devlink,u8 mode,struct netlink_ext_ack * extack)4129 int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
4130 struct netlink_ext_ack *extack)
4131 {
4132 struct mlx5_core_dev *dev = devlink_priv(devlink);
4133 struct mlx5_eswitch *esw;
4134 u8 mlx5_mode;
4135 int err;
4136
4137 esw = mlx5_devlink_eswitch_get(devlink);
4138 if (IS_ERR(esw))
4139 return PTR_ERR(esw);
4140
4141 down_write(&esw->mode_lock);
4142
4143 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
4144 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
4145 if (mode == DEVLINK_ESWITCH_INLINE_MODE_NONE) {
4146 err = 0;
4147 goto out;
4148 }
4149
4150 fallthrough;
4151 case MLX5_CAP_INLINE_MODE_L2:
4152 NL_SET_ERR_MSG_MOD(extack, "Inline mode can't be set");
4153 err = -EOPNOTSUPP;
4154 goto out;
4155 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
4156 break;
4157 }
4158
4159 if (atomic64_read(&esw->offloads.num_flows) > 0) {
4160 NL_SET_ERR_MSG_MOD(extack,
4161 "Can't set inline mode when flows are configured");
4162 err = -EOPNOTSUPP;
4163 goto out;
4164 }
4165
4166 err = esw_inline_mode_from_devlink(mode, &mlx5_mode);
4167 if (err)
4168 goto out;
4169
4170 esw->eswitch_operation_in_progress = true;
4171 up_write(&esw->mode_lock);
4172
4173 err = mlx5_esw_vports_inline_set(esw, mlx5_mode, extack);
4174 if (!err)
4175 esw->offloads.inline_mode = mlx5_mode;
4176
4177 down_write(&esw->mode_lock);
4178 esw->eswitch_operation_in_progress = false;
4179 up_write(&esw->mode_lock);
4180 return 0;
4181
4182 out:
4183 up_write(&esw->mode_lock);
4184 return err;
4185 }
4186
mlx5_devlink_eswitch_inline_mode_get(struct devlink * devlink,u8 * mode)4187 int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode)
4188 {
4189 struct mlx5_eswitch *esw;
4190
4191 esw = mlx5_devlink_eswitch_get(devlink);
4192 if (IS_ERR(esw))
4193 return PTR_ERR(esw);
4194
4195 return esw_inline_mode_to_devlink(esw->offloads.inline_mode, mode);
4196 }
4197
mlx5_eswitch_block_encap(struct mlx5_core_dev * dev,bool from_fdb)4198 bool mlx5_eswitch_block_encap(struct mlx5_core_dev *dev, bool from_fdb)
4199 {
4200 struct mlx5_eswitch *esw = dev->priv.eswitch;
4201 enum devlink_eswitch_encap_mode encap;
4202 bool allow_tunnel = false;
4203
4204 if (!mlx5_esw_allowed(esw))
4205 return true;
4206
4207 down_write(&esw->mode_lock);
4208 encap = esw->offloads.encap;
4209 if (esw->mode == MLX5_ESWITCH_LEGACY ||
4210 (encap == DEVLINK_ESWITCH_ENCAP_MODE_NONE && !from_fdb)) {
4211 allow_tunnel = true;
4212 esw->offloads.num_block_encap++;
4213 }
4214 up_write(&esw->mode_lock);
4215
4216 return allow_tunnel;
4217 }
4218
mlx5_eswitch_unblock_encap(struct mlx5_core_dev * dev)4219 void mlx5_eswitch_unblock_encap(struct mlx5_core_dev *dev)
4220 {
4221 struct mlx5_eswitch *esw = dev->priv.eswitch;
4222
4223 if (!mlx5_esw_allowed(esw))
4224 return;
4225
4226 down_write(&esw->mode_lock);
4227 esw->offloads.num_block_encap--;
4228 up_write(&esw->mode_lock);
4229 }
4230
mlx5_devlink_eswitch_encap_mode_set(struct devlink * devlink,enum devlink_eswitch_encap_mode encap,struct netlink_ext_ack * extack)4231 int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,
4232 enum devlink_eswitch_encap_mode encap,
4233 struct netlink_ext_ack *extack)
4234 {
4235 struct mlx5_core_dev *dev = devlink_priv(devlink);
4236 struct mlx5_eswitch *esw;
4237 int err = 0;
4238
4239 esw = mlx5_devlink_eswitch_get(devlink);
4240 if (IS_ERR(esw))
4241 return PTR_ERR(esw);
4242
4243 down_write(&esw->mode_lock);
4244
4245 if (encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE &&
4246 (!MLX5_CAP_ESW_FLOWTABLE_FDB(dev, reformat) ||
4247 !MLX5_CAP_ESW_FLOWTABLE_FDB(dev, decap))) {
4248 err = -EOPNOTSUPP;
4249 goto unlock;
4250 }
4251
4252 if (encap && encap != DEVLINK_ESWITCH_ENCAP_MODE_BASIC) {
4253 err = -EOPNOTSUPP;
4254 goto unlock;
4255 }
4256
4257 if (esw->mode == MLX5_ESWITCH_LEGACY) {
4258 esw->offloads.encap = encap;
4259 goto unlock;
4260 }
4261
4262 if (esw->offloads.encap == encap)
4263 goto unlock;
4264
4265 if (atomic64_read(&esw->offloads.num_flows) > 0) {
4266 NL_SET_ERR_MSG_MOD(extack,
4267 "Can't set encapsulation when flows are configured");
4268 err = -EOPNOTSUPP;
4269 goto unlock;
4270 }
4271
4272 if (esw->offloads.num_block_encap) {
4273 NL_SET_ERR_MSG_MOD(extack,
4274 "Can't set encapsulation when IPsec SA and/or policies are configured");
4275 err = -EOPNOTSUPP;
4276 goto unlock;
4277 }
4278
4279 esw->eswitch_operation_in_progress = true;
4280 up_write(&esw->mode_lock);
4281
4282 esw_destroy_offloads_fdb_tables(esw);
4283
4284 esw->offloads.encap = encap;
4285
4286 err = esw_create_offloads_fdb_tables(esw);
4287
4288 if (err) {
4289 NL_SET_ERR_MSG_MOD(extack,
4290 "Failed re-creating fast FDB table");
4291 esw->offloads.encap = !encap;
4292 (void)esw_create_offloads_fdb_tables(esw);
4293 }
4294
4295 down_write(&esw->mode_lock);
4296 esw->eswitch_operation_in_progress = false;
4297
4298 unlock:
4299 up_write(&esw->mode_lock);
4300 return err;
4301 }
4302
mlx5_devlink_eswitch_encap_mode_get(struct devlink * devlink,enum devlink_eswitch_encap_mode * encap)4303 int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink,
4304 enum devlink_eswitch_encap_mode *encap)
4305 {
4306 struct mlx5_eswitch *esw;
4307
4308 esw = mlx5_devlink_eswitch_get(devlink);
4309 if (IS_ERR(esw))
4310 return PTR_ERR(esw);
4311
4312 *encap = esw->offloads.encap;
4313 return 0;
4314 }
4315
4316 static bool
mlx5_eswitch_vport_has_rep(const struct mlx5_eswitch * esw,u16 vport_num)4317 mlx5_eswitch_vport_has_rep(const struct mlx5_eswitch *esw, u16 vport_num)
4318 {
4319 /* Currently, only ECPF based device has representor for host PF. */
4320 if (vport_num == MLX5_VPORT_PF &&
4321 (!mlx5_core_is_ecpf_esw_manager(esw->dev) ||
4322 !mlx5_esw_host_functions_enabled(esw->dev)))
4323 return false;
4324
4325 if (vport_num == MLX5_VPORT_ECPF &&
4326 !mlx5_ecpf_vport_exists(esw->dev))
4327 return false;
4328
4329 return true;
4330 }
4331
mlx5_eswitch_register_vport_reps(struct mlx5_eswitch * esw,const struct mlx5_eswitch_rep_ops * ops,u8 rep_type)4332 void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw,
4333 const struct mlx5_eswitch_rep_ops *ops,
4334 u8 rep_type)
4335 {
4336 struct mlx5_eswitch_rep_data *rep_data;
4337 struct mlx5_eswitch_rep *rep;
4338 unsigned long i;
4339
4340 esw->offloads.rep_ops[rep_type] = ops;
4341 mlx5_esw_for_each_rep(esw, i, rep) {
4342 if (likely(mlx5_eswitch_vport_has_rep(esw, rep->vport))) {
4343 rep->esw = esw;
4344 rep_data = &rep->rep_data[rep_type];
4345 atomic_set(&rep_data->state, REP_REGISTERED);
4346 }
4347 }
4348 }
4349 EXPORT_SYMBOL(mlx5_eswitch_register_vport_reps);
4350
mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch * esw,u8 rep_type)4351 void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type)
4352 {
4353 struct mlx5_eswitch_rep *rep;
4354 unsigned long i;
4355
4356 if (esw->mode == MLX5_ESWITCH_OFFLOADS)
4357 __unload_reps_all_vport(esw, rep_type);
4358
4359 mlx5_esw_for_each_rep(esw, i, rep)
4360 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
4361 }
4362 EXPORT_SYMBOL(mlx5_eswitch_unregister_vport_reps);
4363
mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch * esw,u8 rep_type)4364 void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type)
4365 {
4366 struct mlx5_eswitch_rep *rep;
4367
4368 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
4369 return rep->rep_data[rep_type].priv;
4370 }
4371
mlx5_eswitch_get_proto_dev(struct mlx5_eswitch * esw,u16 vport,u8 rep_type)4372 void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,
4373 u16 vport,
4374 u8 rep_type)
4375 {
4376 struct mlx5_eswitch_rep *rep;
4377
4378 rep = mlx5_eswitch_get_rep(esw, vport);
4379
4380 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
4381 esw->offloads.rep_ops[rep_type]->get_proto_dev)
4382 return esw->offloads.rep_ops[rep_type]->get_proto_dev(rep);
4383 return NULL;
4384 }
4385 EXPORT_SYMBOL(mlx5_eswitch_get_proto_dev);
4386
mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch * esw,u8 rep_type)4387 void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type)
4388 {
4389 return mlx5_eswitch_get_proto_dev(esw, MLX5_VPORT_UPLINK, rep_type);
4390 }
4391 EXPORT_SYMBOL(mlx5_eswitch_uplink_get_proto_dev);
4392
mlx5_eswitch_vport_rep(struct mlx5_eswitch * esw,u16 vport)4393 struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
4394 u16 vport)
4395 {
4396 return mlx5_eswitch_get_rep(esw, vport);
4397 }
4398 EXPORT_SYMBOL(mlx5_eswitch_vport_rep);
4399
mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch * esw)4400 bool mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch *esw)
4401 {
4402 return !!(esw->flags & MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED);
4403 }
4404 EXPORT_SYMBOL(mlx5_eswitch_reg_c1_loopback_enabled);
4405
mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch * esw)4406 bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw)
4407 {
4408 return !!(esw->flags & MLX5_ESWITCH_VPORT_MATCH_METADATA);
4409 }
4410 EXPORT_SYMBOL(mlx5_eswitch_vport_match_metadata_enabled);
4411
mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch * esw,u16 vport_num)4412 u32 mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw,
4413 u16 vport_num)
4414 {
4415 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
4416
4417 if (WARN_ON_ONCE(IS_ERR(vport)))
4418 return 0;
4419
4420 return vport->metadata << (32 - ESW_SOURCE_PORT_METADATA_BITS);
4421 }
4422 EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_match);
4423
mlx5_esw_vport_vhca_id_map(struct mlx5_eswitch * esw,struct mlx5_vport * vport)4424 int mlx5_esw_vport_vhca_id_map(struct mlx5_eswitch *esw,
4425 struct mlx5_vport *vport)
4426 {
4427 u16 *old_entry, *vhca_map_entry, vhca_id;
4428
4429 if (WARN_ONCE(MLX5_VPORT_INVAL_VHCA_ID(vport),
4430 "vport %d vhca_id is not set", vport->vport)) {
4431 int err;
4432
4433 err = mlx5_vport_get_vhca_id(vport->dev, vport->vport,
4434 &vhca_id);
4435 if (err)
4436 return err;
4437 vport->vhca_id = vhca_id;
4438 }
4439
4440 vhca_id = vport->vhca_id;
4441 vhca_map_entry = kmalloc(sizeof(*vhca_map_entry), GFP_KERNEL);
4442 if (!vhca_map_entry)
4443 return -ENOMEM;
4444
4445 *vhca_map_entry = vport->vport;
4446 old_entry = xa_store(&esw->offloads.vhca_map, vhca_id, vhca_map_entry, GFP_KERNEL);
4447 if (xa_is_err(old_entry)) {
4448 kfree(vhca_map_entry);
4449 return xa_err(old_entry);
4450 }
4451 kfree(old_entry);
4452 return 0;
4453 }
4454
mlx5_esw_vport_vhca_id_unmap(struct mlx5_eswitch * esw,struct mlx5_vport * vport)4455 void mlx5_esw_vport_vhca_id_unmap(struct mlx5_eswitch *esw,
4456 struct mlx5_vport *vport)
4457 {
4458 u16 *vhca_map_entry;
4459
4460 vhca_map_entry = xa_erase(&esw->offloads.vhca_map, vport->vhca_id);
4461 kfree(vhca_map_entry);
4462 }
4463
mlx5_eswitch_vhca_id_to_vport(struct mlx5_eswitch * esw,u16 vhca_id,u16 * vport_num)4464 int mlx5_eswitch_vhca_id_to_vport(struct mlx5_eswitch *esw, u16 vhca_id, u16 *vport_num)
4465 {
4466 u16 *res = xa_load(&esw->offloads.vhca_map, vhca_id);
4467
4468 if (!res)
4469 return -ENOENT;
4470
4471 *vport_num = *res;
4472 return 0;
4473 }
4474
mlx5_eswitch_get_vport_metadata_for_set(struct mlx5_eswitch * esw,u16 vport_num)4475 u32 mlx5_eswitch_get_vport_metadata_for_set(struct mlx5_eswitch *esw,
4476 u16 vport_num)
4477 {
4478 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
4479
4480 if (WARN_ON_ONCE(IS_ERR(vport)))
4481 return 0;
4482
4483 return vport->metadata;
4484 }
4485 EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_set);
4486
mlx5_devlink_port_fn_hw_addr_get(struct devlink_port * port,u8 * hw_addr,int * hw_addr_len,struct netlink_ext_ack * extack)4487 int mlx5_devlink_port_fn_hw_addr_get(struct devlink_port *port,
4488 u8 *hw_addr, int *hw_addr_len,
4489 struct netlink_ext_ack *extack)
4490 {
4491 struct mlx5_eswitch *esw = mlx5_devlink_eswitch_nocheck_get(port->devlink);
4492 struct mlx5_vport *vport = mlx5_devlink_port_vport_get(port);
4493
4494 mutex_lock(&esw->state_lock);
4495
4496 mlx5_query_nic_vport_mac_address(esw->dev, vport->vport, true,
4497 vport->info.mac);
4498 ether_addr_copy(hw_addr, vport->info.mac);
4499 *hw_addr_len = ETH_ALEN;
4500 mutex_unlock(&esw->state_lock);
4501 return 0;
4502 }
4503
mlx5_devlink_port_fn_hw_addr_set(struct devlink_port * port,const u8 * hw_addr,int hw_addr_len,struct netlink_ext_ack * extack)4504 int mlx5_devlink_port_fn_hw_addr_set(struct devlink_port *port,
4505 const u8 *hw_addr, int hw_addr_len,
4506 struct netlink_ext_ack *extack)
4507 {
4508 struct mlx5_eswitch *esw = mlx5_devlink_eswitch_nocheck_get(port->devlink);
4509 struct mlx5_vport *vport = mlx5_devlink_port_vport_get(port);
4510
4511 return mlx5_eswitch_set_vport_mac(esw, vport->vport, hw_addr);
4512 }
4513
mlx5_devlink_port_fn_migratable_get(struct devlink_port * port,bool * is_enabled,struct netlink_ext_ack * extack)4514 int mlx5_devlink_port_fn_migratable_get(struct devlink_port *port, bool *is_enabled,
4515 struct netlink_ext_ack *extack)
4516 {
4517 struct mlx5_eswitch *esw = mlx5_devlink_eswitch_nocheck_get(port->devlink);
4518 struct mlx5_vport *vport = mlx5_devlink_port_vport_get(port);
4519
4520 if (!MLX5_CAP_GEN(esw->dev, migration)) {
4521 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support migration");
4522 return -EOPNOTSUPP;
4523 }
4524
4525 if (!MLX5_CAP_GEN(esw->dev, vhca_resource_manager)) {
4526 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support VHCA management");
4527 return -EOPNOTSUPP;
4528 }
4529
4530 mutex_lock(&esw->state_lock);
4531 *is_enabled = vport->info.mig_enabled;
4532 mutex_unlock(&esw->state_lock);
4533 return 0;
4534 }
4535
mlx5_devlink_port_fn_migratable_set(struct devlink_port * port,bool enable,struct netlink_ext_ack * extack)4536 int mlx5_devlink_port_fn_migratable_set(struct devlink_port *port, bool enable,
4537 struct netlink_ext_ack *extack)
4538 {
4539 struct mlx5_eswitch *esw = mlx5_devlink_eswitch_nocheck_get(port->devlink);
4540 struct mlx5_vport *vport = mlx5_devlink_port_vport_get(port);
4541 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
4542 void *query_ctx;
4543 void *hca_caps;
4544 int err;
4545
4546 if (!MLX5_CAP_GEN(esw->dev, migration)) {
4547 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support migration");
4548 return -EOPNOTSUPP;
4549 }
4550
4551 if (!MLX5_CAP_GEN(esw->dev, vhca_resource_manager)) {
4552 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support VHCA management");
4553 return -EOPNOTSUPP;
4554 }
4555
4556 mutex_lock(&esw->state_lock);
4557
4558 if (vport->info.mig_enabled == enable) {
4559 err = 0;
4560 goto out;
4561 }
4562
4563 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
4564 if (!query_ctx) {
4565 err = -ENOMEM;
4566 goto out;
4567 }
4568
4569 err = mlx5_vport_get_other_func_cap(esw->dev, vport->vport, query_ctx,
4570 MLX5_CAP_GENERAL_2);
4571 if (err) {
4572 NL_SET_ERR_MSG_MOD(extack, "Failed getting HCA caps");
4573 goto out_free;
4574 }
4575
4576 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
4577 MLX5_SET(cmd_hca_cap_2, hca_caps, migratable, enable);
4578
4579 err = mlx5_vport_set_other_func_cap(esw->dev, hca_caps, vport->vport,
4580 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2);
4581 if (err) {
4582 NL_SET_ERR_MSG_MOD(extack, "Failed setting HCA migratable cap");
4583 goto out_free;
4584 }
4585
4586 vport->info.mig_enabled = enable;
4587
4588 out_free:
4589 kfree(query_ctx);
4590 out:
4591 mutex_unlock(&esw->state_lock);
4592 return err;
4593 }
4594
mlx5_devlink_port_fn_roce_get(struct devlink_port * port,bool * is_enabled,struct netlink_ext_ack * extack)4595 int mlx5_devlink_port_fn_roce_get(struct devlink_port *port, bool *is_enabled,
4596 struct netlink_ext_ack *extack)
4597 {
4598 struct mlx5_eswitch *esw = mlx5_devlink_eswitch_nocheck_get(port->devlink);
4599 struct mlx5_vport *vport = mlx5_devlink_port_vport_get(port);
4600
4601 if (!MLX5_CAP_GEN(esw->dev, vhca_resource_manager)) {
4602 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support VHCA management");
4603 return -EOPNOTSUPP;
4604 }
4605
4606 mutex_lock(&esw->state_lock);
4607 *is_enabled = vport->info.roce_enabled;
4608 mutex_unlock(&esw->state_lock);
4609 return 0;
4610 }
4611
mlx5_devlink_port_fn_roce_set(struct devlink_port * port,bool enable,struct netlink_ext_ack * extack)4612 int mlx5_devlink_port_fn_roce_set(struct devlink_port *port, bool enable,
4613 struct netlink_ext_ack *extack)
4614 {
4615 struct mlx5_eswitch *esw = mlx5_devlink_eswitch_nocheck_get(port->devlink);
4616 struct mlx5_vport *vport = mlx5_devlink_port_vport_get(port);
4617 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
4618 u16 vport_num = vport->vport;
4619 void *query_ctx;
4620 void *hca_caps;
4621 int err;
4622
4623 if (!MLX5_CAP_GEN(esw->dev, vhca_resource_manager)) {
4624 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support VHCA management");
4625 return -EOPNOTSUPP;
4626 }
4627
4628 mutex_lock(&esw->state_lock);
4629
4630 if (vport->info.roce_enabled == enable) {
4631 err = 0;
4632 goto out;
4633 }
4634
4635 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
4636 if (!query_ctx) {
4637 err = -ENOMEM;
4638 goto out;
4639 }
4640
4641 err = mlx5_vport_get_other_func_cap(esw->dev, vport_num, query_ctx,
4642 MLX5_CAP_GENERAL);
4643 if (err) {
4644 NL_SET_ERR_MSG_MOD(extack, "Failed getting HCA caps");
4645 goto out_free;
4646 }
4647
4648 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
4649 MLX5_SET(cmd_hca_cap, hca_caps, roce, enable);
4650
4651 err = mlx5_vport_set_other_func_cap(esw->dev, hca_caps, vport_num,
4652 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
4653 if (err) {
4654 NL_SET_ERR_MSG_MOD(extack, "Failed setting HCA roce cap");
4655 goto out_free;
4656 }
4657
4658 vport->info.roce_enabled = enable;
4659
4660 out_free:
4661 kfree(query_ctx);
4662 out:
4663 mutex_unlock(&esw->state_lock);
4664 return err;
4665 }
4666
4667 int
mlx5_eswitch_restore_ipsec_rule(struct mlx5_eswitch * esw,struct mlx5_flow_handle * rule,struct mlx5_esw_flow_attr * esw_attr,int attr_idx)4668 mlx5_eswitch_restore_ipsec_rule(struct mlx5_eswitch *esw, struct mlx5_flow_handle *rule,
4669 struct mlx5_esw_flow_attr *esw_attr, int attr_idx)
4670 {
4671 struct mlx5_flow_destination new_dest = {};
4672 struct mlx5_flow_destination old_dest = {};
4673
4674 if (!esw_setup_uplink_fwd_ipsec_needed(esw, esw_attr, attr_idx))
4675 return 0;
4676
4677 esw_setup_dest_fwd_ipsec(&old_dest, NULL, esw, esw_attr, attr_idx, 0, false);
4678 esw_setup_dest_fwd_vport(&new_dest, NULL, esw, esw_attr, attr_idx, 0, false);
4679
4680 return mlx5_modify_rule_destination(rule, &new_dest, &old_dest);
4681 }
4682
4683 #ifdef CONFIG_XFRM_OFFLOAD
mlx5_devlink_port_fn_ipsec_crypto_get(struct devlink_port * port,bool * is_enabled,struct netlink_ext_ack * extack)4684 int mlx5_devlink_port_fn_ipsec_crypto_get(struct devlink_port *port, bool *is_enabled,
4685 struct netlink_ext_ack *extack)
4686 {
4687 struct mlx5_eswitch *esw;
4688 struct mlx5_vport *vport;
4689 int err = 0;
4690
4691 esw = mlx5_devlink_eswitch_get(port->devlink);
4692 if (IS_ERR(esw))
4693 return PTR_ERR(esw);
4694
4695 if (!mlx5_esw_ipsec_vf_offload_supported(esw->dev)) {
4696 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support IPSec crypto");
4697 return -EOPNOTSUPP;
4698 }
4699
4700 vport = mlx5_devlink_port_vport_get(port);
4701
4702 mutex_lock(&esw->state_lock);
4703 if (!vport->enabled) {
4704 err = -EOPNOTSUPP;
4705 goto unlock;
4706 }
4707
4708 *is_enabled = vport->info.ipsec_crypto_enabled;
4709 unlock:
4710 mutex_unlock(&esw->state_lock);
4711 return err;
4712 }
4713
mlx5_devlink_port_fn_ipsec_crypto_set(struct devlink_port * port,bool enable,struct netlink_ext_ack * extack)4714 int mlx5_devlink_port_fn_ipsec_crypto_set(struct devlink_port *port, bool enable,
4715 struct netlink_ext_ack *extack)
4716 {
4717 struct mlx5_eswitch *esw;
4718 struct mlx5_vport *vport;
4719 u16 vport_num;
4720 int err;
4721
4722 esw = mlx5_devlink_eswitch_get(port->devlink);
4723 if (IS_ERR(esw))
4724 return PTR_ERR(esw);
4725
4726 vport_num = mlx5_esw_devlink_port_index_to_vport_num(port->index);
4727 err = mlx5_esw_ipsec_vf_crypto_offload_supported(esw->dev, vport_num);
4728 if (err) {
4729 NL_SET_ERR_MSG_MOD(extack,
4730 "Device doesn't support IPsec crypto");
4731 return err;
4732 }
4733
4734 vport = mlx5_devlink_port_vport_get(port);
4735
4736 mutex_lock(&esw->state_lock);
4737 if (!vport->enabled) {
4738 err = -EOPNOTSUPP;
4739 NL_SET_ERR_MSG_MOD(extack, "Eswitch vport is disabled");
4740 goto unlock;
4741 }
4742
4743 if (vport->info.ipsec_crypto_enabled == enable)
4744 goto unlock;
4745
4746 if (!esw->enabled_ipsec_vf_count && esw->dev->num_ipsec_offloads) {
4747 err = -EBUSY;
4748 goto unlock;
4749 }
4750
4751 err = mlx5_esw_ipsec_vf_crypto_offload_set(esw, vport, enable);
4752 if (err) {
4753 NL_SET_ERR_MSG_MOD(extack, "Failed to set IPsec crypto");
4754 goto unlock;
4755 }
4756
4757 vport->info.ipsec_crypto_enabled = enable;
4758 if (enable)
4759 esw->enabled_ipsec_vf_count++;
4760 else
4761 esw->enabled_ipsec_vf_count--;
4762 unlock:
4763 mutex_unlock(&esw->state_lock);
4764 return err;
4765 }
4766
mlx5_devlink_port_fn_ipsec_packet_get(struct devlink_port * port,bool * is_enabled,struct netlink_ext_ack * extack)4767 int mlx5_devlink_port_fn_ipsec_packet_get(struct devlink_port *port, bool *is_enabled,
4768 struct netlink_ext_ack *extack)
4769 {
4770 struct mlx5_eswitch *esw;
4771 struct mlx5_vport *vport;
4772 int err = 0;
4773
4774 esw = mlx5_devlink_eswitch_get(port->devlink);
4775 if (IS_ERR(esw))
4776 return PTR_ERR(esw);
4777
4778 if (!mlx5_esw_ipsec_vf_offload_supported(esw->dev)) {
4779 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support IPsec packet");
4780 return -EOPNOTSUPP;
4781 }
4782
4783 vport = mlx5_devlink_port_vport_get(port);
4784
4785 mutex_lock(&esw->state_lock);
4786 if (!vport->enabled) {
4787 err = -EOPNOTSUPP;
4788 goto unlock;
4789 }
4790
4791 *is_enabled = vport->info.ipsec_packet_enabled;
4792 unlock:
4793 mutex_unlock(&esw->state_lock);
4794 return err;
4795 }
4796
mlx5_devlink_port_fn_ipsec_packet_set(struct devlink_port * port,bool enable,struct netlink_ext_ack * extack)4797 int mlx5_devlink_port_fn_ipsec_packet_set(struct devlink_port *port,
4798 bool enable,
4799 struct netlink_ext_ack *extack)
4800 {
4801 struct mlx5_eswitch *esw;
4802 struct mlx5_vport *vport;
4803 u16 vport_num;
4804 int err;
4805
4806 esw = mlx5_devlink_eswitch_get(port->devlink);
4807 if (IS_ERR(esw))
4808 return PTR_ERR(esw);
4809
4810 vport_num = mlx5_esw_devlink_port_index_to_vport_num(port->index);
4811 err = mlx5_esw_ipsec_vf_packet_offload_supported(esw->dev, vport_num);
4812 if (err) {
4813 NL_SET_ERR_MSG_MOD(extack,
4814 "Device doesn't support IPsec packet mode");
4815 return err;
4816 }
4817
4818 vport = mlx5_devlink_port_vport_get(port);
4819 mutex_lock(&esw->state_lock);
4820 if (!vport->enabled) {
4821 err = -EOPNOTSUPP;
4822 NL_SET_ERR_MSG_MOD(extack, "Eswitch vport is disabled");
4823 goto unlock;
4824 }
4825
4826 if (vport->info.ipsec_packet_enabled == enable)
4827 goto unlock;
4828
4829 if (!esw->enabled_ipsec_vf_count && esw->dev->num_ipsec_offloads) {
4830 err = -EBUSY;
4831 goto unlock;
4832 }
4833
4834 err = mlx5_esw_ipsec_vf_packet_offload_set(esw, vport, enable);
4835 if (err) {
4836 NL_SET_ERR_MSG_MOD(extack,
4837 "Failed to set IPsec packet mode");
4838 goto unlock;
4839 }
4840
4841 vport->info.ipsec_packet_enabled = enable;
4842 if (enable)
4843 esw->enabled_ipsec_vf_count++;
4844 else
4845 esw->enabled_ipsec_vf_count--;
4846 unlock:
4847 mutex_unlock(&esw->state_lock);
4848 return err;
4849 }
4850 #endif /* CONFIG_XFRM_OFFLOAD */
4851
4852 int
mlx5_devlink_port_fn_max_io_eqs_get(struct devlink_port * port,u32 * max_io_eqs,struct netlink_ext_ack * extack)4853 mlx5_devlink_port_fn_max_io_eqs_get(struct devlink_port *port, u32 *max_io_eqs,
4854 struct netlink_ext_ack *extack)
4855 {
4856 struct mlx5_vport *vport = mlx5_devlink_port_vport_get(port);
4857 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
4858 u16 vport_num = vport->vport;
4859 struct mlx5_eswitch *esw;
4860 void *query_ctx;
4861 void *hca_caps;
4862 u32 max_eqs;
4863 int err;
4864
4865 esw = mlx5_devlink_eswitch_nocheck_get(port->devlink);
4866 if (!MLX5_CAP_GEN(esw->dev, vhca_resource_manager)) {
4867 NL_SET_ERR_MSG_MOD(extack,
4868 "Device doesn't support VHCA management");
4869 return -EOPNOTSUPP;
4870 }
4871
4872 if (!MLX5_CAP_GEN_2(esw->dev, max_num_eqs_24b)) {
4873 NL_SET_ERR_MSG_MOD(extack,
4874 "Device doesn't support getting the max number of EQs");
4875 return -EOPNOTSUPP;
4876 }
4877
4878 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
4879 if (!query_ctx)
4880 return -ENOMEM;
4881
4882 mutex_lock(&esw->state_lock);
4883 err = mlx5_vport_get_other_func_cap(esw->dev, vport_num, query_ctx,
4884 MLX5_CAP_GENERAL_2);
4885 if (err) {
4886 NL_SET_ERR_MSG_MOD(extack, "Failed getting HCA caps");
4887 goto out;
4888 }
4889
4890 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
4891 max_eqs = MLX5_GET(cmd_hca_cap_2, hca_caps, max_num_eqs_24b);
4892 if (max_eqs < MLX5_ESW_MAX_CTRL_EQS)
4893 *max_io_eqs = 0;
4894 else
4895 *max_io_eqs = max_eqs - MLX5_ESW_MAX_CTRL_EQS;
4896 out:
4897 mutex_unlock(&esw->state_lock);
4898 kfree(query_ctx);
4899 return err;
4900 }
4901
4902 int
mlx5_devlink_port_fn_max_io_eqs_set(struct devlink_port * port,u32 max_io_eqs,struct netlink_ext_ack * extack)4903 mlx5_devlink_port_fn_max_io_eqs_set(struct devlink_port *port, u32 max_io_eqs,
4904 struct netlink_ext_ack *extack)
4905 {
4906 struct mlx5_vport *vport = mlx5_devlink_port_vport_get(port);
4907 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
4908 u16 vport_num = vport->vport;
4909 struct mlx5_eswitch *esw;
4910 void *query_ctx;
4911 void *hca_caps;
4912 u16 max_eqs;
4913 int err;
4914
4915 esw = mlx5_devlink_eswitch_nocheck_get(port->devlink);
4916 if (!MLX5_CAP_GEN(esw->dev, vhca_resource_manager)) {
4917 NL_SET_ERR_MSG_MOD(extack,
4918 "Device doesn't support VHCA management");
4919 return -EOPNOTSUPP;
4920 }
4921
4922 if (!MLX5_CAP_GEN_2(esw->dev, max_num_eqs_24b)) {
4923 NL_SET_ERR_MSG_MOD(extack,
4924 "Device doesn't support changing the max number of EQs");
4925 return -EOPNOTSUPP;
4926 }
4927
4928 if (check_add_overflow(max_io_eqs, MLX5_ESW_MAX_CTRL_EQS, &max_eqs)) {
4929 NL_SET_ERR_MSG_MOD(extack, "Supplied value out of range");
4930 return -EINVAL;
4931 }
4932
4933 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
4934 if (!query_ctx)
4935 return -ENOMEM;
4936
4937 mutex_lock(&esw->state_lock);
4938 err = mlx5_vport_get_other_func_cap(esw->dev, vport_num, query_ctx,
4939 MLX5_CAP_GENERAL_2);
4940 if (err) {
4941 NL_SET_ERR_MSG_MOD(extack, "Failed getting HCA caps");
4942 goto out;
4943 }
4944
4945 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
4946 MLX5_SET(cmd_hca_cap_2, hca_caps, max_num_eqs_24b, max_eqs);
4947
4948 if (mlx5_esw_is_sf_vport(esw, vport_num))
4949 MLX5_SET(cmd_hca_cap_2, hca_caps, sf_eq_usage, 1);
4950
4951 err = mlx5_vport_set_other_func_cap(esw->dev, hca_caps, vport_num,
4952 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2);
4953 if (err)
4954 NL_SET_ERR_MSG_MOD(extack, "Failed setting HCA caps");
4955 vport->max_eqs_set = true;
4956 out:
4957 mutex_unlock(&esw->state_lock);
4958 kfree(query_ctx);
4959 return err;
4960 }
4961
4962 int
mlx5_devlink_port_fn_max_io_eqs_set_sf_default(struct devlink_port * port,struct netlink_ext_ack * extack)4963 mlx5_devlink_port_fn_max_io_eqs_set_sf_default(struct devlink_port *port,
4964 struct netlink_ext_ack *extack)
4965 {
4966 return mlx5_devlink_port_fn_max_io_eqs_set(port,
4967 MLX5_ESW_DEFAULT_SF_COMP_EQS,
4968 extack);
4969 }
4970